JP2009236989A - Plasma display device and driving method of plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate stable writing discharge without increasing writing pulse voltage. <P>SOLUTION: A plasma display device comprises: a plasma display panel 10 including a plurality of discharge cells having a display electrode pair comprising a scanning electrode and a maintenance electrode; a scanning electrode drive circuit 43 including a plurality of sub-fields having an initialization period, a writing period and a maintenance period within one field period, which generates and applies a downward ramped waveform voltage descending in the initialization period to the scanning electrode; and a lighting rate detection circuit 47 which detects, for each sub-field, a ratio of discharge cells to be lighted to all the discharge cells of the plasma display panel 10 as a lighting rate. The scanning electrode drive circuit 43 changes the lowest voltage of the downward ramped waveform voltage to be generated in the initialization period of the current sub-field according to the lighting rate of the last sub-field detected by the lighting rate detection circuit 47. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon in a partial pressure ratio is sealed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method for driving the panel, a subfield method is generally used (see, for example, Patent Document 1). In the subfield method, one field period is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell. Thereby, wall charges necessary for the subsequent address operation are formed in each discharge cell.

  In the address period, a scan pulse is sequentially applied to the scan electrodes (hereinafter, this operation is also referred to as “scan”), and an address pulse corresponding to an image signal to be displayed is applied to the data electrodes (hereinafter, these operations are performed). Are collectively referred to as “writing”). Thereby, an address discharge is selectively generated between the scan electrode and the data electrode, and a wall charge is selectively formed.

  In the subsequent sustain period, a predetermined number of sustain pulses corresponding to the luminance to be displayed are alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode. Thereby, a discharge is selectively caused in the discharge cell in which the wall charge is formed by the address discharge, and the discharge cell is caused to emit light. Thereby, an image is displayed.

The plurality of scan electrodes are driven by a scan electrode drive circuit, the plurality of sustain electrodes are driven by a sustain electrode drive circuit, and the plurality of data electrodes are driven by a data electrode drive circuit.
JP 2006-18298 A

  In recent years, the panel has been further refined, but in the case of a discharge cell miniaturized as the panel becomes highly refined, the charge that causes the wall charge formed in the discharge cell to be lost by the initializing discharge is lost. It has been confirmed that a phenomenon called omission is likely to occur. In addition, it is known that the wall charges are gradually lost with time, and the wall charges are influenced by the address pulse applied to the data electrode in order to generate the address discharge in other discharge cells. It has also been confirmed that it will decrease. Therefore, in a discharge cell in which the scan pulse is applied in the address period after the initialization discharge has occurred, more wall charges are easily lost until the scan pulse and the address pulse are applied to the discharge cell. Discharge failure during operation is likely to occur. In particular, in a high-definition panel, since the time spent for scanning becomes longer due to the increase in the number of scanning electrodes, the reduction of wall charges in the discharge cells that are written toward the end of the address period becomes even greater. It is easy to make the address discharge unstable.

  Therefore, in order to generate a stable address discharge, it is important to appropriately adjust the wall charges in the initialization operation. However, since the initialization discharge may vary depending on the lighting state of the discharge cell, it is difficult to properly adjust the wall charge regardless of the lighting state of the discharge cell.

  The present invention has been made in view of these problems, and the wall charge can be appropriately adjusted by controlling the initialization discharge according to the lighting state of the discharge cell, so that stable address discharge is generated. An object of the present invention is to provide a plasma display device and a panel driving method that can be performed.

  A plasma display apparatus according to the present invention includes a panel including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode, and a subfield having an initialization period, an address period, and a sustain period within one field period. A plurality of scanning electrode driving circuits for generating a falling ramp waveform voltage that falls during the initialization period and applying the voltage to the scanning electrodes, and a ratio of discharge cells to be lit to all discharge cells of the panel as a lighting rate for each subfield A scan rate driving circuit for detecting a lighting rate of the subfield immediately before the scan rate detecting circuit detects the lowest voltage of the downward ramp waveform voltage generated in the initializing period of the current subfield. It changes according to.

  As a result, the initialization discharge of the current subfield can be controlled according to the lighting rate of the immediately preceding subfield and the wall charge can be adjusted appropriately, so that stable address discharge can be performed without increasing the address pulse voltage. Can be generated.

  Further, in this plasma display device, the scan electrode driving circuit includes a subfield for performing an all-cell initializing operation for generating an initializing discharge in all the discharge cells of the panel and an address period for the immediately preceding subfield within one field period. And a subfield performing a selective initializing operation for generating an initializing discharge only in a discharge cell in which an address discharge has been generated. In a subfield performing an all-cell initializing operation, the lighting rate of the immediately preceding subfield is set to Regardless, the minimum voltage of the downward ramp waveform voltage may be constant.

  Also, the panel driving method of the present invention provides a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, and a subfield having an initialization period, an address period, and a sustain period in one field. A panel driving method in which a plurality of ramp voltages are provided in a period and a falling ramp waveform voltage that falls in an initialization period is generated and applied to a scan electrode, and the ratio of discharge cells to be lit to all discharge cells of the panel is determined. The lighting rate is detected for each subfield, and the minimum voltage of the downward ramp waveform voltage generated in the initialization period of the current subfield is changed according to the lighting rate of the immediately preceding subfield.

  As a result, the initialization discharge of the current subfield can be controlled according to the lighting rate of the immediately preceding subfield and the wall charge can be adjusted appropriately, so that stable address discharge can be performed without increasing the address pulse voltage. Can be generated.

  Further, the panel driving method of the present invention includes a subfield for performing an all-cell initializing operation for generating an initializing discharge in all the discharge cells of the panel within one field period, and an address discharge in the address period of the immediately preceding subfield. A subfield for performing a selective initializing operation for generating an initializing discharge only in a discharge cell that has generated a fault, and in a subfield for performing an all-cell initializing operation, a subfield is output regardless of the lighting rate of the immediately preceding subfield. The minimum voltage of the ramp waveform voltage may be constant.

  According to the present invention, the wall charge can be appropriately adjusted by controlling the initializing discharge in accordance with the lighting state of the discharge cell, and thus a plasma display device capable of generating stable address discharge and It is possible to provide a panel driving method.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed on a glass front plate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is formed from a material mainly composed of MgO having excellent properties.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by barrier ribs 34, and discharge cells are formed at portions where display electrode pairs 24 and data electrodes 32 intersect. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 according to the embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) arranged in the row direction. The m data electrodes D1 to Dm (data electrodes 32 in FIG. 1) extending in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. A region where m × n discharge cells are formed becomes a display region of the panel 10.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 3 is a circuit block diagram of plasma display device 1 in accordance with the exemplary embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, a lighting rate detection circuit 47, a memory 48, and each circuit block. Is provided with a power supply circuit (not shown) for supplying the necessary power.

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield according to the number of pixels of the panel 10.

  The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm based on the timing signal.

  The lighting rate detection circuit 47 detects the ratio of the number of discharge cells to be lit to the total number of discharge cells, that is, the lighting rate, for each subfield, based on the image data for each subfield. Then, the detected lighting rate is compared with a plurality of predetermined lighting rate threshold values (in this embodiment, 40% and 70%), and a signal representing the result is output to the timing generation circuit 45. The signal output from the lighting rate detection circuit 47 is delayed by one subfield period in the memory 48 and input to the timing generation circuit 45. The lighting rate threshold value is not limited to these numerical values, and is preferably set to an optimal value based on the characteristics of the panel and the specifications of the plasma display device.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H, the vertical synchronization signal V, and the output from the lighting rate detection circuit 47, and each circuit block (image signal processing) Circuit 41, data electrode drive circuit 42, scan electrode drive circuit 43 and sustain electrode drive circuit 44).

  Scan electrode drive circuit 43 has an initialization waveform generation circuit (not shown) for generating an initialization waveform to be applied to scan electrode SC1 through scan electrode SCn in the initialization period, and scan electrode SC1 through scan electrode SCn in the sustain period. A sustain pulse generating circuit (not shown) for generating a sustain pulse to be applied to the scan pulse, and a scan pulse generating circuit for generating a scan pulse to be applied to scan electrode SC1 through scan electrode SCn in the address period, having a plurality of scan ICs 52. Then, each scan electrode SC1 to scan electrode SCn is driven based on the timing signal.

  Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit (not shown) for generating voltage Ve1 and voltage Ve2, and drives sustain electrode SU1 through sustain electrode SUn based on a timing signal.

  Scan electrode driving circuit 43 in the present embodiment changes the initialization waveform applied to scan electrode SC1 through scan electrode SCn during the initialization period based on the lighting rate detected by lighting rate detection circuit 47. . As a result, in the plasma display device 1 according to the present embodiment, the wall charge is appropriately adjusted in the initialization operation and the address discharge is stabilized. Details of this will be described later.

  Next, details of the scan electrode driving circuit 43 will be described. FIG. 4 is a circuit diagram of scan electrode driving circuit 43 according to the embodiment of the present invention. The scan electrode drive circuit 43 includes a sustain pulse generation circuit 50 that generates a sustain pulse, an initialization waveform generation circuit 51 that generates an initialization waveform, and a scan pulse generation circuit 52 that generates a scan pulse. Each output terminal is connected to each of scan electrode SC1 to scan electrode SCn of panel 10. In FIG. 4, when a circuit using the negative voltage Va (for example, the Miller integrating circuit 54) is operated, the circuit, the sustain pulse generating circuit 50, and a circuit using the voltage Vr (for example, a mirror) A separation circuit using a switching element Q4 for electrically separating the integration circuit 53) is shown. In the following description, the operation for turning on the switching element is expressed as “on”, the operation for cutting off the switching element is expressed as “off”, the signal for turning on the switching element is expressed as “Hi”, and the signal for turning off is expressed as “Lo”.

  Sustain pulse generation circuit 50 includes a generally used power recovery circuit (not shown) and a clamp circuit (not shown), and each switching provided therein based on a timing signal output from timing generation circuit 45. A sustain pulse is generated by switching elements. In FIG. 4, details of the signal path of the timing signal are omitted. Further, a Miller integration circuit (not shown) for generating a rising ramp waveform voltage is provided, and an erase ramp waveform to be described later is generated at the end of the sustain period.

  The initialization waveform generation circuit 51 includes a switching element Q1, a capacitor C1, and a resistor R1, and includes a Miller integration circuit 53 that raises the reference potential A of the scan pulse generation circuit 52 in a ramp shape, a switching element Q2, a capacitor C2, and a resistance R2. And a Miller integrating circuit 54 that drops the reference potential A of the scanning pulse generating circuit 52 in a ramp shape. Miller integrating circuit 53 generates a ramp waveform voltage that increases during the initialization operation, and Miller integration circuit 54 generates a ramp waveform voltage that decreases during the initialization operation. In FIG. 4, the input terminal of Miller integrating circuit 53 is shown as input terminal IN1, and the input terminal of Miller integrating circuit 54 is shown as input terminal IN2.

  In this embodiment, the initialization waveform generating circuit 51 employs a Miller integration circuit using a field effect transistor (FET) that is practical and has a relatively simple configuration. The circuit is not limited to this configuration, and any circuit may be used as long as it can raise or lower the reference potential A in a ramp shape.

  Scan pulse generation circuit 52 includes a plurality of scan ICs 55 (in this embodiment, scan IC (1) to scan IC (12)) that output a scan pulse to each of scan electrode SC1 to scan electrode SCn, and an address period. A switching element Q5 for connecting the reference potential A to the negative voltage Va, a diode D31 and a capacitor C31 for applying a voltage Vc obtained by superimposing the voltage Vscn on the voltage Va to the high voltage side of the scan IC 55, and two inputs A comparator CP1 for comparing the magnitudes of input signals input to the terminals, a switching element SW1 for applying a voltage (Va + Vset2) to one input terminal of the comparator CP1, and a voltage to one input terminal of the comparator CP1 The switching element SW2 for applying (Va + Vset3) and the voltage (Va) at one input terminal of the comparator CP1. And a switching element SW3 for applying the Vset4). The other input terminal of the comparator CP1 is connected to the reference potential A.

  The scan IC 55 has two input terminals, an input terminal INa that is a low voltage side input terminal and an input terminal INb that is a high voltage side input terminal, and is input to the two input terminals based on a control signal. Output one of the signals. Each of the scan ICs 55 is supplied with a control signal OC1 output from the timing generation circuit 45 and a control signal OC2 output from the comparator CP1 as control signals. The scan start signal SID (1) output from the timing generation circuit 45 immediately after the start of the address period is input to the scan IC (1) that performs the scan first in the address period. In addition, a clock signal which is a synchronization signal for synchronizing the signal processing operation is commonly input to all the scan ICs 55 (in this embodiment, the scan IC (1) to the scan IC (12)). However, the path is omitted in FIG.

  Scan pulse generation circuit 52 is controlled by timing generation circuit 45 to output the voltage waveform of initialization waveform generation circuit 51 in the initialization period and to output the voltage waveform of sustain pulse generation circuit 50 in the sustain period. The

  FIG. 5 is a schematic diagram showing a state of connection between scan IC 55 of scan electrode driving circuit 43 and scan electrode SC1 through scan electrode SCn in one embodiment of the present invention. In FIG. 5, circuits other than the scan IC 55 (scan IC (1) to scan IC (12)) are omitted.

  Scan pulse generation circuit 52 includes switching elements QH1 to QHn and switching elements QL1 to QLn for applying a scan pulse voltage to each of n scan electrodes SC1 to SCn. Switching element QH1 to switching element QHn and switching element QL1 to switching element QLn are integrated into a plurality of outputs and integrated into an IC. This IC is a scanning IC 55.

  In the present embodiment, it is assumed that switching elements for 90 outputs are integrated as one monolithic IC, and the panel 10 includes 1080 scanning electrodes 22. That is, it is assumed that scan pulse generation circuit 52 is configured by using 12 scan ICs (1) to IC (12), and n = 1080 scan electrodes SC1 to scan electrodes SCn are driven. In this way, by making a large number of switching elements QH1 to QHn and switching elements QL1 to QLn into an IC, the number of parts can be reduced and the mounting area can be reduced. However, the numerical values shown in this embodiment are merely examples, and the present invention is not limited to these numerical values.

  In the address operation, first, scan IC (1) connected to scan electrode SC1 to scan electrode SC90 is operated, and then scan IC (2) connected to scan electrode SC91 to scan electrode SC180 is operated. Thereafter, the scan IC (3) to the scan IC (12) are sequentially operated.

  Switching of switching elements QH1 to QHn and switching elements QL1 to QLn is performed by scanning start signal SID, control signal OC1, and control signal OC2, as described above.

  Next, the operation of the scan IC 55 will be described. FIG. 6 is a diagram illustrating a correspondence relationship between the control signals OC1 and OC2 and the operation state of the scan IC 55 in the embodiment of the present invention.

  As shown in FIG. 6, when both the control signal OC1 and the control signal OC2 are at a high level (hereinafter referred to as “Hi”), the scan IC 55 is in the “All-Hi” state, that is, the output terminal of the scan IC 55. All the switching elements provided in the scan IC 55 are switched so that all are electrically connected to the input terminal INb on the high voltage side.

  When the control signal OC1 is “Hi” and the control signal OC2 is at a low level (hereinafter referred to as “Lo”), the scan IC 55 is in an “All-Lo” state, that is, all the output terminals of the scan IC 55 are at a low voltage. All the switching elements provided in the scan IC 55 are switched so as to be electrically connected to the input terminal INa on the side. For example, when the initialization waveform generation circuit 51 or the sustain pulse generation circuit 50 is operating, the control signal OC1 is set to “Hi”, the control signal OC2 is set to “Lo”, and the scan IC 55 is set to the “All-Lo” state. To. As a result, the switching elements QH1 to QHn are turned off, the switching elements QL1 to QLn are turned on, and all the output terminals of the scan IC 55 are electrically connected to the input terminal INa, and the switching elements QL1 to QLn. The initialization waveform or the sustain pulse can be applied to each of scan electrode SC1 through scan electrode SCn via.

  When both the control signal OC1 and the control signal OC2 are “Lo”, the scan IC 55 is in a “high impedance” (hereinafter referred to as “HiZ”) state. In this "HiZ" state, the output voltage at the time when the scan IC 55 is in the "HiZ" state is held and output from each output terminal of the scan IC 55 as it is.

  When the control signal OC1 is “Lo” and the control signal OC2 is “Hi”, the scan IC 55 is in the “DATA” state, that is, a series of operations determined in advance based on the scan start signal SID input to the scan IC 55. It will be in the state to perform.

  Specifically, when the scan IC 55 is in the “DATA” state, the scan start signal SID is input to the scan IC 55 (in this embodiment, the scan start signal SID changes from “Hi” to “Lo”). Thus, the scan IC 55 performs the following operation. First, only the first output terminal of the scan IC 55 is electrically connected to the input terminal INa on the low voltage side, and all the remaining output terminals are electrically connected to the input terminal INb on the high voltage side. After the state continues for a predetermined time (for example, 1 μsec), only the second output terminal of the scan IC 55 is then electrically connected to the low voltage side input terminal INa, and all the remaining output terminals are high. It is electrically connected to the voltage side input terminal INb. Then, after the state is continued for a predetermined time, only the third output terminal of the scan IC 55 is electrically connected to the low voltage side input terminal INa. In this manner, each output terminal of the scan IC 55 is electrically connected to the low voltage side input terminal INa in order for a predetermined time. In the address period, by setting the scan IC 55 to this operation state, it is possible to sequentially generate the scan pulse voltage Va from each output terminal of the scan IC 55 and to scan the scan electrodes SC1 to SCn.

  In the present embodiment, only the scanning start signal SID (1) used for the scanning IC (1) that performs scanning at the beginning of the address period is generated by the timing generation circuit 45, and the remaining scanning start signals, that is, scanning Each scan start signal from the scan start signal SID (2) used for the IC (2) to the scan start signal SID (12) used for the scan IC (12) is generated by each scan IC 55.

  For example, the scan IC (1) delays the scan start signal SID (1) for a predetermined time using a shift register or the like after the scan to all the scan electrodes 22 connected to the scan IC (1) is completed. The created scan start signal SID (2) is output and supplied to the next scan IC (2). Similarly, the scan IC (2) supplies the scan start signal SID (3) created by delaying the scan start signal SID (2) for a predetermined time to the next-stage scan IC (3). Similarly, each scan IC 55 creates a new scan start signal SID (i + 1) by delaying the input scan start signal SID (i) for a predetermined time, and supplies it to the next-stage scan IC 55. With this configuration, it is not necessary to generate the scanning start signal SID (2) to the scanning start signal SID (12) by the timing generation circuit 45, and the timing generation circuit 45 and the scan electrode drive circuit 43 are connected. The number of wiring lines for control signals can be reduced.

  Further, as shown in FIG. 4, the comparator CP1 that outputs the control signal OC2 compares the voltage (Va + Vset2) with the reference potential A when the switching element SW1 is on and the switching element SW2 and the switching element SW3 are off. When the switching element SW2 is on and the switching element SW1 and the switching element SW3 are off, the voltage (Va + Vset3) is compared with the reference potential A. When the switching element SW3 is on and the switching element SW1 and the switching element SW2 are off, the voltage (Va + Vset4) ) And the reference potential A. If the reference potential A is higher, “Lo” is output, otherwise “Hi” is output and supplied to the scan ICs (1) to (12).

  In the scan IC 55, the lowest voltage of the falling ramp waveform voltage is switched by a plurality of voltages having different voltage values by the control signal OC2. It is assumed that the switching elements SW1 to SW3 are turned on / off by the timing generation circuit 45.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described with reference to FIG. Note that the plasma display device in this embodiment is a subfield method, that is, one field period is divided into a plurality of subfields on the time axis, luminance weights are set for each subfield, and each discharge is performed for each subfield. It is assumed that gradation display is performed by controlling light emission / non-light emission of the cell.

  In this subfield method, for example, one field is composed of eight subfields (first SF, second SF,..., Eighth SF), and each subfield is (1, 2, 4, 8, 16, 32). , 64, 128). Further, among the plurality of subfields, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed in the initializing period of one subfield, and the immediately preceding period is set in the initializing period of the other subfield. By performing selective initializing operation that selectively generates initializing discharge for discharge cells that have undergone sustain discharge in the subfield, it is possible to reduce light emission not related to gradation display as much as possible and improve the contrast ratio. is there.

  In the present embodiment, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the eighth SF. As a result, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation in the first SF, and the black luminance that is the luminance of the black display area that does not generate the sustain discharge is weak in the all-cell initialization operation. Only the emission of light makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  In the present invention, the number of subfields and the luminance weight of each subfield are not limited to the above values as in the present embodiment, and the subfield configuration is switched based on an image signal or the like. It may be.

  FIG. 7 is a waveform diagram of drive voltage applied to each electrode of panel 10 in one embodiment of the present invention.

  In FIG. 7, scan electrode SC1 that performs scanning first in the address period, scan electrode SCn that scans last in the address period (for example, scan electrode SC1080), sustain electrode SU1 to sustain electrode SUn, and data electrode D1 ~ Shows drive waveforms of the data electrode Dm.

  FIG. 7 also shows drive voltage waveforms of two subfields, that is, a first subfield (first SF) of a subfield (referred to as “all-cell initialization subfield”) that performs an all-cell initialization operation, A second subfield (second SF) of a subfield (referred to as “selective initialization subfield”) for performing a selective initialization operation is shown. The drive voltage waveform in the other subfields is substantially the same as the drive voltage waveform of the second SF except that the number of sustain pulses in the sustain period is different. Further, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the respective electrodes based on image data.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to each of the data electrode D1 to the data electrode Dm, the sustain electrode SU1 to the sustain electrode SUn, and the scan electrode SC1 to the scan electrode SCn starts from 0 (V). A voltage Vi1 equal to or lower than the discharge start voltage is applied to sustain electrode SU1 through sustain electrode SUn, and a ramp waveform voltage (hereinafter referred to as an “up-ramp waveform”) gradually rising from voltage Vi1 toward voltage Vi2 exceeding the discharge start voltage. L1 is applied.

  While the rising ramp waveform L1 rises, between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm. Each weak initializing discharge occurs continuously. Negative wall voltage is accumulated above scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated above data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, 0 (V) is applied to data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn. Down-slope waveform voltage (hereinafter referred to as “down-ramp waveform”) that gently falls from sustain voltage SU1 to sustain electrode SUn to a negative voltage exceeding the discharge start voltage from voltage Vi3 that is equal to or lower than the discharge start voltage. ) Apply L2. In the present embodiment, the lowest voltage in the down-ramp waveform L2 is the voltage (Va + Vset2).

  During this time, weak initialization discharges occur between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm, respectively. . Then, the negative wall voltage above scan electrode SC1 through scan electrode SCn and the positive wall voltage above sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage above data electrode D1 through data electrode Dm is used for the write operation. It is adjusted to a suitable value. Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  In the subsequent address period, a scan pulse voltage is sequentially applied to scan electrode SC1 through scan electrode SCn, and data electrode Dk (k = 1) corresponding to a discharge cell to emit light is applied to data electrode D1 through data electrode Dm. To m), a positive address pulse voltage Vd is applied to selectively generate an address discharge in each discharge cell.

  In this address period, voltage Ve2 is first applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc (Vc = Va + Vscn) is applied to scan electrode SC1 through scan electrode SCn.

  The negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. A positive write pulse voltage Vd is applied to. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. Since voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (Ve2-Va) and sustain electrode SU1. The difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this way, an address operation is performed in which an address discharge is caused in the discharge cell to emit light in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of data electrode D1 to data electrode Dm to which scan pulse SC1 is not applied with address pulse voltage Vd does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission.

  In this sustain period, first, positive sustain pulse voltage Vs is applied to scan electrode SC1 through scan electrode SCn, and a ground potential serving as a base potential, that is, 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as the base potential is applied to scan electrode SC1 through scan electrode SCn, and sustain pulse voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, thereby giving a potential difference between the electrodes of display electrode pair 24. As a result, the sustain discharge is continuously performed in the discharge cells that have caused the address discharge in the address period.

  At the end of the sustain period, after the sustain electrode SU1 to the sustain electrode SUn are returned to 0 (V), the ramp waveform voltage increases from 0 (V), which is the base potential, toward the voltage Vers exceeding the discharge start voltage. L3 (hereinafter referred to as “erasing ramp waveform”) is applied to scan electrode SC1 through scan electrode SCn. Then, a weak discharge (hereinafter referred to as “erase discharge”) occurs between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. The charged particles generated by the erasing discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to alleviate the voltage difference between the sustain electrode SUi and the scan electrode SCi. Thus, the wall voltage on the scan electrode SCi and the sustain electrode SUi remains the difference between the voltage applied to the scan electrode SCi and the discharge start voltage, that is, (voltage Vers−discharge) while leaving the positive wall charge on the data electrode Dk. It is weakened to the extent of the starting voltage.

  Thereafter, scan electrode SC1 to scan electrode SCn are returned to 0 (V), and the sustain operation in the sustain period is completed.

  In the initialization period of the second SF, a drive voltage waveform in which the first half of the initialization period of the first SF is omitted is applied to each electrode. That is, voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm, respectively, and voltage that is equal to or less than the discharge start voltage (for example, 0) is applied to scan electrode SC1 through scan electrode SCn. (V)) is applied to the ramp-down waveform L4 that gently falls toward the negative voltage Vi4.

  As a result, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has occurred in the sustain period of the immediately preceding subfield (first SF in FIG. 7), and the wall voltage on the scan electrode SCi and on the sustain electrode SUi is weakened. The wall voltage above the data electrode Dk (k = 1 to m) is also adjusted to a value suitable for the write operation. On the other hand, discharge cells in which no sustain discharge has occurred in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. As described above, the initializing operation in the second SF is a selective initializing operation in which the initializing discharge is performed on the discharge cells in which the sustain operation has been performed in the sustain period of the immediately preceding subfield.

  FIG. 7 shows an example in which the lowest voltage Vi4 in the down-ramp waveform L4 is the voltage (Va + Vset4). However, in this embodiment, the voltage value of the lowest voltage Vi4 in the down-ramp waveform L4 is variable. The configuration is changed in accordance with the lighting rate of the immediately preceding subfield.

  In the address period of the second SF, a drive waveform similar to that in the address period of the first SF is applied to scan electrode SC1 through scan electrode SCn, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm.

  In the sustain period of the second SF, similarly to the sustain period of the first SF, a predetermined number of sustain pulses are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. As a result, a sustain discharge is generated in the discharge cells that have generated the address discharge in the address period.

  In the subfields after the third SF, scan electrode SC1 to scan electrode SCn, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm differ from the second SF except for the number of sustain pulses in the sustain period. A similar drive waveform is applied.

  The above is the outline of the driving voltage waveform applied to each electrode of the panel 10.

  Next, the relationship between the lowest voltage Vi4 of the down ramp waveform and the lighting rate in the present embodiment will be described.

  FIG. 8 is a diagram illustrating an example of the relationship between the lowest voltage Vi4 of the down-ramp waveform and the lighting rate of the immediately preceding subfield in the embodiment of the present invention. In FIG. 8A, the minimum voltage Vi4 is variable when one field is composed of eight subfields, the first SF is an all-cell initializing subfield, and the remaining is a selective initializing subfield. FIG. 8B shows a configuration example when the detection value of the lighting rate in the immediately preceding subfield is divided into three ranges.

  In the present embodiment, as shown in FIG. 8A, the minimum voltage Vi4 of the down-ramp waveform L4 in the selection initialization subfield (second SF to eighth SF) is made variable, and according to the lighting rate of the immediately preceding subfield. Thus, the voltage is switched to one of three different voltage values, for example, voltage (Va + Vset2), voltage (Va + Vset3), and voltage (Va + Vset4).

  Then, as shown in FIG. 8B, the lighting rate of the immediately preceding subfield is divided into, for example, three ranges of less than 40%, 40% or more and less than 70%, and 70% or more. If the lighting rate is 70% or more, the lowest voltage Vi4 of the down-ramp waveform L4 is set to the voltage (Va + Vset4) (for example, Vset4 = 10 (V)) in the current subfield to generate the down-ramp waveform L4. If the lighting rate of the immediately preceding subfield is 40% or more and less than 70%, the lowest voltage Vi4 is set to a voltage (Va + Vset3) lower than the voltage (Va + Vset4) in the current subfield (for example, Vset3 = 8 (V)). In this way, the down-ramp waveform L4 is generated. If the lighting rate of the immediately preceding subfield is less than 40%, the lowest voltage Vi4 is set to a voltage (Va + Vset2) lower than the voltage (Va + Vset3) (for example, Vset2 = 6 (V)) in the current subfield. A down-ramp waveform L4 is generated.

  Thus, in this embodiment, in the selected initialization subfield, the minimum voltage Vi4 of the down-ramp waveform L4 of the current subfield is changed according to the lighting rate of the immediately preceding subfield. As a result, stable address discharge is realized in the present embodiment, which is due to the following reason.

  In the present embodiment, the minimum voltage Vi4 is changed for the purpose of changing the duration of the voltage drop in the down-ramp waveform L4. For this reason, the slope of the down-ramp waveform L4 is kept constant (for example, −1.3 V / μsec) regardless of the change in the minimum voltage Vi4, but the variation in the slope that occurs with the change in the minimum voltage Vi4 is allowed. Shall be.

  FIG. 9 is a diagram schematically showing the relationship between the lighting rate and the initializing discharge in one embodiment of the present invention. FIG. 9 shows schematic waveforms of the sustain pulse, erase ramp waveform L3, and down ramp waveform L4 applied to scan electrode SC1 through scan electrode SCn, and the outline of the light emission waveform at that time, when the lighting rate is high In order to compare and show the difference between when the lighting rate is low, the upper diagram of FIG. 9 shows the schematic waveforms when the lighting rate is high, and the lower diagram shows the schematic waveforms when the lighting rate is low. ing.

  There is a relationship between the discharge rate of the discharge cells and the discharge intensity of the sustain discharge. For example, when the lighting rate is high, the discharge intensity of the sustain discharge is relatively weak as shown in the upper diagram of FIG. When the lighting rate was low, it was confirmed that the discharge intensity of the sustain discharge was relatively strong as shown in the lower diagram of FIG. This is because the driving load of the panel 10 as viewed from the driving circuit varies depending on the combination of lighting / non-lighting of the discharge cells, and the lighting rate is increased due to the rising slope of the sustain pulse, the waveform distortion of the rising waveform, the ultimate potential of the sustain pulse, etc. This is considered to be due to a difference depending on the situation.

  On the other hand, in the sustain operation, it was confirmed that a weak discharge (hereinafter referred to as “self-erasing discharge”) may occur at the falling edge of the sustain pulse. The self-erase discharge changes depending on the discharge intensity of the sustain pulse. When a strong discharge occurs at the rising edge of the sustain pulse, a relatively strong self-erase discharge occurs as shown in the lower diagram of FIG. It was confirmed that it occurred. Such a self-erasing discharge reduces the wall charge formed by the sustain discharge, and therefore, the wall charge necessary for the subsequent discharge may be insufficient. For example, if this self-erasing discharge occurs in the sustain pulse immediately before the erasing discharge, the wall charge necessary for the erasing discharge may be insufficient. If the wall charge necessary for the erasing discharge is insufficient, as shown in the lower diagram of FIG. 9, the timing at which the erasing discharge is generated in the erasing ramp waveform L3 is the case where the wall charges necessary for the erasing discharge are sufficiently high. Compared to

  If the timing at which the erase discharge occurs in the erase ramp waveform L3 is late, the erase discharge is not sufficiently performed. As a result, as shown in the lower diagram of FIG. Compared to the case of the above figure where the erasing discharge is performed, the operation is delayed. Then, when the timing at which the initializing discharge occurs in the down-ramp waveform L4 is delayed, the initializing operation ends with the duration of the initializing discharge being insufficient, that is, the wall charge adjustment time being insufficient.

  If the address period that continues with insufficient adjustment of the wall charge is started, it becomes difficult to stably generate the address discharge. Further, in a high-definition panel, the time spent for scanning becomes longer due to an increase in the number of scanning electrodes, so that there is a risk that the wall charge will be further insufficient in the discharge cells that are addressed toward the end of the address period. Address discharge tends to become more unstable.

  In order to stably generate the address discharge in such a case, the wall charge adjustment time, that is, the length of the initialization discharge duration in the down-ramp waveform L4 may be adjusted appropriately. For that purpose, the minimum voltage of the down-ramp waveform L4 should be made smaller and the time during which the voltage drop continues in the down-ramp waveform L4 should be extended.

  However, simply reducing the minimum voltage of the down-ramp waveform L4 has a relatively high lighting rate in the immediately preceding subfield as shown in the upper diagram of FIG. 9, and is initialized at a relatively early timing in the down-ramp waveform L4. In the case where discharge occurs, the duration of the initialization discharge is unnecessarily increased, which not only makes the wall charge adjustment excessive, but also causes an increase in power consumption, which is not desirable.

  Therefore, in the present embodiment, as described above, the minimum voltage Vi4 of the down-ramp waveform L4 of the current subfield is changed according to the lighting rate of the immediately preceding subfield. That is, when it is determined that the lighting rate of the immediately preceding subfield is low and the initializing discharge in the initializing period of the current subfield is determined to occur relatively late, compared to the case where the lighting rate of the immediately preceding subfield is high, The minimum voltage Vi4 of the down-ramp waveform L4 is reduced so that the time during which the voltage drop continues in the down-ramp waveform L4 is extended. This makes it possible to optimally control the duration of the initializing discharge in the initializing operation and to adjust the wall charge without excess or deficiency, so that the wall charge in the discharge cell can be brought into an appropriate state. Thus, the subsequent write operation can be generated stably.

  FIG. 10 is a characteristic diagram showing the relationship between the address pulse voltage Vd necessary for generating a stable address discharge and the lighting rate of the immediately preceding subfield in one embodiment of the present invention. In FIG. 10, the vertical axis represents the address pulse voltage Vd required to generate a stable address discharge, and the horizontal axis represents the lighting rate of the immediately preceding subfield. In FIG. 10, the characteristic indicated by the broken line is a measurement result when the minimum voltage Vi4 of the down-ramp waveform L4 is made constant at the voltage (Va + Vset4), and the characteristic indicated by the solid line is the minimum voltage Vi4 of the down-ramp waveform L4. Is a measurement result when is varied as shown in FIG. 8B according to the lighting rate of the immediately preceding subfield.

  Then, as shown in FIG. 10, by controlling the minimum voltage Vi4 of the down-ramp waveform L4 of the current subfield according to the lighting rate of the immediately preceding subfield, the address pulse necessary for generating a stable address discharge. It was confirmed that the voltage Vd can be reduced. In the measurement result shown in FIG. 10, for example, when the lighting rate of the immediately preceding subfield is 10%, the address pulse voltage Vd necessary for generating a stable address discharge in the current subfield is compared with the characteristic indicated by the broken line. About 5 (V).

  As described above, according to the present embodiment, the minimum voltage Vi4 of the down-ramp waveform L4 of the current subfield is changed according to the lighting rate of the immediately preceding subfield, so that initialization by the downramp L4 is performed. The wall charge in the discharge cell can be appropriately controlled by optimally controlling the discharge duration, and stable without increasing the address pulse voltage Vd required for generating the address discharge. An address discharge can be generated.

  In the present embodiment, in the first SF, which is the all-cell initialization subfield, an example in which the minimum voltage of the down-ramp waveform L2 is fixed instead of variable is described. In the field, since the initializing discharge is generated in all the discharge cells by the rising ramp waveform L1, it is necessary to consider the effect of the lighting rate of the immediately preceding subfield when the initializing discharge is generated by the downward ramp waveform L2. Because there is no. The minimum voltage in the down-ramp waveform L2 is the voltage (Va + Vset2). This is set to the smallest voltage value among the settable minimum voltages, so that the initial discharge of the first SF, that is, one field period. This is because the wall charge adjustment by the initializing discharge generated first is more reliably performed.

  The numerical values given here are merely examples, and the present invention is not limited to these numerical values. It is desirable that the minimum voltage Vi4 and the lighting rate threshold value be set to optimum values based on panel characteristics, plasma display device specifications, and the like.

  Next, the operation of the scan electrode driving circuit 43 and the generation of the down-ramp waveform will be described with reference to FIGS. First, the operation when generating the initialization waveform and the down-ramp waveform L2 in the all-cell initialization period will be described with reference to FIG. 11, and then the case of generating the down-ramp waveform L4 with reference to FIGS. The operation of will be described.

  In FIGS. 11 to 13, it is assumed that the voltage Vi1 and the voltage Vi3 are equal to the voltage Vs, and the voltage Vi2 is equal to the voltage Vr.

  FIG. 11 is a timing chart for explaining an example of the operation of scan electrode driving circuit 43 in the all-cell initializing period in one embodiment of the present invention. Here, the drive voltage waveform for performing the all-cell initialization operation is divided into four periods indicated by a period T1, a period T2, a period T3, and a period T41, and each period will be described.

(Period T1)
First, the power recovery circuit of sustain pulse generating circuit 50 is operated to increase the voltage of scan electrode SC1 through scan electrode SCn. Thereafter, the clamp circuit of sustain pulse generation circuit 50 is operated to set the potential of scan electrode SC1 to scan electrode SCn to voltage Vs (equal to voltage Vi1 in the present embodiment).

(Period T2)
Next, the input terminal IN1 of the Miller integrating circuit 53 that generates the up-ramp waveform is set to “Hi”. Specifically, a predetermined constant current is input to the input terminal IN1. Then, a constant current flows from the resistor R1 toward the capacitor C1, the source voltage of the switching element Q1 rises in a ramp shape, and the output voltage of the scan electrode drive circuit 43 also starts to rise in a ramp shape. This voltage increase continues while the input terminal IN1 is “Hi”.

  When this output voltage rises to the voltage Vr (equal to the voltage Vi2 in this embodiment), the input terminal IN1 is then set to “Lo”. Specifically, for example, 0 (V) is applied to the input terminal IN1.

  In this manner, the voltage Vs (equal to the voltage Vi1 in the present embodiment) which is equal to or lower than the discharge start voltage gradually decreases toward the voltage Vr (equal to the voltage Vi2 in the present embodiment) exceeding the discharge start voltage. Is applied to scan electrode SC1 through scan electrode SCn.

(Period T3)
When the input terminal IN1 is set to “Lo”, the voltage of scan electrode SC1 through scan electrode SCn decreases to voltage Vs (equal to voltage Vi3 in this embodiment).

(Period T41)
Next, the input terminal IN2 of the Miller integrating circuit 54 for generating the down-ramp waveform voltage is set to “Hi”. Specifically, a predetermined constant current is input to the input terminal IN2. Then, a constant current flows from the resistor R2 toward the capacitor C2, the drain voltage of the switching element Q2 falls in a ramp shape, and the output voltage of the scan electrode drive circuit 43 also starts to fall in a ramp shape.

  When generating the down-ramp waveform L2, the comparator CP1 generates the reference potential A, that is, the down-ramp waveform output from the initialization waveform generation circuit 51, and the voltage (Va + Vset2) obtained by adding the voltage Vset2 to the voltage Va. The comparison result is used as the control signal OC2. Therefore, in the period T41, the switching element SW1 is turned on, and the switching element SW2 and the switching element SW3 are turned off. As a result, the output signal from the comparator CP1, that is, the control signal OC2, is switched from “Lo” to “Hi” at time t41 when the down-ramp waveform at the reference potential A becomes equal to or lower than the voltage (Va + Vset2).

  Therefore, at time t41, both the control signal OC1 and the control signal OC2 are “Hi”, and the scan IC 55 is in the “All-Hi” state. That is, the output voltage from the scan IC 55 is the voltage input to the input terminal INb (in the configuration shown in FIG. 4, the voltage Vscn is superimposed on the reference potential A), and the voltage drop up to that time is at time t41. Switch to voltage rise. As a result, the descending ramp waveform applied to scan electrode SC1 through scan electrode SCn becomes the descending ramp waveform L2 having the lowest voltage (Va + Vset2).

  Then, immediately before the initialization period ends, for example, 0 (V) is applied to the input terminal IN2, and the input terminal IN2 is set to “Lo”.

  As described above, scan electrode driving circuit 43 rises gradually with respect to scan electrode SC1 through scan electrode SCn from voltage Vi1 that is equal to or lower than the discharge start voltage toward voltage Vi2 that exceeds the discharge start voltage. And then, a downward ramp waveform L2 that gently falls from voltage Vi3 toward voltage (Va + Vset2) can be generated and applied to scan electrode SC1 through scan electrode SCn.

  Next, the operation for generating the down-ramp waveform L4 will be described with reference to FIG. FIG. 12 is a timing chart for explaining an example of the operation of scan electrode drive circuit 43 in the selective initialization period according to one embodiment of the present invention, and sets ramp-down waveform L4 to minimum voltage Vi4 as voltage (Va + Vset3). 6 is a timing chart for explaining an operation when generating the error.

(Maintenance period)
Although details are omitted, the power recovery circuit and the clamp circuit of the sustain pulse generation circuit 50 are alternately operated to generate a predetermined number of sustain pulses. Then, at the end of the sustain period, the erase ramp waveform L3 is generated. Thus, the maintenance period ends.

(Initialization period)
In the subsequent initialization period T42, the input terminal IN2 of the Miller integrating circuit 54 that generates the down-ramp waveform voltage is set to “Hi”. As a result, the output voltage of the scan electrode driving circuit 43 starts to drop in a ramp shape.

  When the lowest voltage Vi4 is set to the voltage (Va + Vset3) to generate the down-ramp waveform L4, the comparator CP1 makes a comparison between the down-ramp waveform at the reference potential A and the voltage (Va + Vset3), and controls the comparison result. Used as signal OC2. Therefore, in the period T42, the switching element SW2 is turned on, and the switching elements SW1 and SW3 are turned off. As a result, the output signal from the comparator CP1, that is, the control signal OC2, is switched from “Lo” to “Hi” at time t42 when the down-ramp waveform at the reference potential A becomes equal to or lower than the voltage (Va + Vset3).

  Therefore, at time t42, both the control signal OC1 and the control signal OC2 are set to “Hi”, and the scan IC 55 is set to the “All-Hi” state. That is, the output voltage from the scan IC 55 is the voltage input to the input terminal INb (the voltage obtained by superimposing the voltage Vscn on the reference potential A), and the voltage drop up to that time is switched to the voltage rise at time t42. The down-ramp waveform applied to electrode SC1 through scan electrode SCn is a down-ramp waveform L4 with the lowest voltage Vi4 being the voltage (Va + Vset3).

  FIG. 13 is a timing chart for explaining another example of the operation of scan electrode drive circuit 43 in the selective initialization period according to the embodiment of the present invention. The minimum voltage Vi4 is set to voltage (Va + Vset4), and the down ramp is performed. It is a timing chart explaining operation when generating waveform L4. Note that the operation in the sustain period is the same as that in FIG.

(Initialization period)
In the period T43, similarly to the period T42, the input terminal IN2 of the Miller integrating circuit 54 that generates the down-ramp waveform voltage is set to “Hi”. As a result, the output voltage of the scan electrode driving circuit 43 starts to drop in a ramp shape.

  Note that when the lowest voltage Vi4 is set to the voltage (Va + Vset4) to generate the downward ramp waveform L4, the comparator CP1 compares the downward ramp waveform at the reference potential A with the voltage (Va + Vset4). Therefore, in the period T43, the switching element SW3 is turned on, and the switching elements SW1 and SW2 are turned off. As a result, the output signal from the comparator CP1, that is, the control signal OC2, is switched from “Lo” to “Hi” at time t43 when the down-ramp waveform at the reference potential A becomes equal to or lower than the voltage (Va + Vset4).

  Therefore, at time t43, the control signal OC1 and the control signal OC2 are both “Hi”, and the scan IC 55 is in the “All-Hi” state. That is, the down-ramp waveform output from the scan IC 55 is a down-ramp waveform L4 in which the voltage drop is switched to a voltage rise at time t43 and the minimum voltage Vi4 becomes the voltage (Va + Vset4).

  Although not described with reference to the drawings, the switching element SW1 is turned on and the switching elements SW2 and SW3 are turned off in the selective initialization period, so that the comparator CP1 has a down ramp at the reference potential A. The waveform can be compared with the voltage (Va + Vset2). As a result, when the down-ramp waveform at the reference potential A becomes equal to or lower than the voltage (Va + Vset2), both the control signal OC1 and the control signal OC2 can be set to “Hi”. Therefore, the lowering with the lowest voltage Vi4 set to the voltage (Va + Vset2). The ramp waveform L4 can be output from the scan IC 55.

  As described above, in the present embodiment, by changing the minimum voltage Vi4 of the down-ramp waveform L4 of the current subfield according to the lighting rate of the immediately preceding subfield, the initialization discharge by the down-ramp L4 is performed. Since the wall charge in the discharge cell can be appropriately controlled by optimally controlling the duration, the address pulse voltage Vd necessary for generating a stable address discharge can be reduced, and the stable A write operation can be performed.

  In the present embodiment, the down-ramp waveform L2 and the down-ramp waveform L4 are shown as waveform shapes that immediately switch to voltage increase after the voltage of the down-ramp waveform reaches the lowest voltage. However, this is merely such a waveform shape in the circuit configuration of the scan electrode drive circuit 43, and the present embodiment is not limited to this waveform shape. For example, the waveform shape may be such that after the voltage of the down-ramp waveform reaches the minimum voltage, the voltage is held for a certain period.

  In this embodiment, the voltage Vset2 is set to 6 (V), the voltage Vset3 is set to 8 (V), and the voltage Vset4 is set to 10 (V). However, these numerical values are merely examples, and the characteristics of the panel And an optimum voltage value may be set according to the specifications of the plasma display device.

  Further, the timing charts shown in FIG. 11 to FIG. 13 are merely examples in the embodiment, and are not limited to these timing charts.

  In the present embodiment, a configuration has been described in which the minimum voltage Vi4 of the down-ramp waveform L4 is switched between three different voltage values of voltage (Va + Vset2), voltage (Va + Vset3), and voltage (Va + Vset4) in the selective initialization period. However, the present invention is not limited to this configuration. For example, voltage values such as voltage (Va + Vset5) and voltage (Va + Vset6) may be provided, and the lighting rate may be divided into four or more regions to further control the minimum voltage Vi4 of the down-ramp waveform L4. .

  It should be noted that the specific numerical values such as the threshold of the lighting rate, the minimum voltage of the down ramp waveform, the number of subfields, and the address pulse voltage shown in the present embodiment are merely examples, and the present invention is not limited to these numerical values. It is not limited to.

  As another example of the embodiment of the present invention, when determining the subfield for changing the minimum voltage of the down ramp waveform, the voltage value of the minimum voltage of the down ramp waveform, the threshold value of the lighting rate, or the like. Alternatively, the weighting may be performed using a predetermined condition. As an example of this weighting, for example, it is conceivable to detect the temperature distribution of the panel and reflect the detection result.

  In the embodiment of the present invention, the scan electrode and the scan electrode are adjacent to each other, and the sustain electrode and the sustain electrode are adjacent to each other. , Scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,... ”Is also effective in a panel having an electrode structure (referred to as“ ABBA electrode structure ”).

  The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel of 50 inches and 1080 pairs of display electrodes, and are shown as an example in the embodiment. Not too much. The present invention is not limited to these numerical values, and is desirably set optimally according to the characteristics of the panel, the specifications of the plasma display device, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. In addition, the polarity of each control signal shown when explaining the operation of the scan IC 55 is merely an example, and may be a polarity opposite to the polarity shown in the description.

  In the embodiment of the present invention, the configuration in which the erase ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn has been described. However, the erase ramp waveform voltage is applied to sustain electrode SU1 through sustain electrode SUn. You can also. Alternatively, an erasing discharge may be generated not by an erasing ramp waveform voltage but by a so-called narrow erasing pulse.

  In the present invention, since the wall charge can be adjusted appropriately by controlling the initializing discharge according to the lighting state of the discharge cell, the address pulse voltage necessary for generating the address discharge is not increased. This makes it possible to generate a stable address discharge and is useful as a driving method for a plasma display device and a panel.

The disassembled perspective view which shows the structure of the panel in one embodiment of this invention. Electrode arrangement of the panel The circuit block diagram of the plasma display apparatus in one embodiment of the present invention 1 is a circuit diagram of a scan electrode driving circuit according to an embodiment of the present invention. Schematic diagram showing a state of connection between a scan IC and a scan electrode of a scan electrode driving circuit in an embodiment of the present invention The figure which shows the correspondence of control signal OC1, control signal OC2, and the operation state of scan IC in one embodiment of this invention Drive voltage waveform diagram applied to each electrode of panel in one embodiment of the present invention The figure which shows an example of the relationship between the lowest voltage of the down-ramp waveform in one embodiment of this invention, and the lighting rate of the last subfield. The figure which shows schematically the relationship between the lighting rate and initialization discharge in one embodiment of this invention The characteristic view which shows the relationship between the address pulse voltage required in order to generate the stable address discharge in one embodiment of this invention, and the lighting rate of the last subfield 4 is a timing chart for explaining an example of the operation of the scan electrode driving circuit during the all-cell initialization period in one embodiment of the present invention. 4 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the selective initialization period according to an embodiment of the present invention. 4 is a timing chart for explaining another example of the operation of the scan electrode driving circuit in the selective initialization period in one embodiment of the present invention.

Explanation of symbols

1 Plasma display device 10 Panel (Plasma display panel)
21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 47 Lighting rate detection circuit 48 Memory 50 Sustain pulse generation circuit 51 Initialization waveform generation circuit 52 Scan pulse generation circuit 53, 54 Miller integration circuit 55 Scan IC
CP1 Comparator C1, C2, C31 Capacitor SW1, SW2, SW3, Q1, Q2, Q4, Q5, QH1 to QHn, QL1 to QLn Switching element R1, R2 Resistor D31 Diode

Claims (4)

A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode;
A plurality of subfields each having an initialization period, an address period, and a sustain period, and a scan electrode driving circuit that generates a falling ramp waveform voltage that falls in the initialization period and applies the same to the scan electrode; ,
A lighting rate detection circuit that detects a ratio of discharge cells to be lit to all discharge cells of the plasma display panel as a lighting rate for each subfield;
The scan electrode driving circuit includes:
A plasma display device characterized in that a minimum voltage of the descending ramp waveform voltage generated in the initialization period of a current subfield is changed according to a lighting rate of a subfield immediately before detected by the lighting rate detection circuit. . The scan electrode driving circuit is within one field period,
An initializing discharge is generated only in a subfield that performs an all-cell initializing operation for generating an initializing discharge in all the discharge cells of the plasma display panel and in a discharge cell that has generated an address discharge in the address period of the immediately preceding subfield. A subfield for performing a selective initialization operation,
The plasma display apparatus according to claim 1, wherein, in the subfield performing the all-cell initializing operation, the lowest voltage of the downward ramp waveform voltage is made constant regardless of the lighting rate of the immediately preceding subfield. . A plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode,
A plasma display panel in which a plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field period, and a descending ramp waveform voltage that falls in the initialization period is generated and applied to the scan electrode. Driving method,
The ratio of discharge cells to be lit with respect to all discharge cells of the plasma display panel is detected as a lighting rate for each subfield, and the lowest voltage of the downward ramp waveform voltage generated in the initialization period of the current subfield is determined immediately before. A method for driving a plasma display panel, wherein the method is changed according to the lighting rate of the subfield. Only in a subfield that performs an all-cell initializing operation for generating an initializing discharge in all the discharge cells of the plasma display panel within one field period, and in a discharge cell that has generated an address discharge in the addressing period of the immediately preceding subfield. A subfield for performing a selective initializing operation for generating an initializing discharge;
4. The plasma display panel according to claim 3, wherein, in the subfield performing the all-cell initialization operation, the lowest voltage of the downward ramp waveform voltage is made constant regardless of the lighting rate of the immediately preceding subfield. Driving method.

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