JP2009231456A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the occurrence of leak current of a first MIS transistor and a second MIS transistor cannot be prevented because of reduction in the film of inclination parts of an element isolation film surrounding an element region, in a semiconductor device which includes the first MIS transistor equipped with a first gate insulating film and the second MIS transistor equipped with a second gate insulating film in the same element region. <P>SOLUTION: The semiconductor device has a structure in which the first gate insulating film, the second gate insulating film or an upper insulating film of a thickness different from that of the insulating films are arranged on the top of the inclination parts of the element isolation film. By this structure, the film of the inclination parts of the element isolation film is not reduced and the occurrence of leak current can be prevented. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which MIS (Metal Insulator Semiconductor) transistors having different operation functions are provided in the same element region.

In recent semiconductor devices, MIS type transistors having different operation functions are mixedly mounted in the same element region of a semiconductor substrate, so that a complex operation is possible and high added value is obtained. For example, a memory transistor and an address transistor that controls the operation of the memory transistor are formed in the same element region.
In addition, a transistor for controlling data writing to the memory transistor needs to be a high voltage transistor with a driving voltage of 5V or 30V. Such a high breakdown voltage transistor and a normal transistor are mounted together.
The address transistor has the same element structure as a transistor (logic transistor) constituting a normal logic.

Since the memory transistor and the address transistor have different electrical operations, a gate insulating film corresponding to the electrical operation is necessary.
The gate insulating film of the memory transistor has a laminated film structure in which a plurality of insulating films including an insulating film having a function of accumulating charges are transferred between the gate electrode and the semiconductor substrate. The gate insulating film of the address transistor does not transfer charges between the gate electrode and the semiconductor substrate, that is, does not transfer charges.

  Further, when a high breakdown voltage transistor is mounted together, the high breakdown voltage transistor is constituted by a gate insulating film thicker than the gate insulating film of the address transistor and adopts a structure that can withstand a high gate electric field.

On the other hand, when a semiconductor circuit is formed on a semiconductor substrate, an element isolation film provided for partitioning or defining an element region is an indispensable element for a semiconductor device. Conventionally, a selective oxide film has been widely used for forming an element isolation region. A selective oxide film is an element isolation film obtained by a method in which an oxidation-resistant thin film such as a silicon nitride film is provided at a portion corresponding to an element region formed on a semiconductor substrate, and the oxide film is partially formed by thermal oxidation. It is.
Since this selective oxide film employs a silicon oxide film, there are advantages of high electrical and mechanical reliability and a simple manufacturing method.

  In a semiconductor device in which a memory transistor, an address transistor, and a high breakdown voltage transistor are combined and mounted as described above, a problem is a leakage current generated at the boundary between the element isolation region and the element region defined by the element isolation film. Is the occurrence of

  In a MIS transistor used in a semiconductor device, a gate insulating film corresponding to a gate width of, for example, 350 nm or less used for an address transistor is about 8 nm. However, when a memory transistor or a high breakdown voltage transistor is mixedly mounted, It is necessary to provide a gate insulating film suitable for each element depending on the element.

For example, in the case of a MONOS type memory transistor, a cumulative film having a tunnel film thickness of 2 nm, a charge storage layer nitride film of 10 nm, and an upper oxide film thickness of about 3 nm in this order from the semiconductor substrate side.
In the case of a high withstand voltage transistor having a withstand voltage of 5V, the gate insulating film thickness is 20 nm, and in the case of a high withstand voltage transistor having a withstand voltage of 30V, the gate insulating film thickness is 80 nm. It becomes.

  In order to form the plurality of gate insulating films, the gate insulating films are sequentially formed for each element to be mounted. For example, when a memory transistor and an address transistor are mixedly mounted, a first gate insulating film for the memory transistor is formed, and then a second gate insulating film for the address transistor is formed.

  Specifically, an element region in which a memory transistor and an address transistor are provided is formed, and a first gate insulating film is formed on the entire upper surface thereof. Thereafter, the first insulating film on the upper portion of the memory transistor region is not etched, and the first gate insulating film on the address transistor region is removed by etching, and an insulating film such as a thermal oxide film is formed on the etched region. A film is provided and this is used as a second gate insulating film.

At this time, the element isolation film is also etched and retracted simultaneously, the inclined portion of the element region is expanded, the lower surface of the end of the element isolation film is exposed, and the element region has a convex shape. When the gate insulating film or the gate electrode is in contact with the exposed end portion, the leakage of the memory transistor region or the address transistor region increases.
In order to avoid such a leakage problem, various countermeasures have been proposed (for example, see Patent Document 1).

  The prior art shown in Patent Document 1 will be described. FIG. 11 is a cross-sectional view of a conventional MIS transistor disclosed in Patent Document 1. In FIG. This figure has been rewritten for easy explanation without departing from the gist. Moreover, the same number is given about what has the same function.

In FIG. 11, 10 is a semiconductor substrate, 31 is a shallow trench isolation film, 33 is a first insulating film, 34 is a second insulating film, 35 is a boundary between the first insulating film and the second insulating film, Reference numeral 37 denotes a gate electrode. Reference numeral 38 denotes a source region, and 39 denotes a drain region. The diagram shown in FIG. 11 shows a state in which different insulating films are formed at the end portions of the element isolation film.
The first insulating film 33 side is a high breakdown voltage transistor region, and the second insulating film 34 side is a logic transistor region.

A surface of the semiconductor substrate 10 is provided with a shallow trench isolation film 31 using a trench isolation method, and a first insulating film 33 constituting a high breakdown voltage transistor having a thick gate insulating film in the element region of the semiconductor substrate 10; A second insulating film 34 constituting a logic transistor is provided.
Furthermore, a gate electrode 37 is provided on the top surfaces of the first insulating film 33 and the second insulating film 34, and a boundary 35 between the first insulating film 33 and the second insulating film 34 is provided inside the logic transistor region. It has been.

  The conventional technique shown in Patent Document 1 having such a structure prevents generation of gate leakage current in the high breakdown voltage transistor region even when MIS type transistor devices having different gate insulating films are mixedly mounted in the same element region. There is a feature that can be.

Japanese Patent Application Laid-Open No. 2000-200246 (Section 10, FIG. 7)

In the prior art disclosed in Patent Document 1, when the second insulating film 34 is provided, the first insulating film 33 is provided.
It has been found that the boundary 35 between the first and second insulating films 34 recedes, the generation of a junction leakage current in the logic transistor region cannot be prevented, and the memory transistor cannot be mounted together.

  Furthermore, the level difference at the boundary 35 between the first insulating film 33 and the second insulating film 34 causes an etching residue of the gate material in the logic transistor region, and the gate leakage current in the logic transistor region cannot be prevented. I understood it.

  By the way, when an insulating film is formed on a semiconductor substrate, the semiconductor substrate is subjected to a cleaning process in order to stabilize the electrical characteristics of the insulating film. The cleaning step is a step of cleaning the semiconductor surface using, for example, an aqueous solution of hydrofluoric acid, sulfuric acid, hydrochloric acid or the like.

  It is assumed that a general silicon oxide film is used for the conventional gate insulating film disclosed in Patent Document 1. At that time, if the above-described cleaning process (use of hydrofluoric acid aqueous solution) is performed for the purpose of removing the natural oxide film, the silicon oxide film is soluble in the hydrofluoric acid aqueous solution, and the natural oxide film is removed and the boundary 35 is formed. The film is retracted, and the end portion of the shallow trench isolation film 31 is reduced.

  That is, the prior art disclosed in Patent Document 1 can prevent the remaining etching of the gate material in the high breakdown voltage transistor region when the gate electrode 37 is provided, but the film loss at the end of the shallow trench isolation film 31 occurs in the element region. As a result, the lower surface of the edge of the device isolation film is exposed and the device region has a convex shape. When the gate insulating film or the gate electrode comes into contact with the exposed end portion, the leakage of the logic transistor region increases.

  In addition, when a memory transistor is mixedly mounted, the memory insulating film is etched by this hydrofluoric acid aqueous solution, causing a malfunction of the memory element.

  Further, in the logic transistor region, due to the step of the boundary 35, an etching residue is generated when the gate material is etched, so that a gate leakage current is generated and the electrical characteristics of the semiconductor device are deteriorated.

  The present invention has been made to solve the above-described problems, and provides a semiconductor device that prevents leakage of a transistor in a semiconductor device in which a memory transistor, a logic transistor, or a high voltage transistor is embedded. It is.

  In order to solve the above problems, the semiconductor device of the present invention employs the following configuration.

An element region is selectively provided on the surface of the semiconductor substrate, an element isolation film is provided on the surface of the semiconductor substrate so as to surround the element region with an inclined portion around the element region,
In a semiconductor device in which a first MIS transistor and a second MIS transistor are provided in an element region,
A first gate insulating film constituting the first MIS transistor or a second gate insulating film constituting the second MIS transistor is provided on the inclined portion.

  The first gate insulating film or the second gate insulating film is characterized in that the film thickness differs between the upper portion of the channel region and the upper portion of the inclined portion constituting each MIS transistor.

  A first gate insulating film or a second gate insulating film is provided above a source region or a drain region constituting each MIS transistor.

  The MIS transistors are arranged so that the gate electrodes constituting the first MIS transistors are opposed to each other, a region sandwiched between the gate electrodes is defined as a common region, and the common region is defined as the MIS transistor. A source region or a drain region is used.

  A boundary between the first gate insulating film and the second gate insulating film is provided above the common region.

The first MIS transistor is a memory transistor, and the first gate insulating film is a stacked film in which a plurality of insulating films including an insulating film having a role of accumulating charges are stacked.
The second MIS transistor is an address transistor that controls the first MIS transistor, and the second gate insulating film is a single layer film.

In the semiconductor device of the present invention, the first gate insulating film or the second gate insulating film constituting the MIS transistor is provided on the upper part of the inclined portion of the element isolation film around the element region. Thereby, even when MIS transistors having different operation functions are mixedly mounted, it is possible to suppress the film loss of the inclined portion around the element region in the manufacturing process.
Therefore, expansion and exposure of the end portion of the element region can be suppressed, and leakage of the logic transistor can be prevented.
In addition, since the electrical characteristics of the logic transistor are stabilized, the yield of the semiconductor device is also improved.

Hereinafter, a structure of a semiconductor device and a manufacturing method thereof in an optimum mode for carrying out the present invention will be described with reference to the drawings. In the following embodiments of the present invention, a case where a memory transistor and an address transistor that controls the memory transistor are mixedly mounted will be described as an example.
An example in which a MOS (Metal Oxide Semiconductor) transistor is used as the address transistor and a MONOS (Metal Oxide Semiconductor) memory transistor is used as the memory transistor will be described. Note that the MOS transistor is a MIS transistor that uses an oxide film as a gate insulating film.
An example in which the gate electrodes constituting each transistor are arranged so as to face each other, a region sandwiched between the gate electrodes is set as a common region, and the source region is used as the common region will be described.

  The structure will be described by taking as an example the case where an element region is provided in a silicon semiconductor substrate without using a well, an element isolation film is formed by a selective oxidation method, and a diffusion layer is formed by an ion implantation method. In the description of each drawing, the same number is assigned to the component having the same function.

[Description of Structure of First Embodiment of the Present Invention: FIG. 1]
The structure of the first embodiment of the semiconductor device of the present invention will be described with reference to FIG.
FIG. 1A is a plan view of the semiconductor device of the present invention. FIG. 1B is an end view taken along a cutting line AA ′ shown in FIG. In FIG. 1, 10 is a semiconductor substrate, and 11 is an element isolation film. An element region 9 is provided with a memory transistor and an address transistor. 3 is a first gate insulating film, and 4 is a second gate insulating film. 7 is a first gate electrode, and 8 is a second gate electrode. Reference numeral 22 denotes a common area, which is a source area. 21a and 21b are drain regions. Reference numeral 23 denotes an inclined portion of the element isolation film.

Reference numeral 70 denotes a first MIS type transistor, which is a MONOS type memory transistor. Reference numeral 80 denotes a second MIS type transistor, which is a MOS type address transistor.
The MONOS memory transistor 70 includes a first gate insulating film 3, a first gate electrode 7, a drain region 21 a, and a source region 22.
The MOS address transistor 80 includes a second gate insulating film 4, a second gate electrode 8, a drain region 21b, and a source region 22. Both of these transistors share the source region 22. The semiconductor substrate 10 below each gate electrode becomes a channel region.

  The first gate electrode 7 of the MONOS type memory transistor 70 and the second gate electrode 8 of the MOS type address transistor 80 are provided in parallel with each other with their gate length directions facing each other. A portion sandwiched between these two gate electrodes is a source region 22.

  In the semiconductor device of the present invention, an element isolation film 11 using a selective oxidation method is provided on a semiconductor substrate 10 as shown in FIG. A region where the element isolation film 11 is not provided becomes the element region 9. A boundary portion between the element region 9 and the element isolation film 11, that is, an upper portion of a so-called bird's beak is an inclined portion 23. Then, the first gate insulating film 3 is provided on the inclined portion 23.

In the semiconductor device of the present invention, by providing the first gate insulating film 3 on the upper portion of the inclined portion 23, the inclined portion 23 can be prevented from retreating due to the etching process in the manufacturing process.
As a result, the end of the element region 9 becomes convex or the end of the element region 9 is not exposed, and the first gate insulating film 3, the first gate electrode 7, or the second gate insulating film 4 is not exposed. In addition, the second gate electrode 8 does not come into contact with the exposed portion, and no leak current is generated from the element region 9.

As shown in FIG. 1A, the first gate insulating film 3 of the MONOS type memory transistor 70 is provided slightly larger than its channel region. That is, the first gate insulating film 3 extends the end of the first gate electrode 7 in the gate length direction (also referred to as the channel width direction) to a position covering the upper portion of the element isolation film 11, and the gate width An end portion in the direction (also referred to as a channel length direction) is provided extending from the end portion of the first gate electrode 7 in the direction of the source region 22 and the drain region 21a. And as already demonstrated, the 1st gate insulating film 3 is provided also in the upper part of the inclination part 23 in a channel width direction.
With such a configuration, the first gate electrode 7 is not in contact with the element region 9, so that no leak current is generated.

  Further, in the channel length direction, the allowance for overlaying the first gate insulating film 3 and the first gate electrode 7 is improved, and gate leakage current due to misalignment can be prevented.

  In the example described above, the configuration in which the first gate insulating film 3 of the MONOS type memory transistor 70 is provided above the inclined portion 23 has been described. However, instead of the first gate insulating film 3, the MOS address transistor 80 The second gate insulating film 4 may be used.

[Description of Structure of Second Embodiment of the Present Invention: FIG. 2]
Next, the structure of the second embodiment of the semiconductor device of the present invention will be described with reference to FIG.
FIG. 2A is a plan view of the semiconductor device of the present invention. FIG. 2B is an end view taken along the cutting line BB ′ shown in FIG. The same numbers are assigned to the same configurations already described.

  The difference between the configuration shown in FIG. 2 and the configuration shown in FIG. 1 is the structure of the upper part of the source region, the drain region, and the inclined portion 23.

  That is, the first gate insulating film 3 of the MONOS type memory transistor 70 shown in FIG. 2 extends in the gate length direction and the gate width direction, and has the same configuration as that shown in FIG. A second gate insulating film 4 is provided on the drain regions 21a and 21b and the source region 22 which is a common region. The second gate insulating film 4 is also provided on the upper portion of the inclined portion 23.

As shown in FIG. 2A, the first gate insulating film 3 and the second gate insulating film 4 have a boundary above the source region 22 and above the drain region 21a.
Further, as shown in FIG. 2B, the second gate insulating film 4 provided above the inclined portion 23 in the region of the MOS address transistor 80 and the second gate insulating film 4 provided above the drain region 21a; Are integrated with no boundaries.

  In the second embodiment of the present invention, the first gate insulating film 3 and the second gate insulating film 4 are described as having the same film thickness. As a result, as shown in FIG. 2B, both gate insulating films in the element region 9 have no step.

  In the semiconductor device according to the second embodiment of the present invention, the second gate insulating film 4 is provided on the upper portion of the inclined portion 23, and in the manufacturing process, as in the first embodiment, the inclined portion is formed by the etching process. 23 can be prevented from retreating, and no leak current is generated from the element region 9.

  Further, as in the configuration illustrated in FIG. 2, by making the film thicknesses of the first gate insulating film 3 and the second gate insulating film 4 the same, the step at the boundary is alleviated, and the first gate insulating film 3 is reduced. The etching residue at the time of etching the electrode 7 and the second gate electrode 8 can be suppressed.

[Description of Structure of Third Embodiment of the Present Invention: FIG. 3]
Next, the structure of the third embodiment of the semiconductor device of the present invention will be described with reference to FIG.
FIG. 3A is a plan view of the semiconductor device of the present invention. FIG. 3B is an end view taken along a cutting line CC ′ shown in FIG. The same numbers are assigned to the same configurations already described.

  The difference between the configuration shown in FIG. 3 and the configuration shown in FIGS. 1 and 2 is the structure of the upper part of the source region, the drain region, and the inclined portion 23, and the configuration shown in FIG. The configuration shown in FIG.

  That is, the first gate insulating film 3 of the MONOS type memory transistor 70 shown in FIG. 3 extends in the gate length direction and the gate width direction, and has the same configuration as shown in FIGS. is there. A second gate insulating film 4 is provided above the drain regions 21a and 21b and the source region 22 which is a common region, and has the same configuration as shown in FIG. Further, the first gate insulating film 3 is also provided on the upper portion of the inclined portion 23, and is the same as the configuration shown in FIG.

  As shown in FIG. 3A, the first gate insulating film 3 and the second gate insulating film 4 have a boundary between the upper part of the source region 22 and the upper part of the drain region 21a.

  In the third embodiment of the present invention, the first gate insulating film 3 and the second gate insulating film 4 are described as having the same film thickness. Thereby, as shown in FIG. 3B, both gate insulating films in the element region 9 have no step.

  The effect of the semiconductor device according to the third embodiment of the present invention is that the first gate insulating film 3 provided on the upper portion of the inclined portion 23 is similar to the first embodiment and the second embodiment described above. In the manufacturing process, the inclined portion 23 can be prevented from retreating. Further, as in the configuration illustrated in FIG. 3, the first gate insulating film 3 and the second gate insulating film 4 have the same film thickness, so that the step difference at the boundary is alleviated and the first gate is formed. Etching residue when the electrode 7 and the second gate electrode 8 are etched can be suppressed.

[Description of Structure of Fourth Embodiment of the Present Invention: FIG. 4]
Next, the structure of the fourth embodiment of the semiconductor device of the present invention will be described with reference to FIG.
FIG. 4A is a plan view of the semiconductor device of the present invention. FIG. 4B is an end view taken along the cutting line DD ′ shown in FIG. In FIG. 4, 5 is an upper insulating film. The same numbers are assigned to the same configurations already described.

  The upper insulating film 5 is an insulating film having a film thickness different from that of the first gate insulating film 3 and the second gate insulating film 4. The difference between the configuration shown in FIG. 4 and the configuration shown in FIGS. 1, 2 and 3 is a structure in which the upper insulating film 5 is provided on the upper portion of the inclined portion 23. The configuration shown in FIG. In the configuration shown, the first gate insulating film 3 provided on the upper portion of the inclined portion 23 is changed to the upper insulating film 5.

  That is, the first gate insulating film 3 of the MONOS type memory transistor 70 shown in FIG. 4 extends in the gate length direction and the gate width direction, respectively, and has the configuration shown in FIGS. Is the same. Then, the second gate insulating film 4 is provided on the drain regions 21a and 21b and the source region 22 which is a common region, and has the same configuration as shown in FIGS. However, the upper insulating film 5 is provided above the inclined portion 23.

  As shown in FIG. 4A, the first gate insulating film 3 and the second gate insulating film 4 have a boundary between the upper part of the source region 22 and the upper part of the drain region 21a.

  In the fourth embodiment of the present invention, the first gate insulating film 3 and the second gate insulating film 4 are described as having the same film thickness. As a result, as shown in FIG. 4B, both gate insulating films in the element region 9 have no step.

  The effect of the semiconductor device of the fourth embodiment of the present invention is that the upper insulating film 5 provided on the upper portion of the inclined portion 23 is inclined in the manufacturing process as in the first to third embodiments already described. The retreat of the part 23 can be prevented. Further, as in the configuration illustrated in FIG. 4, by making the film thicknesses of the first gate insulating film 3 and the second gate insulating film 4 the same, the step at the boundary is alleviated and the first gate is reduced. Etching residue when the electrode 7 and the second gate electrode 8 are etched can be suppressed.

  The film thickness of the upper insulating film 5 is different from that of the first gate insulating film 3 and the second gate insulating film 4, but the film thickness can be freely selected. Moreover, it can be combined with other structures. For example, the following cases.

In the semiconductor device of the present invention, an element region may be provided in addition to the element region 9 shown in FIG. For example, there is a case where a high breakdown voltage MIS transistor is provided in the element region. In such a case, the upper insulating film 5 can be used as the gate insulating film constituting the high voltage transistor. In this way, it is not necessary to provide the upper insulating film 5 separately.
At that time, the upper insulating film 5 is thicker than the first gate insulating film 3 and the second gate insulating film 4.

In addition, for example, a miniaturized MIS transistor may be provided in another element region. Such a miniaturized transistor is an analog switching element that requires a low voltage operation, and has a low breakdown voltage transistor structure. In such a case, the upper insulating film 5 can be used as the gate insulating film constituting the low breakdown voltage transistor. In this way, it is not necessary to provide the upper insulating film 5 separately.
At that time, the upper insulating film 5 is thinner than the first gate insulating film 3 and the second gate insulating film 4.

  Furthermore, a film provided during the manufacture of the semiconductor device can be used. For example, a sacrificial oxide film provided for the purpose of cleaning the element region of the semiconductor device. The sacrificial oxide film may be processed so as to remain above the inclined portion 23.

[Description of Manufacturing Method 1: FIGS. 5 to 9]
Next, a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.
The semiconductor device of the present invention is not particularly limited, but can be manufactured by the following manufacturing method. In the description of this manufacturing method, the structure of the first embodiment of the present invention shown in FIG. 1 will be described as an example. FIGS. 5 to 9 show the same end face as FIG. 1 (b). Although an actual MIS transistor manufacturing method is complicated, only the main points will be described.

First, the element isolation process will be described.
As shown in FIG. 5, the element isolation film 11 and the inclined portion 23 are formed in the semiconductor substrate 10 by a known selective oxidation method. The region isolated by the element isolation film 11 becomes the element region 9 of the semiconductor device.

  In the selective oxidation method, a silicon nitride film that is not easily oxidized is selectively formed in the element region 9, and then oxidized in a water vapor atmosphere at 1000 ° C., for example, so that the thick element isolation film 11 is removed from the element region 9. It is the method of forming. This is known as a method for forming a so-called field insulating film. That is, the boundary portion between the element region 9 and the element isolation film 11, that is, the upper part of the so-called bird's beak becomes the inclined portion 23.

Next, the first insulating film forming step will be described with reference to FIG.
In this step, a three-layered film is formed as the first gate insulating film 3, and a tunnel insulating film that is an oxide film, a memory nitride film that is a nitride film, and a top insulating film that is an oxide film Is a step of forming.
A description will be made sequentially. In a partial pressure atmosphere of oxygen (O 2) and nitrogen (N 2) at a temperature of about 900 ° C., an oxide film having a thickness of about 2 nm is formed on the entire surface of the semiconductor substrate 10. This becomes a tunnel insulating film. Subsequently, a silicon nitride film having a thickness of about 12 nm is formed by a low pressure CVD method using dichlorosilane (SiH 2 Cl 2) and ammonia (NH 3) as a reaction gas having a temperature of about 700 ° C. This becomes a memory nitride film. Subsequently, an oxide film having a thickness of about 4 nm is formed in a steam atmosphere at a temperature of about 950 ° C. This is the top insulating film.

The tunnel insulating film has a function of tunneling the charge of the semiconductor substrate 10 and injecting the charge into the memory nitride film, and the memory nitride film has a function of trapping the tunneled charge.
The top insulating film has a function of preventing charge injection from the first gate electrode 7 of the MONOS type memory transistor 70.

Next, a process of processing the first gate insulating film 3 formed on the surface of the semiconductor substrate 10 in the element region 9 by the above-described manufacturing method into a predetermined shape will be described with reference to FIG.
A resist pattern 41 having a predetermined shape is formed in the element region 9 and the inclined portion 23. Thereafter, the first gate insulating film 3 is etched using the resist pattern 41. The first gate insulating film 3 is left only under the resist pattern by dry etching using mainly carbon tetrafluoride (CF4) as an etching gas. Thereafter, the resist pattern 41 is removed by ashing.

Next, the second gate insulating film forming step will be described with reference to FIG.
As shown in FIG. 8, after cleaning the surface with a mixed solution of hydrochloric acid (HCL), hydrogen peroxide (H 2 O 2) and pure water (H 2 O), the temperature is about 900 ° C. in a partial pressure atmosphere of O 2 and N 2. Oxidation is performed to form a second gate insulating film 4 having a thickness of about 8 nm on the entire surface.

The first gate insulating film 3 has a nitride film therein, and this nitride film functions as an anti-oxidation film. Therefore, the first gate insulating film 3 is provided with a second gate insulating film 4 on the surface of the semiconductor substrate 10. However, the increase in the thickness of the first gate insulating film 3 hardly occurs.
In this description, since the semiconductor substrate 10 is a P-type silicon semiconductor, the element isolation film 11 is also a silicon oxide film. With the formation of the second gate insulating film 4 in the inclined portion 23, the upper portion of the element isolation film 11 is also oxidized, and the film thickness increases, but illustration is omitted.

Next, a gate electrode formation step and a source region and drain region formation step will be described with reference to FIGS.
As shown in FIG. 9, polycrystalline silicon, which is a constituent material of the first gate electrode 7 and the second gate electrode 8, is formed by a low pressure CVD method using monosilane (SiH 4) as a reaction gas at a temperature of about 650 ° C. Deposit with a film thickness of 350 nm.
Next, a resist pattern (not shown) is formed so that the first gate electrode 7 and the second gate electrode 8 have a predetermined shape.

In particular, the first gate electrode 7 is formed so that the end in the gate width direction (also referred to as the channel length direction) is inside the first gate insulating film 3 formed in the steps already described.
Further, the first gate electrode 7 is formed at a predetermined position above the first gate insulating film 3 by dry etching using mainly chlorine (Cl 2) as an etching gas, and at the same time, the second gate electrode 8 is formed on the second gate electrode 8. The gate insulating film 4 is formed at a predetermined position. Thereafter, a resist pattern (not shown) is removed by ashing.

Subsequently, arsenic (As) is ion-implanted under the conditions of an ion implantation energy of 70 KeV and a dose of 3 × 10 15 atoms / cm 2, thereby forming a region serving as a base for the N-type source region 22 and drain regions 21a and 21b.
Thereafter, annealing is performed in an N 2 atmosphere at a temperature of about 900 ° C., and the source region 22 and the drain regions 21a and 21b are activated, thereby completing the semiconductor device.

[Description of Manufacturing Method 2: FIG. 10]
The manufacturing method described above takes the structure of the first embodiment of the present invention shown in FIG. 1 as an example. Next, the method of manufacturing the structure of the second embodiment of the present invention shown in FIG. Let me illustrate. FIG. 10 shows the same end face as in FIG. In addition, only the step of forming the second gate insulating film 4 that is different from the manufacturing method already described will be described.

FIG. 10 is a cross-sectional view showing a process of forming the second gate insulating film 4 after forming the first gate insulating film 3 in the element region 9.
As shown in FIG. 10, after cleaning the surface with a mixed solution of hydrochloric acid (HCL), hydrogen peroxide (H 2 O 2) and pure water (H 2 O), the temperature is about 900 ° C. in a partial pressure atmosphere of O 2 and N 2. Oxidation is performed to form a second gate insulating film 4 having a thickness of about 8 nm on the entire surface.
The first insulating film 3 has a nitride film therein, and this nitride film functions as an anti-oxidation film. Therefore, even after the step of providing the second insulating film 4 on the surface of the semiconductor substrate 10 is performed. An increase in the thickness of the insulating film 3 hardly occurs.
Also in this description, since the semiconductor substrate 10 is a P-type silicon semiconductor, the element isolation film 11 is also a silicon oxide film. With the formation of the second gate insulating film 4 in the inclined portion 23, the upper portion of the element isolation film 11 is also oxidized, and the film thickness increases, but illustration is omitted.

  The manufacturing method of the semiconductor device in which the second gate insulating film 4 is formed on the upper portion of the inclined portion 23 does not require an etching process for leaving the insulating film on the upper portion of the inclined portion 23. The margin of overlay of the second gate electrode 8 is improved, and gate leakage current due to misalignment can be prevented.

  The manufacturing method described above is an example, and the present invention is not limited to this. Also, the manufacturing methods of the third embodiment and the fourth embodiment of the present invention, whose descriptions are omitted, can be realized by applying the manufacturing methods described above.

In the third embodiment, the second gate insulating film 4 is provided on the drain regions 21 a and 21 b and the source region 22. In this case, since the second gate insulating film 4 is selectively provided in a predetermined region, it can be easily formed by a manufacturing method using film formation and etching removal as already described.
In the fourth embodiment, an insulating film different from the first gate insulating film 3 and the second gate insulating film 4 is formed on the inclined portion 23. The thickness of the upper insulating film 5 can be freely selected. Also in this embodiment, similarly to the third embodiment, it can be easily formed by a manufacturing method using film formation and etching removal.

  In the semiconductor device of the present invention, no leakage current is generated even when transistors having different element structures are mixedly mounted. Therefore, it is suitable for a semiconductor device mounted on an electronic device that requires high reliability.

1A and 1B are a plan view and a cross-sectional view illustrating the structure of a semiconductor device according to a first embodiment of the invention. It is the top view and sectional drawing explaining the structure of the semiconductor device of the 2nd Embodiment of this invention. It is the top view and sectional drawing explaining the structure of the semiconductor device of the 3rd Embodiment of this invention. It is the top view and sectional drawing explaining the structure of the semiconductor device of the 4th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention, Comprising: It is sectional drawing explaining the process of forming an element area | region. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention, Comprising: It is sectional drawing explaining the process of forming a 1st gate insulating film. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention, Comprising: It is sectional drawing explaining the etching process of the 1st gate insulating film. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention, Comprising: It is sectional drawing explaining the process of forming a 2nd gate insulating film. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention, Comprising: It is sectional drawing explaining the process of forming a 1st gate electrode and a 2nd gate electrode. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention, Comprising: It is sectional drawing explaining the process of forming a 2nd gate insulating film in an inclination part. It is sectional drawing for demonstrating the prior art shown in patent document 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 3 1st gate insulating film 4 2nd gate insulating film 5 Upper insulating film 7 1st gate electrode 8 2nd gate electrode 9 Element area | region 10 Semiconductor substrate 11 Element isolation | separation film | membrane 21a, 21b Drain area | region 22 Source area | region 23 Inclination 70 MONOS type memory transistor 80 MOS type address transistor

Claims (6)

An element region is selectively provided on the surface of the semiconductor substrate, and an element isolation film is provided on the surface of the semiconductor substrate so as to surround the element region with an inclined portion around the element region.
In a semiconductor device in which a first MIS transistor and a second MIS transistor are provided in the element region,
A semiconductor device, wherein a first gate insulating film constituting the first MIS transistor or a second gate insulating film constituting the second MIS transistor is provided on the inclined portion.   2. The film thickness of the first gate insulating film or the second gate insulating film is different between an upper portion of a channel region and an upper portion of the inclined portion constituting each MIS transistor. 2. The semiconductor device according to 1.   3. The semiconductor device according to claim 1, wherein the first gate insulating film or the second gate insulating film is provided on an upper portion of a source region or a drain region constituting each MIS transistor. The MIS transistors are arranged so that the gate electrodes constituting the first MIS transistors face each other.
A region sandwiched between the gate electrodes is a common region,
The semiconductor device according to claim 1, wherein the common region is a source region or a drain region of each MIS transistor.   The semiconductor device according to claim 4, wherein a boundary between the first gate insulating film and the second gate insulating film is provided on the common region. The first MIS transistor is a memory transistor, and the first gate insulating film is a stacked film in which a plurality of insulating films including an insulating film having a role of accumulating charges are stacked.
6. The method according to claim 1, wherein the second MIS transistor is an address transistor that controls the first MIS transistor, and the second gate insulating film is a single layer film. The semiconductor device as described in any one.

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