JP2009224479A - Thin film field-effect transistor and method of manufacturing the same - Google Patents
Thin film field-effect transistor and method of manufacturing the same Download PDFInfo
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- JP2009224479A JP2009224479A JP2008066069A JP2008066069A JP2009224479A JP 2009224479 A JP2009224479 A JP 2009224479A JP 2008066069 A JP2008066069 A JP 2008066069A JP 2008066069 A JP2008066069 A JP 2008066069A JP 2009224479 A JP2009224479 A JP 2009224479A
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Landscapes
- Thin Film Transistor (AREA)
- Dram (AREA)
Abstract
Description
本発明は、薄膜電界効果型トランジスタおよびその製造方法に関する。特に活性層にアモルファス酸化物半導体を用いた薄膜電界効果型トランジスタおよびその製造方法に関する。 The present invention relates to a thin film field effect transistor and a method for manufacturing the same. In particular, the present invention relates to a thin film field effect transistor using an amorphous oxide semiconductor as an active layer and a method for manufacturing the same.
近年、液晶やエレクトロルミネッセンス（ＥｌｅｃｔｒｏＬｕｍｉｎｅｓｃｅｎｃｅ：ＥＬ）技術等の進歩により、平面薄型画像表示装置（Ｆｌａｔ Ｐａｎｅｌ Ｄｉｓｐｌａｙ：ＦＰＤ）が実用化されている。特に、電流を通じることによって励起され発光する薄膜材料を用いた有機電界発光素子（以後、「有機ＥＬ素子」と記載する場合がある）は、低電圧で高輝度の発光が得られるために、携帯電話ディスプレイ、パーソナルデジタルアシスタント（ＰＤＡ）、コンピュータディスプレイ、自動車の情報ディスプレイ、ＴＶモニター、あるいは一般照明を含む広い分野で、デバイスの薄型化、軽量化、小型化、および省電力のなどが期待されている。
これらＦＰＤは、ガラス基板上に設けた非晶質シリコン薄膜や多結晶シリコン薄膜を活性層に用いる電界効果型薄膜トランジスタ（以後の説明で、Ｔｈｉｎ Ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ、もしくはＴＦＴと記載する場合がある）のアクティブマトリクス回路により駆動されている。
2. Description of the Related Art In recent years, flat and thin image display devices (Flat Panel Displays: FPD) have been put into practical use due to advances in liquid crystal and electroluminescence (EL) technologies. In particular, an organic electroluminescent device using a thin film material that emits light when excited by passing an electric current (hereinafter sometimes referred to as “organic EL device”) can emit light with high luminance at a low voltage. Device thinning, lightening, miniaturization, and power saving are expected in a wide range of fields including mobile phone displays, personal digital assistants (PDAs), computer displays, automobile information displays, TV monitors, or general lighting. ing.
These FPDs are active field-effect thin film transistors (hereinafter referred to as “Thin Film Transistor” or “TFT”) that use an amorphous silicon thin film or a polycrystalline silicon thin film provided on a glass substrate as an active layer. It is driven by a matrix circuit.
一方、これらＦＰＤのより一層の薄型化、軽量化、耐破損性の向上を求めて、ガラス基板の替わりに軽量で可撓性のある樹脂基板を用いる試みも行われている。
しかし、上述のシリコン薄膜を用いるトランジスタの製造は、比較的高温の熱工程を要し、一般的に耐熱性の低い樹脂基板上に直接形成することは困難である。
そこで、低温での成膜が可能なＺｎＯに代表される酸化物半導体を活性層に用いた薄膜トランジスタの研究及び開発が近年盛んに行われている。特にアモルファス酸化物半導体、例えば、Ｉｎ−Ｇａ−Ｚｎ−Ｏ系アモルファス酸化物は低温での成膜で、高面内特性均一性かつ高移動度が可能であることから、樹脂基板上に室温成膜可能トランジスタの活性層の材料として注目され、アモルファス酸化物半導体を活性層に用いるＴＦＴの開発が活発に行われている（例えば、非特許文献１参照）。
On the other hand, in order to further reduce the thickness, weight, and breakage resistance of these FPDs, an attempt has been made to use a lightweight and flexible resin substrate instead of a glass substrate.
However, the manufacture of the transistor using the above-described silicon thin film requires a relatively high temperature thermal process and is generally difficult to form directly on a resin substrate having low heat resistance.
Thus, research and development of thin film transistors using an oxide semiconductor typified by ZnO, which can be formed at a low temperature, as active layers have been actively conducted in recent years. In particular, amorphous oxide semiconductors such as In-Ga-Zn-O-based amorphous oxides can be formed on a resin substrate at room temperature because they can be formed at a low temperature and have high in-plane property uniformity and high mobility. Attention has been focused on as an active layer material of a film-capable transistor, and TFTs using an amorphous oxide semiconductor as an active layer are being actively developed (for example, see Non-Patent Document 1).
これらのアモルファス酸化物半導体をチャネルに用いたＴＦＴは、その組成および製造条件によってＴＦＴ特性（Ｉｄ−Ｖｇ特性）にヒステリシスが生じる問題があった。例えば、Ｉｎ又はＺｎを含むアモルファス酸化物膜のチャネル層を有する電界効果型トランジスタであって、アモルファス酸化物膜が１０１６ｃｍ−３以上１０２０ｃｍ−３以下の水素原子又は重水素原子を含有していることによりトランジスタ特性のヒステリシスが改良されることを開示している（例えば、特許文献１参照）。 TFTs using these amorphous oxide semiconductors for the channel have a problem that hysteresis occurs in TFT characteristics (Id-Vg characteristics) depending on the composition and manufacturing conditions. For example, a field effect transistor having a channel layer of an amorphous oxide film containing In or Zn, wherein the amorphous oxide film contains hydrogen atoms or deuterium atoms of 10 16 cm −3 or more and 10 20 cm −3 or less Thus, it is disclosed that the hysteresis of transistor characteristics is improved (see, for example, Patent Document 1).
また、酸化物半導体からなる薄膜トランジスタのゲート絶縁膜および製造方法としては、例えば、酸化亜鉛ＺｎＯを主成分とする酸化物からなる半導体薄膜と、シリコン系絶縁膜からなり該半導体薄膜に接するゲート絶縁膜を有する薄膜トランジスタが開示され、該薄膜トランジスタの製法として、前記半導体薄膜の形成と前記ゲート絶縁膜の形成が真空中にて連続した工程で行われ、前記ゲート絶縁膜が、誘導結合方式プラズマ化学気相成長（ＩＣＰ−ＣＶＤ）法又は電子サイクロトロン共鳴化学気相成長（ＥＣＲ−ＣＶＤ）法により形成され、全製造工程が２００℃以下の温度条件下にて行われる薄膜トランジスタの製法が開示されている（例えば、特許文献２参照）。
本発明の目的は、ＯＦＦ電流が低く、高ＯＮ／ＯＦＦ比を有し、かつ駆動による特性変化、特に閾値電圧変動が少ないアモルファス酸化物半導体を用いたＴＦＴを提供することにある。また、そのＴＦＴの製造方法を提供することにある。 An object of the present invention is to provide a TFT using an amorphous oxide semiconductor having a low OFF current, a high ON / OFF ratio, and a characteristic change caused by driving, in particular, a small threshold voltage fluctuation. Moreover, it is providing the manufacturing method of the TFT.
本発明の上記課題は下記の手段によって解決された。
＜１＞ 基板上にゲート電極、ゲート絶縁膜、アモルファス酸化物半導体からなる活性層、ソース電極、ドレイン電極を有する薄膜電界効果型トランジスタであって、前記ゲート絶縁膜のダングリングボンド密度が５×１０１６ｃｍ−３以下であり、かつ前記ゲート絶縁膜中の水素濃度が１×１０１９ｃｍ−３以下であることを特徴とする薄膜電界効果型トランジスタ。
＜２＞ 前記ゲート絶縁膜が絶縁膜材料としてＳｉ化合物を含有することを特徴とする＜１＞に記載の薄膜電界効果型トランジスタ。
＜３＞ 前記Ｓｉ化合物が酸化シリコン（ＳｉＯｘ）であることを特徴とする＜２＞に記載の薄膜電界効果型トランジスタ。
＜４＞ 前記ゲート絶縁膜中の水素濃度が１０１８ｃｍ−３未満であることを特徴とする＜１＞〜＜３＞のいずれかに記載の薄膜電界効果型トランジスタ。
＜５＞ 前記活性層のアモルファス酸化物半導体が、Ｉｎ、Ｇａ，Ｚｎ及びＳｎよりなる群から選ばれる少なくとも一種を含むことを特徴とする＜１＞〜＜４＞のいずれかに記載の薄膜電界効果型トランジスタ。
＜６＞ 前記活性層のアモルファス酸化物半導体が、Ｉｎを含むことを特徴とする＜５＞に記載の薄膜電界効果型トランジスタ。
＜７＞ 前記アモルファス酸化物半導体が、Ｚｎ又はＧａをさらに含有することを特徴とする＜６＞に記載の薄膜電界効果型トランジスタ。
＜８＞ 前記アモルファス酸化物半導体が、ＺｎとＧａとをさらに含有することを特徴とする＜６＞に記載の薄膜電界効果型トランジスタ。
＜９＞ 前記活性層と前記ソース電極および前記ドレイン電極の少なくとも一方との間に抵抗層を有することを特徴とする＜１＞〜＜８＞のいずれかに記載の薄膜電界効果型トランジスタ。
＜１０＞ ＜１＞〜＜９＞のいずれかに記載の薄膜電界効果型トランジスタの製造方法であって、前記ゲート絶縁膜をＡｒガスに対する酸素ガスの流量比（Ｏ２流量／Ａｒ流量）が１０％以上の雰囲気下でスパッタ法により形成することを特徴とする薄膜電界効果型トランジスタの製造方法。
＜１１＞ 前記ゲート絶縁膜を１５０℃以下の温度で形成することを特徴とする＜１０＞に記載の薄膜電界効果型トランジスタの製造方法。
The above-described problems of the present invention have been solved by the following means.
<1> A thin film field effect transistor having a gate electrode, a gate insulating film, an active layer made of an amorphous oxide semiconductor, a source electrode, and a drain electrode on a substrate, wherein the dangling bond density of the gate insulating film is 5 ×. 10. The thin film field-effect transistor is characterized by being 10 16 cm −3 or less and a hydrogen concentration in the gate insulating film being 1 × 10 19 cm −3 or less.
<2> The thin film field effect transistor according to <1>, wherein the gate insulating film contains a Si compound as an insulating film material.
<3> The thin film field effect transistor according to <2>, wherein the Si compound is silicon oxide (SiO x ).
<4> The thin-film field effect transistor according to any one of <1> to <3>, wherein a hydrogen concentration in the gate insulating film is less than 10 18 cm −3 .
<5> The thin film electric field according to any one of <1> to <4>, wherein the amorphous oxide semiconductor of the active layer includes at least one selected from the group consisting of In, Ga, Zn, and Sn. Effect transistor.
<6> The thin film field effect transistor according to <5>, wherein the amorphous oxide semiconductor of the active layer contains In.
<7> The thin film field effect transistor according to <6>, wherein the amorphous oxide semiconductor further contains Zn or Ga.
<8> The thin film field effect transistor according to <6>, wherein the amorphous oxide semiconductor further contains Zn and Ga.
<9> The thin film field effect transistor according to any one of <1> to <8>, wherein a resistance layer is provided between the active layer and at least one of the source electrode and the drain electrode.
<10> The method for manufacturing a thin film field effect transistor according to any one of <1> to <9>, wherein a flow rate ratio of oxygen gas to Ar gas (O 2 flow rate / Ar flow rate) is set in the gate insulating film. A method for manufacturing a thin film field effect transistor, characterized by being formed by sputtering in an atmosphere of 10% or more.
<11> The method for producing a thin film field effect transistor according to <10>, wherein the gate insulating film is formed at a temperature of 150 ° C. or lower.
アモルファス酸化物半導体を用いたＴＦＴは、室温成膜が可能であり、可撓性プラスチックフイルムを基板として作製が可能であるので、フイルム（フレキシブル）ＴＦＴの活性層の材料として注目された。特に特開２００６−１６５５２９号公報および同２００６−１８６３１９号公報で開示されているように、ポリエステルフィルム基板上にキャリア濃度を１０１８／ｃｍ３未満のアモルファス酸化物半導体を活性層に用いて、電界効果移動度１０ｃｍ２／Ｖｓ、ＯＮ／ＯＦＦ比１０３超の性能を持つＴＦＴが報告されている。 A TFT using an amorphous oxide semiconductor can be formed at room temperature and can be manufactured using a flexible plastic film as a substrate, and thus has attracted attention as a material for an active layer of a film (flexible) TFT. In particular, as disclosed in JP-A Nos. 2006-165529 and 2006-186319, an amorphous oxide semiconductor having a carrier concentration of less than 10 18 / cm 3 is used as an active layer on a polyester film substrate. A TFT having an effective mobility of 10 cm 2 / Vs and an ON / OFF ratio exceeding 10 3 has been reported.
しかしながら、本発明者らによるこれらのＴＦＴの動作特性の詳細な解析の結果、ＴＦＴを長時間、繰り返し駆動すると、ＴＦＴの閾値電圧が変動する問題が判明した。このＴＦＴの閾値電圧の変動は有機ＥＬ表示装置のように電流値駆動型の表示装置に用いると発光ムラを生じるので極めて重大な解決すべき課題であった。 However, as a result of detailed analysis of the operating characteristics of these TFTs by the present inventors, it has been found that the TFT threshold voltage fluctuates when the TFT is repeatedly driven for a long time. The variation in the threshold voltage of the TFT is a very serious problem to be solved because it causes unevenness in light emission when used in a current value driving type display device such as an organic EL display device.
本発明者らは、あらゆる観点より本課題の解決に努力した。一般的には活性層材料の課題と考えられ、活性層材料の改良が続けられた。しかしながら、本発明者らは思いがけず、活性層に隣接するゲート絶縁膜が閾値電圧の変動に影響を与えていることを発見した。さらにその改良を鋭意続けた結果、本願の発明に到達したものである。特に、ゲート絶縁膜中のＳｉダングリングボンド密度、および水素濃度を減らすことにより、低オフ電流・高ＯＮ／ＯＦＦ比を維持したまま、閾値電圧の変動を抑制できることを見出した。具体的には、ゲート絶縁膜中のＳｉダングリングボンド密度を５×１０１６ｃｍ−３以下にすることにより、閾値電圧の変動を抑制し、かつゲート絶縁膜中の水素濃度を１×１０１９ｃｍ−３未満にすることにより、低オフ電流で且つ高ＯＮ／ＯＦＦ比を維持できる。また、そのゲート絶縁膜の製造方法を見出した。 The present inventors made efforts to solve this problem from all points of view. In general, it was considered a problem of the active layer material, and the improvement of the active layer material was continued. However, the present inventors have unexpectedly discovered that the gate insulating film adjacent to the active layer affects the fluctuation of the threshold voltage. Furthermore, as a result of continual improvement, the present invention has been achieved. In particular, it has been found that by reducing the Si dangling bond density and the hydrogen concentration in the gate insulating film, fluctuations in the threshold voltage can be suppressed while maintaining a low off-current / high ON / OFF ratio. Specifically, by setting the Si dangling bond density in the gate insulating film to 5 × 10 16 cm −3 or less, fluctuation of the threshold voltage is suppressed, and the hydrogen concentration in the gate insulating film is set to 1 × 10 19. By making it less than cm −3 , it is possible to maintain a low off-current and a high ON / OFF ratio. Moreover, the manufacturing method of the gate insulating film was discovered.
特開２００７−１０３９１８には、アモルファス酸化物膜を活性層に用いたＴＦＴにおいて、電子キャリア濃度を水素ドーパント量で制御することができることが開示され、１０１８／ｃｍ３程度の電子キャリア濃度を実現するためには、１０１８ｃｍ−３以上１０２０ｃｍ−３以下の水素を添加することでヒステリシスが改善できることが開示されている。しかしながら、チャネル層についての条件は明記されているものの、ヒステリシス改良という観点でゲート絶縁膜の関与は何ら教唆されていない。 Japanese Patent Application Laid-Open No. 2007-103918 discloses that an electron carrier concentration can be controlled by the amount of hydrogen dopant in a TFT using an amorphous oxide film as an active layer, and an electron carrier concentration of about 10 18 / cm 3 is realized. In order to do so, it is disclosed that hysteresis can be improved by adding hydrogen of 10 18 cm −3 or more and 10 20 cm −3 or less. However, although the conditions regarding the channel layer are specified, the involvement of the gate insulating film is not taught at all from the viewpoint of improving the hysteresis.
本発明によると、ＯＦＦ電流が低く、高ＯＮ／ＯＦＦ比を示すＴＦＴでかつ連続駆動安定性に優れたＴＦＴが提供される。特に、可撓性基板を用いたフイルム（フレキシブル）ＴＦＴとして有用な薄膜電界効果型トランジスタが提供される。また、これらのＴＦＴを用いた表示装置を提供される。 According to the present invention, a TFT having a low OFF current, a high ON / OFF ratio, and excellent continuous drive stability is provided. In particular, a thin film field effect transistor useful as a film (flexible) TFT using a flexible substrate is provided. In addition, a display device using these TFTs is provided.
１．薄膜電界効果型トランジスタ（ＴＦＴ）
本発明のＴＦＴは、少なくとも、ゲート電極、ゲート絶縁膜、活性層、ソース電極及びドレイン電極を順次有し、ゲート電極に電圧を印加して、活性層に流れる電流を制御し、ソース電極とドレイン電極間の電流をスイッチングする機能を有するアクテイブ素子である。ＴＦＴ構造として、スタガ構造及び逆スタガ構造いずれをも形成することができる。
本発明のＴＦＴについて詳細に説明する。
1. Thin film field effect transistor (TFT)
The TFT of the present invention has at least a gate electrode, a gate insulating film, an active layer, a source electrode, and a drain electrode in order, and controls the current flowing through the active layer by applying a voltage to the gate electrode, It is an active element having a function of switching a current between electrodes. As the TFT structure, either a staggered structure or an inverted staggered structure can be formed.
The TFT of the present invention will be described in detail.
１）ゲート絶縁膜
本発明に於けるゲート絶縁膜は、ダングリングボンド密度が５×１０１６ｃｍ−３以下であり、かつ前記ゲート絶縁膜中の水素濃度が１０１９ｃｍ−３以下である。
ダングリングボンド密度は、ゲート絶縁膜を構成する絶縁材料中の未結合手の密度であって、例えば、酸化シリコン（ＳｉＯ２）の場合、酸素と共有結合していないＳｉの未結合手の密度である。
1) Gate Insulating Film The gate insulating film in the present invention has a dangling bond density of 5 × 10 16 cm −3 or less and a hydrogen concentration in the gate insulating film of 10 19 cm −3 or less.
The dangling bond density is the density of dangling bonds in the insulating material constituting the gate insulating film. For example, in the case of silicon oxide (SiO 2 ), the density of dangling bonds of Si that is not covalently bonded to oxygen. It is.
本発明に於けるダングリングボンド密度は下記の測定により得られる値である。
＜ダングリングボンド密度の測定方法＞
ゲート絶縁膜中のダングリングボンドはＥＳＲ（電子スピン共鳴法）にて測定できる。
本発明に於けるダングリングボンド密度は、好ましくは５×１０１６ｃｍ−３以下、さらに好ましくは３×１０１６ｃｍ−３以下である。
The dangling bond density in the present invention is a value obtained by the following measurement.
<Dangling bond density measurement method>
The dangling bond in the gate insulating film can be measured by ESR (electron spin resonance method).
The dangling bond density in the present invention is preferably 5 × 10 16 cm −3 or less, more preferably 3 × 10 16 cm −3 or less.
本発明に於ける水素濃度は下記の測定により得られる値である。
＜水素濃度の測定方法＞
ゲート絶縁膜中の水素濃度は、ＳＩＭＳ（２次イオン質量分析）にて測定できる。
本発明に於けるゲート絶縁膜中の水素濃度は、好ましくは１×１０１９ｃｍ−３以下、さらに好ましくは１×１０−１８ｃｍ−３未満である。
The hydrogen concentration in the present invention is a value obtained by the following measurement.
<Measurement method of hydrogen concentration>
The hydrogen concentration in the gate insulating film can be measured by SIMS (secondary ion mass spectrometry).
The hydrogen concentration in the gate insulating film in the present invention is preferably 1 × 10 19 cm −3 or less, more preferably less than 1 × 10 −18 cm −3 .
ゲート絶縁膜に用いられる絶縁材料としては、酸化シリコン（ＳｉＯｘ）、窒化シリコン（ＳｉＮｙ）、酸窒化シリコン（ＳｉＯＮ）、酸化アルミニウム（Ａｌ２Ｏ３）、酸化イットリウム（Ｙ２Ｏ３）、酸化タンタル（Ｔａ２Ｏ５）、酸化ハフニウム（ＨｆＯ２）等の絶縁体、又はそれらの化合物を少なくとも二つ以上含む混晶化合物を用いることができる。
また、ポリイミドのような高分子絶縁体もゲート絶縁膜として用いることができる。好ましい絶縁膜材料はＳｉ化合物である。特に好ましくは酸化シリコン（ＳｉＯｘ）である。ｘは一般に１．７〜２．３である。
As an insulating material used for the gate insulating film, silicon oxide (SiO x ), silicon nitride (SiN y ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), An insulator such as tantalum oxide (Ta 2 O 5 ) or hafnium oxide (HfO 2 ), or a mixed crystal compound containing at least two of these compounds can be used.
A polymer insulator such as polyimide can also be used as the gate insulating film. A preferred insulating film material is a Si compound. Particularly preferred is silicon oxide (SiO x ). x is generally 1.7 to 2.3.
ゲート絶縁膜の製造方法について説明する。
本発明のダングリングボンド密度が５×１０１６ｃｍ−３以下であり、かつ前記ゲート絶縁膜中の水素濃度が１０１９ｃｍ−３以下であるゲート絶縁膜は、Ａｒガスに対する酸素ガスの流量比（Ｏ２流量／Ａｒ流量）が１０％以上の雰囲気下でスパッタ法により形成することにより得られる。
好ましくは、Ｏ２流量／Ａｒ流量が１０％以上であり、より好ましくは１３％以上である。スパッタ温度は、樹脂基板を想定した場合、好ましくは１８０℃以下であり、より好ましくは１５０℃以下である。
ゲート絶縁膜を形成後、熱処理を施しても良い。
A method for manufacturing the gate insulating film will be described.
The gate insulating film having a dangling bond density of 5 × 10 16 cm −3 or less and a hydrogen concentration in the gate insulating film of 10 19 cm −3 or less of the present invention has a flow ratio of oxygen gas to Ar gas. It can be obtained by forming by sputtering in an atmosphere where (O 2 flow rate / Ar flow rate) is 10% or more.
Preferably, the O 2 flow rate / Ar flow rate is 10% or more, more preferably 13% or more. When the resin substrate is assumed, the sputtering temperature is preferably 180 ° C. or lower, and more preferably 150 ° C. or lower.
Heat treatment may be performed after the gate insulating film is formed.
ゲート絶縁膜の膜厚としては１０ｎｍ〜１０μｍが好ましい。ゲート絶縁膜はリーク電流を減らす、電圧耐性を上げる為に、ある程度膜厚を厚くする必要がある。しかし、ゲート絶縁膜の膜厚を厚くすると、ＴＦＴの駆動電圧の上昇を招く結果となる。 The thickness of the gate insulating film is preferably 10 nm to 10 μm. The gate insulating film needs to be thickened to some extent in order to reduce leakage current and increase voltage resistance. However, increasing the thickness of the gate insulating film results in an increase in the driving voltage of the TFT.
２）活性層
本発明に用いられる活性層には、アモルファス酸化物半導体が用いられる。アモルファス酸化物半導体は、低温で成膜可能である為に、プラスティックのような可撓性のある樹脂基板に作製が可能である。低温で作製可能な良好なアモルファス酸化物半導体としては、Ｉｎを含む酸化物、ＩｎとＺｎを含む酸化物、Ｉｎ、Ｇａ及びＺｎを含有する酸化物であり、組成構造としては、ＩｎＧａＯ３（ＺｎＯ）ｍ（ｍは６未満の自然数）のものが好ましいことが知られている。これらは、キャリアが電子のｎ型半導体である。もちろん、ＺｎＯ・Ｒｈ２Ｏ３、ＣｕＧａＯ２、ＳｒＣｕ２Ｏ２のようなｐ型酸化物半導体を活性層に用いても良い。特開２００６−１６５５２９に開示されている酸化物半導体を用いることもできる。
2) Active layer An amorphous oxide semiconductor is used for the active layer used in the present invention. Since an amorphous oxide semiconductor can be formed at a low temperature, it can be formed on a flexible resin substrate such as a plastic. Good amorphous oxide semiconductors that can be manufactured at low temperatures include oxides containing In, oxides containing In and Zn, and oxides containing In, Ga, and Zn. As the composition structure, InGaO 3 (ZnO ) M (m is a natural number of less than 6) is known to be preferable. These are n-type semiconductors whose carriers are electrons. Of course, a p-type oxide semiconductor such as ZnO.Rh 2 O 3 , CuGaO 2 , or SrCu 2 O 2 may be used for the active layer. An oxide semiconductor disclosed in JP-A-2006-165529 can also be used.
本発明においては、Ｉｎ、Ｇａ，Ｚｎ及びＳｎよりなる群から選ばれる少なくとも一種を含有するアモルファス酸化物半導体が好ましい。より好ましくは、Ｉｎを含有するアモルファス酸化物半導体である。さらに好ましくは、Ｉｎに加えて、Ｚｎ又はＧａをさらに含有するアモルファス酸化物半導体である。最も好ましくは、Ｉｎに加えて、ＧａとＺｎとをさらに含有するアモルファス酸化物半導体である。 In the present invention, an amorphous oxide semiconductor containing at least one selected from the group consisting of In, Ga, Zn, and Sn is preferable. More preferably, it is an amorphous oxide semiconductor containing In. More preferably, it is an amorphous oxide semiconductor further containing Zn or Ga in addition to In. Most preferably, the amorphous oxide semiconductor further contains Ga and Zn in addition to In.
具体的に本発明に係るアモルファス酸化物半導体は、Ｉｎ−Ｇａ−Ｚｎ−Ｏを含み構成され、結晶状態における組成がＩｎＧａＯ３（ＺｎＯ）ｍ（ｍは６未満の自然数）で表されるアモルファス酸化物半導体が好ましい。特に、ＩｎＧａＺｎＯ４がより好ましい。 Specifically, the amorphous oxide semiconductor according to the present invention includes In—Ga—Zn—O, and the composition in the crystalline state is represented by InGaO 3 (ZnO) m (m is a natural number of less than 6). A physical semiconductor is preferred. In particular, InGaZnO 4 is more preferable.
本発明におけるアモルファス酸化物半導体のキャリア濃度は、種々の手段により所望の数値に調整することができる。 The carrier concentration of the amorphous oxide semiconductor in the present invention can be adjusted to a desired value by various means.
活性層のキャリア濃度の調整手段としては、下記の手段を挙げることが出来る。
（１）酸素欠陥による調整
酸化物半導体において、酸素欠陥ができると、活性層のキャリア濃度が増加し、電気伝導度が大きくなることが知られている。よって、酸素欠陥量を調整することにより、酸化物半導体のキャリア濃度を制御することが可能である。酸素欠陥量を制御する具体的な方法としては、成膜中の酸素分圧、成膜後の後処理時の酸素濃度と処理時間等がある。ここでいう後処理とは、具体的に１００℃以上の熱処理、酸素プラズマ、ＵＶオゾン処理がある。これらの方法の中でも、生産性の観点から成膜中の酸素分圧を制御する方法が好ましい。成膜中の酸素分圧を調整することにより、酸化物半導体のキャリア濃度の制御ができることは、特開２００６−１６５５２９に開示されており、本手法を利用することができる。
Examples of the means for adjusting the carrier concentration of the active layer include the following means.
(1) Adjustment by oxygen defect It is known that when an oxygen defect is formed in an oxide semiconductor, the carrier concentration in the active layer increases and the electrical conductivity increases. Therefore, the carrier concentration of the oxide semiconductor can be controlled by adjusting the amount of oxygen defects. Specific methods for controlling the amount of oxygen defects include oxygen partial pressure during film formation, oxygen concentration and treatment time during post-treatment after film formation, and the like. Specific examples of post-treatment include heat treatment at 100 ° C. or higher, oxygen plasma, and UV ozone treatment. Among these methods, a method of controlling the oxygen partial pressure during film formation is preferable from the viewpoint of productivity. JP-A-2006-165529 discloses that the carrier concentration of an oxide semiconductor can be controlled by adjusting the oxygen partial pressure during film formation, and this technique can be used.
（２）組成比による調整
酸化物半導体の金属組成比を変えることにより、キャリア濃度が変化することが知られている。例えば、ＩｎＧａＺｎ１−ＸＭｇＸＯ４において、Ｍｇの比率が増えていくと、キャリア濃度が小さくなることが、特開２００６−１６５５２９に開示されている。また、（Ｉｎ２Ｏ３）１−Ｘ（ＺｎＯ）Ｘの酸化物系において、Ｚｎ／Ｉｎ比が１０％以上では、Ｚｎ比率が増加するにつれ、キャリア濃度が小さくなることが報告されている（「透明導電膜の新展開II」シーエムシー出版Ｐ．３４−３５）。これら組成比を変える具体的な方法としては、例えば、スパッタによる成膜方法においては、組成比が異なるターゲットを用いる。または、多元のターゲットにより、共スパッタし、そのスパッタレートを個別に調整することにより、膜の組成比を変えることが可能である。
(2) Adjustment by composition ratio It is known that the carrier concentration is changed by changing the metal composition ratio of the oxide semiconductor. For example, JP 2006-165529 discloses that, in InGaZn 1-X Mg X O 4 , the carrier concentration decreases as the Mg ratio increases. In addition, in the oxide system of (In 2 O 3 ) 1-X (ZnO) X , it is reported that when the Zn / In ratio is 10% or more, the carrier concentration decreases as the Zn ratio increases ( “New development of transparent conductive film II”, CMC Publishing, P.34-35). As specific methods for changing these composition ratios, for example, in a film formation method by sputtering, targets having different composition ratios are used. Alternatively, it is possible to change the composition ratio of the film by co-sputtering with a multi-source target and individually adjusting the sputtering rate.
（３）不純物による調整
酸化物半導体に、Ｌｉ，Ｎａ，Ｍｎ，Ｎｉ，Ｐｄ，Ｃｕ，Ｃｄ，Ｃ，Ｎ，Ｐ等の元素を不純物として添加することによりキャリア濃度を減少させることが可能であることが、特開２００６−１６５５２９に開示されている。不純物を添加する方法としては、酸化物半導体と不純物元素とを共蒸着により行う、成膜された酸化物半導体膜に不純物元素のイオンをイオンドープ法により行う等がある。
キャリア濃度を調整する手段としては、上記（１）〜（３）の方法を単独に用いても良いし、組み合わせても良い。
(3) Adjustment by impurities It is possible to reduce the carrier concentration by adding elements such as Li, Na, Mn, Ni, Pd, Cu, Cd, C, N, and P to the oxide semiconductor as impurities. This is disclosed in Japanese Patent Laid-Open No. 2006-165529. As a method for adding an impurity, an oxide semiconductor and an impurity element are co-evaporated, an ion of the impurity element is added to the formed oxide semiconductor film by an ion doping method, or the like.
As means for adjusting the carrier concentration, the above methods (1) to (3) may be used alone or in combination.
＜活性層の形成方法＞
活性層の成膜方法は、気相成膜法を用いるのが良い。気相成膜法の中でも、スパッタリング法、パルスレーザー蒸着法（ＰＬＤ法）が適している。さらに、量産性の観点から、スパッタリング法が好ましい。
<Method for forming active layer>
As a method for forming the active layer, a vapor phase film forming method is preferably used. Among vapor deposition methods, sputtering and pulsed laser deposition (PLD) are suitable. Furthermore, the sputtering method is preferable from the viewpoint of mass productivity.
例えば、酸化物半導体の多結晶焼結体をターゲットとして、ＲＦマグネトロンスパッタリング蒸着法により、真空度及び酸素流量を制御して成膜される。酸素流量が多いほどキャリア濃度を小さくすることができる。 For example, the film is formed by controlling the degree of vacuum and the oxygen flow rate by RF magnetron sputtering deposition using a polycrystalline sintered body of an oxide semiconductor as a target. The carrier concentration can be reduced as the oxygen flow rate increases.
成膜した膜は、周知のＸ線回折法によりアモルファス膜であることが確認できる。組成比は、ＲＢＳ（ラザフォード後方散乱）分析法により求めることができる。 The formed film can be confirmed to be an amorphous film by a known X-ray diffraction method. The composition ratio can be determined by an RBS (Rutherford backscattering) analysis method.
＜活性層の膜厚＞
本発明に於ける活性層の厚みは、１ｎｍ以上１０００ｎｍ以下が好ましく、より好ましくは２．５ｎｍ以上５００ｎｍ以下、さらに好ましくは５ｎｍ以上１００ｎｍ以下である。
<Thickness of active layer>
The thickness of the active layer in the present invention is preferably from 1 nm to 1000 nm, more preferably from 2.5 nm to 500 nm, still more preferably from 5 nm to 100 nm.
上記の構成の活性層を用いることにより、移動度が１ｃｍ２／（Ｖ・秒）以上の高い移動度のＴＦＴで、オン・オフ比が１０４以上のトランジスタ特性を実現できる。 By using the active layer having the above-described structure, transistor characteristics with a high mobility of 1 cm 2 / (V · sec) or more and an on / off ratio of 10 4 or more can be realized.
３）抵抗層
本発明の好ましい形態は、活性層とソース電極及びドレイン電極の少なくとも一方との間に抵抗層を持つ構成である。本発明における抵抗層の電気伝導度は、活性層の電気伝導度より小さくなるように設ける。好ましくは、抵抗層の電気伝導度に対する活性層の電気伝導度の比率（活性層の電気伝導度／抵抗層の電気伝導度）は、１０１以上１０１０以下が好ましく、より好ましくは１０２以上１０８以下である。前記活性層の電気伝導度の好ましい範囲は１０−４Ｓｃｍ−１以上１０２Ｓｃｍ−２未満である。より好ましくは１０−１Ｓｃｍ−１以上１０２Ｓｃｍ−２未満である。抵抗層の電気伝導度の好ましい範囲は１０−１Ｓｃｍ−１以下である。より好ましくは１０−９Ｓｃｍ−１以上１０−３Ｓｃｍ−２以下である。
3) Resistive layer A preferred embodiment of the present invention is a structure having a resistive layer between the active layer and at least one of the source electrode and the drain electrode. In the present invention, the electric resistance of the resistance layer is provided to be smaller than the electric conductivity of the active layer. Preferably, the ratio of the electrical conductivity of the active layer to the electrical conductivity of the resistive layer (the electrical conductivity of the active layer / the electrical conductivity of the resistive layer) is preferably 10 1 or more and 10 10 or less, more preferably 10 2 or more. 10 8 or less. A preferable range of the electric conductivity of the active layer is 10 −4 Scm −1 or more and less than 10 2 Scm −2 . More preferably, it is 10 −1 Scm −1 or more and less than 10 2 Scm −2 . A preferable range of the electric conductivity of the resistance layer is 10 −1 Scm −1 or less. More preferably, it is 10 −9 Scm −1 or more and 10 −3 Scm −2 or less.
好ましくは、活性層の厚みより抵抗層の厚みが厚い。より好ましくは活性層の厚み／抵抗層の厚みは１を越え１００以下であり、より好ましくは１を越え１０以下である。抵抗層を用いた本形態の場合、活性層の膜厚は、１ｎｍ以上１００ｎｍ以下が好ましく、より好ましくは２．５ｎｍ以上３０ｎｍ以下である。抵抗層の膜厚は、５０ｎｍ以上２００ｎｍ以下が好ましく、より好ましくは１０ｎｍ以上１００ｎｍ以下である。 Preferably, the resistance layer is thicker than the active layer. More preferably, the thickness of the active layer / the thickness of the resistance layer is more than 1 and 100 or less, more preferably more than 1 and 10 or less. In the case of this embodiment using a resistance layer, the thickness of the active layer is preferably 1 nm to 100 nm, more preferably 2.5 nm to 30 nm. The thickness of the resistance layer is preferably 50 nm or more and 200 nm or less, more preferably 10 nm or more and 100 nm or less.
上記の活性層及び抵抗層を用いることにより、活性層のみの構成よりも移動度、ＯＮ／ＯＦＦ比が向上し、また駆動により閾値電圧の変動も抑制できる。
活性層及び抵抗層の電気伝導度は、基板上に当該活性層のみを成膜した物成測定用サンプルを作製し、サンプルの測定されたシート抵抗と膜厚から計算し求められる。ここで、シート抵抗をρ（Ω／□）、膜厚をｄ（ｃｍ）とすると、電気伝導度σ（Ｓｃｍ−１）は、σ＝１／（ρ＊ｄ）として算出される。
By using the active layer and the resistance layer, the mobility and the ON / OFF ratio are improved as compared with the configuration of only the active layer, and the fluctuation of the threshold voltage can be suppressed by driving.
The electrical conductivity of the active layer and the resistance layer can be obtained by preparing a physical property measurement sample in which only the active layer is formed on a substrate, and calculating from the measured sheet resistance and film thickness of the sample. Here, when the sheet resistance is ρ (Ω / □) and the film thickness is d (cm), the electrical conductivity σ (Scm −1 ) is calculated as σ = 1 / (ρ * d).
本発明に用いられる抵抗層には、上記の電気伝導度を満たすものであると特に規定はないが、活性層同様にアモルファス酸化物半導体を用いることが好ましい。アモルファス酸化物半導体は、低温で成膜可能である為に、プラスティックのような可撓性のある樹脂基板に作製が可能である。例えばＡｌ２Ｏ３、Ｇａ２Ｏ３、ＺｒＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ３、ＭｇＯ、ＨｆＯ３等を用いることが可能である。特に活性層と同様にＩｎ、Ｇａ，Ｚｎ及びＳｎよりなる群から選ばれる少なくとも一種を含有するアモルファス酸化物半導体が好ましい。より好ましくは、Ｇａを含有するアモルファス酸化物半導体である。さらに好ましくは、Ｇａに加えて、Ｉｎ又はＺｎをさらに含有するアモルファス酸化物半導体である。最も好ましくは、Ｇａに加えて、ＩｎとＺｎとをさらに含有するアモルファス酸化物半導体である。 The resistance layer used in the present invention is not particularly defined as satisfying the above electric conductivity, but it is preferable to use an amorphous oxide semiconductor like the active layer. Since an amorphous oxide semiconductor can be formed at a low temperature, it can be formed on a flexible resin substrate such as a plastic. For example, Al 2 O 3 , Ga 2 O 3 , ZrO 2 , Y 2 O 3 , Ta 2 O 3 , MgO, HfO 3 or the like can be used. In particular, like the active layer, an amorphous oxide semiconductor containing at least one selected from the group consisting of In, Ga, Zn, and Sn is preferable. More preferably, it is an amorphous oxide semiconductor containing Ga. More preferably, the amorphous oxide semiconductor further contains In or Zn in addition to Ga. Most preferably, the amorphous oxide semiconductor further contains In and Zn in addition to Ga.
＜抵抗層の電気伝導度の調整＞
抵抗層の電気伝導度を調整する方法としては、抵抗層を構成する酸化物半導体のキャリア濃度を調整することで可能である。抵抗層のキャリア濃度の調節手段としては、前述の活性層のキャリア濃度の調節手段と同様の方法にて行うことが可能である。
<Adjustment of electric conductivity of resistance layer>
As a method for adjusting the electric conductivity of the resistance layer, it is possible to adjust the carrier concentration of the oxide semiconductor constituting the resistance layer. As the means for adjusting the carrier concentration of the resistance layer, the same method as the means for adjusting the carrier concentration of the active layer described above can be used.
＜抵抗層の形成方法＞
抵抗層の成膜方法は、気相成膜法を用いるのが良い。気相成膜法の中でも、スパッタリング法、パルスレーザー蒸着法（ＰＬＤ法）が適している。さらに、量産性の観点から、スパッタリング法が好ましい。
例えば、酸化物半導体の多結晶焼結体をターゲットとして、ＲＦマグネトロンスパッタリング蒸着法により、真空度及び酸素流量を制御して成膜される。酸素流量が多いほど電気伝導度を小さくすることができる。
<Method for forming resistance layer>
As a method for forming the resistance layer, a vapor phase film forming method is preferably used. Among vapor deposition methods, sputtering and pulsed laser deposition (PLD) are suitable. Furthermore, the sputtering method is preferable from the viewpoint of mass productivity.
For example, the film is formed by controlling the degree of vacuum and the oxygen flow rate by RF magnetron sputtering deposition using a polycrystalline sintered body of an oxide semiconductor as a target. The greater the oxygen flow rate, the smaller the electrical conductivity.
４）ゲート電極
本発明におけるゲート電極としては、例えば、Ａｌ、Ｍｏ、Ｃｒ、Ｔａ、Ｔｉ、Ａｕ、又はＡｇ等の金属、Ａｌ−Ｎｄ、ＡＰＣ等の合金、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫（ＩＴＯ）、酸化亜鉛インジウム（ＩＺＯ）等の金属酸化物導電膜、ポリアニリン、ポリチオフェン、又はポリピロ−ルなどの有機導電性化合物、またはこれらの混合物を好適に挙げられる。
ゲート電極の厚みは、１０ｎｍ以上１０００ｎｍ以下とすることが好ましい。
4) Gate electrode Examples of the gate electrode in the present invention include metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al-Nd and APC, tin oxide, zinc oxide, indium oxide, Preferable examples include metal oxide conductive films such as indium tin oxide (ITO) and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof.
The thickness of the gate electrode is preferably 10 nm or more and 1000 nm or less.
電極の成膜法は特に限定されることはなく、印刷方式、コ−ティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレ−ティング法等の物理的方式、ＣＶＤ、プラズマＣＶＤ法等の化学的方式、などの中から前記材料との適性を考慮して適宜選択した方法に従って前記基板上に形成することができる。例えば、ＩＴＯを選択する場合には、直流あるいは高周波スパッタリング法、真空蒸着法、イオンプレ−ティング法等に従って行うことができる。またゲート電極の材料として有機導電性化合物を選択する場合には湿式製膜法に従って行うことができる。 The electrode film formation method is not particularly limited, and may be a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a CVD method, a plasma CVD method, or the like. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from among chemical methods. For example, when ITO is selected, it can be performed according to a direct current or high frequency sputtering method, a vacuum deposition method, an ion plating method, or the like. When an organic conductive compound is selected as the material for the gate electrode, it can be performed according to a wet film forming method.
５）ソース電極及びドレイン電極
本発明におけるソース電極及びドレイン電極材料として、例えば、Ａｌ、Ｍｏ、Ｃｒ、Ｔａ、Ｔｉ、Ａｕ、又はＡｇ等の金属、Ａｌ−Ｎｄ、ＡＰＣ等の合金、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫（ＩＴＯ）、酸化亜鉛インジウム（ＩＺＯ）等の金属酸化物導電膜、ポリアニリン、ポリチオフェン、又はポリピロ−ルなどの有機導電性化合物、またはこれらの混合物を好適に挙げられる。
ソース電極及びドレイン電極の厚みは、１０ｎｍ以上１０００ｎｍ以下とすることが好ましい。
5) Source electrode and drain electrode Examples of the source electrode and drain electrode material in the present invention include metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al-Nd and APC, tin oxide, Preferred examples include metal oxide conductive films such as zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof. It is done.
The thickness of the source electrode and the drain electrode is preferably 10 nm or more and 1000 nm or less.
電極の製膜法は特に限定されることはなく、印刷方式、コ−ティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレ−ティング法等の物理的方式、ＣＶＤ、プラズマＣＶＤ法等の化学的方式、などの中から前記材料との適性を考慮して適宜選択した方法に従って前記基板上に形成することができる。例えば、ＩＴＯを選択する場合には、直流あるいは高周波スパッタリング法、真空蒸着法、イオンプレ−ティング法等に従って行うことができる。またソース電極及びドレイン電極の材料として有機導電性化合物を選択する場合には湿式製膜法に従って行うことができる。 The electrode film formation method is not particularly limited, and may be a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a CVD method, a plasma CVD method, or the like. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from among chemical methods. For example, when ITO is selected, it can be performed according to a direct current or high frequency sputtering method, a vacuum deposition method, an ion plating method, or the like. Further, when an organic conductive compound is selected as a material for the source electrode and the drain electrode, it can be performed according to a wet film forming method.
６）基板
本発明に用いられる基板は特に限定されることはなく、例えばＹＳＺ（ジルコニア安定化イットリウム）、ガラス等の無機材料、ポリエチレンテレフタレ−ト、ポリブチレンテレフタレ−ト、ポリエチレンナフタレ−ト等のポリエステル、ポリスチレン、ポリカ−ボネ−ト、ポリエ−テルスルホン、ポリアリレ−ト、アリルジグリコ−ルカ−ボネ−ト、ポリイミド、ポリシクロオレフィン、ノルボルネン樹脂、ポリ（クロロトリフルオロエチレン）等の合成樹脂等の有機材料、などが挙げられる。前記有機材料の場合、耐熱性、寸法安定性、耐溶剤性、電気絶縁性、加工性、低通気性、低吸湿性等に優れていることが好ましい。
6) Substrate The substrate used in the present invention is not particularly limited. For example, YSZ (zirconia stabilized yttrium), inorganic materials such as glass, polyethylene terephthalate, polybutylene terephthalate, polyethylene naphthalate Synthetic resins such as polyester such as polyester, polystyrene, polycarbonate, polyethersulfone, polyarylate, allyl diglycol carbonate, polyimide, polycycloolefin, norbornene resin, poly (chlorotrifluoroethylene), etc. Organic materials, and the like. In the case of the organic material, it is preferable that the organic material is excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, and the like.
本発明においては特に可撓性基板が好ましく用いられる。可撓性基板に用いる材料としては、透過率の高い有機プラスチックフィルムが好ましく、例えばポリエチレンテレフタレート、ポリブチレンフタレート、ポリエチレンナフタレート等のポリエステル、ポリスチレン、ポリカーボネート、ポリエーテルスルホン、ポリアリレート、ポリイミド、ポリシクロオレフィン、ノルボルネン樹脂、ポリ（クロロトリフルオロエチレン）等のプラスティックフィルムを用いることができる。また、フィルム状プラスティック基板には、絶縁性が不十分の場合は絶縁層、水分や酸素の透過を防止するためのガスバリア層、フィルム状プラスティック基板の平坦性や電極や活性層との密着性を向上するためのアンダーコート層等を備えることも好ましい。 In the present invention, a flexible substrate is particularly preferably used. The material used for the flexible substrate is preferably an organic plastic film having a high transmittance. For example, polyesters such as polyethylene terephthalate, polybutylene phthalate, and polyethylene naphthalate, polystyrene, polycarbonate, polyethersulfone, polyarylate, polyimide, polycyclo Plastic films such as olefin, norbornene resin, and poly (chlorotrifluoroethylene) can be used. In addition, if the insulating property is insufficient for the film-like plastic substrate, the insulating layer, the gas barrier layer for preventing the transmission of moisture and oxygen, the flatness of the film-like plastic substrate and the adhesion with the electrode and active layer It is also preferable to provide an undercoat layer or the like for improvement.
ここで、可撓性基板の厚みは、５０μｍ以上５００μｍ以下とすることが好ましい。これは、可撓性基板の厚みを５０μｍ未満とした場合には、基板自体が十分な平坦性を保持することが難しいためである。また、可撓性基板の厚みを５００μｍよりも厚くした場合には、基板自体を自由に曲げることが困難になる、すなわち基板自体の可撓性が乏しくなるためである。 Here, the thickness of the flexible substrate is preferably 50 μm or more and 500 μm or less. This is because it is difficult for the substrate itself to maintain sufficient flatness when the thickness of the flexible substrate is less than 50 μm. Further, when the thickness of the flexible substrate is more than 500 μm, it is difficult to bend the substrate itself freely, that is, the flexibility of the substrate itself is poor.
７）構造
次に、図面を用いて、詳細に本発明におけるＴＦＴの構造を説明する。
図１は、逆スタガ構造のＴＦＴの一例を示す模式図である。基板１がプラスチックフィルムなどの可撓性基板の場合、基板１の少なくとも一方の面に絶縁層６を配し、その上にゲート電極２、ゲート絶縁膜３、活性層４を積層して有し、その表面にソース電極５−１とドレイン電極５−２が設置される。
7) Structure Next, the structure of the TFT in the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic diagram illustrating an example of a TFT having an inverted stagger structure. When the substrate 1 is a flexible substrate such as a plastic film, an insulating layer 6 is disposed on at least one surface of the substrate 1, and a gate electrode 2, a gate insulating film 3, and an active layer 4 are laminated thereon. The source electrode 5-1 and the drain electrode 5-2 are provided on the surface.
図２は、本発明の別の態様のＴＦＴの一例を示す模式図である。活性層４１と抵抗層４２とが積層された構成を有する。活性層４１に対して抵抗層４２はより電気伝導度の低い組成にすることにより、ＴＦＴの移動度、ＯＮ／ＯＦＦ比、また駆動による閾値電圧の変動も改良されるので好ましい。活性層および抵抗層の電気伝導度は、上記の活性層のキャリア濃度の調整を用いて行うことができる。例えば、酸素濃度の調整により、電気伝導度を調節することができる。 FIG. 2 is a schematic view showing an example of a TFT according to another embodiment of the present invention. The active layer 41 and the resistance layer 42 are stacked. It is preferable that the resistance layer 42 has a lower electrical conductivity than the active layer 41 because the mobility of the TFT, the ON / OFF ratio, and the threshold voltage variation due to driving are improved. The electric conductivity of the active layer and the resistance layer can be performed by adjusting the carrier concentration of the active layer. For example, the electrical conductivity can be adjusted by adjusting the oxygen concentration.
８）保護絶縁膜
必要によって、ＴＦＴ上に保護絶縁膜を設けても良い。保護絶縁膜は、活性層または抵抗層の半導体層を大気による劣化から保護する目的や、ＴＦＴ上に作製される電子デバイスを絶縁する目的がある。
8) Protective insulating film If necessary, a protective insulating film may be provided on the TFT. The protective insulating film has a purpose of protecting the semiconductor layer of the active layer or the resistance layer from deterioration due to the atmosphere, and a purpose of insulating an electronic device manufactured over the TFT.
その具体例としては、ＭｇＯ、ＳｉＯ、ＳｉＯ２、Ａｌ２Ｏ３、ＧｅＯ、ＮｉＯ、ＣａＯ、ＢａＯ、Ｆｅ２Ｏ３、Ｙ２Ｏ３、又はＴｉＯ２等の金属酸化物、ＳｉＮｘ、ＳｉＮｘＯｙ等の金属窒化物、ＭｇＦ２、ＬｉＦ、ＡｌＦ３、又はＣａＦ２等の金属フッ化物、ポリエチレン、ポリプロピレン、ポリメチルメタクリレート、ポリイミド、ポリウレア、ポリテトラフルオロエチレン、ポリクロロトリフルオロエチレン、ポリジクロロジフルオロエチレン、クロロトリフルオロエチレンとジクロロジフルオロエチレンとの共重合体、テトラフルオロエチレンと少なくとも１種のコモノマーとを含むモノマー混合物を共重合させて得られる共重合体、共重合主鎖に環状構造を有する含フッ素共重合体、吸水率１％以上の吸水性物質、吸水率０．１％以下の防湿性物質等が挙げられる。 Specific examples thereof include MgO, SiO, SiO 2 , Al 2 O 3 , GeO, NiO, CaO, BaO, Fe 2 O 3 , Y 2 O 3 , or metal oxides such as TiO 2 , SiN x , SiN x. Metal nitride such as O y , metal fluoride such as MgF 2 , LiF, AlF 3 , or CaF 2 , polyethylene, polypropylene, polymethyl methacrylate, polyimide, polyurea, polytetrafluoroethylene, polychlorotrifluoroethylene, polydichloro Difluoroethylene, a copolymer of chlorotrifluoroethylene and dichlorodifluoroethylene, a copolymer obtained by copolymerizing a monomer mixture containing tetrafluoroethylene and at least one comonomer, and a cyclic structure in the copolymer main chain Fluorine-containing copolymer having water absorption of 1% or more And moisture-proof substances having a water absorption rate of 0.1% or less.
保護絶縁膜の形成方法については、特に限定はなく、例えば、真空蒸着法、スパッタリング法、反応性スパッタリング法、ＭＢＥ（分子線エピタキシ）法、クラスターイオンビーム法、イオンプレーティング法、プラズマ重合法（高周波励起イオンプレーティング法）、プラズマＣＶＤ法、レーザーＣＶＤ法、熱ＣＶＤ法、ガスソースＣＶＤ法、コーティング法、印刷法、又は転写法を適用できる。 The method for forming the protective insulating film is not particularly limited. For example, a vacuum deposition method, a sputtering method, a reactive sputtering method, an MBE (molecular beam epitaxy) method, a cluster ion beam method, an ion plating method, a plasma polymerization method ( High-frequency excitation ion plating method), plasma CVD method, laser CVD method, thermal CVD method, gas source CVD method, coating method, printing method, or transfer method can be applied.
９）後処理
必要によって、ＴＦＴの後処理として、熱処理を行っても良い。熱処理としては、温度１００℃以上で、大気下または窒素雰囲気下で行う。熱処理を行う工程としては、半導体層を成膜後でも良いし、ＴＦＴ作製工程の最後に行っても良い。熱処理を行うことにより、ＴＦＴの特性の面内バラつきが抑制される、駆動安定性が向上する等の効果がある。
9) Post-treatment If necessary, heat treatment may be performed as a post-treatment of the TFT. The heat treatment is performed at a temperature of 100 ° C. or higher in the air or in a nitrogen atmosphere. The heat treatment may be performed after the semiconductor layer is formed or at the end of the TFT manufacturing process. By performing the heat treatment, there are effects such as suppression of in-plane variation in TFT characteristics and improvement in driving stability.
２．表示装置
本発明の電界効果型薄膜トランジスタは、液晶やＥＬ素子を用いた画像表示装置、特に平面薄型表示装置（Ｆｌａｔ Ｐａｎｅｌ Ｄｉｓｐｌａｙ：ＦＰＤ）に好ましく用いられる。より好ましくは、基板に有機プラスチックフィルムのような可撓性基板を用いたフレキシブル表示装置に用いられる。特に、本発明の電界効果型薄膜トランジスタは、移動度が高いことから有機ＥＬ素子を用いた表示装置、フレキシブル有機ＥＬ表示装置に最も好ましく用いられる。
図３は、本発明のＴＦＴ素子を用いたアクティブマトリクス駆動型有機ＥＬ表示装置の等価回路の模式図である。本発明における有機ＥＬ表示装置の回路は、特に図３に示すものに限定されるものではなく、従来公知の回路をそのまま応用することができる。
2. Display Device The field effect thin film transistor of the present invention is preferably used for an image display device using liquid crystal or an EL element, in particular, a flat panel display (FPD). More preferably, it is used for a flexible display device using a flexible substrate such as an organic plastic film as the substrate. In particular, the field effect thin film transistor of the present invention is most preferably used for a display device using an organic EL element and a flexible organic EL display device because of its high mobility.
FIG. 3 is a schematic diagram of an equivalent circuit of an active matrix driving type organic EL display device using the TFT element of the present invention. The circuit of the organic EL display device in the present invention is not particularly limited to that shown in FIG. 3, and a conventionally known circuit can be applied as it is.
（応用）
本発明の電界効果型薄膜トランジスタは、液晶やＥＬ素子を用いた画像表示装置、特にＦＰＤのスイッチング素子、駆動素子として用いることができる。特に、フレキシブルＦＰＤ装置のスイッチング素子、駆動素子として用いるのが適している。さらに本発明の電界効果型薄膜トランジスタを用いた表示装置は、携帯電話ディスプレイ、パーソナルデジタルアシスタント（ＰＤＡ）、コンピュータディスプレイ、自動車の情報ディスプレイ、ＴＶモニター、あるいは一般照明を含む広い分野で幅広い分野で応用される。
また、本発明の電界効果型薄膜トランジスタは、表示装置以外にも、有機プラスチックフィルムのような可撓性基板上に本発明の電界効果型薄膜トランジスタを形成し、ＩＣカードやＩＤタグなどに幅広く応用が可能である。
(application)
The field effect thin film transistor of the present invention can be used as an image display device using a liquid crystal or an EL element, particularly as an FPD switching element or driving element. In particular, it is suitable for use as a switching element and a driving element of a flexible FPD device. Further, the display device using the field effect thin film transistor of the present invention is applied in a wide range of fields including a mobile phone display, a personal digital assistant (PDA), a computer display, an automobile information display, a TV monitor, or general lighting. The
In addition to the display device, the field effect thin film transistor of the present invention can be widely applied to IC cards, ID tags, etc. by forming the field effect thin film transistor of the present invention on a flexible substrate such as an organic plastic film. Is possible.
以下に、本発明の薄膜電界効果型トランジスタについて、実施例により説明するが、本発明はこれら実施例により何ら限定されるものではない。 Hereinafter, the thin film field effect transistor of the present invention will be described with reference to examples, but the present invention is not limited to these examples.
実施例１
１．ＴＦＴ素子の作製
基板として、無アルカリガラス基板（コー二ング社、品番イーグル２０００）を用いた。
Example 1
1. Fabrication of TFT element An alkali-free glass substrate (Corning, product number Eagle 2000) was used as the substrate.
＜ゲート電極＞
ＲＦマグネトロンスパッタ（条件：成膜温度２７℃、スパッタガスＡｒ＝１２ｓｃｃｍ、ＲＦパワー３８０Ｗ、成膜圧力０．３６Ｐａ）により、ゲート電極としてのＭｏ薄膜（厚み４０ｎｍ）を形成した。ゲート電極Ｍｏのパターニングには、スパッタ時にシャドウマスクを用いることにより行った。
<Gate electrode>
An Mo thin film (thickness 40 nm) was formed as a gate electrode by RF magnetron sputtering (conditions: film formation temperature 27 ° C., sputtering gas Ar = 12 sccm, RF power 380 W, film formation pressure 0.36 Pa). The gate electrode Mo was patterned by using a shadow mask during sputtering.
＜ゲート絶縁膜＞
次にゲート電極上に、下記のゲート絶縁膜の形成を行った。
ゲート絶縁膜：ＳｉＯｘをＲＦマグネトロンスパッタ真空蒸着法（条件：ターゲット多結晶焼結体ＳｉＯ２、成膜温度５４℃、スパッタガスＡｒ／Ｏ２（Ａｒ＝１２ｓｃｃｍ、Ｏ２ガス流量は表１に記す）、ＲＦパワー４００Ｗ、成膜圧力は表１に記す）にて２００ｎｍ形成し、ゲート絶縁膜を設けた。ゲート絶縁膜ＳｉＯｘのパターニングには、スパッタ時にシャドウマスクを用いることにより行った。
<Gate insulation film>
Next, the following gate insulating film was formed on the gate electrode.
Gate insulating film: SiO x by RF magnetron sputtering vacuum deposition method (conditions: target polycrystalline sintered body SiO 2 , film forming temperature 54 ° C., sputtering gas Ar / O 2 (Ar = 12 sccm, O 2 gas flow rate is shown in Table 1) The film was formed to 200 nm with an RF power of 400 W and a film formation pressure of Table 1), and a gate insulating film was provided. The gate insulating film SiO x was patterned by using a shadow mask during sputtering.
＜活性層＞
この上に、下記の活性層Ａを設けた。活性層のパターニングは、スパッタ時にシャドウマスクを用いることにより行った。
活性層Ａ：ＩｎＧａＺｎＯ４の組成を有する多結晶焼結体をターゲットとして、ＲＦマグネトロンスパッタ真空蒸着法により、Ａｒ流量９７ｓｃｃｍ、Ｏ２流量１．７ｓｃｃｍ、ＲＦパワー２００Ｗ、成膜圧力０．３８Ｐａの条件で厚み５０ｎｍに成膜を行った。
<Active layer>
On this, the following active layer A was provided. The active layer was patterned by using a shadow mask during sputtering.
Active layer A: conditions of Ar flow rate 97 sccm, O 2 flow rate 1.7 sccm, RF power 200 W, film forming pressure 0.38 Pa by RF magnetron sputtering vacuum deposition using a polycrystalline sintered body having a composition of InGaZnO 4 as a target. The film was formed to a thickness of 50 nm.
次いで、上記活性層Ａの上にソース電極及びドレイン電極として酸化インジウム錫（ＩＴＯ）をＲＦマグネトロンスパッタ真空蒸着法により、Ａｒ流量１２ｓｃｃｍ、ＲＦパワー４０Ｗ、成膜圧力０．３６Ｐａの条件で厚み４０ｎｍに成膜を行った。尚、ソース電極およびドレイン電極のパターニングには、スパッタ時にシャドウマスクを用いることにより行った。
以上により、本発明のＴＦＴ素子１〜４および比較のＴＦＴ素子１〜３を作製した。尚、作製したＴＦＴ素子のＴＦＴサイズは全て、チャネル長（Ｌ）＝２００μｍ、チャネル幅（Ｗ）＝１０００μｍである。
Next, indium tin oxide (ITO) as a source electrode and a drain electrode is formed on the active layer A by RF magnetron sputtering vacuum deposition so as to have a thickness of 40 nm under conditions of an Ar flow rate of 12 sccm, an RF power of 40 W, and a deposition pressure of 0.36 Pa. Film formation was performed. The source electrode and the drain electrode were patterned by using a shadow mask at the time of sputtering.
Thus, TFT elements 1 to 4 of the present invention and comparative TFT elements 1 to 3 were produced. The TFT sizes of the fabricated TFT elements are all channel length (L) = 200 μm and channel width (W) = 1000 μm.
２．性能評価
１）ゲート絶縁膜のダングリングボンド密度及び水素濃度の測定
ゲート絶縁膜ＳｉＯｘ中のＳｉダングリングボンド密度はＥＳＲ測定にて行い、ゲート絶縁膜ＳｉＯｘ中の水素濃度はＳＩＭＳにて行った。
2. Performance Evaluation 1) Measurement of dangling bond density and hydrogen concentration of gate insulating film Si dangling bond density in the gate insulating film SiOx was measured by ESR measurement, and hydrogen concentration in the gate insulating film SiOx was measured by SIMS.
２）ＴＦＴ性能の評価
得られた各ＴＦＴ素子について、飽和領域ドレイン電圧（Ｖｄ）＝１０Ｖ（ゲート電圧（Ｖｇ）：−１０Ｖ≦Ｖｇ≦１５Ｖ）でのＴＦＴ伝達特性の測定を行い、ＴＦＴの性能を評価した。ＴＦＴ伝達特性の測定は、半導体パラメータ・アナライザー４１５６Ｃ（アジレントテクノロジー社製）を用いて行った。各パラメータと本発明に於けるその定義は下記の通りである。
・ＴＦＴの閾値電圧（Ｖｔｈ）：ドレイン電流値がＷ／Ｌ×１０ｎＡとなるときのゲート電圧である。ここで、ＴＦＴサイズはＷ／Ｌ＝１０００／２００＝５であるので、ドレイン電流値が５０ｎＡとなる時のゲート電圧を用いた。
・ＯＦＦ電流（Ｉｏｆｆ）：閾値電圧より５Ｖ低いゲート電圧におけるドレイン電流値である。単位は［Ａ］である。
・ＯＮ電流（Ｉｏｎ）：閾値電圧より５Ｖ高いゲート電圧におけるドレイン電流である。
2) Evaluation of TFT performance For each of the obtained TFT elements, TFT transfer characteristics were measured at a saturation region drain voltage (Vd) = 10 V (gate voltage (Vg): −10 V ≦ Vg ≦ 15 V), and the TFT performance was measured. Evaluated. The measurement of TFT transfer characteristics was performed using a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies). Each parameter and its definition in the present invention are as follows.
TFT threshold voltage (Vth): a gate voltage when the drain current value is W / L × 10 nA. Here, since the TFT size is W / L = 1000/200 = 5, the gate voltage when the drain current value is 50 nA was used.
OFF current (Ioff): A drain current value at a gate voltage 5 V lower than the threshold voltage. The unit is [A].
ON current (Ion): drain current at a gate voltage 5 V higher than the threshold voltage.
・閾値電圧のシフト量（Ｖｔｈシフト）：各ＴＦＴ素子に電気ストレスとして、ゲート電圧Ｖｇ＝１０Ｖ、ドレイン電圧Ｖｄ＝０Ｖ（ドレイン電流＝０Ａ）を１０００秒加え、その前後のＴＦＴ閾値電圧の変動量（Ｖｔｈシフト）である。単位は［Ｖ］である。
Ｖｔｈシフトは駆動による特性変化の度合いを示すものであり、小さい方が好ましい。
Threshold voltage shift amount (Vth shift): As an electrical stress on each TFT element, gate voltage Vg = 10 V and drain voltage Vd = 0 V (drain current = 0 A) are applied for 1000 seconds, and the amount of fluctuation in TFT threshold voltage before and after that (Vth shift). The unit is [V].
The Vth shift indicates the degree of characteristic change due to driving, and is preferably smaller.
以上の測定結果から得られたＴＦＴ特性を表１に示した。
表１の結果より、本発明のＴＦＴはＳｉダングリングボンド密度を５×１０−１６ｃｍ−３以下にした本発明の素子は、比較例の素子より閾値シフトが改善され、閾値シフトを１０Ｖ未満まで改善できた。
The TFT characteristics obtained from the above measurement results are shown in Table 1.
From the results shown in Table 1, the TFT of the present invention has an Si dangling bond density of 5 × 10 −16 cm −3 or less, and the threshold shift of the element of the present invention is improved over that of the comparative example, and the threshold shift is less than 10V. I was able to improve.
実施例２
実施例１におけるＴＦＴ素子において、活性層Ａの代わりに下記の活性層Ｂと抵抗層を用いてその他は実施例１と同様にしてＴＦＴ素子を作製した。
ゲート絶縁膜の上に、順に、下記の活性層Ｂと抵抗層を配置した。
活性層Ｂ：ＩｎＧａＺｎＯ４の組成を有する多結晶焼結体をターゲットとして、ＲＦマグネトロンスパッタ真空蒸着法により、Ａｒ流量９７ｓｃｃｍ、Ｏ２流量０．８ｓｃｃｍ、ＲＦパワー２００Ｗ、成膜圧力０．３８Ｐａの条件で厚み１０ｎｍに成膜を行った。
抵抗層：ＩｎＧａＺｎＯ４の組成を有する多結晶焼結体をターゲットとして、ＲＦマグネトロンスパッタ真空蒸着法により、Ａｒ流量９７ｓｃｃｍ、Ｏ２流量２．０ｓｃｃｍ、ＲＦパワー２００Ｗ、成膜圧力０．３８Ｐａの条件で厚み４０ｎｍに成膜を行った。
Example 2
In the TFT element of Example 1, a TFT element was fabricated in the same manner as in Example 1 except that the following active layer B and resistance layer were used instead of the active layer A.
On the gate insulating film, the following active layer B and resistance layer were arranged in order.
Active layer B: conditions of Ar flow rate 97 sccm, O 2 flow rate 0.8 sccm, RF power 200 W, film forming pressure 0.38 Pa by RF magnetron sputtering vacuum deposition using a polycrystalline sintered body having a composition of InGaZnO 4 as a target. The film was formed to a thickness of 10 nm.
Resistance layer: A polycrystalline sintered body having a composition of InGaZnO 4 is used as a target by an RF magnetron sputtering vacuum deposition method under the conditions of an Ar flow rate of 97 sccm, an O 2 flow rate of 2.0 sccm, an RF power of 200 W, and a deposition pressure of 0.38 Pa. Film formation was performed to a thickness of 40 nm.
また、ガラス基板上にそれぞれ活性層Ｂおよび抵抗層を成膜した物性測定用サンプルを作製し、下記の方法により電気伝導度及びキャリア濃度を測定した。電気伝導度及びキャリア濃度の測定方法は以下の手法で求めた。 In addition, samples for measuring physical properties in which an active layer B and a resistance layer were formed on a glass substrate were prepared, and electric conductivity and carrier concentration were measured by the following methods. The measurement methods of electrical conductivity and carrier concentration were determined by the following methods.
−電気伝導度の測定方法−
物性測定用サンプルの電気伝導度は、サンプルの測定されたシート抵抗と膜厚から計算し求めた。ここで、シート抵抗をρ（Ω／□）、膜厚をｄ（ｃｍ）とすると、電気伝導度σ（Ｓｃｍ−１）は、σ＝１／（ρ＊ｄ）として算出される。
-Measuring method of electrical conductivity-
The electrical conductivity of the sample for measuring physical properties was calculated from the measured sheet resistance and film thickness of the sample. Here, when the sheet resistance is ρ (Ω / □) and the film thickness is d (cm), the electrical conductivity σ (Scm −1 ) is calculated as σ = 1 / (ρ * d).
本実施例において、物性測定用サンプルのシート抵抗１０７Ω／□未満の領域ではロレスタ−ＧＰ（三菱化学社製）、シート抵抗１０７Ω／□以上の領域ではハイテスタ−ＵＰ（三菱化学社製）を用いて２０℃の環境下で行った。物性測定用サンプルの膜厚測定には触針式表面形状測定器ＤｅｋＴａｋ−６Ｍ（ＵＬＶＡＣ社製）を用いた。 In this example, (manufactured by Mitsubishi Chemical Corporation) Loresta -GP in sheet resistance 10 7 Ω / □ of less than area of the sample for measuring physical properties, high tester -UP (manufactured by Mitsubishi Chemical Corporation in sheet resistance 10 7 Ω / □ or more regions ) In an environment of 20 ° C. A stylus type surface shape measuring device DekTak-6M (manufactured by ULVAC) was used for measuring the film thickness of the sample for measuring physical properties.
−ホール効果測定法によるキャリア濃度測定−
物性測定用サンプルのキャリア濃度の測定には、ＲｅｓｉＴｅｓｔ８３００型（東陽テクニカ社製）を用いてホール効果測定を行うことにより求めた。ホール効果測定は２０℃の環境下で行った。尚、ホール効果測定を行うことにより、キャリア濃度だけではなく、キャリアのホール移動度も求めることができる。
-Carrier concentration measurement by Hall effect measurement method-
The carrier concentration of the sample for measuring physical properties was measured by performing Hall effect measurement using ResiTest 8300 type (manufactured by Toyo Technica Co., Ltd.). Hall effect measurement was performed in an environment of 20 ° C. By measuring the Hall effect, not only the carrier concentration but also the hole mobility of the carrier can be obtained.
その結果、下記のように活性層Ｂが抵抗層より高い電気伝導を有していた。
＜活性層Ｂ＞ 電気伝導度：２．０×１０１Ｓｃｍ−１、キャリア濃度：８．９×１０１８ｃｍ−３。
＜抵抗層＞ 電気伝導度：２．０×１０−６Ｓｃｍ−１、キャリア濃度：１．６×１０１２ｃｍ−３。
As a result, the active layer B had higher electrical conductivity than the resistance layer as described below.
<Active layer B> Electrical conductivity: 2.0 × 10 1 Scm −1 , carrier concentration: 8.9 × 10 18 cm −3 .
<Resistance layer> Electrical conductivity: 2.0 × 10 −6 Scm −1 , carrier concentration: 1.6 × 10 12 cm −3 .
得られた素子について実施例１と同様に性能を評価した。得られた結果を表２に示した。
表２の結果より、実施例１と同様に本発明の素子は、比較例の素子より閾値シフトが改善され、また、抵抗層を挿入する構成にすることにより、閾値シフトは５Ｖ未満まで改善した。
The performance of the obtained device was evaluated in the same manner as in Example 1. The obtained results are shown in Table 2.
From the results shown in Table 2, the threshold shift of the device of the present invention was improved as compared with the device of the comparative example as in Example 1, and the threshold shift was improved to less than 5 V by adopting a configuration in which a resistance layer was inserted. .
実施例３
実施例１におけるＴＦＴ素子において、無アルカリガラス基板の代わりに、ポリエチレンナフタレートフィルム（厚み１００μｍ）の両面に下記バリア機能を持つ絶縁層を有するバリア付きフイルムを用いて、その他は実施例１と同様にしてＴＦＴ素子を作製した。
Example 3
In the TFT element of Example 1, a film with a barrier having an insulating layer having the following barrier function on both sides of a polyethylene naphthalate film (thickness: 100 μm) was used instead of the alkali-free glass substrate, and the others were the same as in Example 1. Thus, a TFT element was produced.
絶縁層：ＳｉＯＮを５００ｎｍの厚みに蒸着した。ＳｉＯＮの蒸着にはＲＦマグネトロンスパッタリング蒸着法（スパッタリング条件：ターゲットＳｉ３Ｎ４、ＲＦパワー４００Ｗ、ガス流量Ａｒ／Ｏ２＝１２／３ｓｃｃｍ、成膜圧力０．４５Ｐａ）を用いた。 Insulating layer: SiON was deposited to a thickness of 500 nm. For the deposition of SiON, an RF magnetron sputtering deposition method (sputtering conditions: target Si 3 N 4 , RF power 400 W, gas flow rate Ar / O 2 = 12/3 sccm, film forming pressure 0.45 Pa) was used.
得られた素子について実施例１と同様に性能を評価した。得られた結果を表３に示した。
その結果、実施例１と同様に本発明の素子は、比較例の素子より閾値シフトが改善された。
The performance of the obtained device was evaluated in the same manner as in Example 1. The obtained results are shown in Table 3.
As a result, the threshold shift of the device of the present invention was improved as compared with the device of the comparative example as in Example 1.
実施例４
１．ＴＦＴ素子の作製
実施例１におけるＴＦＴ素子において、ゲート絶縁膜ＳｉＯｘをスパッタではなく、ＳｉＨ４＋Ｎ２Ｏガスを用いたＩＣＰ−ＣＶＤにて２００ｎｍ成膜した。その他は実施例１と同様にして、それぞれ比較のＴＦＴ素子３０を作製した。
Example 4
1. Fabrication of TFT Element In the TFT element in Example 1, the gate insulating film SiOx was formed to 200 nm by ICP-CVD using SiH 4 + N 2 O gas instead of sputtering. Other than that, in the same manner as in Example 1, comparative TFT elements 30 were produced.
２．性能評価
得られた素子について実施例１の本発明の素子１と共に実施例１と同様にＴＦＴ性能を評価した。得られた結果を表４に示した。
2. Performance Evaluation The TFT performance of the obtained device was evaluated in the same manner as in Example 1 together with the device 1 of the present invention in Example 1. The results obtained are shown in Table 4.
その結果、比較のＴＦＴ素子３０は水素濃度が１０２１ｃｍ−３を超える高い値を示した。
また、比較のＴＦＴ素子３０のＴＦＴ性能は、閾値シフトが本発明の素子と同程度であるが、閾値電圧がマイナスとなりノーマリオン状態となり、しかもＯＦＦ電流が本発明素子より上昇し、好ましくない。これは、水素濃度が高いことが影響したものである。水素濃度が高くなることは、ＩＣＰ−ＣＶＤでゲート絶縁膜ＳｉＯｘを成膜する成膜方法に伴って生じる避けがたい現象である。
As a result, the comparative TFT element 30 showed a high value in which the hydrogen concentration exceeded 10 21 cm −3 .
Further, the TFT performance of the comparative TFT element 30 is not preferable because the threshold shift is about the same as that of the element of the present invention, but the threshold voltage becomes negative and a normally-on state is obtained, and the OFF current increases from the element of the present invention. This is due to the high hydrogen concentration. The increase in the hydrogen concentration is an unavoidable phenomenon that occurs with the film formation method of forming the gate insulating film SiOx by ICP-CVD.
実施例５
１．有機ＥＬ表示装置の作製
（有機ＥＬ素子部の作製）
１）下部電極の形成
基板にはポリエチレンナフタレートフィルムの両面に下記バリア機能を持つ絶縁層を有するバリア付きフイルムを用いた。前記基板の上に酸化インジウム錫（以後、ＩＴＯと略記）を１５０ｎｍの厚さで蒸着し、陽極とした。
Example 5
1. Production of organic EL display device (production of organic EL element part)
1) Formation of lower electrode A film with a barrier having an insulating layer having the following barrier function on both sides of a polyethylene naphthalate film was used for the substrate. Indium tin oxide (hereinafter abbreviated as ITO) was deposited on the substrate to a thickness of 150 nm to form an anode.
２）有機層の形成
洗浄後、順次、正孔注入層、正孔輸送層、発光層、正孔ブロッキング層、電子輸送層、および電子注入層を設けた。
2) Formation of organic layer After washing, a hole injection layer, a hole transport layer, a light emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer were sequentially provided.
各層の構成は、下記の通りである。各層はいずれも抵抗加熱真空蒸着により設けた。
正孔注入層：４，４’，４”−トリス（２−ナフチルフェニルアミノ）トリフェニルアミン（２−ＴＮＡＴＡと略記する）および２，３，５，６−テトラフルオロ−７，７，８，８−テトラシアノキノジメタン（Ｆ４−ＴＣＮＱと略記する）を２−ＴＮＡＴＡに対して１質量％含有する層、厚み１６０ｎｍ。
正孔輸送層：Ｎ，Ｎ’−ジナフチル−Ｎ，Ｎ’−ジフェニル−［１，１’−ビフェニル］−４，４’−ジアミン（α−ＮＰＤと略記する）、厚み１０ｎｍ。
発光層：１，３−ｂｉｓ（ｃａｒｂａｚｏｌ−９−ｙｌ）ｂｅｎｚｅｎｅ（ｍＣＰと略記する）および白金錯体Ｐｔ−１をｍＣＰに対して１３質量％含有する層、厚み６０ｎｍ。
正孔ブロック層：ｂｉｓ−（２−ｍｅｔｈｙｌ−８−ｑｕｉｎｏｎｙｌｐｈｅｎｏｌａｔｅ）ａｌｕｍｉｎｉｕｍ（ＢＡｌｑと略記する）、厚み４０ｎｍ。
電子輸送層：トリス（８−ヒドロキシキノニナート）アルミニウム（Ａｌｑ３と略記する）、厚み１０ｎｍ。
電子注入層：ＬｉＦ、厚み１ｎｍ。
The configuration of each layer is as follows. Each layer was provided by resistance heating vacuum deposition.
Hole injection layer: 4,4 ′, 4 ″ -tris (2-naphthylphenylamino) triphenylamine (abbreviated as 2-TNATA) and 2,3,5,6-tetrafluoro-7,7,8, A layer containing 1% by mass of 8-tetracyanoquinodimethane (abbreviated as F4-TCNQ) with respect to 2-TNATA, a thickness of 160 nm.
Hole transport layer: N, N′-dinaphthyl-N, N′-diphenyl- [1,1′-biphenyl] -4,4′-diamine (abbreviated as α-NPD), thickness 10 nm.
Light-emitting layer: a layer containing 13% by mass of 1,3-bis (carbazol-9-yl) benzone (abbreviated as mCP) and platinum complex Pt-1 with respect to mCP, thickness 60 nm.
Hole blocking layer: bis- (2-methyl-8-quinonylphenolate) aluminum (abbreviated as BAlq), thickness 40 nm.
Electron transport layer: Tris (8-hydroxyquinoninate) aluminum (abbreviated as Alq3), thickness 10 nm.
Electron injection layer: LiF, thickness 1 nm.
３）上部電極
素子サイズが２ｍｍ×２ｍｍとなるようにシャドウマスクによりパターニングしてＡｌを厚み１００ｎｍに蒸着し、陰極とした。
3) Upper electrode It patterned by the shadow mask so that element size might be set to 2 mm x 2 mm, and Al was vapor-deposited in thickness of 100 nm, and it was set as the cathode.
（保護絶縁膜）
上部電極上に、保護絶縁膜として５００ｎｍのＳｉＯＮ膜をイオンプレーティング法により成膜した。
(Protective insulating film)
A 500 nm SiON film was formed on the upper electrode as a protective insulating film by an ion plating method.
以下に実施例に用いた化合物の構造を示す。 The structures of the compounds used in the examples are shown below.
（駆動試験）
得られた有機ＥＬ素子と実施例１〜３で作製したＴＦＴとを組みあわせて等価回路を構成し、種々の条件下で駆動試験を行った。
その結果、本発明のＴＦＴを用いると連続して長時間駆動させても安定した発光が得られた。
(Driving test)
An equivalent circuit was configured by combining the obtained organic EL element and the TFTs produced in Examples 1 to 3, and driving tests were performed under various conditions.
As a result, when the TFT of the present invention was used, stable light emission was obtained even when continuously driven for a long time.
１：基板
２：ゲート電極
３：ゲート絶縁膜
４：活性層
４１：活性層
４２：抵抗層
５−１：ソース電極
５−２：ドレイン電極
６：絶縁層
２００：スイッチングＴＦＴ
３００：有機ＥＬ素子
４００：信号電極線
５００：走査電極線
６００：コンデンサ
７００：駆動ＴＦＴ
８００：共通電線
1: Substrate 2: Gate electrode 3: Gate insulating film 4: Active layer 41: Active layer 42: Resistance layer 5-1: Source electrode 5-2: Drain electrode 6: Insulating layer 200: Switching TFT
300: Organic EL element 400: Signal electrode line 500: Scan electrode line 600: Capacitor 700: Drive TFT
800: Common wire
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| KR20160098497A (en) | 2013-12-25 | 2016-08-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| US9478664B2 (en) | 2013-12-25 | 2016-10-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US9722056B2 (en) | 2013-12-25 | 2017-08-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US10050132B2 (en) | 2013-12-25 | 2018-08-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| CN107749423A (en) * | 2017-10-12 | 2018-03-02 | 华南理工大学 | A kind of amorphous oxides flexible thin-film transistor and preparation method thereof |
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