JP2009218302A - Method and device for electrolytic plating of semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of filling plating in a through-hole of a silicon wafer having the through-hole without any overhang shape and any internal void. <P>SOLUTION: The plating is performed by arranging towards a plating electrode side a plate with an opening at the same place as a through-hole opening in the silicon wafer by keeping a fixed distance and by making a plate opening consistent with the through-hole opening in the silicon wafer. A diameter of the plate opening is made somewhat smaller than a diameter R of the through-hole opening. When x/R is 0.1 to 0.3 where a difference between the diameter of the plate opening and the diameter R of the through-hole opening is set to 2x, and when a distance between the silicon wafer and a plate is set to 0.05 mm to 1.0 mm, the above described problem can be achieved. It is desirable that the plate is made of an insulator such as a porosity ceramic and a porous material, and a plating growth of a silicon wafer surface can be also suppressed. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to wiring formation in a through hole in a semiconductor device having a through hole.

  In recent years, semiconductor devices have been remarkably miniaturized and highly integrated, and three-dimensional stacking technology for semiconductor devices has been developed as a next-generation technology. In particular, research on through wiring formation technology, which is the key to three-dimensional stacking, is active. The formation of the through wiring includes a technique for forming a through hole and a technique for forming a wiring in the through hole.

  As a method of forming a through hole, for example, a first surface (hereinafter referred to as a front surface) of a semiconductor substrate on which a semiconductor device is formed is connected to a surface I from a second surface (hereinafter referred to as a back surface) opposite to the first surface. In the case where the through hole is formed toward the / O (input / output) pad, the through hole is formed using, for example, a dry etching apparatus.

As a technique for forming the wiring in the through hole, a method by electrolytic plating is generally known. As a method, additives that control the promotion and suppression of plating are prepared, the current value is changed in multiple stages, the plating solution is stirred up, the circulation of the solution into the through hole is promoted, and the current is pulsed. (Reverse), etc., and plating is usually performed alone, or plating is performed by combining a plurality of these.

Patent Document 1 (Japanese Patent Application Laid-Open No. 2003-328185) is an example of combining additive components and current flow, and Patent Document 2 (Japanese Patent Application Laid-Open No. 2006-111896) and Patent Document 3 (Japanese Patent Application Laid-Open No. 2006-111896) are examples of further developed methods. -351968). Further, in order to eliminate stirring of the plating solution and reduce the size of the apparatus, a device such as Patent Document 4 (Japanese Patent Laid-Open No. 2007-231315) has been proposed. Those proposed in these patent documents have the following features and problems.

For example, a technique of adding an additive to a plating solution and plating the inside of the through hole as in Patent Document 1 is generally performed, but the filling condition in the through hole varies greatly with respect to the variation in additive concentration. Therefore, frequent adjustment of the additive component is necessary, and there is a drawback that it takes labor. Furthermore, it is characterized in that the plating electrolysis is reversed between the positive electrolysis and the reverse electrolysis, but there is a drawback that an expensive power supply needs to be purchased. In the case of an apparatus configuration that requires a high current density power source and a low current density power source as in Patent Document 2, a disadvantage is that two types of power sources are required. Furthermore, since the surface plating thickness is not particularly controlled in these technologies, it is necessary to remove the surface plating film by polishing, etching, etc. after completely filling the inside of the through hole. An increase in man-hours is a drawback. Furthermore, since the stress applied to the object to be plated increases as the plating thickness increases, there is a disadvantage that the probability of occurrence of peeling of the plating film, warping or breakage of the object to be plated increases.
JP2003-328185 JP 2006-111896 JP 2006-351968 JP2007-231315

  As described above, the plating methods according to the above-mentioned patent documents that have been used or proposed in the past have their respective features but also have drawbacks. Furthermore, even if plating is performed in the through hole using any one of these plating methods or a combination of these, the plating does not grow sufficiently in the deep part or bottom of the through hole, and the vicinity of the opening of the through hole 9 is fast, the corner 93 of the opening of the through-hole 92 shown in FIG. 9A becomes an abnormally grown plating shape, that is, an overhang shape 94, and when the plating film 95 is further grown, FIG. As shown in (b), the vicinity of the opening of the through hole is closed by plating, and a large void 96 is formed inside the through hole. Such overhang shapes and formation of internal voids are more prominent as the opening is narrower, the through hole is deeper, and the aspect ratio (depth of the through hole / opening diameter) is larger.

  In such a state where the overhang shape or void is formed, the plated wiring connected to the electrode of the through hole bottom 97 is very thin, so that sufficient contact resistance cannot be obtained, and the yield of the product is greatly reduced. cause. Further, since the plated wiring is very thin at the bottom of the through hole or the side surface of the through hole, there is a possibility of cutting with a slight current density, which causes a problem in product reliability. Further, when the vicinity of the opening of the through hole is blocked by plating and a large void (cavity) is formed inside the through hole, the plating solution remains in the void and adversely affects the reliability of the product.

  The present invention solves the above-described problems and provides a plating forming method free from overhang shapes and internal voids.

  The present invention is characterized in that a plate having an opening at the same position as a through hole opened in a semiconductor substrate is disposed between the semiconductor substrate and the electrode. The opening of the plate and the opening of the through hole of the semiconductor substrate are accurately aligned and immersed in the plating solution. The opening diameter of the plate is smaller than the opening diameter of the through hole of the semiconductor device. The plate is not in contact with the semiconductor substrate but is close to it. The material of the plate is preferably an insulator, and is porous to such an extent that the plating solution can penetrate.

  In the present invention, by arranging the plate in the vicinity of the semiconductor substrate surface or back surface (flat surface) on the side where the through hole exists, current concentration at the corner of the through hole opening can be suppressed. The plating growth is promoted. As a result, the occurrence of an overhang shape or internal voids in the through hole is eliminated. Furthermore, since the region other than the through-hole portion on the front or back surface of the semiconductor substrate (mainly a flat portion) is shielded by the plate, plating growth is suppressed, so it is necessary to polish the excess plating after plating. Disappear. Moreover, since the plate uses a porous material, the plating solution passes through the porous portion of the plate and reaches the surface (or the back surface) of the semiconductor substrate. Since the current also passes through the same route and reaches the plating surface, the growth of plating proceeds, but the amount thereof is small compared to the opening of the plate. As a result, the plating growth on the plating surface is greatly suppressed, and when the inside of the through hole is filled with plating, the plating thickness on the wafer surface (or back surface) becomes an appropriate thickness for wiring formation.

  As described above, by using the present invention, the inside of the through hole is completely filled with the plating metal, so that the contact resistance with the I / O pad electrode is improved, the product yield is improved, and the through hole is passed even if a high current flows. The problem of wiring disconnection inside the hole is eliminated. Furthermore, since there is no void, the plating solution does not remain inside the through hole, and the reliability of the product is greatly improved.

  FIG. 1 shows a semiconductor substrate in which a through hole is formed. Examples of the semiconductor substrate include single-element semiconductor materials such as silicon (Si) and germanium, binary compound semiconductor materials such as gallium arsenide and indium phosphide, and multi-element compound semiconductor materials composed of multi-element compounds. The present invention can also be applied to an insulating substrate such as a glass substrate or a ceramic substrate that is not a semiconductor substrate, or a through hole formed in a conductive substrate. In the following description, for convenience of description, this substrate is described as a “silicon wafer” which is a silicon substrate. The through-hole is usually formed by dry etching, but may be formed by wet etching, laser etching, ion milling, a drill method, or the like. The through hole is opened from the back surface of the silicon wafer 1 and reaches the I / O pad 2 (actually, the back side) of the surface of the silicon wafer 1. (In FIG. 1, the back surface of the silicon wafer 1 is up and the surface of the silicon wafer 1 is down.) The I / O pad 2 on the surface of the silicon wafer 1 is exposed at the bottom of the through hole 5. The I / O pad is an electrode and is formed of aluminum (Al) or the like. The side wall (side surface) of the through hole 5 and the back surface of the silicon wafer 1 are covered with an insulating film 6. (However, there may be a part where a part of the window is opened.) The insulating film 6 is a silicon oxide film (SiO film) formed by a chemical vapor deposition (CVD) method, a sputtering method, or the like. A nitride film (SiN film), a silicon oxynitride film (SiON film) or the like is formed. After the formation, the insulating film laminated on the I / O pad 2 at the bottom of the through hole 5 is selectively removed. Thereafter, a metal film for electrolytic plating, a so-called seed layer 8 is formed. The seed layer 8 is usually copper (Cu), but may be another metal film, and is also formed by CVD, sputtering, or vapor deposition. Alternatively, it may be formed by electroless plating. Titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten as a barrier film 7 (so-called barrier metal) in order to provide adhesion with the insulating film 6 and diffusion barrier properties. A metal film such as (W) or chromium (Cr) may be formed between the seed layer 8 and the insulating film 6.

  Although the insulating film 3 normally exists under the I / O pad, the insulating film 3 directly under the I / O pad is removed when the through hole is formed. Further, the surface of the I / O pad and the surface of the silicon wafer are protected by the protective film 4, but a part of the surface of the I / O pad is used as shown in FIG. Although generally open, semiconductor devices are diversified, and there are some substrates in which the I / O pad surface is not open.

  In some cases, a support substrate such as a glass substrate is bonded to the surface of the silicon wafer 1 via a bonding layer. When such a support substrate is bonded to the silicon wafer 1, the thickness of the silicon wafer 1 can be made thinner than that of the silicon wafer alone, so that the depth of the through hole 5 can be reduced, and etching of the through hole 5 and through holes can be performed. When the insulating film 6, the barrier metal 7, and the seed layer 8 are formed inside 5, the coverage becomes good, which is advantageous in various aspects. Of course, it becomes easier to plate the inside of the through-hole described later.

  Next, a method of plating the silicon wafer having the through holes shown in FIG. 1 using the present invention will be described.

  FIG. 2 shows the plate 10 of the present invention having an opening at the same position as the through hole 5 formed in the silicon wafer 1. The plate 10 is literally a plate-like object, and the material of the plate is not particularly defined. However, the plate 10 is resistant to the plating solution at least at a portion in contact with the plating solution, and further from a position other than the opening at the same position as the object to be plated. It is also desirable that the liquid is a porous material that exudes liquid. Moreover, what does not conduct electrically is desirable. Furthermore, since it is necessary to accurately align the opening 11 of the plate with the through hole 5 formed in the silicon wafer 1, the plate material must be a material that can be accurately and accurately formed. Examples of the plate that satisfies these conditions include a porous ceramic plate and a porous polymer plate. Although FIG. 2 shows the cross section, the plate is shown as being divided. However, in actuality, the opening is formed in a plate that is open only through the through hole 5 of the silicon wafer 1, that is, a plate-like one. 11 is formed, the plate can be handled as an integral object. The opening to the plate is formed by laser, drill, sandblasting, etching or the like, but is not particularly limited as long as it can be formed with high accuracy. Further, the opening to the plate should be precisely formed especially at the position of the through hole 5 of the silicon wafer 1 and does not swell when immersed in the plating solution, and the plate 10 is always in the through hole 5 of the silicon wafer 1 during plating. It is important that the openings 11 of each other are joined together.

  In such a state as shown in FIG. 2, that is, in the state where the opening of the through hole 5 on the back surface of the silicon wafer 1 is aligned with the opening 11 of the plate and a space is provided between the plate and silicon, copper sulfate plating is performed. It is immersed in a liquid, and electroplating is performed on the back surface and through holes of the silicon wafer 1. That is, with the silicon wafer 1 as one electrode (cathode), the plate 10 is disposed between the plating electrode (anode) and the silicon wafer 1, and electrolytic plating is performed by passing a current between the electrodes.

  In FIGS. 3 to 6 to be described below, the illustration is simplified for easy understanding, and the I / O pad 2, the insulating film 3, the protective film 4, the insulating film 6, as shown in FIGS. The barrier film 7 and the seed layer 8 are omitted, and only the through holes 5 are formed in the silicon wafer 1, but the structure of the silicon wafer in which the through holes before electrolytic plating are actually formed is shown in FIG. And the same as FIG. (As shown in FIGS. 3 to 6, when the silicon 1 is exposed in the through hole 5 and on the back surface of the silicon wafer 1, the silicon wafer itself is also a conductor, and as shown in FIGS. 1 and 2. Since the state is the same as the state covered with the seed layer 8, electrolytic plating can be performed in the through hole 5 and the back surface of the silicon wafer 1 shown in FIGS. 3 to 6 in the same manner as the silicon wafer 1 covered with the seed layer 8. .)

  FIG. 3 schematically shows the growth of plating when electrolytic plating is performed on the silicon wafer 1 having the through holes 5. Although only one through hole 5 is shown, the same applies to the other through holes. When an electric field is applied between the electrodes, current flows and plating starts, and the plating solution is supplied into the through hole 5 from the opening 11 of the plate, and between the bottom of the through hole 5 and the electrode at the top of the plate. An electric field is applied uniformly. On the other hand, since the back surface 12 of the silicon wafer 1 is covered with the plate 10, the plating solution is not sufficiently supplied. Further, the electric field is also relaxed by the plate 10 on the back surface 12 of the silicon wafer 1. Due to the shielding effect of the plate, the plating growth rate of the through-hole bottom 13 is considerably higher than the plating growth rate of the back surface 12 of the silicon wafer 1. Further, since the electric field on the side surface (through hole side surface) 14 of the through hole 5 is weaker than that of the through hole bottom portion 13, the plating growth rate on the through hole side surface 14 is the plating growth rate on the through hole bottom portion 13 and the plating on the back surface 12 of the silicon wafer 1. It is in the middle of the growth rate. As a result, as shown in FIG. 3 (a), when the plating film 15 bottoms up from the through hole bottom 13 and the plating proceeds further, as shown in FIG. 3 (b), the bottom of the through hole 13 is gradually buried, and the diameter of the through hole 5 is narrowed from the side surface 14 of the through hole. When the plating is further advanced, the through hole 5 is completely filled as shown in FIG. Moreover, it is possible to prevent defects such as voids from remaining in the plating film 15 filling the through holes 5.

  On the other hand, since the growth of the plating film on the back surface 12 of the silicon wafer 1 is slow, the growth rate is small. However, since the plate is porous, fresh plating solution from the outside of the plate gradually oozes through the gaps between the plates, and thus grows to some extent.

  As schematically shown in FIG. 3C, it is possible to obtain a substantially flat back surface of the silicon wafer 1 by stopping the plating with the through hole 5 completely filled. Moreover, according to a required use, it can also be used as an electrode by stopping plating in the state of FIG. 3 (a) or (b), for example.

  As described above, when the plate of the present invention is used, the plating inside the through hole is promoted. The reason for this is considered as follows.

  First, usually, in electroplating, the current distribution is not uniform depending on the shape of the plated object, so that the current density varies depending on the location. For example, the current concentrates on the convex part of the plated product and hardly flows into the concave part. Therefore, the current distribution in the through hole portion is as shown in FIG. 4 (current flow is schematically indicated by arrows. The density of the arrows may be considered as the current density), and the corner portion (convex portion) of the through hole opening portion. However, the current density in the through hole becomes sparse, particularly at the bottom of the through hole, and the plating growth rate becomes slow. As a result, the opening grows abnormally and becomes an overhang, and eventually the upper part of the through hole, that is, the opening is closed, leaving a void (cavity) in the through hole as shown in FIG. 9B. It becomes a shape.

  On the other hand, by installing the plate of the present invention on the plating surface, the corners (convex parts) of the openings of the through holes are covered with the plate 10 (to some extent) as shown in FIG. Becomes sparse, and current concentration at the corners of the opening can be suppressed. As a result, the plating growth at the opening corner is slow. On the other hand, since the plate is open inside the through-hole, the electric field is directly applied to the bottom of the through-hole, so that the current density becomes dense. In particular, the plating speed is increased at the bottom of the through-hole and the plating growth is promoted. . Since the current is bent at the side surface portion 14 of the through hole, the current density is not increased so much, but the current density is larger than the back surface 12 of the silicon wafer covered with the plate 10 and the plating growth is faster. As a result, in the through hole, plating rapidly proceeds from the bottom 13 of the through hole, and the plating film bottoms up. In combination with the plating growth from the side 14 of the through hole, plating without voids (cavities) is formed inside the through hole. The state filled with can be obtained. As can be seen from FIG. 5, it is important to make the opening diameter of the plate somewhat smaller than the opening diameter of the through hole. That is, when the plate opening is aligned with the through-hole, if the corner of the through-hole is slightly hidden by the plate when viewed from above, the electric field is not directly applied to the corner of the through-hole. (Or, if current does not enter directly (linearly) and wraps around the corners of the through holes, current concentration is considerably suppressed.) As a result, abnormal growth of plating at the corners of the through holes can be prevented considerably and overhang There is no longer a plating of shape.

  Further, since the plating surface (that is, the back surface of the silicon wafer 1) is shielded by the plate, the electric field is cut off and the supply amount of the plating solution is very small when the plate is an insulator. Growth is considerably suppressed. However, in the through wiring plating process, it is necessary to grow the plating to some extent on the back surface of the silicon wafer so that it can be used as a wiring. For this reason, the plate of the present invention uses a porous material. That is, the plating solution passes through the porous portion of the plate 10 as shown by the dotted line in FIG. A so-called plating solution oozes out the plate 10 and is supplied to the back surface 12 of the silicon wafer. Further, the current also passes through the same route and reaches the plating surface (silicon wafer back surface 12). As a result, although the plating solution supply amount is small, a fresh plating solution is always supplied and the current density is small, so that the plating grows slowly. Therefore, the amount of plating is small compared to the opening of the plate, and thereby the plating growth on the plating surface is greatly suppressed, and when the inside of the through hole is filled with plating, the wafer surface (silicon wafer back surface 12) The plating thickness is appropriate for wiring formation.

  In the conventional plating method without a plate, the plating thickness on the back surface of the silicon wafer is large, and the plating thickness is adjusted (as a wiring layer) by polishing or etching, but the plating method of the present invention is used. Thus, this plating thickness adjustment process can be eliminated.

  The results of investigations on the opening diameter of the plate of the present invention and the state of plating growth are shown below. The sample used was an 8-inch silicon wafer having the structure shown in the above description. The method for preparing the sample is as described above, but a brief description is as follows. After bonding the surface of the silicon wafer to the glass substrate, the back surface of the silicon wafer was thinned by polishing (although the initial thickness of the silicon wafer was 725 μm) to about 200 μm (micron meter). A through hole was formed from the back surface of the silicon wafer and penetrated to the I / O pad existing on the surface of the silicon wafer. Thereafter, a silicon oxide film was grown by the CVD method to cover the silicon substrate inside the through hole and the back surface of the silicon wafer. Thereafter, the silicon oxide film at the bottom of the through hole was selectively removed to expose the I / O pad at the bottom of the through hole. Next, a titanium film as a barrier metal and a copper film as a seed layer were laminated to obtain a sample of the present invention. The through hole of the sample used in the experiment has an opening diameter of 100 μm, a through hole depth of 200 μm, and a through hole bottom diameter of 80 μm. Aspect ratio = through hole depth / opening diameter = 2.0. After producing plates having various opening diameters and growing the plating, cross-sectional SEM observation of the through-hole portion was performed and evaluation as shown in FIGS.

  FIG. 6 schematically shows the shape of the plating film grown on the through hole. As described above, the laminated film is omitted for convenience of explanation. Further, the through hole bottom diameter and the through hole opening diameter are actually somewhat different, and the actual through hole side surface 63 is inclined with respect to the through hole bottom surface 62, but is shown as being vertical in FIG. The opening diameter of the through hole 65 is R, and the distance between the opening end of the through hole 65 and the opening end of the plate 67 is x. Since the opening diameter 68 of the plate is (R-2x), it indicates that the opening diameter 68 of the plate becomes smaller than the opening diameter of the through hole 65 as (x / R) increases. In addition, regarding the copper thickness after plating, the copper thickness of the silicon wafer back surface 64 is a (um), the copper thickness of the through hole corner portion (convex portion) is r (um), and the copper thickness on the through hole bottom surface 62 is c ( um). r is an index for checking the degree of plating growth in the through hole opening, and represents the distance to the farthest point from the through hole opening end. The distance between the device surface and the plate is y (mm). The alignment of the silicon wafer and the plate was performed using a normal aligner, and the silicon wafer and the plate were fixed using a fixing jig for fixing the periphery. The alignment accuracy at this time was + -2 um. The fixing jig is a stainless steel material coated with a non-conductive material.

  FIG. 7 shows the relationship between the plate opening diameter (x / R) and the plating growth (2r / c) with respect to the through-hole opening diameter. The horizontal axis (x / R) indicates that the opening diameter of the plate decreases as it increases, and 0.5 indicates that there is no plate opening. The vertical axis (2r / c) represents the ratio between the plating growth at the hole bottom and the plating growth rate at the opening. The negative horizontal axis (x / R) indicates that x is negative, that is, the opening diameter 68 of the plate is larger than the opening diameter R of the through hole. When the opening diameter 68 of the plate is larger than the opening diameter R of the through-hole, it can be seen that the current is concentrated at the corner of the through-hole as described above and the plating growth becomes very fast. Even when the opening diameter 68 of the plate is equal to the opening diameter R of the through hole (when x / R = 0), there are about 4 (2r / c), and the growth rate of the plating at the bottom (bottom) of the through hole is increased. However, it can be seen that the through hole is blocked along the way. However, when the opening diameter 68 of the plate is slightly smaller than the opening diameter R of the through-hole (that is, x becomes slightly positive), (2r / c) decreases rapidly, and (x / R) is 0.1 and 0. .5 or less. Since the aspect ratio of the through hole used in this sample is 2.0, in order to bottom up the plating growth and fill the through hole with the plating film, (2r / c) needs to be 0.5 or less. There is. Therefore, it can be seen from FIG. 7 that (x / R) is 0.1 or more in the bottom-up condition. That is, the bottom-up condition is 0.1 ≦ (x / R) <0.5. From the results of SEM observation, it was found that when (x / R) exceeds 0.3, microvoids are generated in the periphery of the through-hole bottom 62, so that it is good within the scope of this sample and experiment. The bottom-up condition is 0.1 ≦ (x / R) ≦ 0.3. However, since the void in this case is very small, there is no problem even if it is 0.3 or more in terms of electrical or reliability. In FIG. 7, the distance (distance) y between the semiconductor substrate and the plate was 1.0 mm.

  FIG. 8 shows the relationship between the distance y (mm) between the silicon wafer back surface 64 and the plate 67 and the plating thickness a (um) of the device surface. The opening diameter of the plate 67 used in this experiment is 80 μm. (That is, x = 10 μm, and the opening diameter R of the through hole is 100 μm, so x / R = 0.1.) In the graph of FIG. Δ indicates that a minute void remains, and × indicates an obvious plating defect such as a plate and wafer adhering or a large void remaining in a through hole. From FIG. 8, when y exceeds 1.0 mm, the plating thickness tends to increase rapidly, which is considered to be due to an increase in the amount of current flowing from the opening 68 of the plate 67. When y is 1.25 mm or more, a defect occurs in the through hole. Further, when the plate is completely brought into contact with the semiconductor substrate, there are problems that the semiconductor substrate is scratched, or that the contact portion is plated and the plating is peeled off when the plate is separated from the semiconductor substrate. Therefore, in consideration of the unevenness of the semiconductor substrate, the distance between the plate and the semiconductor substrate must be at least 0.05 mm. From the above, it can be seen that the range in which plating can be normally formed in the through hole and on the surface is 0.05 mm ≦ y ≦ 1.25 mm, preferably 0.05 mm ≦ y ≦ 1.0 mm. (Increasing the plating thickness on the back surface of silicon 1 may require the plating film to be polished to some extent.)

  As described above, the present invention is characterized in that a plate having openings matching the pattern of through holes formed in a silicon wafer is fixed to the silicon wafer with a certain interval y (mm) and electroplating is performed. It is said. As a result, it is possible to form a through wiring in which the inside of the through hole free from defects such as voids is filled with the plating film.

  Conventionally, there has been a problem that adjustment of the additive component is difficult because an additive is added to the plating solution, but such an additive for forming the through wiring is no longer necessary, so that the work is troublesome. Completely disappears. However, it is necessary to adjust only additives such as a brightener and a stress reducing agent for obtaining an effect that is not for forming the through wiring, but these do not have much influence on the labor.

In the present invention, a single general-purpose DC power source is sufficient as a plating power source, and it is not necessary to use a plurality of expensive pulse plating power sources or power sources, so that equipment can be prepared at low cost.
In the present invention, by making the opening diameter of the plate smaller than the opening diameter of the through-hole, the current density at the corner of the through-hole opening is reduced, and the plating on the side wall and bottom of the through-hole is relatively promoted. The The ratio (x / R) between the opening diameter of the plate and the opening diameter of the through hole is 0.1 ≦ (x / R) <0.5, preferably 0.1 ≦ (x / R) ≦ 0.3. By doing so, it becomes a condition that the growth of the plating is bottomed up, and the plating is not blocked in the opening, so that no void remains in the through hole. This condition slightly changes when the aspect ratio of the through hole (through hole depth / through hole opening diameter) varies. For example, if the aspect ratio is small, x / R may be smaller than 0.1.

  As an example, when the aspect ratio is 1 (when the through-hole depth is 100 μm and the through-hole opening diameter is 100 μm), good bottom-up conditions can be obtained even when x / R = 0.05 (y = 0). 0.05 to 1.0 mm). On the other hand, when the aspect ratio is 4, good bottom-up conditions can be obtained even when x / R = 0.1 (when y = 0.05 to 1.0 mm). This is considered to be because even when the aspect ratio is large, the current concentration at the corner of the through hole is considerably suppressed at x / R = 0.1, and the overhang condition is eliminated. Therefore, it can be said that the above range definition is quite universal.

Furthermore, by making the distance between the wafer and the plate 0.05 mm or more and 1.0 mm or less, the plating growth on the wafer surface can be suppressed, the plating thickness on the surface can be reduced, and it has an appropriate thickness for subsequent wiring formation. Can be formed. Further, since the plating thickness on the wafer surface is thin, the stress on the wafer substrate is reduced. Since the plating thickness on the wafer surface is thin, it is not necessary to remove an unnecessary thickness of the plating film by polishing, etching, or the like, thereby reducing the number of processes and saving resources.
The plate is preferably an insulator. The present invention can be used even when the plate is a good electrical conductor such as a metal, but it is not desirable because it grows on the plate itself. In addition, the plate of the present invention is preferably a porous body. As described above, this plate oozes through the porous portion of the plate and supplies fresh plating solution to the back surface of the silicon wafer, and also passes the current. This is because a thin plating can be formed on the back surface of the silicon wafer. Therefore, when it is not desired to grow the plating excessively, it is not necessarily required to be a porous body. For example, non-porous ceramics, glass, polymer materials, non-conductive metal oxides, and the like.

  The present invention has been described as being applicable to a semiconductor substrate having a through hole. That is, the present invention can be most effectively applied to a through hole having an opening diameter of 10 μm to 200 μm. If it is between these, the above-mentioned range prescribed | regulated by this specification is applicable. When the opening diameter of the through hole is 10 μm or less, the accuracy and alignment (alignment) of the plate becomes considerably difficult. In addition, although the present invention can be used even with an opening diameter of 200 μm or more, in reality, a large opening diameter is not required, and such a wide through hole is completely filled with a plating film. There is no need. (Of course, the present invention can be applied to complete filling.)

Furthermore, although the above-described through-hole has been described as being a hole opened from the back surface of the semiconductor substrate to the I / O pad on the surface of the semiconductor substrate, it is completely said that holes are formed on both surfaces of the semiconductor substrate. Needless to say, the present invention can also be applied to the through-holes.

It goes without saying that the present invention can also be applied to normal contact holes and vias that are not through holes. However, as described above, it is necessary to open the plate and align the opening with the contact hole of the silicon wafer. Therefore, the present invention can be applied to any small through-hole, contact hole, via, or the like as long as the opening of the plate can be formed and aligned. For example, the present invention can also be applied to through holes, contact holes, and vias of 1 μm or less. Furthermore, it goes without saying that the present invention can also be applied to plating formed in a separation groove formed in a semiconductor substrate such as a trench.

  Needless to say, what has been described in the drawings, each embodiment, each example, and the like so far can be applied to the contents not described in each other without contradiction.

  The present invention can be used for a wafer level package having a through hole used in the semiconductor industry.

FIG. 1 is a view showing a semiconductor substrate (silicon wafer) in which through holes are formed. FIG. 2 is a view showing a silicon wafer having a through hole and a plate of the present invention having an opening at the same position as the through hole. FIG. 3 is a diagram schematically showing the growth of plating when electrolytic plating is performed on a silicon wafer having a through hole. FIG. 4 is a diagram schematically showing the current distribution inside the through hole during plating. FIG. 5 is a diagram schematically showing the current distribution inside the through hole during plating when the plate of the present invention is used. FIG. 6 is a diagram schematically showing the shape of the plating film grown on the through hole. FIG. 7 is a diagram showing the relationship between the plate opening diameter (x / R) and the plating growth (2r / c) with respect to the through-hole opening diameter. FIG. 8 is a diagram showing the relationship between the distance y (mm) between the back surface of the silicon wafer and the plate and the plating thickness a (um) on the device surface. FIG. 9 is a view showing a conventional plating shape grown in the through hole.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon wafer, 2 ... I / O pad electrode, 3 ... Insulating film, 4 ... Protective film,
5 ... Through-hole, 6 ... Insulating film, 7 ... Barrier metal, 8 ... Seed layer,
10 ... Plate, 11 ... (Plate) opening, 12 ... Back side of silicon wafer,
13 ... Through-hole bottom part (bottom surface), 14 ... Through-hole side wall (side surface), 15 ... Plating (film | membrane),
61 ... Silicon wafer, 62 ... Through hole bottom (bottom), 63 ... Through hole side wall (side),
64 ... back side of silicon wafer, 65 ... through hole, 66 ... plating (film),
67 ... Plate, 68 ... (Plate) opening, 91 ... Silicon wafer,
92 ... through hole, 93 ... corner of through hole, 94 ... overhang shape,
95 .. Plating (film), 96 ... Void (cavity)

Claims (7)

In the process of forming plated wiring by electrolytic plating at the wafer level in a through hole formed in a semiconductor substrate, an opening is formed at the same position as the through hole opening of the semiconductor substrate between the plating electrode and the semiconductor substrate in the plating solution. A plate-like plate having an opening, and the electrolytic plating is performed in a state where the opening of the plate is aligned and arranged with a certain distance from the opening of the through hole of the semiconductor substrate. Electrolytic plating method. The electrolytic plating method according to claim 1, wherein an opening diameter of the through hole is 10 μm to 200 μm.   The electrolytic plating method according to claim 1 or 2, wherein the opening diameter of the plate opening is smaller than the opening diameter of the through-hole opening of the semiconductor substrate. The relationship between the opening diameter of the plate opening and the opening diameter of the through-hole opening is in the range of 0.1 ≦ (through-hole opening diameter−plate opening diameter) ÷ through-hole opening diameter ÷ 2) ≦ 0.3. The electrolytic plating method according to claim 3, wherein: The electrolytic plating method according to any one of claims 1 to 4, wherein the distance between the semiconductor substrate and the plate is set in a range of 0.05 mm or more and 1.0 mm or less.   The electroplating method according to any one of claims 1 to 4, wherein the plate-like plate is made of a porous ceramic. The electroplating apparatus which can perform electroplating using the electroplating method in any one of Claims 1-6.

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