JP2009200300A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make ON resistance low and withstanding voltage high regardless of micro-patterning in a semiconductor device having a semiconductor substrate of parallel p-n structure. <P>SOLUTION: In the semiconductor device having parallel p-n layers with n-type drift regions 2 and p-type partition regions 3, the drift region 2 and the partition region 3 being alternately arranged, a second trench 4 into which a gate electrode 7 is to be embedded is formed above the n-type drift region 2 or the p-type partition region 3. A round n-type surface buffer region 5 is formed on the bottom surface of the second trench 4. A first trench for forming the parallel p-n layers and the second trench 4 for embedding the gate electrode 7 are formed using same oxide masks. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a vertical semiconductor device for high power, and more particularly to a semiconductor device having a superjunction layer on a part of a semiconductor substrate.

  2. Description of the Related Art Conventionally, in order to reduce the size and performance of power supply equipment in the power electronics field, power semiconductor devices are required to have high breakdown voltage and large current, as well as low loss, high breakdown resistance, and high speed. For this reason, a superjunction substrate has been proposed as the substrate structure of the semiconductor device, and a vertical MOS power device structure has been proposed as the surface structure.

  As a substrate structure of a semiconductor device, a semiconductor substrate having a single conductivity type and a super junction type substrate are widely known. In the super junction type substrate, the first conductivity type and the second conductivity type semiconductor regions are alternately arranged in a direction perpendicular to the semiconductor substrate between the first conductivity type semiconductor substrate and the second conductivity type semiconductor layer. It has a formed super junction layer (parallel pn layer) (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3 below). This superjunction substrate can spread the space charge region over the entire superjunction layer even when the concentration of the semiconductor regions of the first conductivity type and the second conductivity type is high. Therefore, the on-resistance can be reduced particularly in a high breakdown voltage semiconductor device.

Note that in this specification, a semiconductor having n or p means that electrons and holes are majority carriers, respectively. Further, “ ⁺ ” or “ ⁻ ” attached to n or p, such as n ⁺ or n ^−, is relatively higher or lower than the impurity concentration of the semiconductor to which they are not attached. Represents that.

An example of such a vertical MOS device will be described. FIG. 60 is a plan view showing the configuration of the vertical MOS device of the first conventional example. FIG. 61 is a cross-sectional view showing a cross-sectional structure taken along the section line DD ′ of FIG. As shown in FIG. 61, an n-type drift region (first conductive semiconductor region) 42 and a p-type partition are formed on the surface of the n ⁺⁺ substrate 41 having a low resistivity which is an n ⁺⁺ drain region on the first main surface side. A parallel pn layer (superjunction layer) composed of a region (second conductivity type semiconductor region) 43 is provided. The parallel pn layer allows a current to flow through the n-type drift region 42 in the on state, and depletes the n-type drift region 42 and the p-type partition region 43 in the off state. In this manner, a semiconductor substrate having a parallel pn structure including the parallel pn layers in which the n-type drift regions 42 and the p-type partition regions 43 are alternately arranged and the n ⁺⁺ substrate 41 is formed.

A planar type MOS structure is formed on the first main surface side of the parallel pn structure semiconductor substrate. A p base region 48 is provided on the p type partition region 43. In the p base region 48, a first n ⁺ source region 49a and a second n ⁺ source region 49b are provided apart from each other. Although not shown, the first n ⁺ source region 49a and the second n ⁺ source region 49b are often in a ring shape connected at the end of the stripe. The p base region 48 is provided with a p ⁺ pickup region 50 so as to be in contact with the first n ⁺ source region 49a and the second n ⁺ source region 49b. The p ⁺ pickup region 50 occupies a part below the first n ⁺ source region 49a and the second n ⁺ source region 49b.

Further, on the region sandwiched between the n-type drift region 42 and the first n ⁺ source region 49 a or the second n ⁺ source region 49 b in the n-type drift region 42 and the p base region 48, a gate oxide film 46 is interposed. A gate electrode 47 is provided. The source electrode 51 is in contact with the p ⁺ pickup region 50, the first n ⁺ source region 49a, and the second n ⁺ source region 49b. The drain electrode 52 is in contact with the second main surface side of the semiconductor substrate having a parallel pn structure, that is, the surface of the n ⁺⁺ substrate 41 on the second main surface side.

  The p base region 48 protrudes to the n-type drift region 42 in the vicinity of the interface with the gate oxide film 46. Here, the width (neck length) of a portion other than the p base region 48 (the remaining portion of the n type drift region 42) on the surface of the n type drift region 42 is Ln3.

  The n-type drift region 42 and the p-type partition region 43 of the parallel pn layer are provided in a stripe shape. The gate electrode 47 is provided in a stripe shape on the surface of the semiconductor substrate having a parallel pn structure, and is connected to the adjacent gate electrode at an end (not shown). The source electrode 51 covers the gate electrode 47 in a sheet shape via an interlayer insulating film such as BPSG (not shown). Further, in the region below the gate electrode 47, the remaining portion of the n-type drift region 42 is provided in stripes in a direction parallel to the longitudinal direction of the gate electrode 47.

The vertical MOS device having a parallel pn layer as shown in FIG. 60 or 61 has a breakdown voltage determined by the charge balance between the concentration N ₀ of the n-type drift region 42 and the concentration P ₀ of the p-type partition region 43. The on-resistance is determined by the concentration N ₀ of the n-type drift region 42. Therefore, the on-resistance-withstand voltage trade-off relationship is improved as compared with a conventional vertical MOS device using a semiconductor substrate having a single conductivity type whose breakdown voltage is determined only by the n-type drift region. In particular, as shown in FIG. 60, by making the longitudinal direction of the gate electrode 47 parallel to the depth direction of the n-type drift region 42, wasteful current wraparound is suppressed, and the on-resistance is greatly reduced.

  Here, in the semiconductor device shown in FIG. 60 or 61, in order to miniaturize a device, it is necessary to refine the surface structure formed on the first main surface side of the semiconductor substrate having a parallel pn structure. Therefore, the width of the gate electrode 47 must be reduced. On the other hand, the p base region 48 is formed by ion implantation of a p-type impurity such as boron, for example, using the gate electrode 47 as a mask, and performing thermal diffusion. At this time, since the p base region 48 protrudes due to lateral diffusion, when the width Wn of the n-type drift region 42 is narrowed, the neck length Ln3 of the n-type drift region 42 is also narrowed, and the on-resistance is increased. Further, there is a possibility that the neck length Ln3 of the n-type drift region 42 becomes zero, and in this case, the transistor does not turn on.

Here, as a method corresponding to miniaturization, a trench gate type semiconductor device has been proposed (see, for example, Patent Document 4, Patent Document 5, and Patent Document 6). FIG. 62 is a cross-sectional view showing the structure of a trench gate type semiconductor device of a second conventional example. In FIG. 62, a semiconductor device described in Patent Document 4 will be described as a second conventional example. As shown in FIG. 62, for the trench gate which is in contact with the first n ⁺ source region 9a and the second n ⁺ source region 9b and penetrates the p base region 8 on the n type drift region 2 of the parallel pn layer. A trench (second trench) 4 is provided. A gate electrode 7 is provided inside the second trench 4 via a gate oxide film 6. Further, an n-type surface buffer region 65 is provided in a region below the second trench 4. As will be described later, since the n-type surface buffer region 65 is formed by an epitaxial growth method, it has a cornered shape.

63 to 68 are cross-sectional views sequentially showing a method of manufacturing the trench gate type semiconductor device of the second conventional example. As shown in FIG. 63, a conventional trench gate type semiconductor device first epitaxially grows a p-type semiconductor 33 serving as a p-type partition region on the first main surface side of an n ⁺⁺ substrate 1. Then, an oxide film is grown on the surface of the p-type semiconductor 33. Next, the oxide film is patterned to form a first oxide film mask 71 having an opening in a region where an n-type drift region is to be formed.

Next, as shown in FIG. 64, using the first oxide film mask 71 as a mask, the parallel pn layer forming trench (first trench) 22 for forming the n-type drift region 2 reaches the n ⁺⁺ substrate 1. To form. Next, an n-type semiconductor is buried in the first trench 22 and planarized. Further, the first oxide film mask 71 is removed.

  Next, as shown in FIG. 65, an n-type semiconductor 35 is epitaxially grown on the surface of the parallel pn layer. Further, using the second oxide film mask 72 as a mask, p-type impurities are ion-implanted to partition the n-type semiconductor, and the second oxide film mask 72 is removed. In this way, an n-type surface buffer region 65 is formed as shown in FIG. Since the n-type surface buffer region 65 is partitioned by implanting p-type impurities, the portion into which the p-type impurities are ion-implanted has an outwardly convex diffusion shape. Therefore, since the n-type surface buffer region 65 has an inwardly convex shape, the corner at the lower end has an acute corner. Further, when the n-type semiconductor 35 is epitaxially grown to selectively form a trench and the p-type semiconductor is epitaxially grown in the trench, the lower corner of the n-type surface buffer region 65 has a right-angled corner. Become.

  Next, as shown in FIG. 67, a p-type semiconductor 68 that becomes a channel region (p base region 8) is epitaxially grown. Further, as shown in FIG. 68, the second trench 4 penetrating the p-type semiconductor 68 is formed using a third oxide film mask (not shown) as a mask. Next, a gate oxide film 6 is formed on the inner wall of the second trench 4, and a gate electrode 7 is formed on the surface of the gate oxide film 6.

Next, as shown in FIG. 62, a first n ⁺ source region 9a, a second n ⁺ source region 9b, and a p ⁺ pickup region 10 are formed. Further, the interlayer insulating film 24, the source electrode 11, and the drain electrode 12 are formed. In this way, a conventional trench gate type semiconductor device is completed.

  Further, Patent Document 5 discloses a semiconductor device in which the n-type surface buffer region 65 under the second trench 4 is omitted from the semiconductor device shown in FIG.

FIG. 69 is a sectional view showing the structure of a trench gate type semiconductor device of a third conventional example. In FIG. 69, a semiconductor device described in Patent Document 6 will be described as a third conventional example. As shown in FIG. 69, an oxide film 86 thicker than the gate oxide film 6 is provided on the bottom surface of the second trench 84. Further, the p-type partition region 83 of the parallel pn layer does not reach the n ⁺⁺ substrate 1 and is a floating region.

70 to 75 are cross-sectional views sequentially showing a method of manufacturing the trench gate type semiconductor device of the third conventional example. In another conventional trench gate type semiconductor device, first, as shown in FIG. 70, an n-type semiconductor 32 is epitaxially grown on the first main surface side of an n ⁺⁺ substrate 1. Then, an oxide film is grown on the surface of the n-type semiconductor 32. Next, patterning of the oxide film is performed to form a first oxide film mask 71 having an opening in a region where the p-type partition region is to be formed.

  Next, as shown in FIG. 71, a trench 84 is formed using the first oxide film mask 71 as a mask. Next, as shown in FIG. 72, a sacrificial oxide film 23 is formed on the inner wall of the trench 84.

Next, as shown in FIG. 73, p-type impurities are ion-implanted at a high acceleration. Further, as shown in FIG. 74, p-type impurities are ion-implanted at a low acceleration. Next, heat treatment is performed to thermally diffuse the p-type impurity. Thereby, the p base region 8 and the p-type partition region 83 are formed as shown in FIG. Further, a portion of the n-type semiconductor 32 other than the p base region 8 and the p-type partition region 83 becomes an n-type drift region 82. Further, a gate oxide film 6 is formed on the inner wall of the trench 84, and a thick oxide film 86 is formed on the bottom surface. Then, the gate electrode 7 is formed in the trench 84 through the gate oxide film 6 and the thick oxide film 86. Next, as shown in FIG. 69, the first n ⁺ source region 9a, the second n ⁺ source region 9b and the p ⁺ pickup region 10 are formed on the surface of the p base region 8, and the interlayer insulating film 24 and the source electrode 11 are formed. . Further, the drain electrode 12 is formed on the second main surface side of the n ⁺⁺ substrate 1. Thus, the trench gate type semiconductor device of the third conventional example is completed.

  By forming by these methods, since the p base regions are separated from each other by the trench, the neck length of the n-type drift region can be set to a predetermined distance even if the size is reduced. Accordingly, a low on-resistance can be maintained. In addition, since the p-type partition region and the n-type drift region can have a desired charge balance, the on-resistance-breakdown voltage trade-off relationship can be improved.

JP-A-9-266611 US Pat. No. 5,216,275 JP 2004-119611 A JP 2003-124464 A JP 2007-5516 A JP 2007-158275 A

  However, in the technique of Patent Document 4 or Patent Document 5 described above, the first trench for forming the parallel pn layer and the second trench for embedding the gate electrode are formed by different masks. Therefore, if the parallel pn structure is miniaturized, it is likely to be affected by mask displacement. FIG. 76 is a diagram showing a problem of the trench gate type semiconductor device of the second conventional example. As shown in FIG. 76, the first trench and the second trench 4 are shifted in mask so that the side wall of the second trench 4 becomes the n-type drift region 2 and the p-type partition region 3 of the parallel pn layer. Formed at a position shifted from the interface. For this reason, the electric field concentrates in the vicinity of the interface between the n-type surface buffer region 65 and the n-type drift region 2 (region surrounded by the broken line E) below the second trench 4. This causes a problem that the breakdown voltage of the device is lowered. Therefore, it is difficult to miniaturize.

  Furthermore, since the n-type surface buffer region provided in the region below the second trench is formed by epitaxial growth and ion implantation, there is a problem that the manufacturing becomes complicated and the cost is high.

  On the other hand, in the technique of Patent Document 6, it is not necessary to form a parallel pn layer forming trench for forming a parallel pn layer. That is, in the manufacturing process of the semiconductor device, the step of forming the trench is only one time of the step of forming the trench for the trench gate. For this reason, it is easy to manufacture and inexpensive. However, since the p-type partition region of the parallel pn layer is formed by ion implantation and heat treatment, when the parallel pn layer is miniaturized, adjacent p-type partition regions are close to each other. As shown in FIG. 77, when the width Xsp of the extension of the p-type partition region 83 from the trench 84 and the interval St between the trenches 84 satisfy the relationship of the following equation (1), adjacent p The mold partition regions 83 are connected to each other.

    St <2 · Xsp (1)

  For this reason, there is a problem that current does not flow in a region where adjacent p-type partition regions 83 overlap (region surrounded by a broken line F). Therefore, it is difficult to miniaturize.

  In order to solve the above-described problems caused by the prior art, a semiconductor device having a semiconductor substrate having a parallel pn structure has a low on-resistance and a high withstand voltage even when miniaturized, and a method of manufacturing the same The purpose is to provide.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention is a first conductivity type semiconductor substrate having a high impurity concentration and a first conductivity provided on a surface of the semiconductor substrate. Parallel pn layers in which type semiconductor regions and second conductivity type semiconductor regions are alternately arranged, and trenches provided in either the second conductivity type semiconductor region or the first conductivity type semiconductor region of the parallel pn layer; In a semiconductor device comprising an insulating film provided on the inner surface of the trench and a gate electrode provided via the insulating film, a shape having no corners is formed so as to cover at least a corner portion of the bottom surface of the trench. A surface buffer region of the first conductivity type is provided.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the surface buffer region has a thermally diffused shape.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect of the present invention, a back buffer region of a first conductivity type is provided between the semiconductor substrate and the parallel pn layer. It is characterized by being.

  A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the semiconductor substrate and the second conductive type semiconductor region of the parallel pn layer are provided. A second conductivity type layer having a higher impurity concentration than the second conductivity type semiconductor region is provided.

  According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the surface buffer region is provided only in the vicinity of a corner of the bottom surface of the trench. It is characterized by that.

  According to a sixth aspect of the present invention, there is provided a semiconductor device manufacturing method for generating a first conductivity type semiconductor or a second conductivity type semiconductor on a surface of a first impurity type semiconductor substrate having a high impurity concentration, A first trench forming step of forming a first trench in one of the conductive type semiconductors generated in the semiconductor generating step using an insulating film mask as a mask, and generating the other conductive type semiconductor in the first trench A parallel pn layer forming step of forming a parallel pn layer in which one conductive type semiconductor region and the other conductive type semiconductor region are alternately arranged; and using the insulating film mask as a mask, the other conductive type A second trench forming step of forming a second trench in the semiconductor region; and a gate electrode forming step of forming a gate electrode inside the second trench through a gate oxide film. To.

  According to a seventh aspect of the present invention, there is provided a semiconductor device manufacturing method for generating a first conductivity type semiconductor or a second conductivity type semiconductor on a surface of a high impurity concentration first conductivity type semiconductor substrate; A first trench forming step of forming a first trench in one of the conductive type semiconductors generated in the semiconductor generating step using an insulating film mask as a mask, and generating the other conductive type semiconductor in the first trench A parallel pn layer forming step of forming a parallel pn layer in which one conductive type semiconductor region and the other conductive type semiconductor region are alternately arranged; and polishing the other conductive type semiconductor to form the insulating layer A height aligning step of aligning the height of the film mask and the other conductive type semiconductor region, a second trench forming step of forming a second trench by removing the insulating film mask, and the second trench Therein, characterized in that it comprises a gate electrode forming step of forming a gate electrode via a gate oxide film.

  According to a eighth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the sixth or seventh aspect of the present invention, wherein the first conductivity type back surface buffer region is formed on the surface of the semiconductor substrate before the semiconductor generation step. A back surface buffer region forming step of forming

  According to a ninth aspect of the present invention, there is provided a semiconductor device manufacturing method according to any one of the sixth to eighth aspects, wherein the second conductive layer is formed on the surface of the semiconductor substrate before the semiconductor generation step. An epitaxial layer forming step of forming a type epitaxial layer.

  According to a tenth aspect of the present invention, there is provided a semiconductor device manufacturing method according to any one of the sixth to ninth aspects, wherein the second trench forming step and the gate electrode forming step are performed. An ion implantation step of ion-implanting a first conductivity type impurity into at least a corner of the bottom surface of the second trench, and after the gate electrode formation step, the first conductivity type impurity ion-implanted in the ion implantation step It includes a surface buffer region forming step of performing thermal diffusion and forming a surface buffer region at a corner of the bottom surface of the second trench.

  Further, in the semiconductor device manufacturing method according to the invention of claim 11, in the invention of claim 10, in the ion implantation step, an impurity of the first conductivity type is added to a central portion of the bottom surface of the second trench. The ion implantation is not performed.

  According to the first to fifth, tenth, or eleventh aspects of the invention, the surface buffer region of the first conductivity type in contact with the bottom surface of the trench for embedding the gate electrode is formed by ion diffusion and thermal diffusion, for example. It can be easily formed.

  According to the invention of claims 6 to 11, the first trench for forming the parallel pn layer and the second trench for embedding the gate electrode can be formed using the same oxide film mask. it can. Therefore, mask displacement between the first trench and the second trench can be prevented.

  According to the semiconductor device and the method of manufacturing the same according to the present invention, the semiconductor device having the semiconductor substrate having the parallel pn structure has an effect that the on-resistance can be lowered and the withstand voltage can be increased even if the semiconductor device is miniaturized. .

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
FIG. 1 is a plan view showing the structure of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a cross-sectional structure taken along line AA ′ in FIG. As shown in FIG. 2, the semiconductor device according to the first embodiment is manufactured using a semiconductor substrate having a parallel pn structure. A semiconductor substrate of the parallel pn structure, n ⁺ lower n ⁺⁺ first main surface side of the surface of the substrate 1 of the drain region and a resistivity, n-type drift region (first conductive type semiconductor region) 2 and p-type partition A parallel pn layer composed of the region (second conductivity type semiconductor region) 3 is provided.

A p base region 8 is provided on the n type drift region 2. On the surface of the p base region 8, a first n ⁺ source region 9a and a second n ⁺ source region 9b are provided apart from each other. Further, a p ⁺ pickup region 10 is provided between the first n ⁺ source region 9a and the second n ⁺ source region 9b.

The p-type partition region 3 is provided with a trench (second trench) 4 for embedding a gate electrode, and a gate electrode 7 is provided inside the second trench 4 via a gate oxide film 6. ing. The gate electrode 7 is, for example, polysilicon. The above-described n ⁺⁺ substrate 1 to the first n ⁺ source region 9a, the second n ⁺ source region 9b, and the p ⁺ pickup region 10 are semiconductor substrates having a parallel pn structure.

An interlayer insulating film 24 is provided on the first main surface side of the surface of the parallel pn structure semiconductor substrate. An opening is provided in the interlayer insulating film 24, and the source electrode 11 is in contact with the p ⁺ pickup region 10, the first n ⁺ source region 9 a, and the second n ⁺ source region 9 b in this opening. The drain electrode 12 is in contact with the second main surface side of the semiconductor substrate having the parallel pn structure, that is, the surface of the n ⁺⁺ substrate 1 on the second main surface side. As shown in FIG. 1, the depth direction of the gate electrode 7 and the depth direction of the n-type drift region 2 and the p-type partition region 3 are parallel.

Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 3 to 7 are cross-sectional views sequentially illustrating the method for manufacturing the semiconductor device according to the first embodiment. In the semiconductor device according to the first embodiment, first, an n-type semiconductor to be an n-type drift region is epitaxially grown on the first main surface side of the n ⁺⁺ substrate. Then, an insulating film such as an oxide film is deposited on the surface layer of the n-type semiconductor. Next, the oxide film is patterned to form an oxide film mask having an opening in a region where the p-type partition region is to be formed. Then, as shown in FIG. 3, using the oxide film mask 21 as a mask, a parallel pn structure forming trench (first trench) 22 for forming a p-type partition region is formed so as to reach the n ⁺⁺ substrate 1. To do.

  Next, as shown in FIG. 4, a p-type semiconductor 33 serving as a p-type partition region is deposited, and the p-type semiconductor 33 is embedded in the first trench 22. Next, as shown in FIG. 5, the p-type semiconductor 33 on the surface is subjected to CMP polishing and the p-type semiconductor 33 is then over-etched while leaving the oxide film mask 21 to form the p-type partition region 3. At this time, the height of the p-type partition region 3 is set lower than the height of the n-type drift region 2. A step between the p-type partition region 3 and the n-type drift region 2 formed thereby becomes the second trench 4. Next, as shown in FIG. 6, thermal oxidation is performed to form a sacrificial oxide film 23 on the inner wall of the second trench 4. Then, the oxide film mask 21 and the sacrificial oxide film 23 are removed.

  Next, as shown in FIG. 7, a gate oxide film 6 is grown along the inner wall of the second trench 4 to embed the gate electrode 7.

Next, as shown in FIG. 2, ap ⁺ pickup region 10 reaching the p base region 8 is formed in the n-type layer. The n-type layers delimited by the p ⁺ pickup region 10 become the first n ⁺ source region 9a and the second n ⁺ source region 9b, respectively. Then, an interlayer insulating film 24 is deposited to form openings reaching the p ⁺ pickup region 10, the first n ⁺ source region 9a, and the second n ⁺ source region 9b. Further, the source electrode 11 is formed so as to be in contact with the p ⁺ pickup region 10, the first n ⁺ source region 9a, and the second n ⁺ source region 9b. Further, the drain electrode 12 is formed on the second main surface side of the n ⁺⁺ substrate 1. In this way, the semiconductor device according to the first embodiment is completed.

  Next, the semiconductor device according to the first embodiment is compared with the third conventional example (see FIG. 69). Here, as shown in FIG. 3, the thickness of the oxide film mask 21 is the initial film thickness t21, and the depth of the first trench 22 is Dt22. Further, as shown in FIG. 2, the depth of the second trench 4 is Dt4. Further, in FIG. 3, with the oxide film mask 21 as a mask, the etching selection ratio (silicon-silicon oxide selection ratio) when forming the first trench 22 in the n-type semiconductor is S. Here, as shown in FIG. 5, the thickness of the oxide film mask 21 may be about 0.4 μm after the second trench 4 is formed. This is because the p-type semiconductor 33 grown on the oxide film 21 is smoothed by CMP polishing before over-etching the p-type semiconductor 33 in FIG. This is because a thickness of about 0.4 μm is necessary to detect exposure. In this case, the initial film thickness t21 is given by the following equation (2).

    t21 ≧ {(Dt22 + Dt4) / S} +0.4 (2)

  Here, for example, when the depth Dt22 of the first trench 22 is 45 μm and the depth Dt4 of the second trench 4 is 3 μm or 10 μm, the minimum required initial film thickness t21 is t21min. FIG. 8 is a characteristic diagram showing the relationship between the minimum required initial film thickness t21min and the selection ratio S. As shown in FIG. 8, the minimum required initial film thickness t21min decreases as the value of the selection ratio S increases. For example, when Dt4 is 10 μm, the selection ratio S is 90 or more, and the minimum required initial film thickness t21min is about 1 μm. When Dt4 is 3 μm, the selection ratio S is 90 or more, and the minimum required initial film thickness t21min is smaller than 1 μm. Therefore, it can be seen that when the selection ratio S is 90 or more, the minimum required initial film thickness t21min is 1 μm or less. Thus, since the minimum required initial film thickness of the oxide film serving as a mask is small, the throughput is improved.

  FIG. 9 is a characteristic diagram showing the relationship between the on-resistance and the repetition pitch of the n-type drift region and the p-type partition region of the parallel pn layer. In FIG. 9, the on-resistance is normalized by a value given by the following equation (3). However, as shown in FIG. 2, the width of the n-type drift region 2 is Wn, and as shown in FIG. 69, the protruding width of the p-type partition region 83 from the trench 84 is Xsp, and the interval between the trenches 84 is St. And

    Wn / (2Xsp) = St / (2Xsp) = 4 (3)

  For example, the first trench depth Dt22 is 45 μm, the second trench depth Dt4 is 5 μm, the width Wn of the n-type drift region, the width Wp of the p-type partition region, and the distance between the second trenches. It is assumed that St is approximately the same. In this case, as shown in FIG. 9, in the third conventional example, the ON resistance increases when the repetition pitch of the n-type drift region and the p-type partition region becomes smaller than about 1.5 (the value of the B point). . On the other hand, in the first embodiment, even when the repetitive pitch between the n-type drift region and the p-type partition region becomes narrower than the value of the point B, the on-resistance does not increase and further decreases. At this time, since the breakdown voltage is determined by the charge balance between the n-type drift region and the p-type partition region, there is almost no difference between the third conventional example and the first embodiment. Therefore, according to the first embodiment, the trade-off relationship between on-resistance and breakdown voltage is improved even if miniaturization is performed.

  Next, the on-resistance and breakdown voltage of the semiconductor device according to the first embodiment will be described. Here, as shown in FIG. 2, the distance from the interface between the source electrode 11 and the semiconductor to the interface between the p base region 8 and the n-type drift region 2, that is, the diffusion depth of the p base region 8 is expressed as Xj1 To do. Further, the distance from the interface between the p base region 8 and the n-type drift region 2 to the interface between the second trench 4 and the p-type partition region 3, that is, the neck length of the second trench 4 is Ln3. Furthermore, the distance from the interface between the source electrode 11 and the semiconductor to the bottom surface of the second trench 4, that is, the depth of the second trench 4 is Dt 4.

  FIG. 10 is a characteristic diagram showing the relationship between the normalized on-resistance or the normalized breakdown voltage and the neck length of the second trench in the semiconductor device according to the first embodiment. As shown in FIG. 10, the neck length Ln3 of the second trench is given by the following equation (4).

    Dt4 = Xj1 + Ln3 (4)

  In the semiconductor device according to the first embodiment, it is preferably 0.3 μm or more. The reason is that when the neck length Ln3 is less than 0.3 μm, the on-resistance is high, the device may not be turned on, and good characteristics cannot be obtained. Therefore, the depth Dt4 of the second trench is given by the following equation (5).

    Dt4 ≧ Xj1 + 0.3 (5)

  Specifically, when the diffusion depth Xj1 of the p base region is, for example, about 2.5 μm, the depth Dt4 of the second trench may be 2.8 μm or more. On the other hand, as shown in FIG. 10, when the neck length Ln3 becomes larger than the width Wn of the n-type drift region, the breakdown voltage decreases. This is because, as shown in FIG. 11, the electric field (broken line in the figure) concentrates on a region where the side wall of the second trench 4 and the n-type drift region 2 are in contact with each other (region indicated by reference numeral C). . For this reason, the depth Dt4 of the second trench is given by the following equation (6).

    Dt4 ≦ Xj1 + Wn (6)

  Therefore, by summarizing the above equations (4) and (5) and the above equation (6), the relationship between the neck length Ln3 and the width Wn of the n-type drift region is given by the following equation (7). It is done.

    0.3 ≦ Ln3 ≦ Wn (7)

  According to the first embodiment, the first trench and the second trench can be formed using the same mask. Therefore, mask displacement between the first trench and the second trench can be prevented. For this reason, electric field concentration due to mask displacement can be prevented, and a decrease in breakdown voltage can be prevented.

(Embodiment 2)
FIG. 12 is a cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment. As shown in FIG. 12, the semiconductor device according to the second embodiment is provided with an n-type surface buffer region 5 so as to be in contact with the bottom surface of the second trench 4. Here, since the n-type surface buffer region 5 is formed by, for example, ion implantation and thermal diffusion, it has a shape with no corners. That is, the n-type surface buffer region 5 has a shape diffused isotropically from the bottom surface of the second trench 4.

  FIG. 13 or FIG. 14 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment. In the semiconductor device according to the second embodiment, n-type impurities are ion-implanted into the bottom surface of the second trench 4 after the above-described processing of FIGS. Next, as shown in FIG. 13, n-type impurities are ion-implanted into the bottom surface of the second trench 4 using the oxide film mask 21 as a mask. Then, the oxide film mask 21 and the sacrificial oxide film 23 are removed.

Next, as shown in FIG. 14, the gate oxide film 6 is grown along the inner wall of the second trench 4, and the gate electrode 7 is embedded in the second trench 4. Then, heat treatment is performed to form the n-type surface buffer region 5 by thermal diffusion. Next, a p base region 8 to be a channel region and an n-type layer 19 to be a first n ⁺ source region and a second n ⁺ source region are formed. Further, as shown in FIG. 12, as in the first embodiment, the p base region 8, the p ⁺ pickup region 10, the first n ⁺ source region 9a, the second n ⁺ source region 9b, the source electrode 11 and the drain electrode 12 are formed. Then, the semiconductor device according to the second embodiment is completed.

  Next, on-resistance and breakdown voltage of the semiconductor device according to the second embodiment will be described. Here, as shown in FIG. 12, in the semiconductor device according to the second embodiment, the width of the region in contact with the n-type surface buffer region 5 on the bottom surface of the second trench 4 is 2 · Ln4.

  FIGS. 15 and 16 are characteristic diagrams showing the relationship between the normalized on-resistance or the normalized breakdown voltage and the neck length of the second trench in the semiconductor device according to the second embodiment. 15 shows on-resistance and breakdown voltage when Ln4 is 0.3 μm or more, and FIG. 16 shows on-resistance and breakdown voltage when Ln4 is 0.3 μm or less.

  As shown in FIG. 15 or FIG. 16, since the n-type surface buffer region 5 is formed in the semiconductor device according to the second embodiment, the value of the neck length Ln3 when the on-resistance rapidly increases is The value of Ln4 is lower than the value (for example, 0.3 μm) of the neck length Ln3 of the semiconductor device according to the first embodiment. Therefore, as compared with the semiconductor device according to the first embodiment, it can be seen that the depth Dt4 of the second trench can be formed shallower by the above-described equation (4). For example, even when the depth Dt4 of the second trench is shallower than the diffusion depth Xj1 of the p base region, since the n-type surface buffer region is provided, the neck length Ln3 is larger than that of the semiconductor device according to the first embodiment. The value can be increased. In addition, since the neck length Ln4 can be secured also in the direction parallel to the bottom surface of the second trench, the range of Ln3 that keeps the on-resistance low is longer by the value of Ln4 than the semiconductor device according to the first embodiment. , The on-resistance can be lowered. In order to suppress the electric field concentration as shown in FIG. 11, Ln3 that satisfies Expression (7) may be used as in the first embodiment.

  According to the second embodiment, the on-resistance can be made lower than that of the first embodiment. Further, since the n-type surface buffer region can be easily formed by, for example, ion implantation and thermal diffusion, the cost is reduced.

(Embodiment 3)
FIG. 17 is a cross-sectional view illustrating the structure of the semiconductor device according to the third embodiment. As shown in FIG. 17, in the semiconductor device according to the third embodiment, the n-type surface buffer region 5 is not formed in the center portion of the second trench 4.

  18 to 20 are cross-sectional views sequentially illustrating the method for manufacturing the semiconductor device according to the third embodiment. In the semiconductor device according to the third embodiment, after the processes in FIGS. 3 to 6 described above, first, as shown in FIGS. 18 and 19, an n-type impurity is formed in the second trench 4 using the oxide film mask 21 as a mask. Are implanted at an angle. At this time, the shadow effect by adjusting the implantation angle is used to prevent the n-type impurity from being implanted into the central portion of the second trench 4.

Then, as shown in FIG. 20, the gate oxide film 6 is grown along the inner wall of the second trench 4 to embed the gate electrode 7. Further, as shown in FIG. 17, as in the semiconductor device of the first or second embodiment, the p base region 8, the p ⁺ pickup region 10, the first n ⁺ source region 9a, the second n ⁺ source region 9b, Interlayer insulating film 24, source electrode 11, and drain electrode 12 are formed. In this way, the semiconductor device according to the third embodiment is completed. In the third embodiment, the width of the region where one corner is in contact with the n-type surface buffer region 5 on the bottom surface of the second trench 4 is Ln4.

  According to the third embodiment, the same effect as in the second embodiment can be obtained.

(Embodiment 4)
Next, a semiconductor device according to Embodiment 4 will be described. The semiconductor device according to the fourth embodiment is different in the depth of the p-type partition region in the parallel pn structure semiconductor substrate included in the semiconductor device according to the first to third embodiments. 21 and 22 are cross-sectional views illustrating the structure of the semiconductor device according to the fourth embodiment. Here, as an example, an example in which the fourth embodiment is applied to the semiconductor device according to the first embodiment will be described. In the following description, description of the same configuration as in the first embodiment will be omitted. In FIG. 21, the first trench 22 does not reach the n ⁺⁺ substrate 1. That is, the depth of the p-type partition region 3 is shallower than the interface between the n-type drift region 2 and the n ⁺⁺ substrate 1.

In FIG. 22, the depth of the first trench 22 is deeper than the interface between the n-type drift region 2 and the n ⁺⁺ substrate 1. That is, the depth of the p-type partition region 3 is deeper than the interface between the n-type drift region 2 and the n ⁺⁺ substrate 1. Here, the distance Xb from the bottom surface of the n-type drift region 2 to the bottom surface of the p-type partition region 3 is preferably 10 μm or less. The reason is that when the distance Xb is greater than 10 μm, the p-type partition region 3 and the drain electrode 12 approach each other and the breakdown voltage decreases.

  Note that the semiconductor device according to the fourth embodiment can be manufactured by adjusting the depth of the first trench when the first trench is formed (see FIG. 3). The fourth embodiment is also applicable to the semiconductor device according to the second or third embodiment.

According to the fourth embodiment, the region between the position of the bottom surface of the p-type partition region and the position of the interface between the n-type drift region and the n ⁺⁺ substrate is defined as the bottom surface of the p-type partition region of the parallel pn layer. The charge balance can be different from the upper region. For this reason, avalanche tolerance can be improved.

(Embodiment 5)
Next, a semiconductor device according to Embodiment 5 will be described. 23 to 27 are cross-sectional views illustrating the structure of the semiconductor device according to the fifth embodiment. Here, as an example, an example in which the fifth embodiment is applied to the semiconductor device according to the first embodiment will be described. As shown in FIGS. 23 to 27, the semiconductor device according to the fifth embodiment includes an n-type back buffer region 35 having an impurity concentration different from that of the n-type drift region 2 between the parallel pn layer and the n ⁺⁺ substrate 1. Is provided.

In FIG. 23, the interface between n-type drift region 2 and n-type back buffer region 35 and the interface between p-type partition region 3 and n-type back buffer region 35 have the same depth. In FIG. 24, the p-type partition region 3 does not reach the n-type back buffer region 35. In FIG. 25, the position of the bottom surface of the p-type partition region 3 is in the n-type back surface buffer region 35. In FIG. 26, the position of the bottom surface of the p-type partition region 3 is the interface between the n-type drift region 2 and the n ⁺⁺ substrate 1. In FIG. 27, the position of the bottom surface of the p-type partition region 3 is in the n ⁺⁺ substrate 1. As described above, the position of the bottom surface of the p-type partition region 3 and the position of the interface between the n-type drift region 2 and the n-type back buffer region 35 may be different. In FIG. 27, the distance Xb from the interface between the n-type back surface buffer region 35 and the n ⁺⁺ substrate 1 to the bottom surface of the p-type partition region 3 is preferably 10 μm or less. The reason is that when the distance Xb is greater than 10 μm, the p-type partition region 3 and the drain electrode 12 approach each other and the breakdown voltage decreases.

Note that the semiconductor device according to the fifth embodiment can be manufactured by forming an n-type back buffer region before epitaxially growing an n-type semiconductor on the first main surface side of the n ⁺⁺ substrate. Then, an n-type semiconductor serving as an n-type drift region is epitaxially grown on the surface of the n-type back buffer region. The fifth embodiment can also be applied to the semiconductor device according to the second or third embodiment.

According to the fifth embodiment, the region between the position of the bottom surface of the p-type partition region and the position of the interface between the n-type back surface buffer region and the n ⁺⁺ substrate is defined as the p-type partition region of the parallel pn layer. The charge balance can be made different from the region above the bottom surface. For this reason, avalanche tolerance can be improved.

(Embodiment 6)
FIG. 28 is a cross-sectional view illustrating the structure of the semiconductor device according to the sixth embodiment. As shown in FIG. 28, in the semiconductor device according to the sixth embodiment, the second trench 4 is provided above the n-type drift region 2 having the parallel pn structure. That is, in the semiconductor substrate having the parallel pn structure included in the semiconductor device according to the first embodiment, the n-type drift region 2 and the p-type partition region 3 are replaced.

Next, a method for manufacturing the semiconductor device according to the sixth embodiment will be described. 29 to 33 are cross-sectional views sequentially showing the method for manufacturing the semiconductor device according to the sixth embodiment. As shown in FIG. 29, in the semiconductor device according to the sixth embodiment, first, a p-type semiconductor to be the p-type partition region 3 is epitaxially grown on the first main surface side of the n ⁺⁺ substrate 1. Then, an oxide film is deposited on the surface layer of the p-type semiconductor. Next, the oxide film is patterned to form an oxide film mask 21 having an opening in a region where an n-type drift region is to be formed. Then, using the oxide film mask 21 as a mask, a first trench 22 for forming an n-type drift region is formed so as to reach the n ⁺⁺ substrate 1. As described above, the manufacturing method of the semiconductor device according to the sixth embodiment is the same as that of the semiconductor device manufacturing method according to the first embodiment described with reference to FIGS. The region 2 and the p-type partition region 3 are replaced. Therefore, the other configuration and the manufacturing method are the same as those in the first embodiment, and thus the description thereof is omitted.

  FIG. 34 is a characteristic diagram showing the relationship between the normalized on-resistance or the normalized breakdown voltage and the neck length of the second trench in the semiconductor device according to the sixth embodiment. Here, in FIG. 28, the distance from the interface between the p base region 8 and the p-type partition region 3 to the interface between the second trench 4 and the n-type drift region 2, that is, the neck length of the second trench 4 is expressed as Lp3. And As shown in FIG. 34, the range of Lp3 in which the trade-off relationship between on-resistance and breakdown voltage is good is wider than the range of Ln3 of the semiconductor device according to the first embodiment (see FIG. 15). The reason is that even if the n-type surface buffer region is not formed, the bottom surface of the second trench is in contact with the n-type semiconductor layer (for example, the n-type drift region). This is because the horizontal neck length Ln4 can be secured. In FIG. 28, the neck length Lp3 is given by the following equation (8) or (9).

    Xj1 ≦ Dt4 = Xj1 + Lp3 ≦ Xj1 + Wp (8)

    0 ≦ Lp3 ≦ Wp (9)

  The reason is that in FIG. 28, if the depth Dt4 of the second trench 4 is shallower than the diffusion depth Xj1 of the p base region 8, the left and right p base regions of the second trench 4 below the second trench 4. This is because 8 is connected and cannot be turned on. In addition, when the depth Dt4 of the second trench 4 is deeper than the value obtained by adding the width Wp of the p-type partition region 3 to the diffusion depth Xj1 of the p base region 8, the breakdown voltage decreases or the channel length Lch increases. This is because the on-resistance increases.

  According to the sixth embodiment, the same effect as in the first embodiment can be obtained. Furthermore, according to the sixth embodiment, the trade-off relationship between on-resistance and withstand voltage can be improved as compared with the first embodiment.

(Embodiment 7)
FIG. 35 is a sectional view showing the structure of the semiconductor device according to the seventh embodiment. FIGS. 36 and 37 are sectional views showing the method for manufacturing the semiconductor device according to the seventh embodiment. The semiconductor device according to the seventh embodiment is a semiconductor device in which the second embodiment is applied to the semiconductor device according to the sixth embodiment. That is, the semiconductor device according to the seventh embodiment is obtained by replacing the semiconductor device according to the second embodiment with the n-type drift region 2 and the p-type partition region 3 having a parallel pn structure. Accordingly, the other configuration and the manufacturing method are the same, and the description thereof is omitted.

(Embodiment 8)
FIG. 38 is a cross-sectional view illustrating the structure of the semiconductor device according to the eighth embodiment, and FIGS. 39 to 41 are cross-sectional views sequentially illustrating the method for manufacturing the semiconductor device according to the eighth embodiment. The semiconductor device according to the eighth embodiment is a semiconductor device in which the third embodiment is applied to the semiconductor device according to the sixth embodiment. That is, the semiconductor device according to the eighth embodiment is obtained by replacing the semiconductor device according to the third embodiment with the n-type drift region 2 and the p-type partition region 3 having a parallel pn structure. Therefore, the other configuration and the manufacturing method are the same, and the description thereof is omitted.

(Embodiment 9)
Next, a semiconductor device according to Embodiment 9 will be described. In the semiconductor device according to the ninth embodiment, in the parallel pn structure semiconductor substrate of the semiconductor device according to the sixth embodiment, the position of the bottom surface of the n-type drift region is from the interface between the p-type partition region and the n ⁺⁺ substrate 1. Is also in a shallow position. Here, as an example, an example in which the ninth embodiment is applied to the semiconductor device according to the sixth embodiment will be described.

FIG. 42 is a cross-sectional view illustrating the structure of the semiconductor device according to the ninth embodiment. As shown in FIG. 42, the depth of the first trench 22 is deeper than the position of the interface between the p-type partition region 3 and the n ⁺⁺ substrate 1. That is, the position of the bottom surface of the n-type drift region 2 is deeper than the position of the interface between the p-type partition region 3 and the n ⁺⁺ substrate 1. Here, the distance Xb from the interface between the p-type partition region 3 and the n ⁺⁺ substrate 1 to the bottom surface of the n-type drift region 2 is preferably 10 μm or less. The reason for this is that when the distance Xb is greater than 10 μm, the distance between the n-type drift region 2 and the drain electrode 12 approaches and the breakdown voltage decreases.

If the depth of the first trench 22 for forming the n-type drift region 2 is shallower than the position of the interface between the p-type partition region and the n ⁺⁺ substrate 1, the n-type drift region 2 and the n ⁺⁺ substrate 1 And are not connected electrically. This is not preferable because the device does not turn on. The ninth embodiment can also be applied to the semiconductor device according to the seventh or eighth embodiment.

  According to the ninth embodiment, the same effect as in the fourth embodiment can be obtained.

(Embodiment 10)
Next, a semiconductor device according to Embodiment 10 will be described. Here, as an example, an example in which the tenth embodiment is applied to the semiconductor device according to the sixth embodiment will be described. 43 and 44 are sectional views showing the structure of the semiconductor device according to the tenth embodiment. As shown in FIGS. 43 and 44, the semiconductor device according to the tenth embodiment includes a p epitaxial layer having a different impurity concentration from that of the p type partition region 3 between the p type partition region 3 and the n ⁺⁺ substrate 1. 38 is provided. In FIG. 43, the bottom surface of n type drift region 2 is in contact with the interface between p epitaxial layer 38 and n ⁺⁺ substrate 1. In FIG. 44, the position of the bottom surface of the n-type drift region 2 is in the n ⁺⁺ substrate 1. Thus, according to the tenth embodiment, n-type drift region 2 needs to be in contact with n ⁺⁺ substrate 1.

In FIG. 44, the distance Xb from the interface between n ⁺⁺ substrate 1 and p epitaxial layer 38 to the bottom surface of n-type drift region 2 is preferably 10 μm or less. The reason is that when the distance Xb is greater than 10 μm, the distance between the n-type drift region 2 and the drain electrode 12 approaches and the breakdown voltage decreases. The tenth embodiment is also applicable to the semiconductor device according to the seventh or eighth embodiment.

According to the tenth embodiment, the region between the position of the bottom surface of the n-type drift region and the position of the interface between the p epitaxial layer and the n ⁺⁺ substrate is determined from the bottom surface of the p-type partition region of the parallel pn layer. The charge balance can be different from the upper area. For this reason, avalanche tolerance can be improved.

(Embodiment 11)
Next, a semiconductor device according to Embodiment 11 will be described. Here, as an example, an example in which the eleventh embodiment is applied to the semiconductor device according to the sixth embodiment will be described. 45 to 48 are sectional views showing the structure of the semiconductor device according to the eleventh embodiment. As shown in FIGS. 45 to 48, in the semiconductor device according to the eleventh embodiment, an n-type back buffer region 35 is provided between the p-type partition region 3 and the n ⁺⁺ substrate 1. The impurity concentration of the n-type back buffer region 35 may be equal to or different from the impurity concentration of the n-type drift region 2.

In FIG. 45, the bottom surface of n-type drift region 2 is in contact with the interface between n-type back surface buffer region 35 and n ⁺⁺ substrate 1. In FIG. 46, the position of the bottom surface of the n-type drift region 2 is in the n-type back surface buffer region 35. In FIG. 47, the bottom surface of the n-type drift region 2 is in contact with the interface between the p partition region and the n-type back buffer region 35. In FIG. 48, the position of the bottom surface of n type drift region 2 is in n ⁺⁺ substrate 1.

In FIG. 48, the distance Xb from the interface between the n ⁺⁺ substrate 1 and the n-type back buffer region 35 to the bottom surface of the n-type drift region 2 is preferably 10 μm or less. The reason is that when the distance Xb is greater than 10 μm, the distance between the n-type drift region 2 and the drain electrode 12 approaches and the breakdown voltage decreases. Further, the eleventh embodiment is applicable to the semiconductor device according to the seventh or eighth embodiment.

  According to the eleventh embodiment, the same effect as in the tenth embodiment can be obtained.

(Embodiment 12)
Next, a twelfth embodiment will be described. The twelfth embodiment differs from the first to eleventh embodiments in the method of manufacturing a semiconductor substrate having a parallel pn structure. 49 to 53 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the twelfth embodiment. In the twelfth embodiment, as an example, an example in which the twelfth embodiment is applied to the semiconductor device according to the first embodiment is shown.

In the twelfth embodiment, first, as shown in FIG. 49, a p-type semiconductor serving as a p-type partition region is epitaxially grown on the surface of the n ⁺⁺ substrate 1 on the first main surface side. At this time, the height of the p-type semiconductor is set to a value obtained by subtracting the depth Dt4 of the second trench from the depth Dt22 of the first trench 22 shown in FIG. Then, an oxide film is deposited on the surface layer of the p-type semiconductor. Next, the oxide film is patterned to form an oxide film mask 21 having an opening in a region where an n-type drift region is to be formed. Here, the thickness t21 ′ of the oxide film mask 21 is a value obtained by adding the depth of the second trench to the initial film thickness t21 shown in FIG. Then, using the oxide film mask 21 as a mask, a first trench 22 for forming an n-type drift region is formed so as to reach the n ⁺⁺ substrate 1. At this time, the etching depth is (Dt22−Dt4), which can be made smaller than the etching depth (Dt22) in the first embodiment.

  Next, as shown in FIG. 50, an n-type semiconductor 32 to be an n-type drift region is deposited, and the n-type semiconductor 32 is embedded in the first trench 22. Next, as shown in FIG. 51, polishing is performed by CMP (Chemical Mechanical Polishing) using the oxide film mask 21 as a stopper, and the heights of the n-type semiconductor and the oxide film mask 21 are made uniform. Thereby, the n-type drift region 2 is formed. At this time, the depth of the oxide film mask 21 is set to the depth Dt4 of the second trench to be formed later.

  Next, as shown in FIG. 52, thermal oxidation is performed on the polished surface to form a sacrificial oxide film 23. Further, using the oxide film mask 21 as a mask, ion implantation of p-type impurities for forming the p base region is performed. Then, the oxide film mask 21 and the sacrificial oxide film 23 are removed.

Next, as shown in FIG. 53, a gate oxide film 6 is grown along the inner wall of the second trench 4 formed by removing the oxide film mask, and a gate electrode 7 is embedded. In addition, an n-type layer 19 serving as a first n ⁺ source region and a second n ⁺ source region is formed on the surface layer of the p base region 8. Next, as shown in FIG. 2, the p ⁺ pickup region 10, the first n ⁺ source region 9a, the second n ⁺ source region 9b, the source electrode 11 and the drain electrode 12 are formed, and the first embodiment shown in FIG. Thus, a semiconductor device having the same structure as that of the semiconductor device is completed.

  In the twelfth embodiment, an n-type surface drift layer may be formed. In this case, before the gate oxide film is grown on the inner wall of the second trench formed by removing the oxide film mask, n-type impurities are ion-implanted at a predetermined position and heat treatment is performed.

  Next, an example in which the twelfth embodiment is applied to the semiconductor device according to the sixth embodiment will be described. 54 to 58 are sectional views showing another method for manufacturing the semiconductor device according to the twelfth embodiment. 54 to 58 are obtained by replacing the n-type drift region 2 and the p-type partition region 3 having a parallel pn structure in the manufacturing method described with reference to FIGS. 49 to 53 described above. Therefore, since other manufacturing methods are the same, description will be omitted.

  FIG. 59 is a characteristic diagram showing the relationship between the minimum required initial film thickness t21′min and the selection ratio S. Since the selection ratio S is finite, for example, even when silicon is etched, a part of the oxide film mask which is a silicon oxide film is etched. Therefore, t21′min must be larger than the finished depth of the second trench. The twelfth embodiment can also be applied to the semiconductor device according to the second to fifth embodiments or the seventh to eleventh embodiments.

  According to the twelfth embodiment, the depth of the etching can be reduced when the first trench is formed by setting the height of the oxide film mask to the depth of the second trench. Further, since the height of the oxide film mask becomes the depth of the second trench, the depth of etching after the semiconductor is buried in the first trench can be reduced.

  In the above description of the semiconductor device, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. The same holds true.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for manufacturing a high-power semiconductor element, and in particular, have a parallel pn structure semiconductor substrate, and have high breakdown voltage and on-resistance characteristics. It is suitable for a semiconductor device that can achieve both improvements.

It is a top view which shows the structure of the semiconductor device concerning Embodiment 1 of this invention. FIG. 2 is a cross-sectional view illustrating a cross-sectional structure taken along a cutting line AA ′ in FIG. 1. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. It is a characteristic view showing the relationship between the minimum required initial film thickness t21min and the selection ratio S. It is a characteristic view which shows the relationship between the repetition pitch of the n-type drift area | region and p-type partition area | region of a parallel pn layer, and ON resistance. FIG. 6 is a characteristic diagram showing a relationship between a normalized on-resistance or a normalized breakdown voltage and a neck length of a second trench in the semiconductor device according to the first embodiment; It is explanatory drawing which shows the area | region where an electric field concentrates. 6 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment; FIG. FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 10 is a characteristic diagram illustrating a relationship between a normalized on-resistance or a normalized breakdown voltage and a neck length of a second trench in the semiconductor device according to the second embodiment; FIG. 10 is a characteristic diagram illustrating a relationship between a normalized on-resistance or a normalized breakdown voltage and a neck length of a second trench in the semiconductor device according to the second embodiment; FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device according to a third embodiment. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. FIG. 6 is a cross-sectional view showing a structure of a semiconductor device according to a fourth embodiment. FIG. 6 is a cross-sectional view showing a structure of a semiconductor device according to a fourth embodiment. FIG. 9 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment. FIG. 9 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment. FIG. 9 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment. FIG. 9 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment. FIG. 9 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment. FIG. 9 is a cross-sectional view showing a structure of a semiconductor device according to a sixth embodiment. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a sixth embodiment; FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a sixth embodiment; FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a sixth embodiment; FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a sixth embodiment; FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a sixth embodiment; FIG. 10 is a characteristic diagram showing a relationship between a normalized on-resistance or a normalized breakdown voltage and a neck length of a second trench in the semiconductor device according to the sixth embodiment; FIG. 10 is a cross-sectional view showing a structure of a semiconductor device according to a seventh embodiment. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a seventh embodiment; FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a seventh embodiment; FIG. 10 is a sectional view showing a structure of a semiconductor device according to an eighth embodiment; FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an eighth embodiment; FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an eighth embodiment; FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an eighth embodiment; FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to a ninth embodiment. FIG. 16 is a cross-sectional view showing the structure of the semiconductor device according to the tenth embodiment; FIG. 16 is a cross-sectional view showing the structure of the semiconductor device according to the tenth embodiment; 14 is a sectional view showing a structure of a semiconductor device according to an eleventh embodiment; FIG. 14 is a sectional view showing a structure of a semiconductor device according to an eleventh embodiment; FIG. 14 is a sectional view showing a structure of a semiconductor device according to an eleventh embodiment; FIG. 14 is a sectional view showing a structure of a semiconductor device according to an eleventh embodiment; FIG. FIG. 22 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the twelfth embodiment; FIG. 22 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the twelfth embodiment; FIG. 22 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the twelfth embodiment; FIG. 22 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the twelfth embodiment; FIG. 22 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the twelfth embodiment; FIG. 23 is a cross-sectional view showing another method for manufacturing the semiconductor device according to the twelfth embodiment; FIG. 23 is a cross-sectional view showing another method for manufacturing the semiconductor device according to the twelfth embodiment; FIG. 23 is a cross-sectional view showing another method for manufacturing the semiconductor device according to the twelfth embodiment; FIG. 23 is a cross-sectional view showing another method for manufacturing the semiconductor device according to the twelfth embodiment; FIG. 23 is a cross-sectional view showing another method for manufacturing the semiconductor device according to the twelfth embodiment; FIG. 6 is a characteristic diagram showing a relationship between a minimum required initial film thickness t21′min and a selection ratio S. It is a top view which shows the structure of the vertical MOS device of a 1st prior art example. FIG. 61 is a cross-sectional view showing a cross-sectional structure along a cutting line DD ′ in FIG. 60. It is sectional drawing which shows the structure of the trench gate type semiconductor device of the 2nd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 2nd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 2nd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 2nd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 2nd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 2nd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 2nd prior art example. It is sectional drawing which shows the structure of the trench gate type semiconductor device of a 3rd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 3rd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 3rd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 3rd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 3rd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 3rd prior art example. It is sectional drawing which shows the manufacturing method of the trench gate type semiconductor device of a 3rd prior art example. It is a figure which shows the problem of the trench gate type semiconductor device of the 2nd prior art example. It is a figure which shows the problem of the trench gate type semiconductor device of a 3rd prior art example.

Explanation of symbols

1 n ⁺⁺ substrate 2 n-type drift region (first conductivity type semiconductor region)
3 p-type partition region (second conductivity type semiconductor region)
4 second trench 5 n-type surface buffer region 6 gate oxide film 7 gate electrode 8 p base region 9a first n ⁺ source region 9b second n ⁺ source region 10 p ⁺ pickup region 11 source electrode 12 drain electrode 24 interlayer insulating film

Claims (11)

A first impurity type semiconductor substrate having a high impurity concentration; a parallel pn layer provided on the surface of the semiconductor substrate, wherein the first and second conductivity type semiconductor regions are alternately arranged; and the parallel pn layer A trench provided in either the second conductive type semiconductor region or the first conductive type semiconductor region of the layer, an insulating film provided on an inner surface of the trench, and a gate electrode provided via the insulating film In a semiconductor device comprising:
A semiconductor device characterized in that a first-conductivity-type surface buffer region having no corner is provided so as to cover at least a corner of the bottom surface of the trench.   The semiconductor device according to claim 1, wherein the surface buffer region has a thermally diffused shape.   3. The semiconductor device according to claim 1, wherein a back surface buffer region of a first conductivity type is provided between the semiconductor substrate and the parallel pn layer.   A second conductivity type layer having a higher impurity concentration than that of the second conductivity type semiconductor region is provided between the semiconductor substrate and the second conductivity type semiconductor region of the parallel pn layer. Item 4. The semiconductor device according to any one of Items 1 to 3.   The semiconductor device according to claim 1, wherein the surface buffer region is provided only in the vicinity of a corner portion of the bottom surface of the trench. A semiconductor generation step of generating a first conductivity type semiconductor or a second conductivity type semiconductor on the surface of a first conductivity type semiconductor substrate having a high impurity concentration;
A first trench formation step of forming a first trench in one of the conductive type semiconductors generated in the semiconductor generation step using an insulating film mask as a mask;
A parallel pn layer forming step for forming a parallel pn layer in which one conductive type semiconductor region and the other conductive type semiconductor region are alternately arranged by generating a semiconductor of the other conductive type in the first trench. When,
A second trench forming step of forming a second trench in the semiconductor region of the other conductivity type using the insulating film mask as a mask;
Forming a gate electrode in the second trench through a gate oxide film; and
A method for manufacturing a semiconductor device, comprising: A semiconductor generation step of generating a first conductivity type semiconductor or a second conductivity type semiconductor on a surface of a first impurity type semiconductor substrate having a high impurity concentration;
A first trench formation step of forming a first trench in one of the conductivity type semiconductors generated in the semiconductor generation step using an insulating film mask as a mask;
A parallel pn layer forming step for forming a parallel pn layer in which one conductivity type semiconductor region and the other conductivity type semiconductor region are alternately arranged by generating a semiconductor of the other conductivity type in the first trench. When,
Polishing the other conductivity type semiconductor to align the height of the insulating film mask and the other conductivity type semiconductor region;
A second trench forming step of forming a second trench by removing the insulating film mask;
Forming a gate electrode in the second trench through a gate oxide film; and
A method for manufacturing a semiconductor device, comprising:   8. The method of manufacturing a semiconductor device according to claim 6, further comprising a back surface buffer region forming step of forming a back surface buffer region of a first conductivity type on the surface of the semiconductor substrate before the semiconductor generation step. Method.   The semiconductor according to claim 6, further comprising an epitaxial layer forming step of forming a second conductivity type epitaxial layer on the surface of the semiconductor substrate before the semiconductor generating step. Device manufacturing method. Between the second trench formation step and the gate electrode formation step,
An ion implantation step of ion-implanting a first conductivity type impurity into at least a corner of the bottom surface of the second trench;
After the gate electrode formation process,
And a surface buffer region forming step of performing thermal diffusion on the first conductivity type impurities implanted in the ion implantation step to form a surface buffer region at a corner of the bottom surface of the second trench. Item 10. A method for manufacturing a semiconductor device according to any one of Items 6 to 9.   11. The method of manufacturing a semiconductor device according to claim 10, wherein in the ion implantation step, the first conductivity type impurity is not ion-implanted into a central portion of a bottom surface of the second trench.

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