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JP2009200203A - Die bonder and die-bonding method - Google Patents

Die bonder and die-bonding method Download PDF

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Publication number
JP2009200203A
JP2009200203A JP2008039634A JP2008039634A JP2009200203A JP 2009200203 A JP2009200203 A JP 2009200203A JP 2008039634 A JP2008039634 A JP 2008039634A JP 2008039634 A JP2008039634 A JP 2008039634A JP 2009200203 A JP2009200203 A JP 2009200203A
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substrate
chip
pattern
bonding
transparent member
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JP4831091B2 (en
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Kazuhiro Noda
和宏 野田
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a die bonder that can carry out a die-bonding process on a BOC-type electronic component at low cost using a conventional die bonder, as well as, to provide a die-bonding method for the component. <P>SOLUTION: A substrate 1, whose pattern formation surface 1a is turned downward is placed on an upper surface of a transparent member 21, having a mirror member 20 on its lower surface, with the mirror member whose mirror side 20a being turned upward, and by having the inside of the wire insertion hole 17 imaged from above the substrate 1 placed on the upper surface of the transparent member 21; and the reflected image of a substrate-side pattern 2 that is projected onto the mirror surface 20a is acquired and this is perceived through the wire insertion hole 17 and the transparent member 21, and the position of the substrate-side pattern 2 is recognized. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、いわゆるＢＯＣ（ボードオンチップ）タイプの電子部品の製造過程におけるダイボンディング工程で使用されるダイボンディング装置及びダイボンディング方法に関するものである。   The present invention relates to a die bonding apparatus and a die bonding method used in a die bonding process in a manufacturing process of a so-called BOC (board on chip) type electronic component.

従来、電子部品のサイズを小さくする目的等から、チップの電極形成面にリードを接着し、チップ側の電極とリードとをワイヤ接続した、いわゆるＬＯＣ（リードオンチップ）タイプの電子部品が知られている（特許文献１、２、３）。また、このＬＯＣタイプの電子部品と類似した構成を有する電子部品として、基板のパターン形成面とは反対側の面（チップ接合面）にチップを接合し、基板の板厚方向に貫通して設けられた貫通孔を通して基板側電極とチップ側電極をワイヤ接続したＢＯＣタイプの電子部品も知られている。   Conventionally, for the purpose of reducing the size of an electronic component, a so-called LOC (lead-on-chip) type electronic component in which a lead is bonded to a chip electrode forming surface and the chip-side electrode and the lead are wire-connected is known. (Patent Documents 1, 2, and 3). Further, as an electronic component having a configuration similar to this LOC type electronic component, a chip is bonded to a surface (chip bonding surface) opposite to the pattern forming surface of the substrate, and is provided so as to penetrate in the plate thickness direction of the substrate. A BOC type electronic component in which a substrate side electrode and a chip side electrode are wire-connected through the formed through hole is also known.

図９は従来のＢＯＣタイプの電子部品の製造過程におけるダイボンディング工程の実行手順を示す図である。この図に示すように、従来では、基板１側の電極（基板側電極）を含む基板側パターン２が形成されたパターン形成面１ａを上に向けた状態で基板１を所定位置に保持した後、チップ３側の電極（チップ側電極４）を上に向けたチップ３を移動ステージ５の上面に載置し、移動ステージ５を基板１の下方に移動させて基板１のパターン形成面１ａと反対側のチップ接合面１ｂ（ここでは下面）にチップ３を下方から当接させ（図中に示す矢印Ａ）、次いで基板１の上方から熱圧着ツール６により移動ステージ５上のチップ３に基板１を押し付けて（図中に示す矢印Ｂ）基板１にチップ３を接合していた。このような方法では、基板１側のパターン形成面１ａとチップ３側の電極形成面３ａのそれぞれを上方からカメラ（基板１側のパターン形成面１ａの認識を行う基板側認識カメラ７及びチップ３側の電極形成面３ａの認識を行うチップ側認識カメラ８）で認識することができるので、基板１に対するチップ３の位置合わせ（アライメント）を容易に行うことができる。
特開平１１−２９７７２２号公報 特開２００１−８５４５１号公報 特開２００４−１４０１３９号公報 FIG. 9 is a diagram showing an execution procedure of a die bonding process in the manufacturing process of a conventional BOC type electronic component. As shown in this figure, conventionally, after the substrate 1 is held at a predetermined position with the pattern formation surface 1a on which the substrate-side pattern 2 including the substrate-side electrode (substrate-side electrode) is formed facing upward The chip 3 with the chip 3 side electrode (chip side electrode 4) facing upward is placed on the upper surface of the moving stage 5, and the moving stage 5 is moved below the substrate 1 to form the pattern forming surface 1 a of the substrate 1. The chip 3 is brought into contact with the chip bonding surface 1b (the lower surface in this case) on the opposite side from below (arrow A shown in the figure), and then the substrate 1 is placed on the chip 3 on the moving stage 5 from above the substrate 1 by the thermocompression bonding tool 6. 1 was pressed (arrow B shown in the figure), and the chip 3 was bonded to the substrate 1. In such a method, the pattern forming surface 1a on the substrate 1 side and the electrode forming surface 3a on the chip 3 side are respectively viewed from above with a camera (the substrate side recognition camera 7 for recognizing the pattern forming surface 1a on the substrate 1 side and the chip 3). Since it can be recognized by the chip side recognition camera 8) for recognizing the side electrode forming surface 3a, the alignment (alignment) of the chip 3 with respect to the substrate 1 can be easily performed.
JP 11-297722 A JP 2001-85451 A JP 2004-140139 A

しかしながら、上記従来の方法では、上述の動作を行うＢＯＣ専用のダイボンディング装置が必要であったため、コスト高であるという問題点があった。そこで、現在多くの電子部品の製造現場で用いられている従来型のダイボンディング装置（例えばフリップチップ型のダイボンディング装置）を流用することが考えられるが、そうすると、基板１はパターン形成面１ａが下を向く状態で基板載置台（図９には図示せず）に載置したうえで、基板１の上面となっているチップ接合面１ｂに、チップ３側の電極形成面３ａを下に向けたチップ３を上方から押し付けて熱圧着することになる。   However, the above-described conventional method has a problem in that the cost is high because a BOC-dedicated die bonding apparatus that performs the above-described operation is required. Thus, it is conceivable to use a conventional die bonding apparatus (for example, a flip chip type die bonding apparatus) that is currently used in many electronic component manufacturing sites. In this case, the substrate 1 has a pattern forming surface 1a. After placing on a substrate mounting table (not shown in FIG. 9) facing downward, the electrode forming surface 3a on the chip 3 side faces downward on the chip bonding surface 1b which is the upper surface of the substrate 1. The chip 3 is pressed from above and thermocompression bonded.

ところが、このような方法では、チップ３側の電極形成面３ａはチップ３を基板１上に移動させるまでの間に、撮像面を上方に向けて配置したチップ側認識カメラ８によって下方から認識することができるものの、基板載置台に載置された基板１のパターン形成面１ａは基板載置台の上面に接触しているため、パターン形成面１ａに形成された基板側電極等の基板側パターン２の位置を認識することができず、ダイボンディング工程に必要な基板１とチップ３の正確な位置合わせを行うことができない。このため、従来型のダイボンディング装置を流用することはできず、ＢＯＣタイプの電子部品の製造過程におけるダイ
ボンディング工程を安価に行うことができなかった。 However, in such a method, the electrode forming surface 3a on the chip 3 side is recognized from below by the chip-side recognition camera 8 arranged with the imaging surface facing upward until the chip 3 is moved onto the substrate 1. However, since the pattern forming surface 1a of the substrate 1 placed on the substrate mounting table is in contact with the upper surface of the substrate mounting table, the substrate side pattern 2 such as a substrate side electrode formed on the pattern forming surface 1a. Cannot be recognized, and accurate alignment of the substrate 1 and the chip 3 required for the die bonding process cannot be performed. For this reason, the conventional die bonding apparatus cannot be used, and the die bonding process in the manufacturing process of the BOC type electronic component cannot be performed at low cost.

そこで本発明は、従来型のダイボンディング装置を流用してＢＯＣタイプの電子部品のダイボンディング工程を安価に行うことができるダイボンディング装置及びダイボンディング方法を提供することを目的とする。   Accordingly, an object of the present invention is to provide a die bonding apparatus and a die bonding method capable of diverting a die bonding process of a BOC type electronic component at low cost by using a conventional die bonding apparatus.

請求項１に記載のダイボンディング装置は、基板側電極を含む基板側パターンが形成されたパターン形成面、パターン形成面と反対側のチップ接合面及び板厚方向に貫通して設けられた貫通孔を有した基板のチップ接合面にチップを接合するダイボンディング装置であって、ミラー面を上方に向けたミラー部材を下面に有した透明部材と、パターン形成面を下方に向けた基板が透明部材の上面に載置された状態で、基板の上方から貫通孔内を撮像することにより、貫通孔及び透明部材を通して視認されるミラー面に映った基板側パターンの反射画像を取得し、その取得した基板側パターンの反射画像から基板側パターンの位置の認識を行う認識手段と、認識手段において認識した基板側パターンの位置に基づいて基板とチップの位置合わせを行い、基板のチップ接合面にチップを接合するチップ接合手段とを備えた。   The die bonding apparatus according to claim 1, wherein a pattern forming surface on which a substrate-side pattern including a substrate-side electrode is formed, a chip bonding surface opposite to the pattern forming surface, and a through-hole provided through the plate thickness direction A die bonding apparatus for bonding a chip to a chip bonding surface of a substrate having a transparent member having a mirror member with a mirror surface facing upward and a substrate with a pattern forming surface facing downward. In the state of being placed on the upper surface of the substrate, by capturing an image of the inside of the through-hole from above the substrate, a reflection image of the substrate-side pattern reflected on the mirror surface viewed through the through-hole and the transparent member is acquired and acquired. Recognition means for recognizing the position of the substrate side pattern from the reflection image of the substrate side pattern, and alignment of the substrate and the chip based on the position of the substrate side pattern recognized by the recognition means There was a chip bonding means for bonding the chip to the chip bonding surface of the substrate.

請求項２に記載のダイボンディング方法は、基板側電極を含む基板側パターンが形成されたパターン形成面、パターン形成面と反対側のチップ接合面及び板厚方向に貫通して設けられた貫通孔を有した基板のチップ接合面にチップを接合するダイボンディング方法であって、ミラー面を上方に向けたミラー部材を下面に有した透明部材の上面に、パターン形成面を下方に向けた基板を載置する基板載置工程と、透明部材の上面に基板を載置した状態で基板の上方から貫通孔内を撮像することにより、貫通孔及び透明部材を通して視認されるミラー面に映った基板側パターンの反射画像を取得し、その取得した基板側パターンの反射画像から基板側パターンの位置の認識を行なう認識工程と、認識工程において認識した基板側パターンの位置に基づいて基板とチップの位置合わせを行い、基板のチップ接合面にチップを接合するチップ接合工程とを含む。   3. The die bonding method according to claim 2, wherein a pattern forming surface on which a substrate side pattern including a substrate side electrode is formed, a chip bonding surface opposite to the pattern forming surface, and a through hole provided penetrating in the plate thickness direction. A die bonding method for bonding a chip to a chip bonding surface of a substrate having a substrate, wherein a substrate having a mirror member facing upward is provided on the upper surface of a transparent member having a mirror member facing downward, and a substrate having a pattern forming surface directed downward. Substrate placement process, and substrate side reflected on the mirror surface viewed through the through hole and the transparent member by imaging the inside of the through hole from above the substrate with the substrate placed on the upper surface of the transparent member Acquire a reflection image of the pattern, recognize the position of the substrate side pattern from the acquired reflection image of the substrate side pattern, and the position of the substrate side pattern recognized in the recognition step It aligns the substrate and the chip Zui, and a chip bonding step of bonding the chip to the chip bonding surface of the substrate.

本発明では、ミラー面を上方に向けたミラー部材を下面に有した透明部材の上面に、パターン形成面を下方に向けた基板を載置し、その透明部材の上面に載置した基板の上方から貫通孔内を撮像することにより、貫通孔及び透明部材を通して視認されるミラー面に映った基板側パターンの反射画像を取得し、基板側パターンの位置の認識を行うようになっている。このため従来型のダイボンディング装置を流用することができ、ＢＯＣタイプの電子部品のダイボンディング工程を安価に行うことができる。   In the present invention, a substrate with a pattern forming surface facing downward is placed on the upper surface of a transparent member having a mirror member with the mirror surface facing upward, and the substrate placed on the upper surface of the transparent member is placed above the transparent member. By picking up an image of the inside of the through hole, a reflected image of the substrate side pattern reflected on the mirror surface viewed through the through hole and the transparent member is acquired, and the position of the substrate side pattern is recognized. Therefore, a conventional die bonding apparatus can be used, and the die bonding process for BOC type electronic components can be performed at low cost.

以下、図面を参照して本発明の実施の形態について説明する。図１は本発明の一実施の形態におけるダイボンディング装置の構成図、図２は本発明の一実施の形態における基板をパターン形成面側から見た図、図３は本発明の一実施の形態における基板をチップ接合面側から見た図、図４（ａ），（ｂ）、図５（ａ），（ｂ）及び図６（ａ），（ｂ）は本発明の一実施の形態におけるダイボンディング工程の手順を示す工程図、図７は本発明の一実施の形態におけるダイボンディング装置の基板側認識カメラによって視認される基板側パターンの反射画像を含む画像の一例を示す図、図８は本発明の一実施の形態におけるダイボンディング装置によりダイボンディング工程を行ったチップから製造されるＢＯＣタイプの電子部品の側断面図である。   Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a die bonding apparatus according to an embodiment of the present invention, FIG. 2 is a diagram of a substrate according to an embodiment of the present invention viewed from the pattern forming surface side, and FIG. 3 is an embodiment of the present invention. FIGS. 4A, 4B, 5A, 5B, 6A, and 6B show the substrate in FIG. 6 as viewed from the chip bonding surface. FIG. 7 is a process diagram showing the procedure of the die bonding process, and FIG. 7 is a diagram showing an example of an image including a reflection image of the substrate side pattern visually recognized by the substrate side recognition camera of the die bonding apparatus in one embodiment of the present invention. These are the sectional side views of the BOC type electronic component manufactured from the chip | tip which performed the die bonding process with the die bonding apparatus in one embodiment of this invention.

図１において、本発明の一実施の形態におけるダイボンディング装置１０は従来知られたフリップチップ型のダイボンディング装置を流用した構成を有しており、基板１が載置
される基板載置台１１、基板１に接合されるチップ３ごとに裁断された半導体ウェハ１２（各チップ３の電極形成面３ａは上向き）を保持するウェハ保持部１３、半導体ウェハ１２から供給されるチップ３を吸着（ピックアップ）して水平方向に移動するとともに、水平軸回りに回転してチップ３の上下面を反転させる反転ツール１４、反転ツール１４により上下が反転されたチップ３を吸着して基板載置台１１に載置された基板１に移載し、その移載したチップ３を基板１上に熱圧着する熱圧着機能付きの移載ツール１５、撮像面を下方に向けて設けられ、基板載置台１１に載置された基板１上を上方から視認する基板側認識カメラ７、撮像面を上方に向けて設けられ、移載ツール１５に吸着されたチップ３の下面（電極形成面３ａ）を下方から視認するチップ側認識カメラ８及び制御装置１６を備える。制御装置１６は、反転ツール１４によるチップ３の吸着と移動及び上下反転の制御、移載ツール１５によるチップ３の吸着と基板１上への移載の制御、基板側認識カメラ７とチップ側認識カメラ８の作動制御を行うほか、基板側認識カメラ７及びチップ側認識カメラ８から送られてきた画像情報に基づいた所要の演算処理等を行う。 In FIG. 1, a die bonding apparatus 10 according to an embodiment of the present invention has a configuration using a conventionally known flip chip type die bonding apparatus, and includes a substrate mounting table 11 on which a substrate 1 is mounted, Wafer holder 13 for holding a semiconductor wafer 12 cut for each chip 3 bonded to the substrate 1 (the electrode forming surface 3a of each chip 3 faces upward), and the chip 3 supplied from the semiconductor wafer 12 is picked up (pickup) The reversing tool 14 that rotates in the horizontal direction and rotates about the horizontal axis to reverse the upper and lower surfaces of the chip 3 and the chip 3 whose top and bottom are reversed by the reversing tool 14 are sucked and placed on the substrate mounting table 11. The transfer tool 15 having a thermocompression bonding function for transferring and transferring the transferred chip 3 onto the substrate 1 is provided with the imaging surface facing downward. A substrate-side recognition camera 7 for visually recognizing the substrate 1 placed on the table 11 from above, the lower surface of the chip 3 (electrode formation surface 3a) provided with the imaging surface facing upward and attracted to the transfer tool 15 A chip-side recognition camera 8 and a control device 16 that are viewed from below are provided. The control device 16 controls the suction and movement of the chip 3 by the reversing tool 14 and the upside down control, the control of the suction of the chip 3 by the transfer tool 15 and the transfer onto the substrate 1, the substrate side recognition camera 7 and the chip side recognition. In addition to controlling the operation of the camera 8, necessary arithmetic processing based on image information sent from the substrate-side recognition camera 7 and the chip-side recognition camera 8 is performed.

図２及び図３において、基板１は例えば樹脂製の板状の部材から成る。基板１の一方の面は基板１側の電極（基板側電極２ａ）や各基板側電極２ａに対応して設けられた半田ボール形成パッド２ｂ等から成る基板側パターン２が形成されたパターン形成面１ａとなっており、パターン形成面１ａと反対側の面はチップ３が搭載されるチップ接合面１ｂとなっている。   2 and 3, the substrate 1 is made of, for example, a resin plate-like member. One surface of the substrate 1 is a pattern forming surface on which a substrate side pattern 2 composed of electrodes (substrate side electrodes 2a) on the substrate 1 side, solder ball forming pads 2b provided corresponding to the respective substrate side electrodes 2a, etc. is formed. The surface opposite to the pattern forming surface 1a is a chip bonding surface 1b on which the chip 3 is mounted.

図２及び図３において、基板１には基板１を板厚方向（基板１の厚さ方向）に貫通する貫通孔である細長形状のワイヤ挿通孔１７が複数、格子状に整列して設けられており、基板側電極２ａは各ワイヤ挿通孔１７のエッジ１７ａ（主としてワイヤ挿通孔１７の長手方向のエッジ）の近傍領域に複数並んで設けられており、ワイヤ挿通孔１７を挟んで対称（ワイヤ挿通孔１７の幅方向（図２の紙面上下方向）に対して対称）となる位置に、ワイヤ挿通孔１７の長手方向に延びた２列の電極列を形成している（図２中の拡大図参照）。半田ボール形成パッド２ｂは基板側電極２ａの電極列の外側の領域に、エッジ１７ａに沿って（すなわち基板側電極２ａに沿って）並んで設けられている。   2 and 3, the substrate 1 is provided with a plurality of elongated wire insertion holes 17 which are through holes penetrating the substrate 1 in the plate thickness direction (thickness direction of the substrate 1), arranged in a lattice pattern. A plurality of substrate side electrodes 2a are provided side by side in the vicinity of the edge 17a of each wire insertion hole 17 (mainly the edge in the longitudinal direction of the wire insertion hole 17). Two electrode rows extending in the longitudinal direction of the wire insertion hole 17 are formed at positions that are symmetric with respect to the width direction of the insertion hole 17 (the vertical direction in FIG. 2) (enlarged in FIG. 2). (See figure). The solder ball forming pads 2b are provided along the edge 17a (that is, along the substrate side electrode 2a) in a region outside the electrode row of the substrate side electrode 2a.

図４（ａ）において、基板載置台１１は、板状のベース部材１９と、ベース部材１９の上面側に設けられてミラー面２０ａを上方に向けたミラー部材２０と、ミラー部材２０の上面側に設けられた板状の透明部材（例えばガラス板）２１を有して成る。すなわち基板載置台１１は、ミラー面２０ａを上方に向けたミラー部材２０を下面に有した透明部材２１を備えている。この透明部材２１の上面には、パターン形成面１ａを下方に向けた基板１が載置される。基板載置台１１には透明部材２１に載置された基板１を着脱自在に保持する図示しない基板保持機構が備えられている。   4A, the substrate mounting table 11 includes a plate-like base member 19, a mirror member 20 provided on the upper surface side of the base member 19 with the mirror surface 20a facing upward, and an upper surface side of the mirror member 20. And a plate-like transparent member (for example, a glass plate) 21 provided on the plate. That is, the substrate mounting table 11 includes a transparent member 21 having a mirror member 20 on the lower surface with the mirror surface 20a facing upward. On the upper surface of the transparent member 21, the substrate 1 is placed with the pattern forming surface 1a facing downward. The substrate mounting table 11 is provided with a substrate holding mechanism (not shown) that detachably holds the substrate 1 placed on the transparent member 21.

ミラー部材２０はベース部材１９及び透明部材２１と別個の部材として設けられ、これがベース部材１９及び透明部材２１と貼り合わされているのであってもよいし、透明部材２１の下面若しくはベース部材１９の上面に銀やアルミニウム等を蒸着して形成した（コーティングした）反射膜であってもよい。なお、ベース部材１９、ミラー部材２０及び透明部材２１は、チップ３を基板１に熱圧着するときの押圧力に耐え得る強度を有している。   The mirror member 20 is provided as a separate member from the base member 19 and the transparent member 21, and may be bonded to the base member 19 and the transparent member 21, or the lower surface of the transparent member 21 or the upper surface of the base member 19. Alternatively, a reflective film formed by coating (coating) silver or aluminum may be used. The base member 19, the mirror member 20, and the transparent member 21 have a strength that can withstand the pressing force when the chip 3 is thermocompression bonded to the substrate 1.

次に、図４、図５及び図６を用いて上記ダイボンディング装置１０によりチップ３を基板１に接合するダイボンディング工程の手順を説明する。ここで示すダイボンディング工程の手順は、本発明の一実施の形態におけるダイボンディング方法に相当する。基板１上には複数のチップ３が接合されるが、チップ３は１つずつ、以下に示す手順で基板１上に接合される。   Next, a procedure of a die bonding process for bonding the chip 3 to the substrate 1 by the die bonding apparatus 10 will be described with reference to FIGS. 4, 5, and 6. The procedure of the die bonding step shown here corresponds to the die bonding method in one embodiment of the present invention. A plurality of chips 3 are bonded on the substrate 1, and the chips 3 are bonded onto the substrate 1 one by one in the following procedure.

基板１にチップ３を接合するには、先ず、図４（ａ）及び図４（ｂ）に示すように、基板１を基板載置台１１の透明部材２１の上面に載置する（図４（ａ）中に示す矢印Ｃ）。このとき基板１はパターン形成面１ａが下方を向く状態とし、上面のチップ接合面１ｂにはチップ３を接着するための接着剤２２（ここでは熱硬化性樹脂とする）を予め塗布しておく。基板載置台１１に基板１が載置されると、図４（ｂ）に示すように、基板１のパターン形成面１ａが透明部材２１を介してミラー部材２０のミラー面２０ａと上下に対向した状態となる。基板載置台１１に基板１を載置したら、基板保持機構によって基板１を基板載置台１１に保持する（基板載置工程）。   In order to bond the chip 3 to the substrate 1, first, the substrate 1 is placed on the upper surface of the transparent member 21 of the substrate platform 11 as shown in FIGS. a) Arrow C) shown in the figure. At this time, the substrate 1 is in a state in which the pattern forming surface 1a faces downward, and an adhesive 22 (here, a thermosetting resin) for bonding the chip 3 is previously applied to the upper chip bonding surface 1b. . When the substrate 1 is placed on the substrate platform 11, the pattern forming surface 1 a of the substrate 1 faces the mirror surface 20 a of the mirror member 20 in the vertical direction via the transparent member 21 as shown in FIG. It becomes a state. After the substrate 1 is placed on the substrate platform 11, the substrate 1 is held on the substrate platform 11 by the substrate holding mechanism (substrate placement step).

基板載置工程が終了したら、制御装置１６から反転ツール１４の作動制御を行って、ウェハ保持部１３上に保持された半導体ウェハ１２から１つのチップ３を吸着して取り出す（図１中に示す矢印Ｄ）。そして、そのチップ３を吸着した反転ツール１４を移載ツール１５が待機する所定の位置まで移動させた後（図１中に示す矢印Ｅ）、反転ツール１４を水平軸回りに回転させて、チップ３を上下反転させる（図１中に示す矢印Ｆ）。このチップ３の上下反転により、チップ３の電極形成面３ａは下方を向くことになる。   When the substrate placement process is completed, the control device 16 controls the operation of the reversing tool 14 to suck and take out one chip 3 from the semiconductor wafer 12 held on the wafer holding unit 13 (shown in FIG. 1). Arrow D). Then, after the reversing tool 14 that has sucked the chip 3 is moved to a predetermined position where the transfer tool 15 waits (arrow E shown in FIG. 1), the reversing tool 14 is rotated around the horizontal axis, and the chip is rotated. 3 is turned upside down (arrow F shown in FIG. 1). As the chip 3 is turned upside down, the electrode forming surface 3a of the chip 3 faces downward.

制御装置１６は反転ツール１４によりチップ３を上下反転させたら、次いで移載ツール１５の作動制御を行って、反転ツール１４が吸着しているチップ３を移載ツール１５に吸着させる（図１中に示す矢印Ｇ）。そして、移載ツール１５の作動制御を行って、移載ツール１５が吸着したチップ３が撮像面を上方に向けたチップ側認識カメラ８の撮像視野内に入る位置まで移載ツール１５を移動させる（図１中に示す矢印Ｈ）。移載ツール１５が吸着したチップ３がチップ側認識カメラ８の撮像視野内に入ったら、制御装置１６はチップ側認識カメラ８の作動制御を行って、チップ側認識カメラ８にチップ３の下面（電極形成面３ａ）の撮像を行わせる。制御装置１６は、チップ側認識カメラ８から送られてきたチップ３の電極形成面３ａの画像情報に基づいて、チップ側電極４の位置の認識を行う。   After the chip 16 is turned upside down by the reversing tool 14, the control device 16 then controls the operation of the transfer tool 15 to suck the chip 3 sucked by the reversing tool 14 onto the transfer tool 15 (in FIG. 1). Arrow G). Then, the operation control of the transfer tool 15 is performed, and the transfer tool 15 is moved to a position where the chip 3 attracted by the transfer tool 15 falls within the imaging field of view of the chip-side recognition camera 8 with the imaging surface facing upward. (Arrow H shown in FIG. 1). When the chip 3 attracted by the transfer tool 15 enters the imaging field of view of the chip-side recognition camera 8, the control device 16 controls the operation of the chip-side recognition camera 8 and causes the chip-side recognition camera 8 to control the lower surface of the chip 3 ( The electrode forming surface 3a) is imaged. The control device 16 recognizes the position of the chip side electrode 4 based on the image information of the electrode forming surface 3 a of the chip 3 sent from the chip side recognition camera 8.

制御装置１６は、チップ側認識カメラ８によるチップ側電極４の位置の認識を行った後、若しくはその間に、基板側パターン２（基板側電極２ａ）の位置の認識を行う。基板側パターン２の位置の認識を行うには、先ず、基板１に対して基板側認識カメラ７を相対移動させ、下方に向けた基板認識側カメラ７の撮像面が、これから接合しようとしているチップ３の基板１上の目標搭載位置の直上に位置するようにする。チップ３の基板１上の目標搭載位置は、基板１上に設けられたワイヤ挿通孔１７の位置に対応しており、制御装置１６は、基板側認識カメラ７の撮像視野内にワイヤ挿通孔１７が入るように基板１と基板側認識カメラ７の位置調整を行う。   The control device 16 recognizes the position of the substrate side pattern 2 (substrate side electrode 2a) after or during the recognition of the position of the chip side electrode 4 by the chip side recognition camera 8. In order to recognize the position of the substrate-side pattern 2, first, the substrate-side recognition camera 7 is moved relative to the substrate 1, and the imaging surface of the substrate-recognition-side camera 7 facing downward is the chip to be joined. 3 is positioned immediately above the target mounting position on the substrate 1. The target mounting position of the chip 3 on the substrate 1 corresponds to the position of the wire insertion hole 17 provided on the substrate 1, and the control device 16 includes the wire insertion hole 17 in the imaging field of view of the substrate side recognition camera 7. The positions of the substrate 1 and the substrate-side recognition camera 7 are adjusted so that.

基板側認識カメラ７の撮像視野内にワイヤ挿通孔１７が入ったら、制御装置１６は、基板１に対する基板側認識カメラ７の位置を更に微調整し、ワイヤ挿通孔１７及び透明部材２１を通して、ミラー面２０ａに映った基板側パターン２（基板側電極２ａ）の反射画像（映り込み画像）が視認できるようにする（図５（ａ））。   When the wire insertion hole 17 enters the imaging field of the substrate side recognition camera 7, the control device 16 further finely adjusts the position of the substrate side recognition camera 7 with respect to the substrate 1, and passes through the wire insertion hole 17 and the transparent member 21 to pass through the mirror. A reflection image (reflection image) of the substrate side pattern 2 (substrate side electrode 2a) reflected on the surface 20a is made visible (FIG. 5A).

図７はこのとき基板側認識カメラ７によって視認される基板側パターン２の反射画像を含む画像２３の一例を示すものであり、ワイヤ挿通孔１７のエッジ１７ａを含む基板１の上面（チップ接合面１ｂ）の一部の画像とともに、ワイヤ挿通孔１７のエッジ１７ａの近傍の基板１の下面（パターン形成面１ａ）の一部がミラー面２０ａに映った反射画像として映し出されている（図７ではこの反射画像を破線で示している）。   FIG. 7 shows an example of an image 23 including a reflection image of the substrate-side pattern 2 visually recognized by the substrate-side recognition camera 7 at this time. The upper surface (chip bonding surface) of the substrate 1 including the edge 17a of the wire insertion hole 17 is shown. A part of the lower surface (pattern forming surface 1a) of the substrate 1 in the vicinity of the edge 17a of the wire insertion hole 17 is displayed as a reflected image reflected on the mirror surface 20a together with a part of the image 1b) (in FIG. 7). This reflection image is indicated by a broken line).

制御装置１６は、ワイヤ挿通孔１７及び透明部材２１を通して、ミラー面２０ａに映った基板側パターン２の反射画像が視認できるようになったら、その視認された上記画像２３を撮像する。これにより制御装置１６は、ミラー面２０ａに映った基板側パターン２の反射画像を取得することができる。制御装置１６は、基板側パターン２の反射画像を含む
画像２３を取得したら、その取得した画像２３に基づいて所要の演算を行い、基板側パターン２（基板側電極２ａ）の位置の認識を行う（認識工程）。そして、認識した基板側パターン２の位置から、目標搭載位置の正確な位置を算出する。 When the reflected image of the substrate side pattern 2 reflected on the mirror surface 20a can be visually recognized through the wire insertion hole 17 and the transparent member 21, the control device 16 captures the visually recognized image 23. Thereby, the control apparatus 16 can acquire the reflection image of the board | substrate side pattern 2 reflected on the mirror surface 20a. When acquiring the image 23 including the reflection image of the substrate side pattern 2, the control device 16 performs a required calculation based on the acquired image 23 and recognizes the position of the substrate side pattern 2 (substrate side electrode 2 a). (Recognition process). Then, an accurate position of the target mounting position is calculated from the recognized position of the substrate side pattern 2.

このように本実施の形態におけるダイボンディング装置１０では、基板側認識カメラ７及び制御装置１６から成る認識手段を備えており、この認識手段が、基板載置台１１の透明部材２１の上面に載置された基板１の上方からワイヤ挿通孔１７内を撮像することにより、ワイヤ挿通孔１７及び透明部材２１を通して視認されるミラー面２０ａに映った基板側パターン２の反射画像を取得し、その取得した基板側パターン２の反射画像から基板側パターン２の位置の認識を行うようになっている。   As described above, the die bonding apparatus 10 according to the present embodiment includes the recognition means including the substrate side recognition camera 7 and the control device 16, and this recognition means is placed on the upper surface of the transparent member 21 of the substrate placement table 11. The reflection image of the substrate side pattern 2 reflected on the mirror surface 20a viewed through the wire insertion hole 17 and the transparent member 21 is obtained by imaging the inside of the wire insertion hole 17 from above the obtained substrate 1, and the acquired The position of the substrate side pattern 2 is recognized from the reflected image of the substrate side pattern 2.

制御装置１６は、上記の認識工程が終わったら、基板側認識カメラ７を基板１に対して相対的に遠ざけた後、移載ツール１５の作動制御を行って、移載ツール１５に吸着させたチップ３を基板１上の目標搭載位置の直上に位置させる（図１中に示す矢印Ｉ）。   When the above recognition process is finished, the control device 16 moves the substrate side recognition camera 7 relatively away from the substrate 1, and then controls the operation of the transfer tool 15 so as to be attracted to the transfer tool 15. The chip 3 is positioned immediately above the target mounting position on the substrate 1 (arrow I shown in FIG. 1).

チップ３が基板１上の目標搭載位置の直上に位置したら、次いで制御装置１６は、認識工程において認識した基板側パターン２の位置に基づいて基板１とチップ３の位置合わせを行い、そのうえで、図５（ｂ）に示すように移載ツール１５を基板１に対して下降させる（図１中及び図５（ｂ）中に示す矢印Ｊ）。そして、移載ツール１５が吸着しているチップ３（前述のようにこのチップ３の電極形成面３ａは下方を向いている）を基板１上の目標搭載位置に載せた後、図６（ａ）に示すようにチップ３を基板１に押し付けて加熱し、接着剤２２を熱硬化させてチップ３を基板１に熱圧着する。これによりチップ３は基板１のチップ接合面１ｂに接合される（チップ接合工程）。   When the chip 3 is positioned immediately above the target mounting position on the substrate 1, the control device 16 then aligns the substrate 1 and the chip 3 based on the position of the substrate-side pattern 2 recognized in the recognition process, and As shown in FIG. 5B, the transfer tool 15 is lowered with respect to the substrate 1 (arrow J shown in FIG. 1 and FIG. 5B). Then, after the chip 3 to which the transfer tool 15 is attracted (the electrode forming surface 3a of the chip 3 faces downward as described above) is placed on the target mounting position on the substrate 1, FIG. ), The chip 3 is pressed against the substrate 1 and heated, the adhesive 22 is thermally cured, and the chip 3 is thermocompression bonded to the substrate 1. Thus, the chip 3 is bonded to the chip bonding surface 1b of the substrate 1 (chip bonding process).

チップ３が基板１のチップ接合面１ｂに接合された状態では、図６（ａ）に示すように、チップ側電極４はワイヤ挿通孔１７内に露出し、基板側電極２ａとチップ側電極４はワイヤ挿通孔１７のエッジ１７ａを挟んでワイヤ挿通孔１７の幅方向（図６の紙面左右方向）に対向する。   In a state where the chip 3 is bonded to the chip bonding surface 1b of the substrate 1, as shown in FIG. 6A, the chip side electrode 4 is exposed in the wire insertion hole 17, and the substrate side electrode 2a and the chip side electrode 4 are exposed. Is opposed to the wire insertion hole 17 in the width direction (left and right direction in FIG. 6) with the edge 17a of the wire insertion hole 17 interposed therebetween.

チップ接合工程が終了したら、制御装置１６は移載ツール１５の作動制御を行って移載ツール１５によるチップ３の吸着を解除し、図６（ｂ）に示すように、移載ツール１５を上昇させる（図６（ｂ）中に示す矢印Ｋ）。これにより、１つのチップ３についてのダイボンディング工程が完了する。   When the chip joining process is completed, the control device 16 controls the operation of the transfer tool 15 to release the suction of the chip 3 by the transfer tool 15 and raises the transfer tool 15 as shown in FIG. (Arrow K shown in FIG. 6B). Thereby, the die bonding process for one chip 3 is completed.

以下、同様にして基板１上の全ての目標搭載位置にチップ３が接合される。そして、基板１上の全ての目標搭載位置にチップ３が接合されたら、その基板１についてのダイボンディング工程は終了し、その後の工程において図８に示すＢＯＣタイプの電子部品３０に加工される。ＢＯＣタイプの電子部品３０に加工されるまでには、上記のダイボンディング工程の後、基板側電極２ａとチップ側電極４を金ワイヤ３１等で接続するワイヤボンディング工程、ワイヤ挿通孔１７内に熱硬化性のモールド用樹脂３２を注入して基板１の下面に盛り付けた後、モールド用樹脂３２を熱硬化させて金ワイヤ３１を基板側電極２ａ及びチップ側電極４とともに一体化するモールド工程、各半田ボール形成パッド２ｂに半田ボール３３を形成する半田ボール形成工程及び基板１をチップ３ごとに裁断する裁断工程が実行される。   Thereafter, the chips 3 are bonded to all target mounting positions on the substrate 1 in the same manner. When the chips 3 are bonded to all the target mounting positions on the substrate 1, the die bonding process for the substrate 1 is completed, and the BOC type electronic component 30 shown in FIG. Before the BOC type electronic component 30 is processed, after the die bonding step, a wire bonding step of connecting the substrate side electrode 2a and the chip side electrode 4 with a gold wire 31 or the like, heat is generated in the wire insertion hole 17. A molding process in which a curable molding resin 32 is injected and placed on the lower surface of the substrate 1, and then the molding resin 32 is thermally cured to integrate the gold wire 31 together with the substrate-side electrode 2 a and the chip-side electrode 4. A solder ball forming process for forming the solder ball 33 on the solder ball forming pad 2b and a cutting process for cutting the substrate 1 for each chip 3 are executed.

以上説明したように、本実施の形態におけるダイボンディング装置１０は、ミラー面２０ａを上方に向けたミラー部材２０を下面に有した透明部材２１、パターン形成面１ａを下方に向けた基板１が透明部材２１の上面に載置された状態で、基板１の上方からワイヤ挿通孔１７（基板１を厚さ方向に貫通する貫通孔）内を撮像することにより、ワイヤ挿通孔１７及び透明部材２１を通して視認されるミラー面２０ａに映った基板側パターン２の
反射画像を取得し、その取得した基板側パターン２の反射画像から基板側パターン２の位置の認識を行う認識手段（基板側認識カメラ７及び制御装置１６）及び認識手段において認識した基板側パターン２の位置に基づいて基板１とチップ３の位置合わせを行い、基板１のチップ接合面１ｂにチップ３を接合するチップ接合手段（移載ツール１５及び制御装置１６）とを備えたものとなっている。 As described above, in the die bonding apparatus 10 according to the present embodiment, the transparent member 21 having the mirror member 20 with the mirror surface 20a facing upward and the substrate 1 with the pattern forming surface 1a facing downward are transparent. By imaging inside the wire insertion hole 17 (through hole penetrating the substrate 1 in the thickness direction) from above the substrate 1 while being placed on the upper surface of the member 21, the wire 21 passes through the wire insertion hole 17 and the transparent member 21. Recognizing means (a substrate-side recognition camera 7 and a recognition device for recognizing the position of the substrate-side pattern 2 from the reflected image of the substrate-side pattern 2 that acquires the reflected image of the substrate-side pattern 2 reflected on the mirror surface 20a that is visually recognized. The substrate 1 and the chip 3 are aligned based on the position of the substrate-side pattern 2 recognized by the control device 16) and the recognition means, and the chip is placed on the chip bonding surface 1b of the substrate 1. Has become that a chip junction means (transfer tool 15 and the controller 16) for joining.

また、本実施の形態におけるダイボンディング方法は、ミラー面２０ａを上方に向けたミラー部材２０を下面に有した透明部材２１の上面に、パターン形成面１ａを下方に向けた基板１を載置する基板載置工程と、透明部材２１の上面に基板１を載置した状態で基板１の上方からワイヤ挿通孔１７内を撮像することにより、ワイヤ挿通孔１７及び透明部材２１を通して視認されるミラー面２０ａに映った基板側パターン２の反射画像を取得し、その取得した基板側パターン２の反射画像から基板側パターン２の位置の認識を行なう認識工程及び認識工程において認識した基板側パターン２の位置に基づいて基板１とチップ３の位置合わせを行い、基板１のチップ接合面１ｂにチップ３を接合するチップ接合工程を含むものとなっている。   Further, in the die bonding method in the present embodiment, the substrate 1 with the pattern forming surface 1a facing downward is placed on the upper surface of the transparent member 21 having the mirror member 20 facing upward and the mirror member 20 facing downward. A mirror surface that is visually recognized through the wire insertion hole 17 and the transparent member 21 by imaging the inside of the wire insertion hole 17 from above the substrate 1 in a state where the substrate 1 is placed on the upper surface of the transparent member 21. The recognition process of acquiring the reflection image of the substrate side pattern 2 shown in 20a and recognizing the position of the substrate side pattern 2 from the acquired reflection image of the substrate side pattern 2, and the position of the substrate side pattern 2 recognized in the recognition process The substrate 1 and the chip 3 are aligned based on the above, and a chip bonding step of bonding the chip 3 to the chip bonding surface 1b of the substrate 1 is included.

このように、本実施の形態におけるダイボンディング装置（ダイボンディング方法）では、ミラー面２０ａを上方に向けたミラー部材２０を下面に有した透明部材２１の上面に、パターン形成面１ａを下方に向けた基板１を載置し、その透明部材２１の上面に載置した基板１の上方からワイヤ挿通孔１７内を撮像することにより、ワイヤ挿通孔１７及び透明部材２１を通して視認されるミラー面２０ａに映った基板側パターン２の反射画像を取得し、基板側パターン２の位置の認識を行うようになっている。このためフリップチップ型のダイボンディング装置のような従来型のダイボンディング装置を流用することができ、ＢＯＣタイプの電子部品３０のダイボンディング工程を安価に行うことができる。   Thus, in the die bonding apparatus (die bonding method) according to the present embodiment, the pattern forming surface 1a is directed downward on the upper surface of the transparent member 21 having the mirror member 20 with the mirror surface 20a facing upward on the lower surface. An image of the inside of the wire insertion hole 17 from above the substrate 1 placed on the upper surface of the transparent member 21 is placed on the mirror surface 20 a that is visible through the wire insertion hole 17 and the transparent member 21. A reflected image of the reflected substrate side pattern 2 is acquired, and the position of the substrate side pattern 2 is recognized. Therefore, a conventional die bonding apparatus such as a flip chip type die bonding apparatus can be used, and the die bonding process of the BOC type electronic component 30 can be performed at low cost.

これまで本発明の実施の形態について説明してきたが、本発明は上述の実施の形態に示したものに限定されない。例えば、上述の実施の形態では、チップ３を基板１のチップ接合面１ｂに接合する接着剤２２は熱硬化性樹脂であるとしていたが、この接着剤２２は、チップ３を基板１上に接合するものであれば必ずしも熱硬化製樹脂でなくてもよく、例えば接着テープ等であってもよい。   Although the embodiments of the present invention have been described so far, the present invention is not limited to those shown in the above-described embodiments. For example, in the above-described embodiment, the adhesive 22 that bonds the chip 3 to the chip bonding surface 1b of the substrate 1 is a thermosetting resin. However, the adhesive 22 bonds the chip 3 to the substrate 1. If it does, it may not necessarily be a thermosetting resin, for example, an adhesive tape or the like.

また、上述の実施の形態では、透明部材２１の上面に載置した基板１の上方からワイヤ挿通孔１７内を撮像することにより、ワイヤ挿通孔１７及び透明部材２１を通して視認されるミラー面２０ａに映った基板側パターン２の反射画像を取得し、これにより基板側パターン２の位置の認識を行なうようになっていたが、基板側パターン２として基板側電極２ａのほかに位置認識専用の認識マークをパターン形成面１ａに設けておき、その認識マークを基板側電極２ａの代わりに、あるいは基板側電極２ａとともに、基板側認識カメラ７によってその反射画像を取得するようにしてもよい。   Further, in the above-described embodiment, by imaging the inside of the wire insertion hole 17 from above the substrate 1 placed on the upper surface of the transparent member 21, the mirror surface 20 a that is visually recognized through the wire insertion hole 17 and the transparent member 21. The reflected image of the reflected substrate-side pattern 2 is acquired, and thereby the position of the substrate-side pattern 2 is recognized. In addition to the substrate-side electrode 2a, the substrate-side pattern 2 is a recognition mark dedicated to position recognition. May be provided on the pattern forming surface 1a, and the reflection image thereof may be acquired by the substrate side recognition camera 7 instead of the substrate side electrode 2a or together with the substrate side electrode 2a.

また、上述の実施の形態において示した基板１の形状は一例であり、パターン形成面１ａ、パターン形成面１ａと反対側のチップ接合面１ｂ及び板厚方向に貫通して設けられた貫通孔（上述の例ではワイヤ挿通孔１７）を有し、パターン形成面１ａに基板側パターン２が配設されたものであれば、その形状等は特に限定されない。   In addition, the shape of the substrate 1 shown in the above-described embodiment is an example. The pattern forming surface 1a, the chip bonding surface 1b opposite to the pattern forming surface 1a, and the through-holes provided through the plate thickness direction ( In the above-described example, the shape or the like is not particularly limited as long as it has the wire insertion hole 17) and the substrate-side pattern 2 is disposed on the pattern forming surface 1a.

従来型のダイボンディング装置を流用してＢＯＣタイプの電子部品のダイボンディング工程を安価に行うことができるダイボンディング装置及びダイボンディング方法を提供する。   Provided are a die bonding apparatus and a die bonding method capable of performing a die bonding process of a BOC type electronic component at a low cost by diverting a conventional die bonding apparatus.

本発明の一実施の形態におけるダイボンディング装置の構成図The block diagram of the die-bonding apparatus in one embodiment of this invention 本発明の一実施の形態における基板をパターン形成面側から見た図The figure which looked at the board | substrate in one embodiment of this invention from the pattern formation surface side 本発明の一実施の形態における基板をチップ接合面側から見た図The figure which looked at the board | substrate in one embodiment of this invention from the chip joint surface side （ａ）（ｂ）本発明の一実施の形態におけるダイボンディング工程の手順を示す工程図(A) (b) Process drawing which shows the procedure of the die bonding process in one embodiment of this invention （ａ）（ｂ）本発明の一実施の形態におけるダイボンディング工程の手順を示す工程図(A) (b) Process drawing which shows the procedure of the die bonding process in one embodiment of this invention （ａ）（ｂ）本発明の一実施の形態におけるダイボンディング工程の手順を示す工程図(A) (b) Process drawing which shows the procedure of the die bonding process in one embodiment of this invention 本発明の一実施の形態におけるダイボンディング装置の基板側認識カメラによって視認される基板側パターンの反射画像を含む画像の一例を示す図The figure which shows an example of the image containing the reflective image of the board | substrate side pattern visually recognized with the board | substrate side recognition camera of the die bonding apparatus in one embodiment of this invention 本発明の一実施の形態におけるダイボンディング装置によりダイボンディング工程を行ったチップから製造されるＢＯＣタイプの電子部品の側断面図1 is a side sectional view of a BOC type electronic component manufactured from a chip subjected to a die bonding process by a die bonding apparatus according to an embodiment of the present invention. 従来のＢＯＣタイプの電子部品の製造過程におけるダイボンディング工程の実行手順を示す図The figure which shows the execution procedure of the die bonding process in the manufacture process of the conventional BOC type electronic component

符号の説明Explanation of symbols

１ 基板
１ａ パターン形成面
１ｂ チップ接合面
２ 基板側パターン
２ａ 基板側電極
３ チップ
７ 基板側認識カメラ（認識手段）
１０ ダイボンディング装置
１５ 移載ツール（チップ接合手段）
１６ 制御装置（認識手段、チップ接合手段）
１７ ワイヤ挿通孔（貫通孔）
２０ ミラー部材
２０ａ ミラー面
２１ 透明部材 DESCRIPTION OF SYMBOLS 1 Substrate 1a Pattern formation surface 1b Chip joint surface 2 Substrate side pattern 2a Substrate side electrode 3 Chip 7 Substrate side recognition camera (recognition means)
10 Die Bonding Equipment 15 Transfer Tool (Chip Bonding Means)
16 Control device (recognition means, chip joining means)
17 Wire insertion hole (through hole)
20 Mirror member 20a Mirror surface 21 Transparent member

Claims (2)

基板側電極を含む基板側パターンが形成されたパターン形成面、パターン形成面と反対側のチップ接合面及び板厚方向に貫通して設けられた貫通孔を有した基板のチップ接合面にチップを接合するダイボンディング装置であって、ミラー面を上方に向けたミラー部材を下面に有した透明部材と、パターン形成面を下方に向けた基板が透明部材の上面に載置された状態で、基板の上方から貫通孔内を撮像することにより、貫通孔及び透明部材を通して視認されるミラー面に映った基板側パターンの反射画像を取得し、その取得した基板側パターンの反射画像から基板側パターンの位置の認識を行う認識手段と、認識手段において認識した基板側パターンの位置に基づいて基板とチップの位置合わせを行い、基板のチップ接合面にチップを接合するチップ接合手段とを備えたことを特徴とするダイボンディング装置。   A chip is placed on a chip-forming surface of a substrate having a pattern-forming surface on which a substrate-side pattern including a substrate-side electrode is formed, a chip-joining surface opposite to the pattern-forming surface, and a through-hole provided through the plate thickness direction. A die bonding apparatus for bonding, wherein a transparent member having a mirror member with a mirror surface facing upward and a substrate with a pattern forming surface facing downward are mounted on the upper surface of the transparent member. By capturing an image of the inside of the through-hole from above, a reflection image of the substrate-side pattern reflected on the mirror surface viewed through the through-hole and the transparent member is acquired, and the substrate-side pattern of the substrate-side pattern is obtained from the acquired reflection image of the substrate-side pattern. Recognizing means for recognizing the position and aligning the substrate and the chip based on the position of the substrate side pattern recognized by the recognizing means, and bonding the chip to the chip bonding surface of the substrate Die bonding apparatus characterized by comprising a chip bonding means. 基板側電極を含む基板側パターンが形成されたパターン形成面、パターン形成面と反対側のチップ接合面及び板厚方向に貫通して設けられた貫通孔を有した基板のチップ接合面にチップを接合するダイボンディング方法であって、ミラー面を上方に向けたミラー部材を下面に有した透明部材の上面に、パターン形成面を下方に向けた基板を載置する基板載置工程と、透明部材の上面に基板を載置した状態で基板の上方から貫通孔内を撮像することにより、貫通孔及び透明部材を通して視認されるミラー面に映った基板側パターンの反射画像を取得し、その取得した基板側パターンの反射画像から基板側パターンの位置の認識を行なう認識工程と、認識工程において認識した基板側パターンの位置に基づいて基板とチップの位置合わせを行い、基板のチップ接合面にチップを接合するチップ接合工程とを含むことを特徴とするダイボンディング方法。   A chip is placed on a chip-forming surface of a substrate having a pattern-forming surface on which a substrate-side pattern including a substrate-side electrode is formed, a chip-joining surface opposite to the pattern-forming surface, and a through-hole provided through the plate thickness direction. A die-bonding method for bonding, a substrate mounting step of mounting a substrate with a pattern forming surface facing downward on a top surface of a transparent member having a mirror member facing the mirror surface upward, and a transparent member By capturing an image of the inside of the through-hole from above the substrate with the substrate placed on the upper surface of the substrate, a reflection image of the substrate-side pattern reflected on the mirror surface viewed through the through-hole and the transparent member is obtained and obtained. Recognizing the position of the substrate side pattern from the reflected image of the substrate side pattern, and aligning the substrate and the chip based on the position of the substrate side pattern recognized in the recognition process, Die bonding method characterized by comprising a chip bonding step of bonding the chip to the chip bonding surface of the plate.
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