JP2009289071A - Register data read circuit, semiconductor integrated circuit, and register data output method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the readout time of the data of a plurality of functional blocks mounted with the same function in a control part or the comparison time of a read data value. <P>SOLUTION: The register data read circuit includes: a data selection part 21 for, when a readout signal corresponding to data stored in registers 12-1 to 12-n associated with respective function blocks mounted with the same function from a control part 10 is made valid, selecting and outputting data as the object of the readout signal; a comparison part 22 for comparing the data stored in the registers 12-1 to 12-n associated with each function block to output comparison results showing whether all the data are matched; and a connection part 23 for connecting the data of the selected function block to be output from the data selection part 21 with the comparison results to be output from the comparison part 22, which is output as a read data corresponding to the readout signal to the control part 10. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  In the field of digital signal processing, the present invention provides a register that is used when a control unit that controls a plurality of functional blocks that implement the same function via a register reads data of the functional block held by the register. The present invention relates to a data read circuit, a semiconductor integrated circuit, and a register data output method.

  In a data processing device in which a processor unit such as a CPU controls a functional block that implements a specific function via a register, the processor unit checks whether each functional block has been reset, and checks and sets status values In order to confirm the value (value for which write control has been performed), the register values for the number of function blocks to be controlled are read and processed.

  For example, in Patent Document 1, data read at the time of memory read matches data to be decoded stored in advance in a register. A memory with a decoding function that outputs a signal that is sometimes effective is described.

  Further, for example, in Patent Document 2, when the value of the destination area is stored in the data register, and the result of comparing the read transfer data with the value of the data register is the same, the destination of the transfer data is the same. A DMA device is described that omits the write operation to the nation area.

  Further, for example, Patent Document 3 describes a memory read processing time shortening circuit for shortening the read processing time in a circuit in which control over the memory is performed by a serial command. In Patent Document 3, a memory read processing time reduction circuit compares the contents of input commands including data read from a plurality of memories, and assembles a match / mismatch command based on the comparison result as one reply command. It is described that it is sent to the control source.

Japanese Patent Laid-Open No. 04-77821 Japanese Patent Laid-Open No. 07-325781 Japanese Patent Publication No. 07-78761

  When the number of functional blocks required for the intended digital signal processing is small, the proportion of the processing time for the processor unit to read the data of each functional block from the register and process it is small in the processing time of the processor unit . However, as the scale of the electronic circuit increases, the number of function blocks to be installed increases, so the time to read the data of each function block from the register and the time to check whether the value is correct are less than the processing time of the processor unit. It takes a large amount of time, and there is a risk of reducing the throughput of the entire data processing apparatus.

  Here, all of the techniques described in Patent Document 1 and Patent Document 2 are intended to reduce processing time by comparing a value written for a certain target with a value actually written. However, there is no idea to shorten the data reading time of a plurality of functional blocks installed.

  Note that the memory read processing time reduction circuit described in Patent Document 3 has the same contents by assembling and sending out a plurality of reply commands returned from a plurality of memories that have been written at the same time. This is intended to shorten the read processing time for a plurality of memory circuits. That is, it is applied based on the premise that it has the same contents, and it is not taken into consideration to apply to an object that does not. For example, when not having the same contents, it is not considered as an error, but it is possible to read individually, or how to shorten such a series of reading times is not considered Absent.

  Therefore, an object of the present invention is to improve the throughput of the entire apparatus by reducing the data read time of a plurality of functional blocks having the same function and the comparison time of read data values.

  In the register data read circuit according to the present invention, a control unit that performs control for a plurality of functional blocks that implement the same function via a register that is associated with each functional block has a function of each functional block held in each register. This is a register data read circuit for reading data, and when the read signal for the data held in the register associated with each functional block from the control unit becomes valid, the data that is the target of the read signal is selected Output from the data selection unit, the data stored in the registers associated with each functional block, and a comparison unit that outputs a comparison result indicating whether or not all match, and output from the data selection unit The data of the selected functional block and the comparison result output from the comparison unit are concatenated to read data corresponding to the read signal. Characterized by comprising a connecting portion for outputting to the control unit as.

  In addition, a semiconductor integrated circuit according to the present invention is mounted in association with a plurality of functional blocks having the same function, and is related to control of the functional block from the outside. A data selection unit that selects and outputs the data that is the target of the read signal when the read signal for the data held in the register associated with each functional block input from becomes valid, and each functional block Compare the data stored in the registers associated with each other, and output a comparison result indicating whether or not they are all matched, and the data of the selected functional block output from the data selection unit And a comparison unit that is connected to the comparison result output from the output unit and outputs the read data as read data for the read signal to the outside. .

  In addition, the register data output method according to the present invention provides each register with respect to a read request from a control unit that performs control for a plurality of functional blocks that implement the same function through a register that is associated with each functional block. This is a register data output method for outputting the data of each held function block, and when the read signal for the data held in the register associated with each function block becomes valid from the control unit Select and output the data that is the target of the signal, compare the data held by the registers associated with each functional block, and output the comparison result indicating whether or not all match, and selected Whether or not all the data obtained by comparing the data of the function block with the data held in each register using a separate comparison unit is the same. And connects the comparing result, and outputs to the control unit as the read data to the read signal.

  According to the present invention, it is possible to reduce the data read time and the data value comparison time of a plurality of functional blocks that implement the same function. As a result, the throughput of the entire apparatus can be improved.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a register data read circuit according to the present invention. In the example illustrated in FIG. 1, the register data read circuit includes a data selection unit 21, a comparison unit 22, and a connection unit 23. In FIG. 1, a dotted line represents a connection relationship of control signals such as a write signal, a read signal, and a CE (chip enable signal). The solid line represents the connection relationship of data signals such as write data and read data.

  In the example shown in FIG. 1, a control unit 10 that performs control on n functional blocks 13-1 to 13-n that implement the same function via registers 12-1 to 12-n that are associated with the respective functional blocks. These are examples of register data read circuits for reading the data of the functional blocks 13-1 to 13-n held in the registers 12-1 to 12-n, respectively. In this example, the correspondence between the functional block and the register is represented by the part following-(hyphen) in the reference numerals. For example, the register corresponding to the functional block 13-1 is the register 12-1. Similarly, the register corresponding to the functional block 13-2 is the register 12-2. Hereinafter, the data of the functional block 13-X held by the register 12-X may be simply expressed as data X (X = 1 to n).

  Here, the function block is used as a general term for a device or a circuit group configured to implement a specific function and operating as a group. As functional blocks, not only memory devices for storing data such as SRAM, DRAM, and EEPROM, but also units for various purposes such as coding processing circuit groups, image processing circuit groups, and communication control circuit groups are available. Conceivable.

  The data selection unit 21 receives a read signal for data held by the register 12 (registers 12-1 to 12-n) associated with each functional block 13 (functional blocks 13-1 to 13-n) from the control unit 10. When becomes effective, the data (one of data 1 to n) that is the target of the read signal is selected and output. For example, the data selection unit 21 may specify the data that is the target of the read signal from the address value indicated by the address bus (not shown) when the read signal becomes valid. For example, if the address bus indicates the address value assigned to the data 1, the data selection unit 12 stores the data of the functional block 13-1 held by the register 12-1 to which the address value is assigned. Can be selected and output.

  Here, the function block data is, for example, a control data value when the control unit 10 controls the function block via a register. Further, for example, it is a write data value when the control unit 10 writes data to the functional block via the register. For example, it may be a status value output from a functional block. In FIG. 1, when the write signal for the register associated with each functional block from the control unit 10 becomes valid, the chip selection unit 11 outputs a CE (chip enable signal), so that the corresponding register Shows an example in which write data is captured and held in the process of output to a functional block.

  The comparison unit 22 compares the data held in the registers 12 (registers 12-1 to 12-n) associated with the respective functional blocks 13 (functional blocks 13-1 to 13-n), and all match. The comparison result indicating whether or not is output.

  The concatenation unit 23 concatenates the data of the selected functional block output from the data selection unit 21 (here, any one of the data 1 to n) and the comparison result output from the comparison unit 22 and reads the data. It outputs to the control part 10 as read data with respect to a signal.

  As described above, according to the present invention, the control unit 10 performs a single read process on the data held in the register associated with a certain functional block, and the value of the data, the data, and another functional block. The comparison result of whether or not all the data held in the register associated with the data match is obtained, so the data read time and the read data of multiple functional blocks that implement the same function Value comparison time can be reduced. As a result, the throughput of the entire apparatus can be improved.

  For example, when checking the initial values of these registers or making a readback after making the same settings for all function blocks and confirming a complete match with a single read process, it was obtained at that time. It is only necessary to perform a desired confirmation process (whether it matches the correct initial value or set value, etc.) using the data value, and the reading process and the confirmation process for other data can be omitted.

  Further, for example, even when a comparison result of all matches cannot be obtained, one data value designated by one reading process can be read, so that each reading process is performed again thereafter. This process does not become an unnecessary process. In other words, even if a completely matched comparison result cannot be obtained, the number of read processes and the number of confirmation processes are not increased as compared with the case where individual read processes are performed.

  Further, the register data read circuit according to the present invention can be configured as shown in FIG. 2, for example. FIG. 2 is a block diagram showing another configuration example of the register data read circuit according to the present invention. As shown in FIG. 2, when a large number of functional blocks are mounted, registers 12-1 to 12-n associated with a plurality of functional blocks 13-1 to 13-n that implement the same function are stored in a plurality of banks. The comparison unit 22 may be mounted for each bank. Here, the registers 12-1 to 12-n are divided into two banks (bank 1 and bank 2), and the registers 12-1 to 12-a (here, a = n ÷ 2 (integer)) are stored in the bank 1. And registers 12- (a + 1) to 12-n are assigned to bank 2. The comparison unit 22-1 is associated with the bank 1, and the comparison unit 22-2 is implemented with the bank 2. In FIG. 2, the control unit 10 for controlling each register and the chip selection unit 11 for selecting the register to be controlled are not shown, but these are the same as the example shown in FIG. is there.

  In such a case, each comparison unit 22 (comparison units 22-1 and 22-2) compares the data of each functional block held by each of the registers assigned to the mounting-destination banks and makes a complete match. The comparison result indicating whether or not is output. For example, the comparison unit 22-1 may compare the data of each functional block held by each of the registers 12-1 to 12-a and output data indicating a comparison result as to whether or not all match. Each bank is divided so that two or more registers belong.

  Each of the comparison units 22 (comparison units 22-1 and 22-2) compares the data of each functional block held by each register assigned to the mounting destination bank to determine whether or not they are all the same. What is necessary is just to output a comparison result.

  In this example, a comparison result selection unit 24 is further provided to correspond to a plurality of comparison units 22 mounted in this way. The comparison result selection unit 24 reads from the control unit 10 the data stored in the registers 12 (registers 12-1 to 12-n) associated with the functional blocks 13 (functional blocks 13-1 to 13-n). When the signal becomes valid, from the comparison unit 22 (one of the comparison units 22-1 and 22-2) mounted on the bank to which the register holding the data that is the target of the read signal belongs. Select and output the comparison result to be output. For example, the comparison result selection unit 24 may specify the bank to which the register holding the data that is the target of the read signal belongs from the address value indicated by the address bus when the read signal becomes valid. For example, if the address bus indicates the address value assigned to the data 1, the comparison result selection unit 24 is output from the comparison unit 22-1 installed for the bank 1 including the address area. The data indicating the comparison results (that is, the comparison results for the registers 12-1 to 12-a) may be selected and output.

  Further, the connecting unit 23 connects the data of the selected functional block output from the data selecting unit 21 and the selected comparison result output from the comparison result selecting unit 24 as read data for the read signal. Just output.

  Thereby, even when many functional blocks are mounted, the number of comparisons can be reduced, and the output time of the comparison results can be reduced. In addition, there is an advantage that it is easy to determine the mismatched register when there is a mismatch.

  In addition, as shown in FIG. 2, a bit mask holding unit 25 that holds a mask value for a bit string of data of a functional block held in a register may be provided. In such a case, the comparison unit 22 performs a comparison only on the bit value that is validated by the mask value held in the bit mask holding unit 25. As a result, it is possible to obtain a comparison result of only those relating to the designated bit.

  Hereinafter, more specific embodiments will be described. FIG. 3 is a schematic circuit diagram showing one embodiment of the register data read circuit according to the present invention. FIG. 3 shows a configuration example of a register data read circuit in the case where the CPU controls n functional blocks via corresponding n registers. In the example shown in FIG. 3, the address bus, write signal, read signal, clock signal (CLK), reset signal (reset 1 to n) and write data of a processor unit (not shown) such as a CPU are used as inputs. This is an example applied to an LSI (semiconductor integrated circuit) that controls the functional block 13.

  In the example illustrated in FIG. 3, as an LSI, a control register group (registers 12-1 to 12-n) that is mounted in association with a plurality of functional blocks 13-1 to 13-n that implement at least the same function, The data selector 21 which comprises the register data read circuit for reading the data which the register | resistors 12-1 to 12-n hold | maintain, the comparator 22, and the bit coupler 23 are provided. Further, a chip selector 11 used for writing data to the registers 12-1 to 12-n is provided. Although the function blocks 13-1 to 13-n can be mounted as one LSI, the function blocks 13-1 to 13-n are not necessarily provided in the LSI.

  The data selector 21 is a control circuit that implements the data selection unit 21 in FIG. The comparator 22 is a control circuit that implements the comparison unit 22 in FIG. The bit coupler 23 is a control circuit that implements the coupling unit 23 in FIG. The chip selector 11 is a control circuit that implements the chip selection unit 11 in FIG.

  In this example, each functional block 13 (functional blocks 13-1 to 13-n) uses the same circuit, and the register 12 (any one of the registers 12-1 to 12-n) associated with the functional block is used. ) Data output (output value from the data signal Q).

  Write data and a clock signal are connected to each register 12 (registers 12-1 to 12-n). The reset signals (reset 1 to n) are connected to the register on a one-to-one basis.

  The write signal is connected to the chip selector 11. The read signal is connected to the data selector 21. The address bus is connected to the chip selector 11 and the data selector 21.

  The chip selector 11 latches a write signal input from the outside (CPU in this example) (captures rising or falling change), captures the contents of the address bus, and according to the value (address value), A chip enable signal (CE) to be output to each register is generated and output. Here, output is performed so that the chip enable signal to the register holding the data to which the address value is assigned becomes a valid value.

  Each of the registers 12-1 to 12-n is associated with control of the function block from the outside (CPU), and holds data of the corresponding function block. Each register 12 is composed of, for example, a flip-flop, latches a chip enable signal from the chip selector 11, captures and holds input write data (input value to the data signal D), and from the data signal Q By outputting, the associated functional block is controlled. In this example, the input write data is output from the data signal Q as it is, but it is also possible to perform a predetermined conversion process and output the data. In such a case, a data output signal for the functional block and a data output signal for read back to the CPU may be provided separately. Hereinafter, data of a functional block held by a register (actually, a value indicated by a data output signal to the CPU regarding the functional block) is referred to as register data.

  The data selector 21 latches a read signal input from the outside (CPU in this example), takes in the contents of the address bus, and stores data (register data) held in the corresponding register according to the address value. ) Is selectively captured and output. In FIG. 3, the register data output from the data selector 21 is shown as selection data.

  The comparator 22 compares all the register data held by each register (registers 12-1 to 12-n), and outputs a comparison result indicating whether or not they all match. For example, the comparator 22 may use a 1-bit data signal for outputting the comparison result, and may output 1 if they all match and 0 if they do not.

  In the bit connector 23, the selection data from the data selector 21 and the comparison result from the comparator 22 are input, and these are connected and output to the outside (CPU) as read data for the read signal.

  FIG. 4 is a block diagram illustrating a configuration example of the comparator 22. The example shown in FIG. 4 is an example of the comparator 22 that compares eight register data and outputs whether or not all match. In the example shown in FIG. 4, as the first-stage comparator group, a comparator A1 that compares register data 1 (register data held in the register 12-1) and register data 2, a register data 3 and a register A comparator A 2 that compares data 4, a comparator A 3 that compares register data 5 and register data 6, and a comparator A 4 that compares register data 7 and register data 8 are provided. In this first-stage comparator, two register data (D1, D2) are input, and the comparison result (R) and one of the register data used for comparison (D1 in the example of FIG. 4) are output. To do.

  Further, as the second-stage comparator group, a comparator B1 that compares register data (D1, D2) output from the comparator A1 and the comparator A2 included in the first-stage comparator group, and a comparator A comparator B2 for comparing register data (D1, D2) output from A3 and the comparator A4. In this second-stage comparator, a total of two register data (D1, D2) output from the two comparators positioned in the previous stage and a total of two comparison results (R1, R2) are input and compared. The result (R) and one of the register data used for comparison (D1 in the example of FIG. 4) are output. The comparator in the second stage outputs the result of comparison by the comparator only when the comparison results (R1, R2) input from the two comparators located in the previous stage are both coincident. If any one of them indicates a mismatch, a comparison result (R) indicating a mismatch unconditionally is output.

  A comparator C1 that compares register data (D1, D2) output from the comparator B1 and the comparator B2 included in the second-stage comparator group is provided as the final-stage comparator group. In this final stage comparator, a total of two register data (D1, D2) respectively output from two comparators located in the previous stage and a total of two comparison results (R1, R2) are input, and the comparison result (R) is output. The output logic of the comparison result is the same as that of the second-stage comparator group. That is, when any one of the comparison results (R1, R2) input from the two comparators located in the preceding stage indicates a mismatch, the comparator only when both indicate a match. If any one of them shows a mismatch, a comparison result (R) indicating a mismatch unconditionally is output.

  By adopting such a configuration, the time required for the comparison processing depending on the number of stages of the comparators can be shortened. In the example shown in FIG. 4, the example of the comparator 22 that compares eight register data and outputs whether or not all match is shown. However, for example, when comparing 16 register data, The first stage comparator group includes comparators A1 to A8, the second stage comparator group includes B1 to B4, and the third stage performs the same processing as the second stage comparator group. What is necessary is just to provide the comparator C1 of the last stage in the next stage provided with B'1-B'2 as a comparator group.

  For example, a method of sequentially comparing data 1, 2, 2, 3, 3, 4,... Is possible, but the number of registers (that is, the number of mounted functional blocks) is large. In this case, it is preferable to operate in parallel as shown in FIG.

  Further, the comparator 22 may be configured as shown in FIG. FIG. 5 is a block diagram illustrating another configuration example of the comparator 22. In the example shown in FIG. 5, registers 1 ′ to 8 ′ latched and fetched from each register holding the register data 1 to 8 to be compared with the value of the counter in the preceding stage of the comparator shown in FIG. 4. It has. By providing the counter, the capture timing can be made uniform.

  Next, the operation of this embodiment will be described. FIG. 6 is a timing chart showing an operation example of this embodiment. Here, a case where the value of n is 4 and each register is a 4-bit register (that is, the register data is 4-bit data) will be described as an example. Further, an example is shown in which the comparison result is 1-bit data and the read data to the CPU is generated as 5-bit data.

  In FIG. 6, resets 1 to 4 are reset signals effective at the low level. Here, it starts from the reset state. In the reset state, the register 12 outputs the register data with the initial value 1 (register data 1 to 4 = 1). At this time, the registers 12-1 to 12-4 are connected to the function blocks 13 that are implemented as different individuals. However, since the registers 12-1 to 12-4 are functions that perform the same control, the comparators 22 all indicate a match as a comparison result. 1 (1b: 1-bit data) is output.

  Here, when resets 1 to 4 are canceled (changed to high level) at time T1, the CPU sets the address bus to 00 and sets the read signal to low level (valid) at time T2. The lead phase is started. In this example, it is assumed that the address values 00 to 03 indicated by the address bus correspond to the device addresses of the registers 1 to 4. For example, if the address value is 00, register data 1 is designated. Similarly, if the address value is 01, register data 1 is designated. The device address can be designated to be converted into a physical address by an address conversion mechanism or the like in the CPU.

  As a result, the data selector 21 that latches the read signal selects the register data 1 to be read based on the value 00 indicated by the address bus, and outputs it as selection data. At this time, all the comparison results remain 1b indicating a match. Therefore, in the bit coupler 23, the value of the register data 1 (1h: 4-bit data) input as the selection data and the comparison result The value (1b: 1 bit data) is concatenated and the read data value is output as 11h (1 0001b: 5 bit data).

  The CPU that has read the read data indicates that all of the registers 12-1 to 12-4 have the same value (1h: initial value) in one read process because the comparison result indicates a complete match. Can be recognized.

  Next, for example, at time T3, when the CPU sets the address bus to 00, the write data to F, the write signal to Low level (valid), and the read signal to High level, the register write phase starts. . Here, first, the chip selector 11 receives the rising edge of the CLK in the low period of the write signal, and outputs a chip enable signal toward the register 12-1. Accordingly, the register 12-1 outputs the control data from the data signal Q while holding the write data value (Fh) as the register data 1. As a result, the register data 1 becomes F. Further, since the register data 1 is changed to F, the comparison result output from the comparator 22 becomes 0 indicating a mismatch. For example, the data to be compared by the comparator 22 may be captured at a timing read by the CPU without being synchronized with the write phase, or may be captured at regular intervals by an input from a separate counter. .

  Here, an example is shown in which the register data is updated only by control from the CPU, but the value of the register data is updated by other factors (output from the functional block or reset signal), or a certain time has elapsed. Then it may be cleared automatically.

  Next, when the CPU again sets the address bus to 00 and sets the read signal to low level at time T4, the data selector 21 that latches the read signal causes the register to be read based on the value 00 indicated by the address bus. Data 1 is selected and output as selection data. As a result, the bit coupler 23 concatenates the value (Fh) of the register data 1 input as selection data and the value (0b) of the comparison result, and outputs the value of the read data as 0Fh (0 1111b). . Here, only the register data 1 is rewritten at time T3, so that read data including 0 indicating mismatch is generated and output as a comparison result.

  Thereafter, when the read phase is continued by sequentially shifting the address bus to 01, 02, 03, the values of the register data 2 to 4 are 1h, so that 01h, 01h, 01h are sequentially output as the read data. become. That is, 01h continues to be output.

  Next, at time T5, the CPU sets 01 to the address bus, sets F to the write data, sets the read signal to High, and sets the write signal to the Low level, and then receives the chip enable signal from the chip selector 11. The register 12-2 holds the write data value (Fh) as the register data 2. Thereafter, the address bus is sequentially shifted to 02 and 03, and each time the write signal falls to the low level (the high level and then the low level), the values of the register data 3 and 4 also become the write data value (Fh). ). By rewriting the write data value (Fh) up to the register data 4, the comparison result output from the comparator 22 becomes 1 indicating complete match.

  Next, when the CPU performs a read process to the register data 1 again at time T6, the data selector 21 that latches the read signal outputs the register data 1 as selection data, so that the bit coupler 23 causes the register data 1 to Is connected to the comparison result value (1b), and the read data value is output as 1Fh (1 1111b). Here, when all the register data 1 to 4 are rewritten to the same value, read data including 1 indicating all coincidence is generated and output as a comparison result.

  The CPU that has read the read data recognizes that the registers 12-1 to 12-4 all hold the same value (Fh) in one read process because the comparison result indicates a complete match. It is not necessary to read out other register data (register data 2 to 4).

  For example, it is assumed that at time T7, the reset 3 becomes low and the register 12-3 is reset. As a result, only the register data 3 is returned to the initial value 1h, and the comparison result becomes 0 indicating a mismatch. Thereafter, when the CPU performs a read process on the register data 1 at time T8, the data selector 21 that latches the read signal outputs the register data 1 as selection data, so that the bit coupler 23 causes the value of the register data 1 to be (Fh) and the comparison result value (0b) are concatenated, and the read data value is output as 0Fh (0 1111b).

  The CPU that has read the read data recognizes that the value of one of the register data is different because the comparison result indicates a mismatch, and reads the other register data (register data 2 to 4) sequentially. .

  Next, an example of the operation of the CPU using the register data read circuit will be shown. FIG. 7 is a flowchart showing an operation example of the CPU using the register data read circuit of the present embodiment. As shown in FIG. 7, when the CPU starts the confirmation process of the control registers 12-1 to 12-n of the functional blocks 13-1 to 13-n, the CPU performs a read process for the start address of the control register (step S101). .

  Next, the comparison result bit included in the read data obtained by the read process is referred to. If the comparison result bit is 1 indicating a complete match (Yes in step S102), the data value indicated by the data bit included in the read data and the CPU Are compared with the expected value (step S103). If they match as a result of the collation, all the data in the control register group are assumed to be normal values, and the process ends normally (step S104).

  On the other hand, if they do not coincide with each other as a result of the collation, all the data in the control register group is regarded as an abnormal value, and the process may be shifted to the abnormal processing system (step S105).

  In step S102, if the comparison result bit is not 1 indicating complete coincidence (No in step S102), the data value indicated by the data bit included in the read data read now is collated with the expected value of the CPU ( In step S106, if they do not match, it is detected that the register data to be read from the read data is an abnormal value (step S107). Until all the data in the register group is read (No in step S108), the next address is read (step S109), and the processes in steps S106 to S107 are repeated. Since the confirmation process for the head address has already been performed using the read data read in step S101, the CPU may resume the individual read process (steps S109 → S106 → S107) from the next address. In the confirmation process following the individual read process, only the data bits need be referred to.

  When all the data in the register group is confirmed, the abnormal processing system may be shifted based on the abnormal register data detected so far (Yes in step S108).

  Thus, according to the present embodiment, the CPU performs a single read process on the register data held in the registers 12-1 to 12-n associated with the functional blocks 13-1 to 13-n. Since it is possible to obtain the value of the specified register data and the comparison result of whether or not the register data and other register data all match, it is possible to obtain the data of multiple functional blocks that implement the same function. The reading time and the comparison time of the read data value can be reduced. As a result, the throughput of the entire apparatus can be improved.

  For example, the time for the CPU to read the register is tr, and the time for the CPU to compare the data read internally is tc. Here, when the time for comparing the n registers by the comparator 22 is trc, when the CPU individually reads n × (tr + tc), in the present embodiment, The time of trc + tr + tc is sufficient.

  For example, when a transmission data generation block that generates transmission data for each transmission channel is applied as a functional block to a radio base station controller that implements 100 channels (n = 100), a register that controls the transmission data generation block is a register. It becomes 100 pieces from 12-1 to 12-100. When checking the initial values of these registers, the time of trc + tr + tc is required in the present embodiment, compared with the case where 100 × (tr + tc) time is required when the CPU individually reads.

  In addition to confirming the initial value, control output enable for all transmission channels via a register, set parameter values such as the baud rate of all transmission channels, and status values indicating the output status of all transmission channels ( This can be used in various situations, such as when confirming (sending / stopping).

  It is also possible to add a mask function that can specify the bits to be compared without making all the bits of the register data to be compared. FIG. 8 is a block diagram illustrating a configuration example of the comparator 22 when a mask function is added. In the example shown in FIG. 8, a mask register 25 that functions as a bit mask holding unit 25 is provided in the preceding stage of the comparator shown in FIG. 4, and the registers 1 ′ to 8 ′ store the register data 1 to 8 to be compared. When fetching, the mask register 25 is configured to mask and fetch with the bit mask value held in the mask register 25. If the bit mask value is fixed, it is possible to provide a comparator 22 that prepares a register that takes in only valid bits and performs comparison using only the number of valid bits.

  It is also possible to divide the register and divide it into a plurality of banks. FIG. 9 is a block diagram showing another embodiment of the register data read circuit. In FIG. 9, only the portion related to the comparison process is shown. Here, a case where there are 512 registers 12 will be described as an example. Here, a total of 512 registers 12 are divided into four banks of 128. The registers belonging to bank 1 are registers 12-1 to 12-128. The registers belonging to bank 2 are registers 12-129 to 12-256. The registers belonging to bank 3 are registers 12-257 to 12-384. The registers belonging to the bank 4 are registers 12-385 to 12-512.

  In this example, comparison of register data is performed at four locations for each bank. A comparison result selector 24 functioning as a comparison result selection unit 24 is provided. The comparison result selector 24 latches a read signal from the CPU, takes in the contents of the address bus, and corresponds to the address value. The comparison result of the comparator 22 (one of the comparators 1 to 4 in FIG. 9) mounted on the bank is selectively captured and output.

  Thereby, the number of comparisons in one comparator 22 is reduced, and the output time of the comparison result can be further reduced. In addition, there is an advantage that it is easy to determine the mismatched register when there is a mismatch.

  The present invention can be suitably applied to an apparatus in which a control unit controls a plurality of functional blocks having the same function via a register in the field of digital signal processing.

It is a block diagram which shows the structural example of the register data read circuit by this invention. It is a block diagram which shows the other structural example of a register data read circuit. It is a schematic circuit diagram which shows one Example of a register data read circuit. 3 is a block diagram illustrating a configuration example of a comparator 22. FIG. 6 is a block diagram illustrating another configuration example of the comparator 22. FIG. It is a timing diagram which shows the operation example of this embodiment. It is a flowchart which shows the operation example of CPU which uses a register data read circuit. It is a block diagram which shows the structural example of the comparator 22 at the time of adding a mask function. It is a block diagram which shows the other Example of a register data read circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Control part 11 Chip selection part, Chip selector 12, 12-1 to 12-n Register 13, 13-1 to 13-n Functional block 21 Data selection part, Data selector 22 Comparison part, Comparator 23 Connection part, Bit connection 24 Comparison result selection unit, Comparison result selector 25 Bit mask holding unit, mask register

Claims (9)

Register data read for reading data of each functional block held in each register by a control unit that performs control over a plurality of functional blocks that implement the same function via a register that is associated with each functional block A circuit,
A data selection unit that selects and outputs the data that is the target of the read signal when a read signal for the data held in the register associated with each functional block from the control unit becomes valid;
A comparison unit that compares the data held by the registers associated with the functional blocks and outputs a comparison result indicating whether or not all match;
A connection unit that connects the data of the selected functional block output from the data selection unit and the comparison result output from the comparison unit, and outputs the result to the control unit as read data for the read signal; A register data read circuit. Registers corresponding to multiple functional blocks that implement the same function are divided and assigned to multiple banks,
A comparison unit is implemented for each bank,
When the read signal for the data held in the register associated with each functional block from the control unit becomes valid, it is mounted on the bank to which the register holding the data that is the target of the read signal belongs. A comparison result selection unit for selecting and outputting the comparison result output from the comparison unit being provided,
Each comparison unit compares the data of each functional block held by each register assigned to the mounting destination bank, and outputs the comparison result.
The concatenation unit concatenates the selected functional block data output from the data selection unit and the selected comparison result output from the comparison result selection unit to the control unit as read data for the read signal. The register data read circuit according to claim 1 for outputting. A bit mask holding unit that holds a mask value for a bit string of data of a functional block held in a register;
3. The register data read circuit according to claim 1, wherein the comparison unit performs comparison only for a bit value that is validated by a mask value held in the bit mask holding unit. 4. The data to be read signal and the bank to which the register holding the data belongs are specified from the address value indicated by the address bus when the read signal is valid. The register data read circuit according to claim 1. The register data read according to any one of claims 1 to 4, wherein the register data read is applied to a radio base station controller in which a transmission data generation block for generating transmission data for each transmission channel is mounted as a functional block. circuit. A register that is implemented in association with a plurality of functional blocks that implement the same function, and that controls the functional block from the outside, and that holds data of the corresponding functional block;
A data selection unit that selects and outputs data that is the target of the read signal when a read signal for data held by a register associated with each functional block input from the outside becomes valid;
A comparison unit that compares the data held by the registers associated with the functional blocks and outputs a comparison result indicating whether or not all match;
A connection unit that connects data of the selected functional block output from the data selection unit and a comparison result output from the comparison unit and outputs the result as read data for the read signal to the outside; A semiconductor integrated circuit. Registers corresponding to multiple functional blocks that implement the same function are divided and assigned to multiple banks,
A comparison unit is implemented for each bank,
When a read signal for data held in a register associated with each functional block input from the outside becomes valid, the bank to which the register holding the data that is the target of the read signal belongs A comparison result selection unit that selects and outputs a comparison result output from the mounted comparison unit,
Each comparison unit compares the data of each functional block held by each register assigned to the mounting destination bank, and outputs the comparison result.
The concatenation unit concatenates the data of the selected functional block output from the data selection unit and the selected comparison result output from the comparison result selection unit, and outputs to the outside as read data for the read signal. The semiconductor integrated circuit according to claim 6. In response to a read request from a control unit that performs control over a plurality of functional blocks that implement the same function through a register that is associated with each functional block, the data of each functional block that is held in each register is A register data output method when outputting,
When the read signal for the data held in the register associated with each functional block from the control unit becomes valid, select and output the target data of the read signal,
Compare the data held by each register associated with each functional block, and output a comparison result indicating whether or not all match,
Concatenating the data of the selected functional block and a comparison result indicating whether or not all obtained as a result of comparing the data held by the register using a separate comparison unit, A register data output method comprising: outputting to the control unit read data corresponding to a read signal. Dividing and assigning registers corresponding to multiple functional blocks that implement the same function into multiple banks,
When the read signal for the data held in the register associated with each functional block from the control unit becomes valid, it is mounted on the bank to which the register holding the data that is the target of the read signal belongs. Select and output the comparison result output from the comparator
The register data output method according to claim 8, wherein the data of the selected functional block and the selected comparison result are connected and output to the control unit as read data for the read signal.

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