JP2009260793A - Local oscillation signal generator unit, signal receiver unit, and synchronization unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a spurious produced in a unit for generating a local oscillation signal. <P>SOLUTION: The local oscillation signal generator unit includes a first reference clock generator for generating a first reference clock, a second reference clock generator for generating a second reference clock having a different frequency from the first reference clock, a selector for selecting the clock producing a smaller spurious between the first reference clock and the second reference clock, and a local oscillator for generating the local oscillation signal using the selected reference clock. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a local oscillation signal generation device, a signal reception device, and a synchronization device.

  Conventionally, a technique for synchronizing the frequency of a transmission signal with a base station in a wireless device such as TDMA (Time Division Multiple Access) has been proposed. FIG. 9 is a diagram illustrating an example of a conventional wireless device that performs such synchronization. The radio apparatus 1000 receives a synchronization signal transmitted from a base station via an antenna 1001. The synchronization signal is input to the CPU 1007 via the switch 1002, the low-pass filter 1003, the low-noise amplifier 1004, the mixer 1005, and the DSP (Digital Signal Processor) 1006. The CPU 1007 adjusts the reference clock input to the reception PLL (Phase-locked loop) 1009 and the transmission PLL 1010 so as to be synchronized with the synchronization signal. The reference clock is generated by a VCTCXO (Voltage Controlled, Temperature Compensated Crystal Oscillator) 1008. Therefore, the CPU 1007 adjusts the frequency of the reference clock by adjusting the voltage applied to the VCTCXO 1008 to achieve synchronization.

In radio apparatus 1000, when the local oscillation signal (reception local) generated by reception PLL 1009 and the frequency of the local oscillation signal (transmission local) generated by transmission PLL 1010 are an integer multiple of the reference clock or the vicinity thereof In this case, the frequency component of the local oscillation signal and the frequency component that is an integral multiple of the reference clock cause a beat. As a result, there is a problem in that the closer the two frequencies are, the stronger spurious is generated.
For such a problem, a technique that can prevent deterioration of spurious characteristics and the like has been proposed (see Patent Document 1).
JP 2006-054907 A

  Certainly, in the case of a narrow-band radio, spurious can be reduced by increasing the frequency of the reference clock or filtering the local oscillation signal with a narrow-band filter. However, in the case of a broadband wireless device, it has been difficult to reduce spurious by such a method.

  In view of the above circumstances, an object of the present invention is to provide an apparatus that can reduce spurious generated in an apparatus that generates a local oscillation signal.

  A first aspect of the present invention is a local oscillation signal generator, a first reference clock generator that generates a first reference clock, and a second reference clock having a frequency different from that of the first reference clock. The selection of the second reference clock generator to be generated and the reference clock used in generating the local oscillation signal, which of the first reference clock and the second reference clock is selected to generate the smaller spurious. And a local oscillation unit that generates a local oscillation signal using the selected reference clock.

  In the first aspect of the present invention, the first reference clock and the second reference clock having a frequency different from that of the first reference clock are used as the reference clock. The selection unit selects one of the two reference clocks with the smaller spurious generated. Therefore, the first aspect of the present invention can reduce spurious generated.

  In the first aspect of the present invention, the second reference clock generation unit divides a value obtained by multiplying the frequency of the first reference clock by an integer and in the vicinity of the frequency that can be taken by the local oscillation signal by a positive number. Alternatively, a signal having a value that cannot be obtained as a frequency and synchronized with the first reference clock may be generated as the second reference clock.

In the first aspect of the present invention, the selection unit may select a reference clock in which the difference between the harmonic frequency of the reference clock and the frequency of the local oscillation signal becomes larger.
In the first aspect of the present invention, when the selection unit indicates that the value representing the closeness between the harmonic frequency of the first reference clock and the frequency of the local oscillation signal is closer to the reference, the second reference A clock may be selected and in other cases the first reference clock may be selected.

  According to a second aspect of the present invention, there is provided a signal reception device, the local oscillation signal generation device described above, a signal reception unit that receives a radio signal from another device, and a local oscillation output from the local oscillation signal generation device. A mixing unit that mixes the signal and the signal received by the signal receiving unit and outputs the mixed signal, and a demodulation unit that demodulates the mixed signal and obtains demodulated data.

  A third aspect of the present invention is a synchronization device, the local oscillation signal generation device described above, a signal reception unit that receives a radio signal from another device, and a local oscillation signal that is output from the local oscillation signal generation device And a signal received by the signal receiving unit, a mixing unit that outputs the mixed signal, a reference clock selected by the selection unit based on the mixed signal, and an amount of frequency deviation between the radio signal A detection unit for detecting, and a control unit for performing control to eliminate the deviation based on the amount of deviation detected by the detection unit.

  The present invention may be specified as a computer program for causing a computer to operate as the selection unit of the above-described local oscillation signal generation device. Further, the present invention may be specified as a selection method performed by a computer functioning as a selection unit of the above-described local oscillation signal generation device.

  According to the present invention, it is possible to reduce spurious generated in an apparatus that generates a local oscillation signal.

  FIG. 1 is a diagram illustrating a configuration of a wireless device 1 (signal receiving device, synchronization device). The wireless device 1 includes an antenna 101, a transmission / reception switch 102, a low pass filter 103, a low noise amplifier 104, a mixer 105, a DSP 106, a local oscillation signal generation device 10, a DSP 111, a mixer 112, a power amplifier 113, and a low pass filter 114.

  The antenna 101 (signal receiving unit) receives a radio signal transmitted from another radio apparatus (for example, a base station apparatus). The antenna 101 transmits a signal that has passed through the low-pass filter 114 as a radio signal. The transmission / reception switch 102 connects the antenna 101 and the low-pass filter 103 when the wireless device 1 performs reception. On the other hand, the transmission / reception switch 102 connects the antenna 101 and the low-pass filter 114 when the wireless device 1 performs transmission. The low-pass filter 103 receives a signal received by the antenna 101 and outputs a signal in which a high-frequency component is suppressed. The low noise amplifier 104 receives the signal output from the low pass filter 103, amplifies the input signal, and outputs an amplified signal.

  The mixer 105 (mixing unit) receives the signal output from the low noise amplifier 104 and the reception local oscillation signal output from the reception PLL 109 of the local oscillation signal generation device 10. The mixer 105 mixes these two signals and outputs a mixed signal. The DSP 106 (demodulation unit) receives the mixed signal output from the mixer 105 and demodulates the mixed signal. Then, the DSP 106 obtains demodulated data represented by a bit string by demodulation processing, and outputs the demodulated data. Further, the DSP 106 (detection unit) receives the signal output from the mixer 105, and shifts in frequency between the signal output from the low noise amplifier 104 and the local oscillation signal output from the local oscillation signal generation device 10. Detect the amount.

  The local oscillation signal generation device 10 generates a local oscillation signal and outputs it to the mixer 105 and the mixer 112. The local oscillation signal generator 10 includes a CPU (Central Processing Unit) 107, a VCTCXO 108, a multiplier 115, a frequency divider 116, a reception switch 117, a transmission switch 118, a reception PLL 109, and a transmission PLL 110.

  When the reception PLL 109 generates a local oscillation signal, the CPU 107 (selection unit) outputs a reference clock (first reference clock) output from the VCTCXO 108 and a reference clock (second reference clock) output from the frequency divider 116. (Clock) to be input to the receiving PLL 109. Then, the reception switch 117 is controlled so that the selected reference clock is input to the reception PLL 109. The CPU 107 selects and controls the transmission PLL 110 and the transmission switch 118 in the same manner. Details of the selection process of the CPU 107 will be described later.

  The CPU 107 (control unit) controls the VCTCXO 108 to eliminate the deviation based on the deviation amount output from the DSP 106. Specifically, the CPU 107 controls the voltage applied to the VCTCXO 108 based on the amount of deviation. Further, the CPU 107 outputs a signal instructing the reception PLL 109 and the transmission PLL 110 to generate a local oscillation signal having a frequency corresponding to the reception channel and the transmission channel. Further, the CPU 107 generates transmission data and outputs it to the DSP 111.

  The VCTCXO 108 (first reference clock generation unit) outputs a first reference clock according to the voltage applied by the CPU 107. The first reference clock is input to the reception switch 117, the transmission switch 118, and the multiplier 115.

  The multiplier 115 (second reference clock generation unit) receives the first reference clock output from the VCTCXO 108 and multiplies the frequency of the first reference clock based on a predetermined magnification (n). The multiplier 115 outputs a signal having a multiplied frequency. The frequency divider 116 (second reference clock generator) receives the signal output from the multiplier 115, divides the frequency of this signal based on a predetermined frequency division number (1 / m), Two reference clocks are generated. That is, the frequency of the second reference clock is n / m times the frequency of the first reference clock. At this time, n and m are different values. Therefore, the frequency of the first reference clock is different from the frequency of the second reference clock. A detailed method for obtaining the value of n and the value of m will be described later. Further, since the second reference clock is obtained by multiplying the first reference clock by frequency division, it is synchronized with the first reference clock. Then, the frequency divider 116 outputs a second reference clock. The second reference clock is input to the reception switch 117 and the transmission switch 118.

  The reception switch 117 switches a circuit connected to the reception PLL 109 based on the control of the CPU 107. The circuit connected to the receiving PLL 109 is either a circuit that transmits the first reference clock output from the VCTCXO 108 or a circuit that transmits the second reference clock output from the frequency divider 116. The transmission switch 118 switches a circuit connected to the transmission PLL 110 based on the control of the CPU 107. The circuit connected to the transmission PLL 110 is either a circuit that transmits the first reference clock output from the VCTCXO 108 or a circuit that transmits the second reference clock output from the frequency divider 116.

  The reception PLL 109 (local oscillation unit) inputs a reference clock (first reference clock or second reference clock) from a circuit connected by the reception switch 117. Further, the reception PLL 109 receives a signal output from the CPU 107 and instructing to generate a local oscillation signal corresponding to the reception channel. Then, the reception PLL 109 outputs a local oscillation signal for reception (reception local) based on the two input signals.

  The transmission PLL 110 (local oscillation unit) inputs a reference clock (first reference clock or second reference clock) from a circuit connected by the transmission switch 118. Further, the transmission PLL 110 inputs a signal output from the CPU 107 and instructing to generate a local oscillation signal corresponding to the transmission channel. Then, the transmission PLL 110 outputs a local oscillation signal for transmission (transmission local) based on the two input signals.

  The DSP 111 modulates transmission data output from the CPU 107 and outputs a modulated signal. The mixer 112 receives the signal output from the DSP 111 and the transmission local oscillation signal output from the transmission PLL 110 of the local oscillation signal generation device 10. The mixer 112 mixes and outputs these two signals. The power amplifier 113 receives the signal output from the mixer 112, amplifies the input signal, and outputs the amplified signal. The low-pass filter 114 receives the signal output from the power amplifier 113 and outputs a signal in which high-frequency components are suppressed.

  2 and 3 are diagrams illustrating a specific example of a method of acquiring a multiplication factor (value of n) and a frequency division number (value of m). Hereinafter, this acquisition method will be described in detail. In order to facilitate the configuration of the circuit, the value of n and the value of m are both positive numbers. FIG. 2 shows the frequency after multiplication and division when the value of n and the value of m take values of 1 to 10, respectively, when the frequency of the first reference clock is 14.4 MHz, for example. FIG. For example, if the value of n is “3” and the value of m is “5”, 8.640 is obtained as a result of the calculation of 14.4 × 3/5. An optimum value is selected as the second reference clock from the values shown in FIG. 2, and one combination of the n value and the m value is selected according to the value. This selection is made in advance by the designer. Since the frequency of the second reference clock is preferably a value close to the frequency of the first reference clock from the viewpoint of facilitating circuit design, in this example, a frequency of less than 10 MHz or more than 20 MHz is an option. It is excluded from.

  The frequency of the second reference clock is a value obtained by multiplying the frequency of the first reference clock by an integer and cannot be obtained by dividing a value in the vicinity of the frequency that can be taken by the local oscillation signal by a positive number. For example, when the frequency of the local oscillation signal can take any of 805 MHz to 825 MHz, 850 MHz to 870 MHz, and 932 MHz to 952.25 MHz, a value in the vicinity thereof (for example, a value in the range of plus or minus 1.0 MHz, The value obtained by multiplying the frequency of the first reference clock by an integer is 806.4 MHz, 820.8 MHz, 849.6 MHz, 864.0 MHz. , 936.0 MHz and 950.4 MHz. Therefore, in this case, the frequency of the second reference clock is a value that cannot be obtained by dividing any of these six values by a positive number. In other words, even if any of these six values is divided by the frequency of the second reference clock, the obtained remainder does not become “0”.

  FIG. 3 is a diagram illustrating a remainder when a value obtained by multiplying the frequency of the first reference clock by an integer (NG frequency list) is divided by a frequency value of each clock candidate (value of each frequency shown in FIG. 2). It is. In other words, in FIG. 3, a clock candidate having no “0” in the remainder value satisfies the frequency condition of the second reference clock described above. In FIG. 3, a clock candidate that satisfies this condition is indicated by a circle in the adoption availability column. One of the frequency values is adopted as the frequency of the second reference clock from among the clock candidates for which adoption is “good”. For example, if the frequency division number is a power of 2, circuit design is facilitated, and therefore, one frequency value may be selected from this point of view. Further, the closer the frequency of the second reference clock is to the value of the frequency of the first reference clock, the closer the signal characteristics related to the design of the loop filter used for the reception PLL 109 and the transmission PLL 110 are. This facilitates circuit design. Therefore, from such a viewpoint, a frequency closer to the frequency of the first reference clock may be selected as the frequency of the second reference clock. From the above viewpoint, “9” may be selected as the value of n, and “8” may be selected as the value of m.

  FIG. 4 is a diagram illustrating a specific example of the selection process performed by the CPU 107. Hereinafter, the selection process performed by the CPU 107 will be described in detail. FIG. 4 shows that when the frequency of the first reference clock is “14.4 MHz” and the frequency of the second reference clock is “16.2 MHz”, the frequency used in the vicinity of the frequency that the local oscillation signal can take. Indicates the situation. The arrow extending from the bottom to the top indicates the harmonic frequency of the first reference clock. An arrow extending from the upper side to the lower side indicates the harmonic frequency of the second reference clock. In addition, two broken lines connected by orthogonal arrows indicate a frequency interval that the local oscillation signal can take.

  The strength of the spurious becomes stronger as the frequency of the local oscillation signal is closer to the harmonic frequency of the reference clock used to generate the local oscillation signal. Therefore, the CPU 107 calculates the difference (first difference) between the harmonic frequency of the first reference clock and the frequency of the local oscillation signal, and the harmonic frequency of the second reference clock and the frequency of the local oscillation signal. The difference (second difference) is compared, and a reference clock that makes this difference larger is selected. For example, when the frequency of the local oscillation signal is 821 MHz, the first difference is 0.2 MHz. The second difference is 4.0 MHz. In this case, since the second difference is larger than the first difference, the CPU 107 selects the second reference clock.

  FIG. 5 is a flowchart of processing performed by the CPU 107 of the wireless device 1. When the wireless device 1 starts preparation for transmission or reception, the CPU 107 calculates the value of the frequency of the local oscillation signal (local oscillation frequency) based on the channel used for communication (step S01). Next, the CPU 107 selects a reference clock used in generating the local oscillation signal based on the calculated frequency value of the local oscillation signal (step S02). Next, the CPU 107 switches the reception switch 117 or the transmission switch 118 so that the selected reference clock is input to the device (the reception PLL 109 or the transmission PLL 110) that generates the local oscillation signal (step S107). S03).

  Next, the CPU 107 calculates the frequency division number to be set in the PLL (reception PLL 109 or transmission PLL 110) that generates the local oscillation signal based on the frequency of the selected reference clock and the frequency of the local oscillation signal. (Step S04). Next, the CPU 107 transmits a control signal including the calculated frequency division number to the PLL that generates the local oscillation signal (step S05). When receiving the control signal, the PLL that generates the local oscillation signal receives the reference clock selected by the CPU 107 and outputs the local oscillation signal based on the frequency division number.

  Next, the CPU 107 monitors the lock detection signal output from the PLL that generates the local oscillation signal, and determines whether or not it is locked (synchronized) (step S06). If the lock does not occur even after a predetermined time has elapsed (step S07-NO), the CPU 107 outputs an error (step S08). On the other hand, when locked within a predetermined time (step S07-YES), the CPU 107 starts reception processing or transmission processing (step S09).

  Thereafter, in the reception process, when the synchronization signal transmitted from the base station is received, the CPU 107 calculates a frequency shift based on the synchronization signal (step S10). Based on this frequency shift, the CPU 107 obtains a voltage to be applied to the VCTCXO 108 and applies this voltage to the VCTCXO 108 (step S11). Then, the CPU 107 ends the transmission process or the reception process.

  In the wireless device 1 configured as described above, the first reference clock and the second reference clock having a frequency different from that of the first reference clock are used as the reference clock. The CPU 107 selects one of the first reference clock and the second reference clock that generates less spurious. Then, a local oscillation signal is generated using the selected reference clock. For this reason, it is possible to reduce spurious generated.

  In the wireless device 1, the frequency value of the second reference clock is a value obtained by multiplying the frequency of the first reference clock by an integer and is a value in the vicinity of the frequency that can be taken by the local oscillation signal by a positive number. This is a value that cannot be obtained. Therefore, the harmonic frequency of the second reference clock does not take the same value as the harmonic frequency of the first reference clock in the vicinity of the frequency that the local oscillation signal can take. In other words, in the vicinity of the frequency that can be taken by the local oscillation signal, the harmonic frequency of the first reference clock does not match the harmonic frequency of the second reference clock. For this reason, by selecting either the first reference clock or the second reference clock, it is possible to reduce spurious with respect to the frequency of more local oscillation signals.

  Further, in the wireless device 1, the first difference and the second difference are compared, and a reference clock having a larger value is selected. Therefore, compared with the case where the other reference clock is selected, the difference between the frequency of the local oscillation signal and the harmonic frequency of the reference clock is increased, and the spurious strength can be reduced.

<Modification>
The CPU 107 may calculate a value representing the closeness between the frequency of the first reference clock and the frequency of the local oscillation signal, and may select the reference clock based on this value. In this case, the CPU 107 selects the second reference clock when the value indicating this proximity indicates that it is closer than the reference. On the other hand, in other cases, the CPU 107 selects the first reference clock.

  Specifically, the value representing the proximity may be, for example, the difference between two frequency values, or the ratio of the two frequency values (for example, the frequency value of the local oscillation signal is the denominator, The frequency value of the reference clock may be numerator. When the value representing the proximity is a difference in frequency value, the reference is set as a threshold value such as 1.8 MHz or 2.5 MHz. In this case, if the difference between the two frequencies is smaller than the threshold, the CPU 107 determines that the value indicating the proximity is closer to the reference, and selects the second reference clock. When the value representing the proximity is a ratio of frequency values, the reference is set as a decimal range including 1 such as 0.99 to 1.01 and 0.995 to 1.010. The In this case, if the ratio between the two frequencies is within this range, the CPU 107 determines that the value indicating the proximity is closer than the reference, and selects the second reference clock.

  FIG. 6 is a table showing correspondence between local oscillation signals and reference clocks. In each table, the value on the left indicates the frequency of the local oscillation signal, and the value on the right indicates the frequency of the reference clock. This table is created in advance by a designer and stored in a RAM (Random Access Memory) or a ROM (Read Only Memory) (not shown). The CPU 107 may select a reference clock corresponding to the frequency of the local oscillation signal by referring to this table. With this configuration, it is possible to speed up the selection process of the CPU 107.

In addition, the multiplication factor (value of n) and the frequency division number (value of m) may be other values such as a decimal number instead of a positive number.
Further, the multiplier 115 and the frequency divider 116 may be configured as an integrated device. FIG. 7 is a diagram illustrating a configuration of a wireless device 1a that is a modification of the wireless device 1 configured as described above.

  A plurality of multipliers and frequency dividers may be provided. FIG. 8 is a diagram illustrating a configuration of a wireless device 1b that is a modified example of the wireless device 1 configured as described above. In FIG. 8, the radio apparatus 1b includes a plurality of multipliers 115a and 115b and a plurality of frequency dividers 116a and 116b. The combination of the values of n and m in the multiplier 115a and the frequency divider 116a and the combination of the values of n and m in the multiplier 115b and the frequency divider 116b are set to be different from each other. 115b and frequency divider 116b generate a third reference clock having a frequency different from the frequency of the first reference clock and the frequency of the second reference clock. The CPU 107 selects a reference clock with the smallest spurious frequency from the first reference clock, the second reference clock, and the third reference clock based on the respective frequencies. With this configuration, it is possible to more efficiently reduce spurious. In FIG. 7, the combination of the multiplier 115 and the frequency divider 116 is two sets, but three or more sets may be provided.

Note that the CPU 107 in the above-described embodiment operates by reading a program for realizing the above-described functions. The program may be for realizing a part of the functions described above.
The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

It is a figure which shows the structure of a radio | wireless apparatus. It is a figure which shows the specific example of the acquisition method of the multiplication factor (value of n) and the frequency division number (value of m). It is a figure which shows the specific example of the acquisition method of the multiplication factor (value of n) and the frequency division number (value of m). It is a figure which shows the specific example of the selection process which CPU performs. It is a flowchart of the process which CPU of a radio | wireless apparatus performs. It is a table which shows matching with a local oscillation signal and a reference clock. It is a figure which shows the structure of the 1st modification of a radio | wireless apparatus. It is a figure which shows the structure of the 2nd modification of a radio | wireless apparatus. It is a figure which shows the example of the conventional apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Radio | wireless apparatus, 101 ... Antenna, 102 ... Transmission / reception switch, 103, 114 ... Low pass filter, 104 ... Low noise amplifier, 105, 112 ... Mixer, 106, 111 ... DSP, 107 ... CPU, 108 ... VCTCXO, 109 ... For reception PLL: 110: PLL for transmission, 113: Power amplifier, 115: Multiplier, 116: Frequency divider, 117: Switch for reception, 118: Switch for transmission, 10: Local oscillation signal generator, 215: Frequency divider , 1000: Wireless device, 1001 ... Antenna, 1002 ... Switch, 1003, 1014 ... Low pass filter, 1004 ... Low noise amplifier, 1005, 1012 ... Mixer, 1006, 1011 ... DSP, 1007 ... CPU, 1008 ... VCTCXO, 1009 Reception PLL, 1010 ... transmission PLL, 1013 ... power amplifier

Claims (6)

A first reference clock generator for generating a first reference clock;
A second reference clock generator for generating a second reference clock having a frequency different from that of the first reference clock;
A selection unit that selects a reference clock used in generating a local oscillation signal, which of the first reference clock and the second reference clock is smaller in spurious generated;
A local oscillation unit that generates a local oscillation signal using the selected reference clock; and
A local oscillation signal generator.   The second reference clock generation unit is a value obtained by dividing the frequency of the first reference clock by an integer and a value in the vicinity of the frequency that can be taken by the local oscillation signal by dividing by a positive number. The local oscillation signal generation device according to claim 1, wherein a signal synchronized with the first reference clock is generated as the second reference clock.   3. The local oscillation signal generation device according to claim 1, wherein the selection unit selects a reference clock in which a difference between a harmonic frequency of a reference clock and a frequency of the local oscillation signal becomes larger.   When the selection unit indicates that the value representing the closeness between the harmonic frequency of the first reference clock and the frequency of the local oscillation signal is closer than the reference, the selection unit selects the second reference clock; The local oscillation signal generation device according to claim 1, wherein the first reference clock is selected in other cases. The local oscillation signal generation device according to any one of claims 1 to 4,
A signal receiving unit for receiving a radio signal from another device;
A mixing unit that mixes the local oscillation signal output from the local oscillation signal generation device and the signal received by the signal reception unit, and outputs a mixed signal;
A demodulator that demodulates the mixed signal to obtain demodulated data;
A signal receiving device. The local oscillation signal generation device according to any one of claims 1 to 4,
A signal receiving unit for receiving a radio signal from another device;
A mixing unit that mixes the local oscillation signal output from the local oscillation signal generation device and the signal received by the signal reception unit, and outputs a mixed signal;
Based on the mixed signal, a detection unit that detects the amount of frequency deviation between the reference clock selected by the selection unit and the radio signal;
A control unit that performs control to eliminate the deviation based on the amount of deviation detected by the detection unit;
A synchronization device.

Images