JP2009123944A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce GIDL which is caused by a high electric field in a semiconductor device without decreasing its driving capability. <P>SOLUTION: A gate electrode 108 includes a first conductive part 108A which is positioned in the center of the direction of channel length of the gate electrode 108 and contacts a high permittivity film 107, namely a gate insulating film and a second conductive parts 108B which are positioned at both ends of the direction of channel length of the gate electrode 108 and contacts the high permittivity film 107, namely the gate insulating film. A first work function of the first conductive part 108A and a second work function of the second conductive part 108B are different. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a structure of a gate electrode of a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

FIG. 22 is a sectional view showing a structure of a conventional semiconductor device, specifically, a MISFET. As shown in FIG. 22, a channel region 13 is formed on the surface of the well region 12 of the substrate 11, extension regions 14 are formed on both sides of the channel region 13, and the channel region 13 and each extension region 14 are connected to each other. Source / drain regions 15 are formed so as to be sandwiched therebetween. A gate insulating film 16 is formed on the channel region 13, and a gate electrode 17 is formed on the gate insulating film 16. An insulating sidewall spacer 18 is formed on the extension region 14 so as to sandwich the gate electrode 17. The gate insulating film 16 is formed of a single kind of material having a low relative dielectric constant such as SiO ₂ . The gate electrode 17 is made of a material having a single work function such as polycrystalline silicon. The insulating sidewall spacer 18 is made of SiO ₂ or SiN. A part of each extension region 14 is formed so as to overlap the gate electrode 17 in a region A (hereinafter referred to as an overlap region A).

  Hereinafter, an increase in the electric field strength inside the semiconductor device accompanying the miniaturization of the MISFET will be described.

  As the speed and performance of a semiconductor device increase and the semiconductor device is miniaturized, the extension region is formed shallower. This increases the sheet resistance in the extension region. For this reason, it is difficult to lower the voltage in order to maintain the current drive capability of the MISFET, and voltage scaling becomes difficult. As a result, the electric field strength inside the semiconductor device increases.

  As an influence of a high electric field inside the semiconductor device, there is a drain current leak (GIDL: Gate Induced Drain Leakage) due to an electric field generated by a gate voltage.

  A mechanism by which the above-described GIDL occurs in the semiconductor device shown in FIG.

  When a drain voltage is applied to the drain region of the source / drain region 15, an electric field generated in the channel length direction by the drain voltage in the overlap region A of the extension region 14 located in the vicinity of the interface with the gate insulating film 16 The electric field generated in the vertical direction (direction perpendicular to the main surface of the substrate 11) by the gate voltage applied to the gate electrode 17 is superimposed, and a high electric field is generated in the overlap region A. As a result, carriers are generated by the band-to-band tunnel, which causes a leakage current, that is, GIDL. GIDL increases as the gate insulating film 16 becomes thinner or the relative dielectric constant of the gate insulating film 16 increases.

  As a method for suppressing this GIDL, Patent Document 1 proposes a semiconductor device having a structure in which the side surface of the gate insulating film enters the inside of the gate electrode rather than the side surface of the gate electrode.

  Hereinafter, a conventional semiconductor device disclosed in Patent Document 1 will be described with reference to FIG. As shown in FIG. 23, a channel region 23 is formed on the surface of a well region 22 of a semiconductor substrate 21 such as a silicon substrate, and source / drain regions 24 are formed on both sides of the channel region 23. A gate insulating film 25 having a high relative dielectric constant (k = 40) is formed on the channel region 23, and a gate electrode 26 is formed on the gate insulating film 25. Insulating sidewall spacers 27 are formed on both side surfaces of the gate electrode 26. A part of each source / drain region 24 is formed so as to overlap the gate electrode 26 in the region A (hereinafter referred to as the overlap region A). That is, the boundary between the channel region 23 and the source / drain region 24 is located on the inner side of the gate electrode 26 with respect to the side surface of the gate electrode 26. In addition, the side surface of the gate insulating film 25 is located closer to the inner side of the gate electrode 26 than the side surface of the gate electrode 26. Specifically, the side surface of the gate insulating film 25 enters the inner side of the gate electrode 26 by an offset amount B from the side surface of the gate electrode 26 and is located on the overlap region A.

By using the structure shown in FIG. 23 disclosed in Patent Document 1, a part of the channel region 23 is not covered with the gate insulating film 25, and the electric field due to the gate voltage does not sufficiently act in the part. , It is possible to weaken the electric field in the overlap region A, thereby reducing GIDL.
JP 2004-186295 A

  However, the conventional semiconductor device shown in FIG. 23 has the following problems. That is, since the side surface of the gate insulating film 25 has a structure in which the side surface of the gate electrode 26 enters the inner side of the gate electrode 26 by the offset amount B than the side surface of the gate electrode 26, the substantial range of the overlap region A is the offset amount B Decrease. That is, in the overlap region A where the gate insulating film 25 is not formed, in the source / drain regions 24, the parasitic resistance increases due to insufficient electric field due to the gate voltage, so that the driving capability is reduced. Problems arise.

  In view of the above, an object of the present invention is to reduce GIDL caused by the influence of a high electric field inside a semiconductor device without reducing driving capability.

  In order to achieve the above object, a semiconductor device according to the present invention includes a gate electrode formed on a semiconductor substrate via a gate insulating film, and impurities formed on both sides of the gate electrode in the surface portion of the semiconductor substrate. The gate electrode is positioned at a central portion in the channel length direction of the gate electrode and in contact with the gate insulating film; and at both ends of the gate electrode in the channel length direction And a second conductive part in contact with the gate insulating film, wherein the first work function of the first conductive part and the second work function of the second conductive part are different.

  According to the semiconductor device of the present invention, the first work function of the gate electrode central portion (first conductive portion) is different from the second work function of both ends of the gate electrode (second conductive portion). Only the second work function can be brought close to the third work function of the impurity regions (for example, extension regions) on both sides of the gate electrode. Therefore, while securing a substantial overlap region between a part of the impurity region and both ends of the gate electrode, the strength of the electric field generated in the direction perpendicular to the main surface of the substrate due to the gate voltage is reduced. It can be reduced only on the lower side of the second conductive part. Therefore, GIDL caused by the influence of the high electric field inside the semiconductor device can be reduced without reducing the driving capability. In addition, since the electric field strength below both ends of the gate electrode, that is, the maximum electric field strength inside the semiconductor device can be reduced, generation of hot carriers can be suppressed.

  That is, in the semiconductor device of the present invention, the third work function of the impurity region is compared with the difference between the third work function of the impurity region and the first work function of the first conductive portion. The difference between the second conductive function and the second work function is small.

  Specifically, in the semiconductor device of the present invention, the impurity region and the second conductive portion are each made of n-type silicon, and the first conductive portion is made of a metal or a metal compound. Good. In this case, the metal may be Mo, Ta, or W, and the metal compound may be TiN, MoSiN, or LaO. Here, the metal compound may be an alloy.

Alternatively, in the semiconductor device of the present invention, the impurity region and the second conductive portion may each be made of p-type silicon, and the first conductive portion may be made of a metal or a metal compound. In this case, the metal may be Ta, W, or Pt, and the metal compound may be TiN, MoSiN, RuO ₂ , TaN, TaC, or PtW.

  In the semiconductor device of the present invention, the impurity region may be an extension region. In this case, a part of the extension region may overlap with both ends of the gate electrode in the channel length direction, and both side surfaces of the gate insulating film may be located on the extension region. The semiconductor device may further include source / drain regions formed on a surface portion of the semiconductor substrate outside the extension region when viewed from the gate electrode, and insulating sidewalls formed on both side surfaces of the gate electrode. A spacer may be provided. Here, the extension region may be an LDD (lightly doped drain) region.

  Further, in the semiconductor device of the present invention, when the gate insulating film includes a high dielectric constant film, the physical film thickness can be increased while reducing the equivalent oxide thickness of the gate insulating film, thereby suppressing leakage current. However, the performance of the transistor can be improved. Here, the high dielectric constant film is an insulating oxide film having a relative dielectric constant higher than that of a silicon oxide film (relative dielectric constant 3.9), desirably a relative dielectric constant of 8 or more. In this case, when the gate insulating film includes an insulating interface layer formed between the semiconductor substrate and the high dielectric constant film, the interface characteristics can be improved.

  In the semiconductor device of the present invention, the first conductive portion and the second conductive portion may be electrically connected, and the first conductive portion is on the second conductive portion. The second conductive part may be formed so as to get on, or the second conductive part may be formed so as to straddle the first conductive part.

  Further, in the semiconductor device of the present invention, when the side surface of the gate insulating film and the side surface of the gate electrode are flush with each other, the side surface of the gate insulating film enters the inner side of the gate electrode rather than the side surface of the gate electrode. As described above, it is possible to avoid a situation in which a substantial overlap region between a part of the impurity region and both ends of the gate electrode is reduced.

  When manufacturing the semiconductor device of the present invention, after forming the second conductive portion on the wall surface of the recess formed using a dummy gate, the first conductive portion is formed so as to fill the recess. By doing so, the gate electrode may be formed. Alternatively, after forming the first conductive portion, a conductive film is formed so as to cover the first conductive portion, and then the conductive film is etched back or patterned to perform the first conductive portion. The gate electrode may be formed by forming the second conductive portion on the side wall.

  According to the present invention, it is possible to selectively reduce the maximum electric field strength inside the semiconductor device that occurs below both ends of the gate electrode, so that the influence of the high electric field inside the semiconductor device does not reduce the driving capability. The generated GIDL can be reduced.

  In addition, according to the present invention, since the maximum electric field strength inside the semiconductor device can be reduced, generation of hot carriers can be suppressed.

(First embodiment)
Hereinafter, the semiconductor device according to the first embodiment of the present invention will be described with an n-type MISFET as an example with reference to the drawings.

FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. As shown in FIG. 1, for example, a p-type well region 102 is formed in a semiconductor substrate 101 such as a silicon substrate, and a p-type channel region 103 is formed on the surface of the well region 102. For example, an n-type extension region 104 is formed on both sides of the channel region 103 on the surface of the well region 102, and an n ⁺ -type source / drain region 105 is sandwiched between the channel region 103 and the extension region 104, for example. Is formed. On the channel region 103, for example, an insulating interface layer 106 having a relative dielectric constant k = 3.9 and a high dielectric constant film 107 having a higher relative dielectric constant (for example, k = 40) than the insulating interface layer 106 are sequentially formed. The gate insulating film is formed. A gate electrode 108 is formed on the high dielectric constant film 107, and an insulating sidewall spacer 109 made of, for example, SiO ₂ is formed on the extension region 104 so as to sandwich the gate electrode 108. Here, the insulating interface layer 106 is, for example, a SiO ₂ film, a SiN film, a HfSiO _x film, a ZrSiO _x film, or an AlSiO _x film. A part of the extension region 104 is formed so as to overlap with both ends of the gate electrode 108 in the channel length direction in the region A (hereinafter referred to as an overlap region A). That is, the boundary between the channel region 103 and the extension region 104 enters the inner side of the gate electrode 108 from the side surface of the gate electrode 108. Note that the side surface of the gate insulating film formed of the insulating interface layer 106 and the high dielectric constant film 107 is flush with the side surface of the gate electrode 108, and both side surfaces of the gate insulating film are located on the extension region 104.

  The feature of this embodiment is that the gate electrode 108 is located in the center of the gate electrode 108 in the channel length direction and the first conductive portion 108A in contact with the high dielectric constant film 107, that is, the gate insulating film, and the channel of the gate electrode 108 A second conductive portion 108B located at both ends in the longitudinal direction and in contact with the high dielectric constant film 107, that is, the gate insulating film, and the first work function of the first conductive portion 108A and the second conductive portion 108B The second work function is different. The first conductive portion 108A and the second conductive portion 108B are electrically connected.

  Specifically, the first conductive portion 108A has a work function (first work function) of 4.4 eV, for example, and is made of metal, for example. The second conductive portion 108B is closer to the work function (third work function) of the extension region 104, that is, the n-type silicon than the first conductive portion 108A, for example, 4.2 eV work function (second work function). Function) and is formed so as to sandwich the first conductive portion 108A. Here, each of the second conductive portions 108B provided on both sides of the first conductive portion 108A has a width (width in the channel length direction) C. That is, the boundary between the first conductive portion 108A and the second conductive portion 108B enters the gate electrode 108 from the side surface of the high dielectric constant film 107, that is, the gate insulating film, by a width C.

  If the width C of the second conductive portion 108B is larger than 0 nm, the effects described later can be obtained. The width C of the second conductive portion 108B may be larger than the length of the overlap region A. However, in order not to deteriorate the transistor characteristics, the second conductive portion 108B has a length relative to the length of the overlap region A. It is preferable that the excess of width C does not exceed 5 nm.

  Hereinafter, when a positive drain voltage and a negative gate voltage are applied to the semiconductor device of the present embodiment shown in FIG. The electric field in the vertical direction (hereinafter the same) will be described. In the present embodiment, the second work function of the portion of the gate electrode 108, that is, the second conductive portion 108 B located on the overlap region A is n-type than the first work function of the first conductive portion 108 A. It is close to the extension region 104, that is, the third work function of n-type silicon. Therefore, the difference between the third work function of the n-type extension region 104 and the second work function of the second conductive portion 108B is the same as the third work function of the n-type extension region 104 and the first conductivity. It becomes smaller than the difference from the first work function of the part 108A. As a result, the length of the overlap region A is kept constant, in other words, due to the gate voltage while securing a substantial overlap region between a part of the extension region 104 and both ends of the gate electrode 108. Thus, the electric field strength generated in the vertical direction can be selectively reduced in the overlap region A. Therefore, GIDL caused by the influence of the high electric field inside the semiconductor device can be reduced without reducing the driving capability. In addition, since the electric field strength below the both ends of the gate electrode 108, that is, the maximum electric field strength inside the semiconductor device can be reduced, generation of hot carriers can be suppressed.

  Hereinafter, the second work function of the second conductive portion 108B in the gate electrode 108 is brought close to the third work function of the n-type extension region 104, that is, n-type silicon, so that the vertical direction in the overlap region A is increased. The reason why the intensity of the electric field can be reduced will be described in detail.

FIG. 2A is a cross-sectional view of a general n-type MISFET. The n-type MISFET shown in FIG. 2A includes a gate electrode, a gate insulating film, a p ⁻ type well region, an n ⁺ type source region, and an n ⁺ type drain region. In order to simplify the description, it is assumed that the gate electrode is made of a material having a single work function. 2 (b) and 2 (c) are schematic views of the band structure along the line AA ′ in FIG. 2 (a), respectively, and FIG. 2 (b) is a work in which the gate electrode is 4.1 eV. FIG. 2C is a schematic diagram of a band structure having a function (corresponding to a work function of n ⁺ -type polysilicon), and FIG. 2C shows a case where the gate electrode has a work function (large work function) of 4.6 eV. It is a schematic diagram of a band structure. In FIGS. 2B and 2C, the work function of the n ⁺ -type drain region is 4.1 eV. Further, both the band structures shown in FIGS. 2B and 2C are for the case where both the gate voltage Vg and the drain voltage Vd are 0V. In FIG. 2B and FIG. 2C, the vertical axis represents the magnitude of the potential (downward is positive), the horizontal axis represents the position, and the slope of the line indicating the band represents the electric field strength. As shown in FIG. 2 (b), when the gate electrode having a work function of 4.1 eV, since there is a difference between the work function of the gate electrode of the drain region, and the n ⁺ -type drain region No band bending occurs between the gate insulating film and the gate insulating film. On the other hand, as shown in FIG. 2C, when the gate electrode has a large work function (4.6 eV), the work function of the gate electrode is larger than the work function of the drain region. Even if both Vd are 0 V, a positive voltage corresponding to the difference (approximately 4.6-4.1 = 0.5 V) is apparently already applied. As a result, as shown in FIG. 2C, the band is bent between the n ⁺ -type drain region and the gate insulating film.

3A and 3B are schematic diagrams of a band structure (a band structure along the line AA ′ in FIG. 2A) under a voltage condition in which GIDL becomes remarkable. 3A is a schematic diagram of a band structure in the case where the gate electrode has a work function of 4.1 eV (corresponding to the work function of n ⁺ -type polysilicon), and FIG. It is a schematic diagram of a band structure in the case of having a work function (large work function) of 6 eV. In FIG. 3A and FIG. 3B, the work function of the n ⁺ -type drain region is 4.1 eV. 3A and 3B both use a voltage condition that makes GIDL conspicuous. Specifically, the gate voltage Vg is 0 V and the drain voltage Vd is 1.2 V. Is the case. 3A and 3B, the vertical axis indicates the magnitude of the potential (downward is positive), the horizontal axis indicates the position, and the slope of the line indicating the band indicates the electric field strength. As shown in FIG. 3A, when the gate electrode has a work function of 4.1 eV, a drain voltage Vd of 1.2 V is applied, so that the n ⁺ -type drain region and the gate insulating film are interposed. , The band is bent by the drain voltage Vd of 1.2V. On the other hand, as shown in FIG. 3B, when the gate electrode has a large work function (4.6 eV), as described above, a positive value corresponding to the difference between the work function of the gate electrode and the work function of the drain region is obtained. Since the drain voltage Vd of 1.2 V is applied in a superimposed manner in the state where the voltage of about 0.5 V has already been applied, the gap between the gate electrode and the drain region is as shown in FIG. A larger voltage than that shown is applied. For this reason, the bending of the band between the n ⁺ -type drain region and the gate insulating film is also larger than that shown in FIG. 3A, and as a result, the electric field intensity corresponding to the slope of the line indicating the band is also increased. As compared with the case shown in FIG.

  As described above, in the case of an n-type MISFET, the strength of the electric field in the vertical direction increases as the work function of the gate electrode increases. Therefore, as in this embodiment, the second work function of the second conductive portion 108B provided at both ends of the gate electrode 108 is reduced to reduce the third work of the n-type extension region 104, that is, the n-type silicon. By approaching the function, the strength of the electric field in the vertical direction in the overlap region A can be reduced.

  In the first embodiment, the work function (first work function) of the first conductive portion 108A of the gate electrode 108 is made closer to the work function of p-type silicon, thereby suppressing DIBL (Drain Induced Barrier Lowering). can do.

In the first embodiment, the relative dielectric constant of the insulating interface layer 106 is set to 3.9. However, the present invention is not limited to this, and an arbitrary value smaller than the relative dielectric constant (40) of the high dielectric constant film 107 is used. Can be set to If the thickness of the insulating interface layer 106 is at least larger than 0, the interface characteristics can be improved. Further, although the relative dielectric constant of the high dielectric constant film 107 is set to 40, the present invention is not limited to this, and is set to an arbitrary value larger than the relative dielectric constant (3.9) of the insulating interface layer (silicon oxide film) 106. can do. As the high dielectric constant film 107, it is desirable to use an insulating oxide film having a relative dielectric constant of 8 or more. For example, an Al ₂ O ₃ film, a ZrO ₂ film, an HfO ₂ film, an HfSiO _x film, and a ZrSiO film are used. _{An x} film, a Y ₂ O ₃ film, a La ₂ O ₃ film, a PrO _x film, or the like can be used.

  In the first embodiment, the work function of the first conductive portion 108A of the gate electrode 108 is set to 4.4 eV. However, the work function is not limited to this, and the p-type silicon is higher than the work function of the second conductive portion 108B. Any value close to the work function can be set. At this time, the constituent material of the first conductive portion 108A may be a semiconductor or a metal. In addition, the work function of the second conductive portion 108B of the gate electrode 108 is set to 4.2 eV. However, the work function is not limited to this, and any work function closer to the work function of n-type silicon than the work function of the first conductive portion 108A is used. Can be set to a value. At this time, the constituent material of the second conductive portion 108B may be a semiconductor or a metal. For example, TiN, Mo, MoSiN, Ta, W, LaO, or the like can be used as the constituent material of the first conductive portion 108A, and n-type polysilicon is used as the constituent material of the second conductive portion 108B. it can.

In the first embodiment, the gate structure of an n-type MISFET has been described. However, the present invention can also be applied to a gate structure of a p-type MISFET. In this case, the constituent material of the first conductive portion 108A of the gate electrode 108 is a semiconductor or metal having a work function closer to the work function of n-type silicon than the second conductive portion 108B. As the constituent material of the second conductive portion 108B, a semiconductor or metal having a work function closer to that of p-type silicon than the first conductive portion 108A is used. For example, TiN, MoSiN, RuO ₂ , Ta, TaN, TaC, W, PtW, or Pt can be used as the constituent material of the first conductive portion 108A, and the constituent material of the second conductive portion 108B is p. Type polysilicon can be used. When the gate structure of a p-type MISFET is targeted, the channel region 103 is made of n-type silicon, the extension region 104 is made of p-type silicon, and the source / drain regions 105 are made of p ⁺ -type silicon.

  Hereinafter, assuming that the semiconductor device of this embodiment shown in FIG. 1 is a p-type MISFET, the vertical electric field generated in the overlap region A when a negative drain voltage and a negative gate voltage are applied, By making the second work function of the second conductive portion 108B in the electrode 108 closer to the third work function of the extension region 104, that is, p-type silicon, the strength of the electric field in the vertical direction in the overlap region A can be reduced. The reason will be explained.

FIG. 4A is a cross-sectional view of a general p-type MISFET. The p-type MISFET shown in FIG. 4A includes a gate electrode, a gate insulating film, an n ⁻ type well region, a p ⁺ type source region, and a p ⁺ type drain region. In order to simplify the description, it is assumed that the gate electrode is made of a material having a single work function. 4 (b) and 4 (c) are schematic views of the band structure along the line AA ′ in FIG. 4 (a), respectively, and FIG. 4 (b) shows a work with a gate electrode of 5.2 eV. FIG. 4C is a schematic diagram of a band structure in the case of having a function (corresponding to the work function of p ⁺ -type polysilicon), and FIG. 4C is a diagram in the case where the gate electrode has a work function (small work function) of 4.6 eV. It is a schematic diagram of a band structure. In FIGS. 4B and 4C, the work function of the p ⁺ -type drain region is assumed to be 5.2 eV. The band structures shown in FIGS. 4B and 4C are for the case where both the gate voltage Vg and the drain voltage Vd are 0V. In FIGS. 4B and 4C, the vertical axis represents the magnitude of the electric potential (downward is positive), the horizontal axis represents the position, and the slope of the line indicating the band represents the electric field strength. As shown in FIG. 4 (b), when the gate electrode having a work function of 5.2 eV, since there is a difference between the work function of the gate electrode of the drain region, and a p ⁺ -type drain region No band bending occurs between the gate insulating film and the gate insulating film. On the other hand, when the gate electrode has a small work function (4.6 eV) as shown in FIG. 4C, the work function of the gate electrode is smaller than the work function of the drain region. Even if both Vd are 0 V, a negative voltage corresponding to the difference (approximately 4.6-5.2 = −0.6 V) is already apparently applied. As a result, as shown in FIG. 4C, the band is bent between the p ⁺ -type drain region and the gate insulating film.

5A and 5B are schematic diagrams of a band structure (a band structure along the line AA ′ in FIG. 4A) under a voltage condition in which GIDL becomes remarkable. FIG. 5A is a schematic diagram of a band structure when the gate electrode has a work function of 5.2 eV (corresponding to the work function of p ⁺ -type polysilicon), and FIG. It is a schematic diagram of a band structure in the case of having a work function (small work function) of 6 eV. In FIGS. 5A and 5B, the work function of the p ⁺ type drain region is assumed to be 5.2 eV. 5A and 5B both use a voltage condition in which GIDL becomes remarkable, specifically, the gate voltage Vg is 0 V and the drain voltage Vd is -1. In the case of 2V. In FIGS. 5A and 5B, the vertical axis represents the magnitude of the electric potential (downward is positive), the horizontal axis represents the position, and the slope of the line indicating the band represents the electric field strength. As shown in FIG. 5A, when the gate electrode has a work function of 5.2 eV, a drain voltage Vd of −1.2 V is applied, whereby the p ⁺ -type drain region and the gate insulating film are In the meantime, the band is bent by the amount of the drain voltage Vd of -1.2V. On the other hand, as shown in FIG. 5B, when the gate electrode has a small work function (4.6 eV), as described above, a negative value corresponding to the difference between the work function of the gate electrode and the work function of the drain region. Since the drain voltage Vd of −1.2 V is applied in a superimposed manner in the state where the voltage of about −0.6 V is already applied, the gap between the gate electrode and the drain region is shown in FIG. That is, a larger voltage than that shown in FIG. For this reason, the bending of the band between the p ⁺ -type drain region and the gate insulating film is also larger than in the case shown in FIG. 5A, and as a result, the electric field intensity corresponding to the slope of the line indicating the band is also increased. As compared with the case shown in FIG.

  As described above, in the case of a p-type MISFET, the strength of the electric field in the vertical direction increases as the work function of the gate electrode decreases. Therefore, by increasing the second work function of the second conductive portion 108B provided at both ends of the gate electrode 108 and bringing it closer to the third work function of the p-type extension region 104, that is, p-type silicon. The strength of the electric field in the vertical direction in the overlap region A can be reduced.

  In the first embodiment, the difference between the work function (4.4 eV) of the first conductive portion 108A and the work function (4.2 eV) of the second conductive portion 108B in the gate electrode 108 (hereinafter simply referred to as work). (Referred to as function difference) is set to 0.2 eV, but the present invention is not limited to this, and the difference can be appropriately set to an arbitrary value in a range from about 10 meV to about 500 meV. Hereinafter, taking an n-type MISFET as an example, it will be described that the GIDL reduction effect of the present invention can be obtained if the work function difference is about 10 meV or more. The inventor of the present application conducted a device simulation on the relationship between the threshold voltage and the substrate leakage current (an increase in GIDL increases the substrate leakage current) for the structure of the semiconductor device of the present embodiment shown in FIG. went. In the device simulation, the drain voltage Vd is 1.2 V, the gate voltage Vg is 0 V, the substrate voltage (source voltage) is 0 V, the length of the overlap region A is 2 nm, the width C of the second conductive portion 108B is 5 nm, The work function difference was set to 200 meV, 150 meV, 100 meV, 50 meV, 30 meV, 20 meV, 10 meV, and 0 meV. FIG. 6 shows the result of device simulation. As shown in FIG. 6, when compared with the same threshold voltage, the work function (second work function) of the second conductive part 108B is compared with the work function (first work function) of the first conductive part 108A. As the function) decreases, that is, as the work function difference increases, the substrate leakage current decreases. Here, even when the work function difference is 10 meV, the substrate leakage current is smaller than when there is no work function difference. Therefore, in the n-type MISFET, if the work function difference is 10 meV or more, the present invention It can be seen that the desired GIDL reduction effect can be obtained.

FIG. 7 shows the relationship between various materials for the gate electrode and the work function. As shown in FIG. 7, when the present invention is applied to the gate structure of an n-type MISFET, TiN, Mo, MoSiN, Ta, W, LaO, or the like is used as the constituent material of the first conductive portion 108A of the gate electrode 108. N-type polysilicon can be used as a constituent material of the second conductive portion 108B. As shown in FIG. 7, when the present invention is applied to the gate structure of a p-type MISFET, the constituent material of the second conductive portion 108B of the gate electrode 108 is TiN, MoSiN, RuO ₂ , Ta, TaN, TaC. , W, PtW, Pt, and the like, and p-type polysilicon can be used as a constituent material of the second conductive portion 108B.

  Hereinafter, an example of a method for manufacturing the semiconductor device of this embodiment shown in FIG. 1 will be described. FIGS. 8A to 8C, FIGS. 9A to 9C, and FIGS. 10A to 10C are cross-sectional views showing respective steps of the semiconductor device manufacturing method of the present embodiment.

  First, as shown in FIG. 8A, a well region 102 is formed on a semiconductor substrate 101 such as a silicon substrate using an ion implantation method, and then a channel region 103 is formed on the surface of the semiconductor substrate 101 using ion implantation. Form. When the well region 102 and the channel region 103 of the n-type MISFET are formed, ion implantation of a p-type impurity such as boron is performed. Further, when the well region 102 and the channel region 103 of the p-type MISFET are formed, ion implantation of an n-type impurity such as phosphorus is performed.

Next, as shown in FIG. 8B, an insulating interface layer 106 made of a silicon oxide film having a thickness of 0.1 to 5.0 nm is formed on the semiconductor substrate 101 by, for example, a thermal oxidation method. A high dielectric constant film 107 made of, for example, an HfO ₂ film is formed on the conductive interface layer 106. The HfO ₂ film is formed by, for example, a CVD (chemical vapor deposition) method using HfCl ₂ and NH ₃ or a CVD method using organic Hf gas. Alternatively, the HfO ₂ film may be formed by forming a hafnium nitride film by sputtering using a hafnium nitride target and then oxidizing the hafnium nitride film. Thereafter, a conductive film 140 made of polysilicon or amorphous silicon and having a thickness of about 200 nm is formed on the high dielectric constant film 107 by, eg, CVD.

  Next, as shown in FIG. 8C, the dummy gate electrode 150 is formed by patterning the conductive film 140 into a gate electrode shape. At this time, the high dielectric constant film 107 and the insulating interface layer 106 outside the dummy gate electrode 150 may be removed.

  Next, as shown in FIG. 9A, by performing ion implantation using the dummy gate electrode 150 as a mask, extension regions 104 are formed on the surface portions of the semiconductor substrate 101 on both sides of the dummy gate electrode 150. When the extension region 104 of the n-type MISFET is formed, ion implantation of an n-type impurity such as arsenic or phosphorus is performed. Further, when the extension region 104 of the p-type MISFET is formed, ion implantation of a p-type impurity such as boron is performed. A part of the extension region 104 is formed so as to overlap with both ends of the dummy gate electrode 150 in the channel length direction in the region A (hereinafter referred to as the overlap region A).

  Next, as shown in FIG. 9B, insulating sidewall spacers 109 are formed on both side surfaces of the dummy gate electrode 150. Specifically, first, after depositing a silicon oxide film on the entire surface of the substrate so as to cover the dummy gate electrode 150 by, for example, the CVD method, the silicon oxide film is etched back to form both sides of the dummy gate electrode 150. An insulating sidewall spacer 109 is formed. Next, by performing ion implantation using the insulating sidewall spacer 109 and the dummy gate electrode 150 as a mask, on the surface portion of the semiconductor substrate 101 located outside the insulating sidewall spacer 109 as viewed from the dummy gate electrode 150, After the source / drain region 105 having a deeper junction than the extension region 104 is formed, an annealing process is performed to activate the implanted impurity ions. In the case of forming the source / drain region 105 of the n-type MISFET, ion implantation of an n-type impurity such as arsenic or phosphorus is performed. Further, when forming the source / drain region 105 of the p-type MISFET, ion implantation of a p-type impurity such as boron is performed.

  Next, as shown in FIG. 9C, an interlayer insulating film 110 made of silicon oxide is formed on the semiconductor substrate 101 so as to cover the dummy gate electrode 150 by, for example, a CVD method. Subsequently, the interlayer insulating film 110 is removed by, for example, a CMP (chemical mechanical polishing) method until the upper surface of the dummy gate electrode 150 is exposed. Next, as shown in FIG. 10A, the dummy gate electrode 150 exposed from the interlayer insulating film 110 is removed by etching to expose the high dielectric constant film 107, that is, the gate insulating film.

  Next, as shown in FIG. 10B, the entire surface of the substrate including the recess formed by removing the dummy gate electrode 150 (hereinafter referred to as a gate electrode forming recess) is formed with a thickness of 2 to 20 nm by CVD, for example. A polysilicon film 151 is deposited. Here, when the n-type MISFET is formed, the polysilicon film 151 is doped with an n-type impurity, and when the p-type MISFET is formed, the polysilicon film 151 is doped with a p-type impurity.

  Next, as shown in FIG. 10C, the polysilicon film 151 is removed except for the portion formed on the wall surface of the recess for forming the gate electrode by etching back the polysilicon film 151. . Thereby, the second conductive portion 108B of the gate electrode 108 shown in FIG. 1 is formed on the wall surface of the gate electrode forming recess.

Next, after filling the recess for forming the gate electrode with the conductive film that becomes the first conductive portion 108A of the gate electrode 108 shown in FIG. 1, the conductive film protruding from the recess is removed by, for example, CMP. The gate electrode structure shown in FIG. 1 is completed. Here, as a material of the conductive film to be the first conductive portion 108A, a pure metal, an alloy, a metal compound, or the like can be used. Specifically, when an n-type MISFET is formed as a conductive film that becomes the first conductive portion 108A by, for example, a sputtering method, a TiN film, a Mo film, a MoSiN film, a Ta film, a W film, a LaO film, or the like is used. In the case of forming a p-type MISFET, a TiN film, a MoSiN film, a RuO ₂ film, a Ta film, a TaN film, a TaC film, a W film, a PtW film, a Pt film, or the like is formed.

  The method for manufacturing the semiconductor device according to the present embodiment described above is characterized in that the first conductive portion 108A is formed after the formation of the second conductive portion 108B of the gate electrode 108. The effect is produced. That is, the dummy gate electrode 150 is removed by etching to form a gate electrode formation recess, the gate insulating film (high dielectric constant film 107) is exposed in the recess, and then the second conductive portion 108B is formed. A second conductive portion 108B is formed by depositing a silicon film 151 in the recess for forming the gate electrode and etching back the polysilicon film 151. Then, the first conductive portion 108A is formed by filling the concave portion for forming the gate electrode with the conductive film to be the first conductive portion 108A and removing the unnecessary portion by the CMP method. The gate electrode 108 thus formed includes a first conductive portion 108A located at the center of the gate electrode 108 in the channel length direction and having a first work function, and both ends of the gate electrode 108 in the channel length direction. And a second conductive portion 108B having a second work function different from the first work function. Therefore, the effect of the semiconductor device of this embodiment shown in FIG. 1, that is, the effect that GIDL can be reduced by selectively reducing the intensity of the electric field generated in the vertical direction due to the gate voltage in the overlap region A. Is obtained.

  In addition, according to the method for manufacturing a semiconductor device according to the present embodiment, the second conductive portion 108B and the first conductive portion 108A are sequentially embedded in the recess for forming the gate electrode formed by removing the dummy gate electrode 150. It is possible to prevent misalignment as in the case of forming the gate electrode structure by patterning.

  Further, in the method of manufacturing a semiconductor device according to the present embodiment, the insulating interface layer 106 and the high dielectric constant film 107 that become the gate insulating film are formed in the step shown in FIG. 8B. Instead, for example, A dummy gate insulating film made of a silicon oxide film having a thickness of 0.1 to 5.0 nm is formed by a thermal oxidation method, and the dummy gate insulating film is removed together with the dummy gate electrode 150 in the step shown in FIG. A gate insulating film made of, for example, an insulating interface layer and a high dielectric constant film may be formed at the bottom of the gate electrode forming recess.

(Modification of the first embodiment)
Hereinafter, a semiconductor device according to a modification of the first embodiment of the present invention will be described with an n-type MISFET as an example with reference to the drawings.

  FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a modification of the first embodiment. In FIG. 11, the same components as those in the first embodiment shown in FIG.

  As shown in FIG. 11, the semiconductor device according to this modification is different from the first embodiment shown in FIG. 1 as follows. That is, in the first embodiment, the second conductive portion 108B located at both ends of the gate electrode 108 in the channel length direction is replaced with the first conductive portion 108A located at the center portion of the gate electrode 108 in the channel length direction. It was formed to sandwich. In other words, the second conductive portion 108B is formed on the entire side wall portion of the gate electrode 108 (from the upper surface to the lower surface of the gate electrode 108). On the other hand, in this modification, the second conductive portion 108B located at both ends of the gate electrode 108 in the channel length direction is formed so as to be in contact with the high dielectric constant film 107, that is, the gate insulating film. As in the first embodiment, the second conductive portion 108B is not formed above the gate electrode 108, and the first conductive portion 108A is formed on the second conductive portion 108B. This is different from the first embodiment.

  That is, the effect of the present invention described in the first embodiment is that if the first conductive portion 108A at the center of the gate electrode and the second conductive portion 108B at the end of the gate electrode are in contact with the gate insulating film, It is obtained, and it does not matter how each conductive portion is formed above the gate electrode.

  When the semiconductor device according to this modification shown in FIG. 11 is manufactured, the polysilicon film 151 formed on the upper surface of the wall surface of the recess for forming the gate electrode in the step shown in FIG. Just remove it. Thus, as shown in FIG. 12, the second conductive portion 108B of the gate electrode 108 is formed except for the upper portion of the wall surface of the gate electrode forming recess.

  According to the method of manufacturing a semiconductor device according to this modification, the dummy gate electrode 150 is removed by etching to form a gate electrode forming recess, and the gate insulating film (high dielectric constant film 107) is exposed in the recess. After forming the second conductive portion 108B by depositing a polysilicon film 151 to be the second conductive portion 108B in the recess for forming the gate electrode and etching back the polysilicon film 151, the gate electrode The width of the forming recess can be increased in the vicinity of the opening surface. Therefore, when the concave portion is filled with the conductive film to be the first conductive portion 108A, the embeddability of the conductive film can be improved. As a result, even when the conductive film to be the first conductive portion 108A is formed by using a film formation method with poor coverage such as a sputtering method, the first conductive is formed in the recess for forming the gate electrode without generating a void. A conductive film to be the portion 108A can be embedded.

(Second Embodiment)
Hereinafter, a semiconductor device according to a second embodiment of the present invention will be described with an n-type MISFET as an example with reference to the drawings.

  FIG. 13 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. In FIG. 13, the same components as those in the first embodiment shown in FIG.

  As shown in FIG. 13, the semiconductor device according to this embodiment differs from the first embodiment shown in FIG. 1 as follows. In other words, in the first embodiment, the second conductive portion 108B located at both ends of the gate electrode 108 in the channel length direction has a rectangular cross section. In contrast, in the present embodiment, the second conductive portion 108B is the same as the first embodiment in that the second conductive portion 108B is located at both ends of the gate electrode 108 in the channel length direction. The point that 108B is rounded in the upper corner of the gate electrode 108 is different from the first embodiment. Note that due to the difference in the shape of the second conductive portion 108B, the shape of the insulating sidewall spacer 109 is slightly different from that of the first embodiment.

  The same effect as that of the first embodiment can also be obtained by the semiconductor device of this embodiment shown in FIG.

  Hereinafter, an example of a method for manufacturing the semiconductor device of this embodiment shown in FIG. 13 will be described. FIGS. 14A to 14C and FIGS. 15A to 15C are cross-sectional views showing respective steps of the method of manufacturing the semiconductor device of this embodiment.

  First, as shown in FIG. 14A, a well region 102 is formed on a semiconductor substrate 101 such as a silicon substrate using an ion implantation method, and then a channel region 103 is formed on the surface of the semiconductor substrate 101 using ion implantation. Form. When the well region 102 and the channel region 103 of the n-type MISFET are formed, ion implantation of a p-type impurity such as boron is performed. Further, when the well region 102 and the channel region 103 of the p-type MISFET are formed, ion implantation of an n-type impurity such as phosphorus is performed.

Next, as shown in FIG. 14B, an insulating interface layer 106 made of a silicon oxide film having a thickness of 0.1 to 5.0 nm is formed on the semiconductor substrate 101 by, for example, a thermal oxidation method. A high dielectric constant film 107 made of, for example, an HfO ₂ film is formed on the conductive interface layer 106. The HfO ₂ film is formed by, for example, a CVD method using HfCl ₂ and NH ₃ or a CVD method using an organic Hf gas. Alternatively, the HfO ₂ film may be formed by forming a hafnium nitride film by sputtering using a hafnium nitride target and then oxidizing the hafnium nitride film. After that, a conductive film 160 having a thickness of up to about 200 nm is formed on the high dielectric constant film 107 as the first conductive portion 108A of the gate electrode 108 shown in FIG. Here, as a material of the conductive film 160, a pure metal, an alloy, a metal compound, or the like can be used. Specifically, for example, when an n-type MISFET is formed as the conductive film 160 by sputtering, a TiN film, a Mo film, a MoSiN film, a Ta film, a W film, a LaO film, or the like is formed, and the p-type MISFET is formed. In the case of forming, a TiN film, a MoSiN film, a RuO ₂ film, a Ta film, a TaN film, a TaC film, a W film, a PtW film, a Pt film, or the like is formed.

  Next, as shown in FIG. 14C, after the conductive film 160 is patterned to form the first conductive portion 108A, as shown in FIG. 15A, the first conductive portion 108A is covered. A polysilicon film 161 having a thickness of 2 to 20 nm is deposited on the entire surface of the substrate by, eg, CVD. Here, when forming an n-type MISFET, the polysilicon film 161 is doped with an n-type impurity, and when forming a p-type MISFET, the polysilicon film 161 is doped with a p-type impurity.

  Next, as shown in FIG. 15B, the polysilicon film 161 is etched back to form the second conductive portion 108B made of the polysilicon film 161 on both side surfaces of the first conductive portion 108A. To do. Thereby, the gate electrode 108 including the first conductive portion 108A and the second conductive portion 108B is formed. At this time, the high dielectric constant film 107 and the insulating interface layer 106 outside the gate electrode 108 may be removed.

  Next, as shown in FIG. 15C, extension regions 104 are formed on the surface portions of the semiconductor substrate 101 on both sides of the gate electrode 108 by performing ion implantation using the gate electrode 108 as a mask. When the extension region 104 of the n-type MISFET is formed, ion implantation of an n-type impurity such as arsenic or phosphorus is performed. Further, when the extension region 104 of the p-type MISFET is formed, ion implantation of a p-type impurity such as boron is performed. A part of the extension region 104 is formed so as to overlap with both ends of the gate electrode 108 in the channel length direction in the region A (hereinafter referred to as the overlap region A).

  Finally, in order to obtain the structure shown in FIG. 13, insulating sidewall spacers 109 are formed on both side surfaces of the gate electrode 108. Specifically, first, a silicon oxide film is deposited on the entire surface of the substrate so as to cover the gate electrode 108 by, for example, a CVD method, and then the silicon oxide film is etched back to thereby insulate both sides of the gate electrode 108. Sidewall spacers 109 are formed. Next, by performing ion implantation using the insulating sidewall spacer 109 and the gate electrode 108 as a mask, an extension region is formed on the surface portion of the semiconductor substrate 101 positioned outside the insulating sidewall spacer 109 as viewed from the gate electrode 108. After the source / drain region 105 having a junction deeper than 104 is formed, an annealing process is performed to activate the implanted impurity ions. In the case of forming the source / drain region 105 of the n-type MISFET, ion implantation of an n-type impurity such as arsenic or phosphorus is performed. Further, when forming the source / drain region 105 of the p-type MISFET, ion implantation of a p-type impurity such as boron is performed.

  The semiconductor device manufacturing method according to the present embodiment described above is characterized in that the second conductive portion 108B is formed after the formation of the first conductive portion 108A of the gate electrode 108. By using the back, the second conductive portion 108B is formed in a self-aligned manner with respect to the first conductive portion 108A. Therefore, misalignment occurs as in the case where the second conductive portion 108B is formed by patterning. Can be prevented.

(Third embodiment)
Hereinafter, a semiconductor device according to a third embodiment of the present invention will be described with an n-type MISFET as an example with reference to the drawings.

  FIG. 16 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. In FIG. 16, the same components as those in the first embodiment shown in FIG.

  As shown in FIG. 16, the semiconductor device according to this embodiment differs from the first embodiment shown in FIG. 1 as follows. That is, in the first embodiment, the first conductive portion 108A located at the center portion of the gate electrode 108 in the channel length direction is replaced by the second conductive portion 108B located at both ends of the gate electrode 108 in the channel length direction. It was formed to be sandwiched. In other words, the first conductive portion 108A is formed over the entire central portion of the gate electrode 108 (from the upper surface to the lower surface of the gate electrode 108). In contrast, in the present embodiment, the first conductive portion 108A located at the center of the gate electrode 108 in the channel length direction is formed so as to be in contact with the high dielectric constant film 107, that is, the gate insulating film. As in the first embodiment, the first conductive portion 108A is not formed except under the gate electrode 108, and the second conductive portion 108B is formed so as to straddle the first conductive portion 108A. This is different from the first embodiment.

  That is, the effect of the present invention described in the first embodiment is that if the first conductive portion 108A at the center of the gate electrode and the second conductive portion 108B at the end of the gate electrode are in contact with the gate insulating film, It is obtained, and it does not matter how each conductive portion is formed above the gate electrode.

  Hereinafter, an example of a method for manufacturing the semiconductor device of this embodiment shown in FIG. 16 will be described. FIGS. 17A to 17C and FIGS. 18A to 18C are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device of the present embodiment.

  First, as shown in FIG. 17A, a well region 102 is formed on a semiconductor substrate 101 such as a silicon substrate using an ion implantation method, and then a channel region 103 is formed on the surface of the semiconductor substrate 101 using ion implantation. Form. When the well region 102 and the channel region 103 of the n-type MISFET are formed, ion implantation of a p-type impurity such as boron is performed. Further, when the well region 102 and the channel region 103 of the p-type MISFET are formed, ion implantation of an n-type impurity such as phosphorus is performed.

Next, as shown in FIG. 17B, an insulating interface layer 106 made of a silicon oxide film having a thickness of 0.1 to 5.0 nm is formed on the semiconductor substrate 101 by, for example, a thermal oxidation method. A high dielectric constant film 107 made of, for example, an HfO ₂ film is formed on the conductive interface layer 106. The HfO ₂ film is formed by, for example, a CVD method using HfCl ₂ and NH ₃ or a CVD method using an organic Hf gas. Alternatively, the HfO ₂ film may be formed by forming a hafnium nitride film by sputtering using a hafnium nitride target and then oxidizing the hafnium nitride film. After that, a conductive film 170 having a thickness of, for example, about 10 to 50 nm is formed on the high dielectric constant film 107 to be the first conductive portion 108A of the gate electrode 108 shown in FIG. Here, as a material of the conductive film 170, a pure metal, an alloy, a metal compound, or the like can be used. Specifically, for example, when an n-type MISFET is formed as the conductive film 170 by sputtering, a TiN film, a Mo film, a MoSiN film, a Ta film, a W film, a LaO film, or the like is formed, and the p-type MISFET is formed. In the case of forming, a TiN film, a MoSiN film, a RuO ₂ film, a Ta film, a TaN film, a TaC film, a W film, a PtW film, a Pt film, or the like is formed.

  Next, as shown in FIG. 17C, after the conductive film 170 is patterned to form the first conductive portion 108A, as shown in FIG. 18A, the first conductive portion 108A is covered. A polysilicon film 171 having a thickness of up to about 200 nm is deposited on the entire surface of the substrate by, eg, CVD. Here, when forming an n-type MISFET, the polysilicon film 171 is doped with an n-type impurity, and when forming a p-type MISFET, the polysilicon film 171 is doped with a p-type impurity.

  Next, as shown in FIG. 18B, dry etching is performed on the polysilicon film 171 using a resist pattern (not shown) covering the gate electrode formation region as a mask, thereby forming the first conductive portion 108A. A second conductive portion 108B made of a polysilicon film 171 is formed so as to cover it. Thereby, the gate electrode 108 including the first conductive portion 108A and the second conductive portion 108B is formed. At this time, the high dielectric constant film 107 and the insulating interface layer 106 outside the gate electrode 108 may be removed.

  Next, as shown in FIG. 18C, extension regions 104 are formed in the surface portions of the semiconductor substrate 101 on both sides of the gate electrode 108 by performing ion implantation using the gate electrode 108 as a mask. When the extension region 104 of the n-type MISFET is formed, ion implantation of an n-type impurity such as arsenic or phosphorus is performed. Further, when the extension region 104 of the p-type MISFET is formed, ion implantation of a p-type impurity such as boron is performed. A part of the extension region 104 is formed so as to overlap with both ends of the gate electrode 108 in the channel length direction in the region A (hereinafter referred to as the overlap region A).

  Finally, in order to obtain the structure shown in FIG. 16, insulating sidewall spacers 109 are formed on both side surfaces of the gate electrode 108. Specifically, first, a silicon oxide film is deposited on the entire surface of the substrate so as to cover the gate electrode 108 by, for example, a CVD method, and then the silicon oxide film is etched back to thereby insulate both sides of the gate electrode 108. Sidewall spacers 109 are formed. Next, by performing ion implantation using the insulating sidewall spacer 109 and the gate electrode 108 as a mask, an extension region is formed on the surface portion of the semiconductor substrate 101 positioned outside the insulating sidewall spacer 109 as viewed from the gate electrode 108. After the source / drain region 105 having a junction deeper than 104 is formed, an annealing process is performed to activate the implanted impurity ions. In the case of forming the source / drain region 105 of the n-type MISFET, ion implantation of an n-type impurity such as arsenic or phosphorus is performed. Further, when forming the source / drain region 105 of the p-type MISFET, ion implantation of a p-type impurity such as boron is performed.

  The method of manufacturing the semiconductor device according to the present embodiment described above is characterized in that the second conductive portion 108B is formed after the formation of the first conductive portion 108A of the gate electrode 108. The effect is produced. That is, after the conductive film 170 to be the first conductive portion 108A of the gate electrode 108 is formed on the gate insulating film (high dielectric constant film 107) and the conductive film 170 is patterned to form the first conductive portion 108A. A polysilicon film 171 having a work function different from that of the first conductive portion 108A is formed so as to cover the first conductive portion 108A, and the polysilicon film 171 is etched to thereby form the second conductive portion 108B. Is forming. The gate electrode 108 thus formed includes a first conductive portion 108A located at the center of the gate electrode 108 in the channel length direction and having a first work function, and both ends of the gate electrode 108 in the channel length direction. And a second conductive portion 108B having a second work function different from the first work function. Therefore, the same effect as that of the semiconductor device of the first embodiment shown in FIG. 1, that is, GIDL is reduced by selectively reducing the strength of the electric field generated in the vertical direction due to the gate voltage in the overlap region A. The effect that it can reduce is acquired.

(Modification of the third embodiment)
Hereinafter, a semiconductor device according to a modification of the third embodiment of the present invention will be described with an n-type MISFET as an example with reference to the drawings.

  FIG. 19 is a cross-sectional view showing a structure of a semiconductor device according to a modification of the third embodiment. In FIG. 19, the same components as those of the first embodiment shown in FIG. 1 or the third embodiment shown in FIG.

  As shown in FIG. 19, the semiconductor device according to this modification is different from the first embodiment shown in FIG. 1 as follows. That is, in the first embodiment, the first conductive portion 108A located at the center portion of the gate electrode 108 in the channel length direction is replaced by the second conductive portion 108B located at both ends of the gate electrode 108 in the channel length direction. It was formed to be sandwiched. In other words, the first conductive portion 108A is formed over the entire central portion of the gate electrode 108 (from the upper surface to the lower surface of the gate electrode 108). In contrast, in the present embodiment, the first conductive portion 108A located at the center of the gate electrode 108 in the channel length direction is formed so as to be in contact with the high dielectric constant film 107, that is, the gate insulating film. As in the first embodiment, the first conductive portion 108A is not formed on the gate electrode 108, and the second conductive portion 108B is formed so as to straddle the first conductive portion 108A. This is different from the first embodiment.

  That is, the effect of the present invention described in the first embodiment is that if the first conductive portion 108A at the center of the gate electrode and the second conductive portion 108B at the end of the gate electrode are in contact with the gate insulating film, It is obtained, and it does not matter how each conductive portion is formed above the gate electrode.

  Further, the semiconductor device according to this modification is different from the third embodiment shown in FIG. 16 as follows. That is, in the third embodiment, the first conductive portion 108A is made of a single material (for example, metal) having a single work function, whereas in the present modification, the first conductive portion 108A is made of the first conductive portion 108A. The portion 108A has a stacked structure of a lower metal-containing layer 111 (in contact with the high dielectric constant film 107, that is, the gate insulating film) and an upper silicon layer 112.

  In addition, in the semiconductor device according to this modification example, as shown in FIG. 19, unlike the first or third embodiment, silicide layers 113 are formed on the surface portions of the gate electrode 108 and the source / drain regions 105, respectively. Has been.

  Hereinafter, an example of a method for manufacturing the semiconductor device of the present modification shown in FIG. 19 will be described. FIGS. 20A to 20C and FIGS. 21A to 21C are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the present modification.

  First, as shown in FIG. 20A, for example, a well region 102 is formed on a semiconductor substrate 101 such as a silicon substrate using an ion implantation method, and then a channel region 103 is formed on the surface portion of the semiconductor substrate 101 using ion implantation. Form. When the well region 102 and the channel region 103 of the n-type MISFET are formed, ion implantation of a p-type impurity such as boron is performed. Further, when the well region 102 and the channel region 103 of the p-type MISFET are formed, ion implantation of an n-type impurity such as phosphorus is performed.

Next, as shown in FIG. 20B, an insulating interface layer 106 made of a silicon oxide film having a thickness of 0.1 to 5.0 nm is formed on the semiconductor substrate 101 by, for example, a thermal oxidation method. A high dielectric constant film 107 made of, for example, an HfO ₂ film is formed on the conductive interface layer 106. The HfO ₂ film is formed by, for example, a CVD method using HfCl ₂ and NH ₃ or a CVD method using an organic Hf gas. Alternatively, the HfO ₂ film may be formed by forming a hafnium nitride film by sputtering using a hafnium nitride target and then oxidizing the hafnium nitride film. Thereafter, a metal-containing layer 111 having a thickness of, for example, about 10 to 50 nm is formed on the high dielectric constant film 107 and becomes a part of the first conductive portion 108A of the gate electrode 108 shown in FIG. Here, as a material of the metal-containing layer 111, a pure metal, an alloy, a metal compound, or the like can be used. Specifically, for example, when an n-type MISFET is formed as the metal-containing layer 111 by sputtering, a TiN film, a Mo film, a MoSiN film, a Ta film, a W film, a LaO film, or the like is formed, and a p-type MISFET is formed. When forming the film, a TiN film, MoSiN film, RuO ₂ film, Ta film, TaN film, TaC film, W film, PtW film, Pt film, or the like is formed. Subsequently, on the metal-containing layer 111, a silicon layer 112 having a thickness of up to about 200 nm, which becomes a part of the first conductive portion 108A of the gate electrode 108 shown in FIG. 19, is deposited using, for example, a CVD method. Here, as a material of the silicon layer 112, either polysilicon or amorphous silicon may be used.

Next, as shown in FIG. 20C, the silicon layer 112 and the metal-containing layer 111 are formed using a resist pattern (not shown) formed so as to cover the formation region of the first conductive portion 108 </ b> A by lithography. Then, dry etching is performed to form a first conductive portion 108A including the metal-containing layer 111 and the silicon layer 112. At this time, instead of the resist pattern, an SiO ₂ film or a silicon nitride film may be used as a mask. Subsequently, as shown in FIG. 21A, the thickness of the second conductive portion 108B of the gate electrode 108 shown in FIG. 19 is about 50 to 200 nm on the entire surface of the substrate so as to cover the first conductive portion 108A. The polysilicon film 181 is deposited by, eg, CVD. Here, when the n-type MISFET is formed, the polysilicon film 181 is doped with an n-type impurity, and when the p-type MISFET is formed, the polysilicon film 181 is doped with a p-type impurity. At this time, the first conductive portion 108 A made of the silicon layer 112 is also doped with the same impurity as the impurity doped in the polysilicon film 181. Further, an amorphous silicon film may be formed instead of the polysilicon film 181.

Next, as shown in FIG. 21B, dry etching is performed on the polysilicon film 181 using a resist pattern (not shown) formed so as to cover the gate electrode formation region by the lithography technique as a mask. A second conductive portion 108B made of a polysilicon film 181 is formed so as to cover the first conductive portion 108A. Thereby, the gate electrode 108 including the first conductive portion 108A and the second conductive portion 108B is formed. At this time, the high dielectric constant film 107 and the insulating interface layer 106 outside the gate electrode 108 may be removed. Further, instead of the resist pattern, an SiO ₂ film or a silicon nitride film may be used as a mask.

  Next, as shown in FIG. 21C, extension regions 104 are formed in the surface portions of the semiconductor substrate 101 on both sides of the gate electrode 108 by performing ion implantation using the gate electrode 108 as a mask. When the extension region 104 of the n-type MISFET is formed, ion implantation of an n-type impurity such as arsenic or phosphorus is performed. Further, when the extension region 104 of the p-type MISFET is formed, ion implantation of a p-type impurity such as boron is performed. A part of the extension region 104 is formed so as to overlap with both ends of the gate electrode 108 in the channel length direction in the region A (hereinafter referred to as the overlap region A).

  Next, in order to obtain the structure shown in FIG. 19, insulating sidewall spacers 109 are formed on both side surfaces of the gate electrode 108. Specifically, first, a silicon oxide film is deposited on the entire surface of the substrate so as to cover the gate electrode 108 by, for example, a CVD method, and then the silicon oxide film is etched back to thereby insulate both sides of the gate electrode 108. Sidewall spacers 109 are formed. Next, by performing ion implantation using the insulating sidewall spacer 109 and the gate electrode 108 as a mask, an extension region is formed on the surface portion of the semiconductor substrate 101 positioned outside the insulating sidewall spacer 109 as viewed from the gate electrode 108. After the source / drain region 105 having a junction deeper than 104 is formed, an annealing process is performed to activate the implanted impurity ions. In the case of forming the source / drain region 105 of the n-type MISFET, ion implantation of an n-type impurity such as arsenic or phosphorus is performed. Further, when forming the source / drain region 105 of the p-type MISFET, ion implantation of a p-type impurity such as boron is performed.

  Finally, silicide layers 113 are formed on the surface portions of the gate electrode 108 and the source / drain regions 105 (portions not covered by the insulating sidewall spacers 109). In forming the silicide layer 113, first, a metal film made of, for example, nickel, cobalt, or platinum is formed on the entire surface of the substrate so as to cover the gate electrode 108 and the source / drain region 105. Subsequently, the silicide layer 113 is formed by reacting silicon and the metal film constituting the surface portions of the gate electrode 108 and the source / drain region 105 by performing heat treatment. Thereafter, the unreacted metal film is removed.

  The manufacturing method of the semiconductor device according to this modification described above is characterized in that the second conductive portion 108B is formed after the formation of the first conductive portion 108A of the gate electrode 108. The effect is produced. That is, a metal-containing layer 111 and a silicon layer 112 to be the first conductive portion 108A of the gate electrode 108 are formed on the gate insulating film (high dielectric constant film 107), and the metal-containing layer 111 and the silicon layer 112 are patterned. After forming the first conductive portion 108A, a polysilicon film 181 having a work function different from the work function of the first conductive portion 108A (more precisely, the metal-containing layer 111) is covered with the first conductive portion 108A. The second conductive portion 108B is formed by etching the polysilicon film 181. The gate electrode 108 thus formed includes a first conductive portion 108A located at the center of the gate electrode 108 in the channel length direction and having a first work function, and both ends of the gate electrode 108 in the channel length direction. And a second conductive portion 108B having a second work function different from the first work function. Therefore, the same effect as that of the semiconductor device of the first embodiment shown in FIG. 1, that is, GIDL is reduced by selectively reducing the strength of the electric field generated in the vertical direction due to the gate voltage in the overlap region A. The effect that it can reduce is acquired.

  The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, when the present invention is applied to the structure of a gate electrode of a MISFET, an effect of suppressing a leakage current is obtained and useful.

FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment of the present invention. 2A to 2C are views for explaining the effects obtained by the semiconductor device according to the first embodiment of the present invention. 3A and 3B are views for explaining the effects obtained by the semiconductor device according to the first embodiment of the present invention. 4A to 4C are views for explaining the effects obtained by the semiconductor device according to the first embodiment of the present invention. FIGS. 5A and 5B are diagrams for explaining the effects obtained by the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a diagram for explaining an effect obtained by the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a diagram showing the relationship between various work materials for the gate electrode that can be used in the semiconductor device according to the first embodiment of the present invention and the work function. 8A to 8C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 9A to 9C are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 10A to 10C are cross-sectional views illustrating respective steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 11 is a sectional view showing the structure of a semiconductor device according to a modification of the first embodiment of the present invention. FIG. 12 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the modification of the first embodiment of the present invention. FIG. 13 is a sectional view showing a structure of a semiconductor device according to the second embodiment of the present invention. 14A to 14C are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIGS. 15A to 15C are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 16 is a sectional view showing the structure of a semiconductor device according to the third embodiment of the present invention. 17A to 17C are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the third embodiment of the present invention. 18A to 18C are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the third embodiment of the present invention. FIG. 19 is a cross-sectional view showing a structure of a semiconductor device according to a modification of the third embodiment of the present invention. FIGS. 20A to 20C are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a modification of the third embodiment of the present invention. FIGS. 21A to 21C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the third embodiment of the present invention. FIG. 22 is a cross-sectional view showing a conventional semiconductor device. FIG. 23 is a cross-sectional view showing a conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 Well area | region 103 Channel area | region 104 Extension area | region 105 Source / drain area | region 106 Insulating interface layer 107 High dielectric constant film | membrane 108 Gate electrode 108A 1st electroconductive part 108B 2nd electroconductive part 109 Insulating side wall spacer 110 Interlayer Insulating film 111 Metal-containing layer 112 Silicon layer 113 Silicide layer 140 Conductive film 150 Dummy gate electrode 151 Polysilicon film 160 Conductive film 161 Polysilicon film 170 Conductive film 171 Polysilicon film 181 Polysilicon film

Claims (20)

A gate electrode formed on a semiconductor substrate via a gate insulating film;
An impurity region formed on both sides of the gate electrode in the surface portion of the semiconductor substrate,
The gate electrode is located at a center portion of the gate electrode in the channel length direction and is in contact with the gate insulating film; and at both ends of the gate electrode in the channel length direction and the gate insulation A second conductive portion in contact with the film,
A semiconductor device, wherein a first work function of the first conductive portion and a second work function of the second conductive portion are different. The semiconductor device according to claim 1,
Compared with the difference between the third work function of the impurity region and the first work function of the first conductive portion, the third work function of the impurity region and the second work function of the second conductive portion. 2. A semiconductor device characterized in that a difference from the work function of 2 is small. The semiconductor device according to claim 1 or 2,
The impurity region and the second conductive portion are each made of n-type silicon,
The semiconductor device, wherein the first conductive portion is made of a metal or a metal compound. The semiconductor device according to claim 3.
The semiconductor device, wherein the metal is Mo, Ta, or W. The semiconductor device according to claim 3.
The semiconductor device is characterized in that the metal compound is TiN, MoSiN, or LaO. The semiconductor device according to claim 1 or 2,
The impurity region and the second conductive portion are each made of p-type silicon,
The semiconductor device, wherein the first conductive portion is made of a metal or a metal compound. The semiconductor device according to claim 6.
The semiconductor device, wherein the metal is Ta, W, or Pt. The semiconductor device according to claim 6.
A semiconductor device, wherein the metal compound is TiN, MoSiN, RuO ₂ , TaN, TaC, or PtW. The semiconductor device according to claim 1,
The semiconductor device, wherein the impurity region is an extension region. The semiconductor device according to claim 9.
A part of the extension region overlaps with both ends of the gate electrode in the channel length direction, and both side surfaces of the gate insulating film are located on the extension region. The semiconductor device according to claim 9 or 10,
A semiconductor device comprising a source / drain region formed in a surface portion of the semiconductor substrate outside the extension region when viewed from the gate electrode. The semiconductor device according to any one of claims 9 to 11,
A semiconductor device comprising insulating sidewall spacers formed on both side surfaces of the gate electrode. The semiconductor device according to any one of claims 1 to 12,
The semiconductor device, wherein the gate insulating film includes a high dielectric constant film. The semiconductor device according to claim 13,
The semiconductor device, wherein the gate insulating film includes an insulating interface layer formed between the semiconductor substrate and the high dielectric constant film. The semiconductor device according to claim 1,
The semiconductor device, wherein the first conductive portion and the second conductive portion are electrically connected. The semiconductor device according to any one of claims 1 to 15,
The semiconductor device according to claim 1, wherein the first conductive portion is formed so as to ride on the second conductive portion. The semiconductor device according to any one of claims 1 to 15,
The semiconductor device, wherein the second conductive portion is formed so as to straddle the first conductive portion. The semiconductor device according to claim 1,
A side surface of the gate insulating film and a side surface of the gate electrode are flush with each other. A method for manufacturing the semiconductor device according to claim 1,
The gate electrode is formed by forming the second conductive portion on the wall surface of the concave portion formed using a dummy gate and then forming the first conductive portion so that the concave portion is filled. A method for manufacturing a semiconductor device. A method for manufacturing the semiconductor device according to claim 1,
After forming the first conductive part, a conductive film is formed so as to cover the first conductive part, and then the conductive film is etched back or patterned to form sidewalls of the first conductive part. A method for manufacturing a semiconductor device, wherein the gate electrode is formed by forming the second conductive portion.

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