JP2009198292A - Semiconductor testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing device capable of shortening a test time by shortening an overhead time generated by using a software. <P>SOLUTION: This semiconductor testing device for setting test condition data in a hardware and performing a test includes: a storage part for storing the test condition data; a selection output part for selecting the test condition data stored in the storage part, and outputting the data in each item; and a setting part for setting the test condition data output from the selection output part in the hardware. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus, and more particularly to a semiconductor test apparatus capable of reducing a test time by performing processing that has been performed by software with reconfigurable hardware.

  Semiconductor test equipment inputs a signal called a pattern to an IC (Integrated Circuit) or LSI (Large Scale Integration), which is a device under test (hereinafter referred to as DUT (Device Under Test)), and expects an output signal from the DUT The quality is determined by comparing with the value pattern.

  The test time in the semiconductor test apparatus affects the profit of the semiconductor manufacturer that manufactures the device to be tested. That is, in a limited time, the number of devices that can be tested decreases as the test time increases, and the number of devices that can be tested increases as the test time decreases. On the other hand, in order to detect a defective device, test items are not often cut, and it is often difficult to shorten the test time by deleting the test items.

  In such a situation, shortening the overhead time in the semiconductor test apparatus is effective for reducing the test time. Since various test items are performed in the semiconductor test, the hardware setting of the semiconductor test apparatus differs for each test item. The overhead time mainly refers to the time required for communication between hardware and hardware setting performed before each test.

  Prior art documents related to conventional semiconductor test equipment include the following.

JP 2004-069545 A

  FIG. 12 is a block diagram showing the configuration of such a conventional semiconductor test apparatus. A CPU (Central Processing Unit) 1 controls the pin electronics card 3 centrally by software. The hardware 2 is, for example, a DAC (Digital to Analog Converter) that supplies a voltage used by a driver, a comparator, or the like, or a TG (Timing Generator) that generates timing.

  In addition to the CPU 1 and the hardware 2, the pin electronics card 3 includes a driver that applies a pattern signal to the DUT 100, a comparator that compares an output signal from the DUT 100 with a preset threshold value, and the like.

  The test head 4 includes a plurality of pin electronics cards 3, a DC card (not shown), an I / F card (not shown) with the main body, and the like. A TSC (Tester Controller) 5 comprehensively controls the semiconductor test apparatus.

  The CPU 1 and TSC 5 of the pin electronics card 3 mounted in the test head 4 are connected via a cable or the like, and the driver and comparator of the pin electronics card 3 and the DUT 100 are connected via an I / F mechanism such as a probe card. . The test head 4 and the TSC 5 constitute a semiconductor test apparatus 50.

  The operation of the conventional example shown in FIG. 12 will be described with reference to FIGS. FIG. 13 is a configuration block diagram of the pin electronics card 3, and FIG. 14 is an explanatory diagram of command exchange and register setting between the TSC-CPU and hardware.

  In FIG. 13, the same reference numerals are given to portions common to FIG. 12. Although not shown in FIG. 12, the memory 6 is actually mounted on the pin electronics card 3. The CPU 1, hardware 2, and memory 6 are connected to the TSC 5 via the bus B, respectively.

  The pin electronics card 3 is controlled by software operating on the CPU 1. The software is loaded from the TSC 5 to the memory 6 of the pin electronics card 3 and expanded when the semiconductor test apparatus 50 is started.

  This will be specifically described with reference to FIG. In the example shown in FIG. 14, the case where test number # 100 and test number # 200 are executed is shown. First, when the test of test number # 100 starts, the TSC 5 transmits a plurality of commands to the CPU 1 of the pin electronics card 3. This command refers to an instruction for instructing the operation of the CPU 1 or test condition data set in the hardware 2.

  The CPU 1 receives a command from the TSC 5 and starts analyzing the command. In this command analysis, the control content of the received command is decoded, or if test condition data is added, the test condition data is extracted.

  When the CPU 1 finishes analyzing the command, the CPU 1 executes a control operation instructed by the command. In the example shown in FIG. 14, since the command received from the TSC 5 is a register setting instruction, the CPU 1 executes an operation of writing setting data in a designated register of the hardware 2.

  Then, the CPU 1 sequentially executes command analysis and register setting repeatedly. When the register setting of the hardware 2 is completed, the TSC 5 performs a test on the DUT 100 by controlling to start pattern running. The test number # 200 is processed in the same manner as the test number # 100.

In the conventional example shown in FIG. 14, since the command is exchanged between the TSC 5 and the CPU 1 and the setting process from the CPU 1 to the hardware 2 is performed by software for each test item, the ratio of these overhead times to the entire test time There was a problem that was large.
Therefore, the problem to be solved by the present invention is to realize a semiconductor test apparatus capable of reducing the test time by reducing the overhead time generated by using software.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In semiconductor test equipment that tests by setting test condition data in hardware,
A storage unit for storing the test condition data, a selection output unit for selecting the test condition data stored in the storage unit and outputting the selected item for each item, and the test condition data output from the selection output unit. And a setting unit for setting the hardware.

The invention according to claim 2
The semiconductor test apparatus according to claim 1,
The test condition data is
Each test is stored separately in the storage unit.

The invention described in claim 3
The semiconductor test apparatus according to claim 1 or 2,
The selection output unit or the setting unit is
The rewritable PLD is characterized in that a circuit can be reconstructed for each test program.

The invention according to claim 4
In semiconductor test equipment that tests by setting test condition data in hardware,
A first storage unit storing the test condition data including a variable; a second storage unit storing numerical data corresponding to the variable; and test condition data including the variable using the numerical data. A calculation unit that calculates, a selection output unit that selects from the test condition data stored in the first storage unit and the test condition data calculated from the calculation unit and outputs the selected item, and the selection output unit And a setting unit for setting the test condition data output from the hardware to the hardware.

The invention according to claim 5
The semiconductor test apparatus according to claim 4,
The test condition data is
Each test is stored separately in the first storage unit.

The invention described in claim 6
The semiconductor test apparatus according to claim 4 or 5,
The numerical data is
Each test is stored separately in the second storage unit.

The invention described in claim 7
The semiconductor test apparatus according to any one of claims 4 to 6,
The second storage unit is
The numerical data can be rewritten during the execution of the test.

The invention described in claim 8
The semiconductor test apparatus according to any one of claims 4 to 7,
The calculation unit, the selection output unit or the setting unit is
The rewritable PLD is characterized in that a circuit can be reconstructed for each test program.

The present invention has the following effects.
According to the first to third aspects of the present invention, in the semiconductor test apparatus for performing the test by setting the test condition data in hardware, the test condition data is stored, and the test condition data is stored in the storage unit. The hardware includes a selection output unit that selects and outputs the test condition data for each item, and a setting unit that sets the test condition data output from the selection output unit in the hardware. Since processing such as setting is performed, overhead time generated by using software is shortened, and test time can be shortened.

  According to the first to third aspects of the present invention, in a semiconductor test apparatus that performs a test by setting test condition data in hardware, the first storage unit that stores the test condition data including a variable; and A second storage unit for storing numerical data corresponding to the variable; an arithmetic unit for calculating test condition data including the variable using the numerical data; and the test condition stored in the first storage unit A selection output unit for selecting data and the test condition data calculated from the calculation unit and outputting the selected item for each item; and a setting unit for setting the test condition data output from the selection output unit in the hardware. Since the hardware performs processing such as register setting, the overhead time generated by using the software is reduced and the test time is reduced. Door is possible. Further, even when there is test condition data including a variable, the processing up to the determination of the variable is executed by hardware, so that the overhead time is shortened and the test time can be shortened.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a semiconductor test apparatus according to the present invention. Components common to those in FIG.

  In FIG. 1, an FPGA (Field Programmable Gate Array) 11 performs setting of the hardware 2 under the control of the TSC 5. In addition to the FPGA 11 and the hardware 2, the pin electronics card 13 includes a driver that applies a pattern signal to the DUT 100, a comparator that compares an output signal from the DUT 100 with a preset threshold value, and the like.

  The test head 14 includes a plurality of pin electronics cards 13, a DC card (not shown), an I / F card (not shown) with the main body, and the like.

  The FPGA 11 and TSC 5 of the pin electronics card 13 mounted in the test head 14 are connected via a cable or the like, and the driver and comparator of the pin electronics card 13 and the DUT 100 are connected via an I / F mechanism such as a probe card. . The test head 14 and the TSC 5 constitute a semiconductor test apparatus 51.

  FIG. 2 is a block diagram showing the configuration of the pin electronics card 13, and the same reference numerals are given to portions common to FIG. 13.

  The bus I / F 15 is a circuit that controls the exchange of data with the TSC 5, and the CPU 16 controls the pin electronics card 13 in a centralized manner as with the CPU 1 shown in FIG. A user-defined block (User Configurable Block: hereinafter referred to as UCB) 17 is a rewritable circuit, such as ROM (Read Only Memory), RAM (Random Access Memory), or flash memory (electrically rewritable ROM). Memory is also included.

  A specific method of using the UCB 17 will be described with reference to FIGS. 3 is an explanatory diagram showing test condition setting information of the test program, FIG. 4 is an explanatory diagram showing a setting framework, FIG. 5 is an explanatory diagram showing test condition data, and FIG. 6 is a block diagram of the UCB 17.

  The test condition setting information is setting items for hardware such as a driver output voltage, a comparator comparison voltage, and an active load output current set when testing the DUT 100, and numerical data (setting values) to be set.

  The semiconductor test apparatus performs a test according to a test program written by a user. The user describes test condition setting information as shown in FIG. 3 in the test program. In FIG. 3, the item “PIN #” represents the pin number of the DUT 100, and “VIH” and “VIL” of the item “IN” represent the high level and the low level of the signal input to the DUT 100, respectively.

  Also, “VOH” and “VOL” of the item “OUT” represent the high level and low level of the comparison voltage when the signals output from the DUT 100 are compared by the comparator, respectively. The items “ALD” “IOH” and “IOL” are active load settings, and represent the load current when the output signal from the DUT 100 is high level and the load current when the output signal is low level. Similarly, “COM” in the item “ALD” represents a threshold voltage (Commutative Voltage) for switching the load current.

  Furthermore, the item “WAVE FMT” represents the waveform format of the signal applied to the DUT 100, and the item “IO FMT” represents the input / output switching format of the input / output pins of the semiconductor test apparatus. The item “FMASK” represents the setting of a fail mask.

  FIG. 4 shows a setting framework in which only the test condition setting information items shown in FIG. 3 are extracted. FIG. 5 shows test condition data obtained by extracting only numerical data of the test condition setting information shown in FIG.

  The internal memory 20 is connected to the data control unit 22 via the memory I / F 21, and the data control unit 22 is connected to the selection output unit 23. The plurality of outputs of the selection output unit 23 are connected to the bus I / F 24, respectively.

  FIG. 6 shows a block diagram of the UCB 17 using the setting framework and test condition data. The test condition data is stored in the internal memory (storage unit) 20, and items shown in the setting framework are output from the selection output unit 23. The data control unit 22 selects from test condition data stored in the internal memory 20 via the memory I / F 21 according to a selection signal from the TSC 5 or the CPU 11, and writes it to the selection output unit 23. The bus I / F (setting unit) 24 sets the test condition data input from the selection output unit 23 in the hardware 2.

  The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 7 is a flowchart from test program creation to test execution. In "S001" in FIG. 7, the user who uses the semiconductor test apparatus 51 describes a test program. In “S002” in FIG. 7, the TSC 5 compiles this test program. In this compilation, a conventional software program for operating the semiconductor test apparatus 51 and configuration information for constructing the circuit of the FPGA 11 are generated.

  In “S003” in FIG. 7, the TSC 5 loads the generated configuration information into the FPGA 11. Then, in “S004” in FIG. 7, the user uses the semiconductor test apparatus 51 to execute the test.

  The present invention will be specifically described with reference to FIGS. FIG. 8 is a configuration block diagram of the UCB 17, and FIG. 9 is an explanatory diagram of command exchange and register setting between the TSC-FPGA-hardware.

  In an actual test, there are a number of test items, and test condition setting information as shown in FIG. 3 exists for each test item. For example, when test items are distinguished by test numbers, test condition data is stored in the internal memory of the UCB 17 for each test number as shown in FIG. Test condition data of test number # 100 is stored in the internal memory 20a, and test condition data of test number # 200 is stored in the internal memory 20b. Similarly, the test condition data of test number # 300 is stored in the internal memory 20c, and the test condition data of test number # 400 is stored in the internal memory 20d.

  In addition, a plurality of setting frameworks are prepared. In the example of FIG. 8, there are two selection output units: a selection output unit 23 a that outputs test setting items of the same type as the test # 100 and a selection output unit 23 b that outputs test setting items different from the test # 100. It is prepared.

  When the number of test categories increases, the selection output section of the setting framework increases accordingly. A category refers to a rough classification for each test item. For example, the function test is classified as category “A”, the DC characteristic test is classified as category “B”, and the AC characteristic test is classified as category “C”. The category is used for improvement in productivity improvement, problem analysis in the design of defective devices, and the like.

  For example, the test category of test number # 100 is “A”, the test category of test number # 200 is “A”, the test category of test number # 300 is “B”, and the test category of test number # 400 is “C”. Assume that the selection output unit 23a of the setting framework is for test condition data of category "A" and the selection output unit 23b of the setting framework is for test condition data of category "B".

  In this case, the number of selection output units for test condition data of category “C” is newly increased. In this way, a setting framework selection output unit is prepared according to the number of test categories. Further, although it is the same function test, a different setting framework may be provided with “A ′” as a category that is partially different from the category “A”. Similarly, another setting framework may be provided for the category “B” and the category “C”.

  The FPGA 11 reduces the number of times that the TSC 5 transmits test condition data and a command for setting to the pin electronics card 13 and dramatically reduces the communication between the TSC and the FPGA. Furthermore, since command analysis and register setting from the CPU, which have been performed by software, are performed by the FPGA 11 which is hardware, these setting processes become very fast.

  A specific estimate of the overhead time reduction according to the present invention is as follows. In the case where all processing is performed by software as usual, it takes at least several μs to several hundreds μs in order to set one data to the hardware. According to the present invention, the clock frequency of the FPGA 11, that is, several tens ns to several hundred ns can be processed.

  As shown in FIG. 9, the TSC 5 transmits a command instructing test execution to which the test number is added to the FPGA 11. Upon receiving this command, the FPGA 11 reads the test condition setting information stored in the internal memory 20 and sets it in the hardware 2 via the selection output unit 23 and the bus I / F 24. After setting the hardware 2 registers, the pattern is run to execute the test.

  The example shown in FIG. 9 shows a case where two tests, test # 100 and test # 200, are executed. In each test, the command transmitted from the TSC 5 to the FPGA 11 is only a test execution instruction, and between TSC and FPGA. The time required for communication is significantly shortened compared to the prior art.

  As a result, the FPGA 11 performs processing such as register setting, which has been conventionally performed by software, so that test condition analysis processing is eliminated, and hardware performs processing such as register setting. Therefore, overhead time generated by using software This shortens the test time.

  Next, an embodiment in which variables are used in the test condition data will be described with reference to FIGS. FIG. 10 is an explanatory diagram showing test condition setting information including variables, and FIG. 11 is a block diagram of the UCB corresponding to the test conditions including variables.

  In an actual test, all test condition data may not be finalized when the test program is loaded. That is, when the test condition data is defined by variables, the test condition data dynamically changes during the test.

  FIG. 10 shows test condition setting information when the test condition data is defined by variables. In FIG. 10, the test condition data defined using the variable is represented by an underline. The VIH of PIN # 1 is defined by the variable “AAA” and VIL is defined by the variable “BBB”. Further, VIH of PIN # 3 is defined by multiplication of a variable “1.650V” and “MIN”, and VIL is defined by multiplication of a variable “0.750V” and “MIN”.

  PIN # 2 VOH and VOL are defined by adding "CCC" to "0.600V". In this way, the test condition data may be defined as a single variable, or the test condition data may be defined using an arithmetic expression such as multiplication of a constant and a variable or addition of a constant and a variable. .

  An embodiment of the present invention in the case of having test condition data including variables will be specifically described with reference to FIG. Portions common to FIG. 6 are denoted by the same reference numerals. The internal memory 20 and the variable memory 25 are respectively connected to the calculation unit 27 via the memory I / F 26, and the calculation unit 27 is connected to the data control unit 22. The other connections are the same as in the embodiment shown in FIG.

  The internal memory 20 stores test condition data including variables, and the variable memory 25 stores numerical data corresponding to each variable. The memory I / F 26 controls writing to and reading from the internal memory 20 and the variable memory 25. The calculation unit 27 performs calculations such as multiplication or addition. The internal memory 20, the data control unit 22, the selection output unit 23, the bus I / F 24, the variable memory 25, the memory I / F 26, and the calculation unit 27 constitute a UCB 28.

  The operation of UCB 28 will be described below. Compiling the test program and loading the configuration information into the FPGA 11 is the same as the embodiment shown in FIG. At this time, test condition data including variables is loaded into the internal memory 20, and numerical data corresponding to each variable is loaded into the variable memory 25.

  When the test is started, test condition data including a variable is read from the internal memory 20 and numerical data corresponding to each variable is read from the variable memory 25 via the memory I / F 21. Test condition data including variables and numerical data corresponding to each variable are input to the calculation unit 26 via the memory I / F 21.

  Then, the arithmetic unit 26 substitutes numerical data for the variable, or in the case of test condition data including an operation such as multiplication or addition, the operation is executed to determine the test condition data. The test condition data determined by the calculation unit 26 is input to the data control unit 22 and set in the hardware 2 as in the embodiment shown in FIG. If the value of the variable changes during the test, the corresponding numerical data in the variable memory 25 is rewritten each time the value changes.

  As a result, the FPGA 11 performs processing such as register setting, which has been conventionally performed by software, so that test condition analysis processing is eliminated, and hardware performs processing such as register setting. Therefore, overhead time generated by using software This shortens the test time. Furthermore, even when there is test condition data including a variable, numerical data corresponding to each variable is stored in the variable memory 25, and the test condition data is determined by substituting or calculating by the calculation unit 27, thereby determining the variable. Since the processes up to the above are executed by hardware, the overhead time is shortened and the test time can be shortened.

  In the embodiment shown in FIG. 1, the FPGA 11 is used. However, the FPGA 11 is not necessarily limited to the FPGA, and a PLD (Programmable Logic Device) similar to the FPGA may be used.

  In the embodiment shown in FIG. 11, the internal memory 20 and the variable memory 25 are separated. However, it is not always necessary to do this, and the internal memory 20 and the variable memory 25 may be configured by one memory. Good.

1 is a configuration block diagram showing an embodiment of a semiconductor test apparatus according to the present invention. It is a block diagram of the configuration of the pin electronics card. It is explanatory drawing which shows the test condition setting information of a test program. It is explanatory drawing which shows a setting framework. It is explanatory drawing which shows test condition data. It is a configuration block diagram of UCB. It is a flowchart from test program creation to test execution. It is a configuration block diagram of UCB. It is explanatory drawing of transmission / reception of a command between TSC-FPGA-hardware, and a register setting. It is explanatory drawing which shows the test condition setting information containing a variable. It is a block diagram of UCB corresponding to test conditions including variables. It is a block diagram showing a conventional semiconductor test apparatus. It is a block diagram of the configuration of the pin electronics card. It is explanatory drawing of transfer of the command between TSC-CPU-hardware, and a register setting.

Explanation of symbols

1,16 CPU
2 Hardware 3,13 pin electronics card 4,14 Test head 5 TSC
6 Memory 11 FPGA
15, 24 Bus I / F
17, 28 User-defined block 20, 20a, 20b, 20c, 20d Internal memory 21, 26 Memory I / F
22 Data control unit 23, 23a, 23b Selection output unit 25 Variable memory 27 Calculation unit 50, 51 Semiconductor test apparatus 100 DUT

Claims (8)

In semiconductor test equipment that tests by setting test condition data in hardware,
A storage unit for storing the test condition data;
A selection output unit that selects the test condition data stored in the storage unit and outputs the selected test condition data;
A semiconductor test apparatus comprising: a setting unit configured to set the test condition data output from the selection output unit in the hardware. The test condition data is
The semiconductor test apparatus according to claim 1, wherein each of the tests is stored in the storage unit. The selection output unit or the setting unit is
3. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is a rewritable PLD, and a circuit can be reconstructed for each test program. In semiconductor test equipment that tests by setting test condition data in hardware,
A first storage unit for storing the test condition data including variables;
A second storage unit for storing numerical data corresponding to the variables;
A calculation unit for calculating test condition data including the variable using the numerical data;
A selection output unit that selects from the test condition data stored in the first storage unit and the test condition data calculated from the calculation unit and outputs the selected item for each item;
A semiconductor test apparatus comprising: a setting unit configured to set the test condition data output from the selection output unit in the hardware. The test condition data is
The semiconductor test apparatus according to claim 4, wherein the semiconductor test apparatus is stored in the first storage unit separately for each test. The numerical data is
6. The semiconductor test apparatus according to claim 4, wherein the semiconductor test apparatus is stored in the second storage unit separately for each test. The second storage unit is
The semiconductor test apparatus according to claim 4, wherein the numerical data can be rewritten during a test execution. The calculation unit, the selection output unit or the setting unit is
8. The semiconductor test apparatus according to claim 4, wherein the semiconductor test apparatus is a rewritable PLD, and a circuit can be reconstructed for each test program.

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