JP2009192240A - Tester and its transmission method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a tester of enhanced performance and its transmission method. <P>SOLUTION: This tester is for serially transferring fail/mask information and summary/status information to a fail control card 130, the summary/status information comprising summary information and status information. This tester is characterized by being equipped with a FIFO memory 2 with the fail/mask information stored therein, a selector 8 for selecting either data outputted from the FIFO memory 2 or the summary/status information according to the number of data stored in the FIFO memory 2, and a first serial I/F circuit 3 for serially transferring an output of the selector 8. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to improving the performance of a test apparatus such as a semiconductor test apparatus.

  A semiconductor test apparatus such as an IC tester gives various test patterns to a device under test (hereinafter referred to as a DUT), and determines pass / fail by the output of the DUT. Serial transfer is used to process this determination result and past summary information by the control card. In this case, high-speed serial transmission can transmit signals at high speed, but since only a bit width corresponding to a signal that requires real-time performance can be prepared due to the circuit configuration, a pin electronics card (hereinafter referred to as a PE card). The total bit width that can be transferred per clock is small. For this reason, since high-speed serial transmission cannot be used for transfer of fail / mask summary information and PE card status, low-speed serial transmission is used.

FIG. 5 is a block diagram showing the configuration of a conventional semiconductor test apparatus.
In FIG. 5, the PE card 20 outputs a test pattern to the DUT 10 and determines whether the DUT 10 is good or bad based on the pattern output from the DUT 10. Fail / mask information, which is a determination result, is output from the PE card 20 to the fail control card 30 via the high-speed serial transmission path 6, and summary information on the past fail / mask information and status information of the PE card 20 are received from the PE card 20. The data is output to the fail control card 30 via the low-speed serial transmission path 7. The fail control card 30 processes these pieces of information.

In the PE card 20, the fail / mask determination circuit 1 compares the pattern output from the DUT 10 with an expected value to determine whether the DUT 10 is good or bad, and also applies a test pattern and a dummy signal applied to the DUT 10 (no processing is performed). From the signal indicating the cycle (hereinafter referred to as a dummy), mask information indicating whether or not the DUT 10 is a determination target is generated. Here, mask information for all DUTs to be tested is generated by the dummy signal, and mask information for each DUT is generated by the test pattern.

A FIFO memory (hereinafter referred to as a FIFO) 2 is a fail signal that is input when a rate signal (hereinafter referred to as a rate) that defines the operation timing of the PE card 20 is input to a WE (WRITE enable) terminal and the rate is “1”. Stores fail / mask information from the mask determination circuit 1.
The fail / mask summary circuit 4 stores the fail / mask information from the fail / mask determination circuit 1, and generates fail / mask summary information based on the past fail / mask information.

A high-speed serial interface circuit (hereinafter referred to as a high-speed serial IF circuit) 3 reads out according to the number of data stored in the FIFO 2, converts the parallel signal into a serial signal, and passes through the high-speed serial transmission path 6. Output to the fail control card 30.

The low-speed serial IF circuit 5 converts the fail / mask summary information and the status signal (hereinafter referred to as status) of the PE card 20 output from the fail / mask summary circuit 4 from a parallel signal into a serial signal, and transmits a low-speed serial transmission line. 7 to the fail control card 30.

Next, the operation of the semiconductor test apparatus of FIG. 5 will be described using the time chart of FIG.
(1) The PE card 20 applies a test pattern to the DUT 10.
(2) The pattern output from the DUT 10 is compared with an expected value by the fail / mask determination circuit 1 to determine whether the DUT 10 is good or bad (good is called “pass” and bad is called “fail”). Further, mask information indicating whether or not the DUT 10 is a determination target is generated from the test pattern applied to the DUT 10 and a dummy (FIG. 6C). Here, the fail / mask information when the dummy is “1” is referred to as dummy data.
(3) The fail / mask information of the DUT 10 generated in the above (2) is input to the FIFO 2 and fail / mask summary circuit 4 on the PE card 20.
(4) The fail / mask information (FIG. 6 (d)) from the fail / mask determination circuit 1 is the FIFO when the rate (FIG. 6 (b)) that defines the operation timing of the PE card 20 is “1”. 2 is stored.

(5) The high-speed serial IF circuit 3 processes and outputs two pieces of data or control codes according to the number of data stored in the FIFO 2 as follows (FIG. 6 (d) (e) ).
(5-1) When the number of data is less than two (5-1-1) Data is not read from the FIFO 2, and a control code indicating “idle (first half)” is transmitted to the fail control card 30.
(5-1-2) A control code indicating “idle (second half)” is output.
(5-1-3) The number of FIFO 2 data is determined. If the number of data is less than 2, the process returns to (5-1-1). If there are two or more, proceed to (5-2-1) below.
(5-2) When the Number of Data is Two or More (5-2-1) One piece of data is read from the FIFO 2, converted into a serial signal, and transmitted to the fail control card 30.
(5-2-2) One data is read again from the FIFO 2, converted into a serial signal, and transmitted to the fail control card 30.
(5-2-3) The number of data in FIFO 2 is determined. If the number of data is less than 2, return to (5-1-1), and if it is two or more, return to (5-2-1).

(6) The fail / mask information from the fail / mask determination circuit 1 is stored in the fail / mask summary circuit 4, and summary information of the fail and mask is generated based on the past fail / mask information.
(7) The fail / mask summary information and the status of the PE card 20 are converted into a serial signal by the low-speed serial IF circuit 5 and transmitted to the fail control card 30.
(8) Fail / mask information for high-speed serial transmission, summary information for fail / mask for low-speed serial transmission, and status of the PE card 20 are processed by the fail control card 30.

  Prior art documents related to semiconductor test equipment include the following.

JP 2003-167031 A

  With the conventional semiconductor test equipment configuration, the transfer speed of low-speed serial transmission is slower than that of high-speed serial transmission, so it takes time to transfer fail / mask summary information and PE card status, which affects the performance of the semiconductor test equipment. There was a problem of affecting.

  The present invention is intended to solve such problems, and an object thereof is to provide a test apparatus with improved performance.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
FIFO information storing fail information based on a comparison result between an output of a DUT to which a test pattern is applied and an expected value, and fail / mask information of the test pattern and mask information generated from a dummy signal, and the fail A test apparatus for serially transferring the fail / mask information of the FIFO memory and the summary information of the fail / mask summary circuit.
A selector that selects either the data output from the FIFO memory or the summary information according to the number of data stored in the FIFO memory;
And a first serial I / F circuit for serially transferring the output of the selector.

The invention according to claim 2
The test apparatus according to claim 1,
The first serial I / F circuit includes:
When the number of data stored in the FIFO memory is N or more, N data is transmitted,
When the number of data stored in the FIFO memory is less than N, M summary information is transmitted following an idle control signal. (However, N and M are positive integers.)

The invention described in claim 3
The test apparatus according to claim 1,
The FIFO memory stores a dummy signal corresponding to the fail / mask information,
The selector selects either the data output from the FIFO memory or the summary information according to the number of data stored in the FIFO memory and a dummy signal,
And a second serial I / F circuit that outputs the data, dummy data, or invalid data in accordance with data or control signals received by serial transmission from the first serial I / F circuit. .

The invention according to claim 4
The test apparatus according to claim 3, wherein
The first serial I / F circuit includes:
When the number of data stored in the FIFO memory is less than N, the M summary information is transmitted following the idle control signal,
When the number of data stored in the FIFO memory is N or more and N pieces of dummy data are consecutive from the top, the L summary information is transmitted following the dummy control signal,
When the number of data stored in the FIFO memory is N or more and any of the N data from the beginning is not dummy data, the N data is transmitted,
The second serial I / F circuit includes:
When the idle control signal is received, the next M data are processed as the summary information and M + 1 invalid data are generated and output,
When the dummy control signal is received, the next L data are processed as the summary information and N dummy data are generated and output,
When the data is received, the data is output. (N, M, and L are positive integers)

The invention according to claim 5
The test apparatus according to any one of claims 1 to 4,
A fail / mask determination circuit is provided that performs pass / fail judgment based on a comparison result between an output of the DUT and an expected value, generates mask information from a test pattern and a dummy signal, and outputs the fail / mask information to the FIFO memory. ,
The fail / mask summary circuit generates summary information from the past fail / mask information and outputs the summary information to the selector.

The invention described in claim 6
The test apparatus according to claim 2 or 4,
N is 2, M and L are 1.

The invention described in claim 7
The test apparatus according to any one of claims 1 to 5,
Status information is used together with the summary information or instead of the summary information.

The invention described in claim 8
The test apparatus according to any one of claims 1 to 7,
The serial transfer is performed between the pin electronics card and the file control card.

The invention according to claim 9
In the transmission method of the test apparatus in which real-time information based on the test result of the device under test and batch information are serially transmitted in parallel,
The batch information is serially transferred using unnecessary cycles included in the serial transmission of the real-time information.

The invention according to claim 10 is:
The transmission method of the test apparatus according to claim 9.
The real-time information consists of fail information based on a comparison result between an output of a device under test to which a test pattern is applied and an expected value, and fail / mask information including mask information generated from the test pattern and a dummy signal. ,
The batch information includes at least one of summary information of fail / mask information and status information,
The unnecessary cycle is configured by at least one of an idle cycle and a dummy cycle.

  As is apparent from the above description, according to the present invention, fail information based on a comparison result between an output of a DUT to which a test pattern is applied and an expected value, and mask information generated from the test pattern and a dummy signal. And a fail / mask summary circuit for generating summary information of the fail / mask information, and the fail / mask information and the fail / mask of the FIFO memory. In a test apparatus that serially transfers the summary information of the summary circuit, a selector that selects either the data output from the FIFO memory or the summary information according to the number of data stored in the FIFO memory; And a first serial I / F circuit for serially transferring the output of the selector. It allows the high-speed serial transmission, can transmit the status and summary information in the conventional effective utilization is not the transmission cycle (idle and dummy), it is possible to provide a testing device performance is improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a semiconductor test apparatus constituting an example of a test apparatus according to an embodiment of the present invention. The same parts as those in FIG. 5 are denoted by the same reference numerals, and redundant description will be omitted, and differences will be mainly described.

  The PE card 120 outputs a test pattern to the DUT 10 and determines whether the DUT 10 is good or bad based on the pattern output from the DUT 10. The fail / mask information, the fail / mask summary information, and the status information of the PE card 120 that are the determination results are output to the fail control card 130 via the high-speed serial transmission path 6. The control card 130 processes these pieces of information. Unlike the case of FIG. 5, the summary / status information is transmitted by high-speed serial transmission via the high-speed serial I / F circuit, and the low-speed serial I / F circuit 5 and the low-speed serial transmission path 7 are not used.

In the PE card 120, the selector 8 inputs fail / mask data output from the FIFO 2, fail / mask summary information output from the fail / mask summary circuit 4, and status information of the PE card 120. Is selected by a selector signal (not shown) sent from the first high-speed serial IF circuit 3 in accordance with the number of data stored in. The selected information is output to the high-speed serial IF circuit 3.

Next, the operation of the semiconductor test apparatus of FIG. 1 will be described with reference to the time chart of FIG. However, FIGS. 2 (a) to (d) are the same as FIGS. 6 (a) to (d).

The fail / mask data output from the FIFO 2, the fail / mask summary information output from the fail / mask summary circuit 4, and the status information of the PE card 120 are input to the selector 8, and one of them is selected. The selected information is transmitted to the fail control card 130 through the high-speed serial transmission path 6 by the high-speed serial I / F circuit 3.

The high-speed serial I / F circuit 3 performs selection control of the selector 8 in accordance with the number of data stored in the FIFO 2 together with transmission control, and processes and outputs data or control codes two by two as shown below (Fig. 2 (d) (e)).

(1) When the number of data is less than 2, (1-1) An idle control signal having a control code indicating status and summary information is transmitted.
(1-2) Output the status and summary information (The transmission order of status and summary information is determined in advance. The fail control card 130 performs processing according to the order).

(2) When there are two or more data (2-1) Data is read from the FIFO 2, converted into a high-speed serial signal, and transmitted.
(2-2) Data is read again from the FIFO 2, converted into a high-speed serial signal, and transmitted.

According to the semiconductor test apparatus configured as described above, a transmission cycle that has not been used in the conventional idle state (data waiting state) (previously, “idle (first half)” or “idle (second half)” was transmitted). By transmitting the summary information and the status using the idle cycle, the summary information and the status can be transferred at a higher speed than before, so that the performance can be improved.

Further, since the low-speed serial transmission line (7 in FIG. 5) is unnecessary, the number of signal lines can be reduced. As a result, printed circuit board design can be facilitated.

  In the above embodiment, the high-speed serial I / F circuit 3 transmits one summary / status information following the idle control signal with reference to the number 2 of data stored in the FIFO memory 2. However, it is not limited to this. That is, when M and N are arbitrary integers, N data is transmitted when the number of data stored in FIFO 2 is N or more, and the number of data stored in FIFO 2 is N. If it is less than M, the M summary / status information may be transmitted following the idle control signal.

In the above embodiment, the selector 8 is switched by the command of the high-speed serial IF circuit 3. However, the data storage count of the FIFO 2 is accumulated by a counter, and a selector signal is generated based on the count value. Also good.

Further, only one of the summary information and the status information may be transmitted as the summary / status information.

FIG. 3 is a configuration block diagram showing a test apparatus constituting a second example of the semiconductor test apparatus according to the embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted, and differences will be mainly described.

  The PE card 220 outputs a test pattern to the DUT 10 and determines whether the DUT 10 is good or bad based on the pattern output from the DUT 10. The fail / mask information, the fail / mask summary information, and the status information of the PE card 220 as the determination result are output to the fail control card 230 via the high-speed serial transmission path 6. The control card 230 processes these pieces of information.

In the PE card 220, the FIFO 2 stores a dummy together with the fail / mask data from the fail / mask determination circuit 1.

The selector 8 inputs fail / mask data output from the FIFO 2, fail / mask summary information output from the fail / mask summary circuit 4, and status information of the PE card 120, and is stored in the FIFO 2. One of them is selected by a selector signal (not shown) sent from the high-speed serial IF circuit 3 in accordance with the number of data and a dummy value. Here, the fail / mask information when the dummy value is “1” is handled as dummy data.

The high-speed serial IF circuit 3 transmits the information selected by the selector 8 to the fail control card 230 via the high-speed serial transmission path 6.

In the fail control card 230, the high-speed serial IF circuit 9 constitutes a second serial I / F circuit, and predetermined data is determined according to the control signal and data received from the PE card 220 via the high-speed serial transmission path 6. Generates output and outputs status / summary information. Further, since it is necessary to distinguish dummy data and invalid data in the fail control card 9 in order to maintain real-time characteristics, dummy data (Dummy data) and invalid data (Invalid data) are generated according to the control signal. The fail control card 230 processes these pieces of information.

Next, the operation of the semiconductor test apparatus of FIG. 3 will be described with reference to the time chart of FIG. However, FIGS. 4 (a) to (d) are the same as FIGS. 2 (a) to (d). Here, the data state in the FIFO 2 is shown for easy understanding.

The fail / mask data from the fail / mask determination circuit 1 and the dummy are stored in the FIFO 2 in association with each clock (FIGS. 4C, 4D, and 4E).

The high-speed serial I / F circuit 3 operates as follows according to the number of data stored in the FIFO 2 and the dummy value corresponding to each data (FIG. 4 (e) (f)).
(1) When data is less than two (1-1) A control code indicating idle (no output data) is transmitted. This control signal is referred to as “control code (IDLE)”.
(1-2) Transmit status and summary information (The transmission order of status and summary information is determined in advance. The fail control card 9 performs processing according to the order)

(2) When there are two or more data, the following operation is performed according to the dummy stored in the FIFO 2.
(2-1) When “Dummy to be output next” and “Dummy to be output next” are both “1” (2-1-1), a control code indicating the dummy is transmitted. This control signal is referred to as “control code (DUMMY)”. At this time, data is read from the FIFO 2, but discarded without being used (the next data in the FIFO 2 can be read).
(2-1-2) Status and summary information are transmitted. At this time, data is read from the FIFO 2 and discarded without being used as described above.
(2-2) When either “Dummy to be output next” or “Dummy to be output next” is “0” (2-2-1) Read data from FIFO 2 and convert it into a high-speed serial signal Convert and send.
(2-2-2) Data is read from FIFO 2 again, converted into a high-speed serial signal, and transmitted.

The high-speed serial IF circuit 9 in the fail control card 230 operates as follows according to the received control signal and data (FIG. 4 (f) (g)).
(3) When the control signal (IDLE) is received, the next data of the control signal is processed as the status and summary information.
In addition, invalid data is generated and output on the assumption that an idle has been received.
(4) When the control signal (DUMMY) is received, processing is performed assuming that the next data of the control signal is status and summary information.
Further, dummy data is generated and output by regarding that the dummy has been received.
(5) When data is received (when no control signal is received)
Assuming that data has been received, the data is output as it is.

According to the semiconductor test apparatus configured as described above, in high-speed serial transmission, a control signal has a meaning (in this case, idle or dummy), and not only an idle cycle but also a dummy cycle that has not been conventionally used ( In the past, dummy data was transmitted effectively to transfer the status and summary information. In addition to the features of the semiconductor test equipment shown in FIG. Furthermore, it can transfer efficiently. Therefore, the performance can be further improved.

In the above embodiment, one summary / status information is transmitted following the control signal based on the number 2 of data stored in the FIFO memory 2, but the present invention is not limited to this. You may do it. That is, when the number of data stored in the FIFO memory 2 is less than N, the serial I / F circuit 3 transmits M summary / status information following the idle control signal and stored in the FIFO memory 2. When the number of stored data is greater than or equal to N and N dummy data continues from the beginning, the L summary / status information is transmitted following the dummy control signal, and the number of data stored in the FIFO memory 2 Is N or more and N data from the head is not dummy data, N data may be transmitted. In this case, when receiving the idle control signal, the second serial I / F circuit 9 processes the next M data as summary / status information and generates and outputs M + 1 invalid data. When the dummy control signal is received, the next L data are processed as the summary / status information and N dummy data are generated and output. When the data is received, the data is output ( N, M, and L are positive integers). The time chart of FIG. 4 shows a case where N = 2 and M = L = 1.

Further, only one of the summary information and the status information may be transmitted as the summary / status information.

In each of the above embodiments, the FIFO 2 may be configured by combining registers and the like.
In each of the above-described embodiments, the case where the present invention is applied to a semiconductor test apparatus is shown. However, the present invention is not limited to this, and real-time information based on the test result of the device under test and batch information are serially transmitted in parallel. The performance can be improved by applying it to various test apparatuses in which serial transmission does not include valid information and includes unnecessary cycles. However, in each of the above embodiments, the fail / mask information based on the comparison result between the output of the device under test to which the test pattern is applied and the expected value constitutes the real-time information, the summary information of the fail / mask information, And / or status information constitutes the batch information, and at least one of an idle cycle and a dummy cycle constitutes the unnecessary cycle.

1 is a block diagram showing a configuration of an example of a test apparatus according to an embodiment of the present invention. It is a time chart which shows operation | movement of the test apparatus of FIG. It is a block diagram which shows the 2nd Example of the testing apparatus which concerns on embodiment of this invention. It is a time chart which shows operation | movement of the test apparatus of FIG. It is a block diagram of the configuration of a test apparatus according to the prior art. It is a time chart which shows operation | movement of the test apparatus of FIG.

Explanation of symbols

1 Fail / Mask Determination Circuit 2 FIFO Memory 3 First Serial I / F Circuit 4 Fail / Mask Summary Circuit 8 Selector 9 Second Serial I / F Circuit 10 Device Under Test 130, 230 Fail Control Card

Claims (10)

FIFO information storing fail information based on a comparison result between an output of a DUT to which a test pattern is applied and an expected value, and fail / mask information of the test pattern and mask information generated from a dummy signal, and the fail A test apparatus for serially transferring the fail / mask information of the FIFO memory and the summary information of the fail / mask summary circuit.
A selector that selects either the data output from the FIFO memory or the summary information according to the number of data stored in the FIFO memory;
A test apparatus comprising: a first serial I / F circuit that serially transfers an output of the selector. The first serial I / F circuit includes:
When the number of data stored in the FIFO memory is N or more, N data is transmitted,
2. The test apparatus according to claim 1, wherein when the number of data stored in the FIFO memory is less than N, M pieces of summary information are transmitted following an idle control signal. (However, N and M are positive integers.) The FIFO memory stores a dummy signal corresponding to the fail / mask information,
The selector selects either the data output from the FIFO memory or the summary information according to the number of data stored in the FIFO memory and a dummy signal,
And a second serial I / F circuit that outputs the data, dummy data, or invalid data in accordance with data or control signals received by serial transmission from the first serial I / F circuit. The test apparatus according to claim 1. The first serial I / F circuit includes:
When the number of data stored in the FIFO memory is less than N, the M summary information is transmitted following the idle control signal,
When the number of data stored in the FIFO memory is N or more and N pieces of dummy data are consecutive from the top, the L summary information is transmitted following the dummy control signal,
When the number of data stored in the FIFO memory is N or more and any of the N data from the beginning is not dummy data, the N data is transmitted,
The second serial I / F circuit includes:
When the idle control signal is received, the next M data are processed as the summary information and M + 1 invalid data are generated and output,
When the dummy control signal is received, the next L data are processed as the summary information and N dummy data are generated and output,
4. The test apparatus according to claim 3, wherein when the data is received, the data is output. (N, M, and L are positive integers) A fail / mask determination circuit is provided that performs pass / fail judgment based on a comparison result between an output of the DUT and an expected value, generates mask information from a test pattern and a dummy signal, and outputs the fail / mask information to the FIFO memory. ,
5. The test apparatus according to claim 1, wherein the fail / mask summary circuit generates summary information from the past fail / mask information and outputs the summary information to the selector.   The test apparatus according to claim 2 or 4, wherein N is 2, M and L are 1.   The test apparatus according to claim 1, wherein status information is used together with the summary information or instead of the summary information.   8. The test apparatus according to claim 1, wherein the serial transfer is performed between a pin electronics card and a file control card. In a transmission method of a test apparatus in which real-time information based on DUT test results and batch information are serially transmitted in parallel,
A method of transmitting a test apparatus, wherein the batch information is serially transferred using an unnecessary cycle included in the serial transmission of the real-time information. The real-time information includes fail information based on a comparison result between an output of a DUT to which a test pattern is applied and an expected value, and fail / mask information including mask information generated from the test pattern and a dummy signal,
The batch information includes at least one of summary information of fail / mask information and status information,
The test apparatus transmitting method according to claim 9, wherein the unnecessary cycle includes at least one of an idle cycle and a dummy cycle.

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