JP2009187585A - Return processing method from standby mode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mechanism for achieving both low standby current due to power shutdown and high-speed return from standby due to interruption. <P>SOLUTION: In an information processing device comprising a first area AE1 including a central processing unit CPU and peripheral circuit modules IP1 and IP2, a second area AE2 having information storage circuits URAM and BUREG for storing values of registers REG1 and 2 included in the peripheral circuit modules IP1 and IP2, and a first power source switch SW1 for controlling current supply to the first area AE1, when the information processing device operates in a first mode, operating current is supplied to the first area AE1 and the second area AE2, and when the information processing device operates in a second mode, the first power source switch SW1 is controlled so as to disconnect the current supply to the first area AE1, and the current supply to the second AE2 continues. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, and is particularly useful when applied to a system LSI or a microprocessor.

  In system LSIs for portable information terminals such as today's mobile phones, it is necessary to realize long-time driving by a battery, and therefore, low current consumption is important. In particular, the standby current, which is the current consumption in the state where there is no processing to be performed, determines the standby time of the portable information terminal, and therefore reduction thereof is particularly important. Therefore, various standby current reduction methods have been proposed and realized at present.

  First, there is a method of stopping all clocks in the system LSI during standby (hereinafter referred to as software standby). In this method, when the standby state is entered, the clock inside the system LSI is stopped, so that the current consumption due to the circuit operation in the system LSI becomes almost zero. As a result, the standby current can be reduced only to the consumption current due to the leakage current. Furthermore, in this method, the internal state (register value, etc.) of the system LSI can be held even during standby, so that recovery from standby can be performed by interrupt processing. As a result, the recovery is completed at a high speed in the time required for restarting the clock.

  However, in the recent miniaturized process, since the leakage current is very large, the current consumption due to the leakage current cannot be ignored. Therefore, a method of shutting off the power supply of the system LSI at the time of standby as shown in Non-Patent Document 1 (hereinafter referred to as “U standby”) has been proposed. In this method, when the standby state is entered, the power supply is cut off except for the minimum circuit necessary for the return process. As a result, not only the current consumption due to the circuit operation but also the current consumption due to the leakage current becomes almost zero, and the standby current can be almost zero.

Yamada et al., “A 133MHz 170mW 10μA Standby Application Processor for 3G Cellular Phones”, ISSCC 2002, February 6, pp.370-371

  The inventors of the present application have examined the above-mentioned two standby modes in making the present invention and found that there are the following problems.

  In the U standby mode, not only the current consumption due to the circuit operation but also the current consumption due to the leakage current can be reduced to almost zero. However, since the entire internal state of the system LSI is destroyed by the power shutdown, the return from standby is interrupted. It cannot be performed by the process, and the return must be performed by the reset process. In the reset process, the initial setting of the system LSI and the start-up of the software are performed, so that the time required for recovery becomes long. In particular, the start-up of software increases the processing time due to the large number of instructions to be executed. Specifically, when returning from the U-standby mode, the interrupt processing cannot be performed as it is even though there is an interrupt request, and after the reset processing is performed and the software is started, the interrupt request is processed. The corresponding processing is performed.

  On the other hand, in software standby, the internal state is maintained, so it is not necessary to start up the software, etc., and it is possible to return from the standby state at high speed. Current will increase.

  Thus, the present inventor has found that it is difficult to achieve both a low standby current and a high-speed standby recovery with the currently proposed technology.

  As one means for solving the above-mentioned problem, a central processing unit and an internal memory are provided, and after the information held by the central processing unit is saved in the internal memory, a power supply to the central processing unit An information processing apparatus having a standby mode for stopping the supply of information from the standby mode, wherein the interrupt request is received when an interrupt request is received from outside the information processing apparatus during the standby mode. The central processing unit stores the information saved in the internal memory when transitioning to the standby mode in response to the presence of the interrupt request and the first step of asserting and holding an interrupt request signal indicating that A second step for returning by executing a predetermined instruction; and after the second step is completed, an interrupt request is validated, and Receiving said interrupt request signal held in one step, and a third step of performing an interrupt processing corresponding to the interrupt request.

  According to the present invention, high-speed operation or low power consumption of a system LSI can be realized.

It is a schematic explanatory drawing of the system by one embodiment of this invention. It is a figure which shows the layout example (floor plan example) of the area | region 1 shown by FIG. It is a figure which shows an example of the power supply net | network of the area | region 1 shown by FIG. FIG. 2 is a diagram showing an example of a configuration of a standby control circuit STBYC shown in FIG. FIG. 7 is a diagram showing another example of the configuration of the standby control circuit STBYC shown in FIG. 1. It is a figure which shows the structure of the register backup mechanism shown by FIG. It is a figure which shows the transition sequence to R standby mode by one embodiment of this invention. It is a figure which shows the return sequence from R standby mode by one embodiment of this invention. It is a figure which shows the processing flow accompanying R standby transition by one embodiment of this invention. It is a figure which shows the processing flow accompanying R standby return by one embodiment of this invention. It is a figure explaining the comparison of each standby. It is the figure which showed the transition between each standby by one embodiment of this invention. It is a figure which shows an example of a structure of the system LSI for mobile phones to which this invention is applied.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a preferred embodiment of an information processing device according to the invention will be described with reference to the accompanying drawings. Although not particularly limited, circuit elements constituting each block of the embodiment are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit technology such as a CMOS (complementary MOS transistor) or a bipolar transistor. It is formed.

  FIG. 1 shows an embodiment for realizing the low current mode (hereinafter referred to as R standby mode) of the present invention. FIG. 1 shows a conceptual diagram of a configuration when applied to an information processing apparatus, in particular, a system LSI (or microprocessor, hereinafter the same). Although not particularly limited, the system LSI is formed on a single semiconductor substrate.

  This system LSI includes a first area AE1, a second area AE2, and a third area AE3 as areas where the power supply can be controlled independently. First, the first area AE1 includes a central processing unit CPU (hereinafter referred to as CPU), peripheral circuit modules IP1 and IP2, a system bus SYSBUS, and a clock generation circuit CPG, and the supply of current is controlled by the power switch SW1. Next, the second area AE2 includes an internal memory URAM (hereinafter referred to as URAM) and a backup register BUREG, and the supply of current is controlled by the power switch SW2. Finally, the third area AE3 includes a standby control circuit STBYC and is always energized. Here, the power switches SW1 and SW2 are disposed between the ground potential Vss and each region and control the supply of current, but may naturally be disposed between the operating potential Vdd and each region. Further, it may be arranged between the ground potential Vss and each region and between the operation potential Vdd and each region.

  The CPU controls the entire system LSI. The peripheral circuit module IP1 is not particularly limited, but is a peripheral circuit module that is not required when a CPU such as an MPEG accelerator fetches an instruction. The peripheral circuit module IP2 is not particularly limited, but is a peripheral circuit module required when the CPU fetches an instruction, such as a bus state controller. The system bus SYSBUS is connected to each circuit module including a CPU, and includes a data bus and an address bus (not shown). The clock generation circuit CPG receives an externally supplied clock signal RCLK and generates an internal clock signal ICLK. The internal clock signal ICLK is supplied to each circuit module, and the system LSI operates according to the internal clock signal ICLK. The URAM is a large-capacity internal memory and holds necessary information such as data currently being processed. The backup register BUREG holds the value of the register REG2 included in the peripheral circuit module IP2 in the R standby mode. In the present invention, the circuit modules included in the region 1AE1 are collectively arranged, and the circuit modules included in the region 2AE2 are collectively arranged. By arranging in this way, the power switches SW1 and SW2 can be provided in common for a plurality of circuit modules, so that the area can be reduced.

  When the system LSI shifts to the R standby mode, the power switch SW1 is turned off and the power switch SW2 is turned on. Accordingly, the supply of current to the CPU, the peripheral modules IP1, IP2, and the clock generation circuit CPG is cut off, so that current consumption can be reduced.

  When transitioning to the R standby mode, the internal information of the system LSI is saved in the URAM or the backup register BUREG. Thereafter, the power switch SW1 is turned off by the power switch control signal SW1-C, and supply of current to each circuit module included in the first area AE1 is stopped. The power switch SW2 is turned on. Therefore, since current is supplied to the circuit modules included in the second area AE2, the saved internal information of the system LSI is held, and is held in the URAM and the backup register BUREG by an external interrupt request. By returning the information to the CPU, IP1, and IP2, it becomes possible to perform interrupt processing when returning from the standby mode. When there is an interrupt request, the standby control circuit STBYC turns on the power switch SW1, supplies current to the first area AE1, and then returns the saved internal information of the system LSI to the CPU, IP1, and IP2. Done. Since this operation is performed in a shorter time compared to the reset process for starting up the software such as the OS, it is possible to return faster than in the U standby mode. Note that the internal information of the system LSI may be saved in an external memory.

  That is, one feature of the present invention is that, when the R standby mode is entered, the current supply to the CPU and the peripheral circuit modules IP1 and IP2 is cut off, and the current to the information holding circuit such as the URAM or the backup register BUREG is reduced. The purpose is to divide the area so that the supply can be continued. This makes it possible to retain information necessary for returning from the R standby mode at high speed.

  From another point of view, interrupt processing is performed at the time of return even though the value of the register indicating the internal state is destroyed by cutting off the current supply to the CPU and the peripheral circuit modules IP1 and IP2. Is possible. As a result, it is possible to recover at high speed because it is not necessary to start up software such as an OS while realizing a standby mode with low current consumption.

  In the present embodiment, other low current modes such as a software standby mode and a U standby mode can be adopted, and the low current mode can be set flexibly depending on the use state of the system LSI. In the software standby mode, both the power switches SW1 and SW2 are turned on, the supply of the internal clock signal ICLK is stopped while the current is supplied to the CPU and the peripheral circuit modules IP1 and IP2, and the circuit operation is stopped. As a result, the circuit operation is stopped and the operating current is reduced. Next, in the U standby mode, both the power switches SW1 and SW2 are turned off, the circuit operation is stopped, and the supply of current is cut off. Therefore, current consumption due to leakage current can be reduced in addition to current consumption due to circuit operation.

  The system of the present invention is not limited by the type and number of processor CPUs and peripheral circuit modules IP1 and IP2, and the number of power supply areas, and can be implemented by configurations other than those shown here. For example, in the present embodiment, the power supply region is divided into three because the software standby mode, the U standby mode, and the R standby mode are provided as the low current mode, but the U standby mode may be omitted. In this case, the second area AE2 and the third area AE3 may be one, and the power may be always supplied. Even in this case, it is possible to realize both a high-speed recovery from the standby mode and a low current. In this embodiment, the power is shut off by a switch placed inside the system LSI, but it is also possible to adopt a configuration in which the power is shut off by a power control circuit placed outside the system LSI.

  FIG. 2 is a diagram for explaining the layout when the areas are divided as shown in FIG. 1, and shows a layout arrangement example of the area 1AE1 shown in FIG. RUSR is an area where MOS transistors constituting each circuit module included in area AE1 are arranged. The ring-shaped area consisting of RPWR1, RPWR2, RPWR3, RPWR4, RPWR5, RPWR6, RPWR7, and RPWR8 has a relatively thick wiring width for power trunks such as power line VDD, ground line VSS, and virtual ground line VSSM The power ring is formed around the circuit. Thereby, the resistance of the power supply line, the ground line, and the virtual ground line supplied to the MOS transistors constituting each circuit module is reduced. The power switch SW1 is connected between the ground line and the virtual ground line, and current supply to each circuit module is performed via the virtual ground line VSSM. Although only the region 1AE1 will be described here, the region 2AE2 is configured similarly. In this embodiment, the power switch SW1 is disposed between the ground line and the virtual ground line. However, a virtual power line may be provided, and the power source SW1 may be disposed between the power line VDD and the virtual power line. In this case, the power switch SW1 may or may not be provided between the ground line and the virtual ground line.

  The power switch SW1 is preferably disposed in the four side regions (RPWR2, RPWR4, RPWR6, RPWR8) of the power ring. In particular, the power switch SW1 is preferably arranged in the regions RPWR4 and RPWR8. As shown in FIG. 3, the power supply line VDD105 (M1) and the virtual ground line VSSM105 (M1) for supplying power and ground to each circuit module extend in the lateral direction. Therefore, the influence of the wiring resistance can be reduced by arranging the power switch SW1 in the regions RPWR4 and RPWR8. On the other hand, when the power switch SW1 is arranged in the regions RPWR2 and RPWR6, the influence of the wiring resistances of the power supply line VDD and the ground line VSS arranged in the regions RPWR4 and RPWR8 is increased. Therefore, when the power switch SW1 is preferentially arranged in the regions RPWR4 and RPWR8, and it is desired to further reduce the influence of the on-resistance of the power switch SW1, it is desirable to further arrange the power switch SW1 in the regions RPWR2 and RPWR6.

  FIG. 3 shows a more specific layout of the power supply line VDD, the ground line VSS, and the virtual ground line VSSM for the portion R14 in FIG. VDD100 to VDD110 are power supply lines, VSS101 to VSS103 and VSS107 to VSS113 are ground lines, and VSSM101 to VSSM107 are virtual ground lines. SIG100 shows only one wiring representative of the wiring crossing the power supply ring in the vertical direction, and SIG101 shows only one wiring representative of the wiring crossing the power supply ring in the horizontal direction. In FIG. 3, symbols M1 to M4 described in parentheses after each symbol indicate the name of the wiring layer used to install the wiring. When a plurality of descriptions are described, it indicates that the wiring is performed by the plurality of wiring layers. M4 is an upper wiring layer as viewed from the semiconductor substrate than M3, M3 is higher than M2, and M2 is higher than M1. In addition, square symbols with X marks indicate vias (VIA) for connecting the wiring layers. A portion indicated by RPWR is a power supply ring region, and a portion indicated by RUSR is a region where MOS transistors constituting each circuit module are arranged.

  The power supply ring is composed of VDD101 to VDD103, VSS101 to VSS103, VSSM101 to VSSM103, and VSS111 to VSS113 by wiring layers M2 to M4 that are relatively higher than the semiconductor substrate. Since the wiring layer relatively higher than the semiconductor substrate can have a wider pitch than the lower wiring layer, the wiring layer thickness can be increased, the sheet resistance can be reduced, and a low resistance wiring can be realized. By using such a low-resistance wiring for the power supply ring, the power supply ring can be formed with a low resistance, and so-called voltage drop can be suppressed small.

  In FIG. 3, a vertical power supply trunk line RPWRV that shunts the power supply ring in the vertical direction is formed by VDD 106 and VSSM 106. Further, a lateral power supply main line RPWRH that shunts the power supply ring in the lateral direction is formed by VDD 107, VSS 107, and VSSM 107. As a result, the resistance of the power supply ring can be further reduced. Here, the horizontal arrangement interval of the vertical power supply trunk line RPWRV and the vertical arrangement interval of the horizontal power supply trunk line RPWRH are not particularly limited, but a relatively lower M2 wiring layer is used for the vertical power supply trunk line RPWRV. Therefore, if too many vertical power supply main lines RPWRV are arranged, the number of channels for the signal line wiring of the MOS transistors constituting the circuit module is reduced. Therefore, for example, it is appropriate to arrange them at intervals of about 100 μm. On the other hand, since the M4 wiring layer which is a relatively upper layer is used for the lateral power supply main line RPWRH, the number of channels for the signal line wiring is rarely reduced. Therefore, a large number of horizontal power supply trunks RPWRH can be arranged.

  The power supply line RIP from the power ring to the MOS transistors constituting each circuit module is performed by VDD 105 and VSSM 105 using the M1 wiring layer. A channel for wiring the signal lines of the MOS transistors constituting each circuit module mainly uses M1 to M3 wiring layers. For the same reason, an M4 wiring layer is used for the power supply line and the grounding line in the four corner regions of the power supply ring, and no lower layer wiring is used.

  For simplicity, only one wiring VDD108 for electrically connecting VDD100 and VDD103 is shown in the figure, but it is actually appropriate to arrange a large number of wirings at a certain interval and connect them to a low resistance. Further, although wiring for directly electrically connecting VDD100 and VDD101 in the vertical direction as in VDD108 is not shown in the figure, it is desirable to arrange them in the same manner as VDD108 using an M2 wiring layer. For simplicity, only one wiring VSS108 for electrically connecting VSS103 and VSS113 is shown, but in practice it is appropriate to arrange a large number of wirings at a certain interval and connect them to a low resistance. is there. Further, although wiring for directly electrically connecting VSS 101 and VSS 111 in the vertical direction as in VSS 108 is not shown, it is desirable to arrange them in the same manner as VSS 108 using an M3 wiring layer.

  With the layout described above, it is possible to supply power to each circuit module with low impedance by efficiently using the wiring layer. Note that FIG. 3 shows a configuration example in which there are four wiring layers. However, if there are more wiring layers, the power supply ring can be further reduced in resistance by using the wiring layers in the configuration diagram of FIG. Can be configured. Although the specific usage method of the wiring layer is not limited, the uppermost wiring layer (M4 in FIG. 3) and the lowermost wiring layer (M1 in FIG. 3) are used to connect the power supply ring from the outside of the power supply ring. It is appropriate to supply power and ground. Further, the lateral power supply main line RPWRH is preferably realized by using the uppermost wiring layer (M4 in FIG. 3). This is because many channels for wiring the signal lines of the MOS transistors constituting each circuit module can be obtained.

  FIG. 4 shows the configuration of the standby control circuit STBYC for controlling the transition / return to the low current mode. The standby control circuit STBYC is connected to the system bus SYSBUS for reading and writing the internal register, and receives an interrupt request signal IRQ, a reset signal RST, and a clock signal RCLK. The output of the standby control circuit STBYC is a backup register write enable signal BU-WE, an interrupt signal INTR for notifying the CPU after returning from the R standby mode, a CPU execution start address RST-VEC after reset, and the first area AE1. The reset signal RST1 and the control signal SW1-C of the power switch SW1, and the reset signal RST2 of the second area AE2 and the control signal SW2-C of the power switch SW2. Although the interrupt signal INTR is directly connected to the CPU in FIG. 1, it may be connected to the CPU via an interrupt controller or the like.

  The standby control circuit STBYC has a standby mode control register STBCR and a boot address register BAR as registers that can be read and written from the system bus SYSBUS. Read / write operations from the system bus SYSBUS are controlled by the decoder DEC. The standby mode control register STBCR holds a value corresponding to the current standby mode. Further, a write request from the system bus SYSBUS to the standby mode control register STBCR is a request for transition to each low current mode. The standby control circuit STBYC in the present embodiment is configured to control the transition to the software standby mode, the U standby mode, and the R standby mode, or the return from these modes. The CPU can also directly instruct the CPG to stop the clock.

  The boot address register BAR holds the address of an instruction that is first executed by the CPU when returning from the R standby mode and releasing the reset. In this embodiment, a request for transition to the R standby mode is given by writing to the standby mode control register STBCR, but a dedicated instruction such as a sleep instruction or a standby instruction is used, or a combination of the standby mode control register STBCR and the dedicated instruction. It is also possible to request a transition by In that case, it is possible for the CPU to transmit a transition request to the standby control circuit STBYC via a sleep request response line (not shown).

  The synchronization circuit SYNC included in the standby control circuit STBYC synchronizes the interrupt request IRQ from the outside of the chip with the external clock signal RCLK. The current mode control sequential circuit STBYC-FSM determines the necessity for transition / return to the standby mode, and outputs a transition / return sequence if necessary. The input is the value of the standby mode register STBCR, the interrupt request IRQ, the state holding register STATE indicating which step is being executed in the sequence at transition / return, the output is the output of the standby control circuit STBYC, and the current R standby mode R standby mode signal RSTBY-MODE indicating whether or not.

  When returning from the R standby mode in response to an external interrupt request signal IRQ, the information saved in the URAM or the external memory is returned to each circuit module in the area 1AE1 such as the CPU, and then the interrupt request signal IRQ is changed to the interrupt request signal IRQ. It is necessary to perform corresponding interrupt processing. This process is performed by executing a predetermined instruction. That is, when returning from the R standby mode, it is necessary to hold the address of the memory storing the instruction to be executed first. Therefore, in the present invention, a boot address register BAR is provided for holding an address of a memory storing an instruction to be executed first when returning from the R standby mode, and the boot address register is set when transitioning to the R standby mode. The execution start address is set in the BAR. Here, since the execution start address when returning from the R standby mode can always be the same, it can be configured in a hard-wired manner and the setting of the execution address at the time of transition to the R standby mode can be omitted. It is. However, in the present embodiment, by providing the boot address register BAR, the software creator can freely set the above execution start address, and the program necessary for returning to the R standby mode can be set at an arbitrary position in the memory space. It is possible to arrange in.

  On the other hand, since the return from the U standby mode is always a reset process, the boot address INIT-VEC is executed first. In the present invention, the selector SEL1 is provided, the R standby mode signal RSTBY-MODE is output from the current mode control sequential circuit STBYC-FSM, and RST-VEC is set to either BAR or the boot address INIT-VEC at normal reset. The configuration to be selected is adopted. As a result, when reset processing is performed to return from the U standby mode, the boot address INIT-VEC is output, and an instruction is executed from the address held in the boot address register BAR only when returning from the R standby mode. Function is realized. To return from software standby, after starting to supply an internal clock signal, an instruction is read from an address corresponding to the type of interrupt request IRQ in the same manner as interrupt processing in the normal operation mode.

  In this embodiment, the execution start address when returning from the R standby mode or the U standby mode is determined by the standby control circuit STBYC and input to the CPU. However, the execution start address after returning to the CPU is used. It is also possible to adopt a configuration in which a register for storing the data is provided and this register is saved and recovered by hardware using the backup register BUREG.

  FIG. 5 shows another embodiment of the standby control circuit STBYC. The difference from FIG. 4 is that when a plurality of interrupt request signals are input in parallel, a priority determination circuit MAPPRI for determining which interrupt request is preferentially accepted can be provided to handle a plurality of interrupt requests. This is the point. In other words, in FIG. 4, the return from the R standby mode or the U standby mode corresponds to only one interrupt request signal IRQ, but in this embodiment, it is possible to return from a plurality of interrupt requests. It becomes. In this embodiment, a mask register IMREG is provided. By setting an interrupt request to be masked at the time of transition to each standby mode in the mask register IMREG, it is possible to change the interrupt request accepted for each transitioned standby mode, and flexibly cope with an embedded system. It becomes possible. Although omitted in FIG. 5, the boot address register BAR and the standby mode control register STBCR can be read / written via the system bus SYSBUS as in FIG. Similarly, the mask register IMREG can be read / written via the system bus SYSBUS.

  FIG. 6 shows the configuration of the backup register BUREG that saves the state when transitioning to the R standby mode. The backup register BUREG is in the second area AE2 and is energized even in the R standby mode and holds the value. On the other hand, since the register REG2 of the peripheral circuit module IP2 is in the first area AE1, the power is cut off during the R standby mode, and the value is destroyed. When the reset of the CPU is released when returning from the R standby mode, the instruction fetch is started from the address of the boot address register BAR. For this reason, the setting registers of the modules that determine the pin states of the peripheral circuit module IP2 and the system LSI necessary for the CPU to fetch instructions are saved and restored by hardware. Examples of such peripheral circuit modules include a clock generation circuit, a bus controller, a memory controller, an interrupt controller, and a pin function controller. Also, registers that cannot be read / written by software need to be saved and restored by hardware if necessary for the CPU to fetch instructions.

  The holding latch HOLD in the backup register BUREG is a latch that stores the value of REG, and stores the value at the rise of BU-WE. The gate G1 masks an indeterminate value output by the REG when the first region AE1 is powered off. In this embodiment, the indeterminate value is masked by utilizing the fact that the reset signal RST1 of the first area AE1 is fixed to 1 when the power of the first area AE1 is shut off. If the indefinite value output from the register can be masked, this part can be freely configured.

  On the other hand, in the register REG2 of the peripheral circuit module IP2, the selectors SEL2 and SEL3 are inserted at the input of the register REG, and the value written to the register REG is the value NORMV at the normal operation, the value HOLDV just before the power is shut off, Select from the initial value INITV. As selection signals for the selectors SEL2 and SEL3, the reset signal RST1 in the first region and the reset signal RST2 in the second region are used. First, when the reset signal RST1 in the first area is 0, the first area AE1 including the peripheral circuit module IP2 is operating normally, so the selector SEL2 selects NORMV as a value to be written in the REG. Next, when the reset signal RST1 of the first area AE1 is 1 and the reset signal RST2 of the second area is 0, since the R standby mode is in effect, HOLDV is selected as a value to be written to the REG. When the reset signals RST1 and RST2 are both 1, both the first area AE1 and the second area AE2 are being initialized, so INITV is selected as a value to be written to the REG. In this embodiment, the selector is controlled using the reset signal, but the selection signal can also be output from the standby control circuit STBYC. By configuring the backup register in this way, it is possible to achieve register saving / returning at a high speed when transitioning to the R standby mode or returning from the R standby mode. Also, information held in a register that cannot be read by software can be saved in the backup register BUREG. In this embodiment, only the IP2 register necessary for fetching the instruction is saved in the backup register BUREG. However, the IP1 register not required for fetching the instruction is also saved in the backup register BUREG. It doesn't matter. In this case, the area is increased, but it is not necessary to save / restore the software to / from the URAM or the external memory, so that high speed operation is possible.

  7 and 8 show a sequence of transition to the R standby mode and return to normal operation. First, FIG. 7 shows a sequence of transition from the normal operation state (NORMAL) to the R standby mode RSTBY. In cycle 1-1, a value RSTBY indicating R standby mode is written from the system bus to the standby mode control register STBCR. The standby control circuit reads the value of STBYC in 1-2, sets the backup write enable signal BU-WE to 1 in cycle 1-3, and stores the value of the register REG2 of the peripheral circuit module IP2 in the backup register BUREG. As a result, in cycle 1-3, the value HOLDV of the holding latch becomes the value of the register REG2 of the peripheral circuit module IP2 before the transition to the R standby mode. Next, since the R standby mode signal RSTBY-MODE and the reset signal RST1 in the first area become 1 in cycle 1-4, the modules in the first area AE1 are reset and stopped. Thereafter, in cycle 1-5, the control signal SW1-C of the power switch SW1 becomes 0, the power of the first area AE1 is cut off, and the transition is completed.

  Next, FIG. 8 shows a sequence for returning from the R standby mode by an interrupt. An interrupt occurs in cycle 2-1, and the interrupt request signal IRQ becomes 1. The standby control circuit STBYC accepts this in cycle 2-2, asserts the interrupt request INTR after the return to the R standby mode, and simultaneously sets the control signal SW1-C of the power supply SW1 to 1 to turn on the power of the first area AE1. . Thereafter, when the reset signal RST1 is set to 0 in cycle 2-3, the reset of the first area AE1 is released, and the operation of the CPU starts from cycle 2-4. At this time, since the value of RST-VEC is the address of boot address register BAR, the operation start address of the CPU is not INIT-RST-VEC but the address of boot address register BAR. Thereafter, in cycle 2-5, the R standby mode signal RSTABY-MODE is updated to 0, the value of the standby mode control register STBCR is updated to NORMAL indicating the normal operation mode, and the return is completed.

  In the present embodiment, there is a URAM in the second area AE2 where the power is not shut off even when the transition to the R standby mode is made, and this content is retained even in the R standby mode. Therefore, the registers of peripheral circuit modules that are not saved and restored by hardware using the URAM can be saved and restored. First, the register value can be saved by executing a program that transfers the register value to be saved and restored to the URAM before writing to the standby mode control register STBCR instructing the transition to the R standby mode. . In this case, in order to recover the register value, a program for transferring the URAM value to the register for recovering the URAM value is placed at the address set in the boot address register BAR. Note that these saving and restoring processes are not required for registers that do not need to hold values during the R standby mode. Therefore, when returning from the R standby mode at a higher speed, the number of registers to be saved and recovered can be reduced.

  FIG. 9 and FIG. 10 show the processing performed by the software when transitioning to and returning from the R standby mode. FIG. 9 shows a processing flow at the time of transition. In this flow, interrupts are first prohibited so that the register value to be saved does not change. Subsequently, the cache contents are written back to the memory, and the cache is invalidated. Next, the value of the register that is not saved and restored by hardware is transferred to the URAM, and the address of the instruction that is executed first after returning from the R standby mode is set in the boot address register BAR. Thereafter, when a value indicating the R standby mode is written in the standby mode control register STBCR, a transition to the R standby mode is performed. Note that when an instruction to transition to the R standby mode is given by an additional instruction (such as a sleep instruction SLEEP or a standby instruction STBY), the instruction is executed at this stage.

  Next, FIG. 10 is a processing flow when returning from the R standby mode. This process is placed at the address set in the boot address register BAR set in the R standby mode transition process. First, the register value stored in the URAM during the transition process is transferred to each register. As a result, the value of the register saved by software is restored. Next, enable the cache. Thereafter, when the interrupt is enabled, the interrupt request INTR output from the standby control circuit STBYC is accepted, and normal interrupt processing is performed. When this interrupt process ends, the R standby mode return process is completed. Since the processing shown here is executed by software, other necessary processing can be freely added and unnecessary processing can be deleted.

  Up to this point, the implementation of the R standby mode in the present embodiment has been described, but the software standby mode and the U standby mode can be implemented with the same configuration. First, software standby is realized by stopping the clock as in the conventional case. Next, the U standby mode can be realized by shutting off not only the first area AE1 but also the second area AE2 at the time of transition in the standby control circuit STBYC and resetting it by an external reset.

  FIG. 11 shows an example of a comparison of the presence / absence of power-off in each standby, transition and recovery methods, recovery time, and current consumption. In the R standby mode, the recovery time is about 10 times that of software standby (S standby), but the current consumption is 1/100. Compared with the U standby mode, the current consumption is about 10 times, but the recovery time is about 1/100.

  FIG. 12 shows a transition diagram between the respective operation modes. Transition from the R standby mode to the normal operation mode is made by an external interrupt or reset. However, in the case of an external interrupt, corresponding interrupt processing is performed, and in the case of reset, reset processing is performed. The transition from the U standby mode to the normal operation mode is made by reset processing.

  FIG. 13 shows the configuration of a system LSI for mobile phones to which the present invention is applied. In this system LSI, in addition to the modules in the embodiment described, the DMA controller DMAC, the memory controller MEMC, the bus controller BUSC, the interrupt controller INTC, and the MPEG accelerator MPEG are in the first area AE1, and the LCD controller LCDC is in the second area AE2. Have been added. Here, although not particularly limited, the DMA controller DMAC and the MPEG accelerator MPEG correspond to the peripheral module circuit IP1, and can return from the R standby mode without holding the internal state. The memory controller MEMC, the bus state controller BUSC, and the interrupt controller INTC correspond to the peripheral circuit module IP2, and the registers included in these are held in the backup register BUREG.

  Further, in this configuration, the LCD controller LCDC is added to the second area AE2 where the power is not cut off even in the R standby in order to continue the display of the external LCD panel LCD-PANEL during the R standby mode.

  Although the embodiments of the present invention have been described above, the present invention can be variously modified based on the technical idea. For example, the first area AE1 is divided into a plurality of areas, and a mode is provided in which the CPU, IP1, and IP2 are individually powered off.

  SW1, SW2 ... Power switch, RCLK ... External clock signal, ICLK ... Internal clock signal, CPU ... Central processing unit, IP1, IP2 ... Peripheral circuit module, REG1, REG2, REG3 ... Register, URAM ... Internal memory, BUREG ... Backup register, STBYC ... Standby control circuit, SYSBUS ... System bus, RST, RST1, RST2 ... Reset signal, IRQ ... Interrupt request signal , INTR ... interrupt signal, SEL1, SEL2, SEL3 ... selector, BAR ... boot address register, STBCR ... standby mode control register, DEC ... decoder, SYNC ... synchronization circuit, STATE ... Status holding register, STBYC-FSM · Current mode control sequence circuit, IMREG ··· mask register, MAPRI ··· priority determining circuit, G1 · · · gate circuit, HOLD · · · retention latch.

Claims (1)

An information processing apparatus comprising a central processing unit and an internal memory, and having a standby mode in which power supply to the central processing unit is stopped after information stored in the central processing unit is saved to the internal memory A return processing method from the standby mode of
A first step of asserting and holding an interrupt request signal indicating the presence of the interrupt request when there is an interrupt request from outside the information processing apparatus during the standby mode;
A second step in which the central processing unit restores the information saved in the internal memory upon transition to the standby mode by executing a predetermined instruction in response to the interrupt request;
A third step of enabling an interrupt request after completion of the second step, accepting the interrupt request signal held in the first step, and performing an interrupt process corresponding to the interrupt request; How to recover from standby mode.

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