JP2009187337A - Device control method, program, control circuit, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent transfer data to be generated in the case of performing DMA transfer with an IDE device from being missed. <P>SOLUTION: In electronic equipment 20, when issuing a command corresponding to a request command from a host device 10 to an IDE device 40, a device controller 30 performs data transfer with the IDE device 40 in a transfer mode (DMA/PIO transfer mode) corresponding to the issued command by referring to a command table 332. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a device control method for a device that reads data from a recording medium.

A device controller that controls data transfer of a device such as a drive that reads / writes data from / on a recording medium such as an HD (HardDisk) includes a combination of a DMA transfer method and a PIO transfer method as a data transfer method ( For example, see Patent Document 1).
JP 2005-242411 A

  In DMA transfer, data transfer is performed by a DMA controller, which is a dedicated LSI separate from the CPU, so that the CPU processing load is reduced and high-speed data transfer compared to PIO transfer in which the CPU performs transfer control. Is possible.

  By the way, in DMA transfer, data transfer between a data transfer memory and a device is performed in units of a predetermined data length (for example, 2 bytes). For this reason, when the data length transferred from the device is not a multiple of the unit data length, for example, half-length data such as the last one byte is not stored in the memory, and a part of the transfer data may be lost.

  Further, since the DMA controller performs data transfer with the transfer data length designated by the CPU, it is necessary to designate the transfer data length to the DMA controller in advance. In other words, when performing data transfer according to the command requested from the host device, the data length requested together with the command is designated as the transfer data length to the DMA controller, but the data transfer is performed. In some commands, the data length (actual data length) of data transferred from the device in response to the command does not match the data length (requested data length) requested from the host device. In this case, the following inconvenience occurs. In other words, if the actual data length is smaller than the requested data length, the transferred data length does not reach the designated transfer data length, so the data transfer is not completed, and conversely, the actual data length is the requested data length. If the length is greater than the length, the data transfer is completed when the transferred data length reaches the designated transfer data length, so that a part of the transfer data is lost.

  The present invention has been made in view of the above circumstances, and an object thereof is to prevent transfer data from being lost during DMA transfer.

  A first invention for solving the above-described problems includes at least a device that reads data from a recording medium, and data is transferred from the device in any one of a DMA transfer mode and a PIO transfer mode. A device control method by a control circuit of an electronic device that outputs data to a host device connected to an external bus standardized by a predetermined standard, and receiving a request command from the host device, Issuing a data transfer command according to the request command to the device, and as a transfer mode corresponding to the command for each command, the data length of the transfer data from the device according to the command is fixed and even For commands that are bytes, the DMA transfer mode is set in advance, and in other cases, the PIO transfer mode is set in advance. A device control method comprising: setting a transfer mode corresponding to the issue command based on the association; and performing data transfer according to the issue command in the set transfer mode It is.

  In addition, the second invention includes at least a device for reading data from a recording medium, and the data transferred from the device in any one of the DMA transfer mode and the PIO transfer mode is A program for causing a computer, which is a control circuit of an electronic device to output to a host device connected to an external bus standardized by a predetermined standard, to execute the device control method of the first invention.

  Further, the third invention incorporates at least a device for reading data from the recording medium, and the data transferred from the device in any one of the DMA transfer mode and the PIO transfer mode, A control circuit for an electronic device that outputs to a host device connected to an external bus standardized by a predetermined standard, a request command receiving unit that receives a request command from the host device, and the request command to the device A command issuing unit that issues a data transfer command according to the request command received by the receiving unit, and a data length of transfer data from the device according to the command as a transfer mode corresponding to the command for each command DMA transfer mode for commands with fixed and even bytes, PIO transfer otherwise A transfer mode setting unit for setting a transfer mode corresponding to the issue command, and a transfer mode set by the transfer mode setting unit based on the association. And a transfer control unit that performs data transfer according to the control circuit.

  The fourth invention includes at least a device for reading data from a recording medium and the control circuit of the third invention for controlling the device, and is hosted by an external bus standardized by a predetermined standard. An electronic device connected to the device.

  According to the first to fourth aspects of the present invention, there is provided a control circuit for an electronic device that includes a device for reading data from a recording medium and outputs data transferred from the device to the host device. When a data transfer command corresponding to the request command is issued and the data length of the transfer data from the device corresponding to the issued command is always an even number of bytes, the DMA transfer mode is set as the transfer mode. In this case, the PIO transfer mode is set as the transfer mode, and data transfer is performed according to the issued command in the set transfer mode. In the DMA transfer mode, since data transfer is performed in a predetermined unit (specifically, 2 bytes), if the data length of the transfer data from the device is not a multiple of the predetermined unit, the transfer data output to the host device However, as in the present invention, when the data length of transfer data is an even number of bytes, data transfer is performed in the DMA transfer mode, and in other cases, data transfer is performed in the PIO transfer mode. Such a loss of transfer data is prevented.

  Preferred embodiments of the present invention will be described below with reference to the drawings. In the following, an electronic apparatus having an HDD as a device will be described, but an embodiment to which the present invention can be applied is not limited to this.

[Constitution]
FIG. 1 is a configuration diagram of an electronic device 20 in the present embodiment. According to the figure, the electronic device 20 is connected to a host device 10 that is a PC by a bus 1 conforming to the IEEE 1394 standard. The host device 10 is not limited to a PC, and may be another electronic device such as a portable information terminal or a mobile phone. Further, the bus 1 is not limited to a bus conforming to the IEEE 1394 standard, and may be a bus conforming to the USB standard.

  The electronic device 20 includes a device controller 30 that is a control circuit and an IDE device 40 that is an HDD. The device controller 30 and the IDE device 40 are connected by a bus 2 that conforms to the ATA / ATAPI standard. Note that the electronic device 20 may include a plurality of IDE devices 40. In this case, the device controller 30 and the IDE device 40 are connected by the bus 2 and are recognized as one HDD as a whole by the host device 10. The IDE device 40 may be any device that can be connected to the ATA / ATAPI interface, and may be a storage device other than a hard disk such as an optical disk drive.

  The device controller 30 is realized by a microcomputer and controls data transfer between the host apparatus 10 and the IDE device 40. The device controller 30 includes a CPU 31, a DMA controller 32, a ROM 33, and a RAM 34.

  The CPU 31 performs various control processes including overall control of the device controller 30. Further, when a command request is input from the host device 10, the CPU 31 performs a transfer control process according to the transfer control program 331. In this transfer control process, a command requested from the host device 10 is analyzed, a command packet is generated, and a packet command to be output to the IDE device 40 is issued. Next, the command table 332 is referenced to determine the transfer mode of this command.

  FIG. 2 is a diagram illustrating an example of a data configuration of the command table 332. According to the figure, the command table 332 stores a transfer mode 332b and a data transfer direction 332c in association with each command 332a. The transfer direction 332c is a direction in which data input from the host device 10 is written to the IDE device 40 (H → D), or a direction in which data is read from the IDE device 40 and output to the host device 10 (H ← D). Here, the transfer mode of each command depends on the data length of the data transferred to the IDE device 40 in accordance with the command or the data transferred from the IDE device 40 (hereinafter referred to as “transfer data”). Determined. That is, the DMA transfer mode is set for a command whose transfer data length is fixed regardless of the IDE device 40 and the transfer data length is an even number of bytes, and the PIO transfer mode is set for other commands. ing. In the data transfer by the DMA transfer method, it is necessary to designate the transfer data length to the DMA controller 32, and data reading / writing to the data buffer 341 by the DMA controller 32 is performed in units of 2 bytes. Because.

  If the determined transfer mode is “DMA transfer mode”, the CPU 31 sets the transfer mode to the DMA transfer mode. Then, the DMA controller 32 is caused to perform data transfer using the data length (requested data length) requested together with the command from the host device 10 as the transfer data length. If the determined transfer mode is “PIO transfer mode”, the transfer mode is set to the PIO transfer mode. Next, the set value of the ByteCount register of the IDE device 40 is read and set as the transfer data length. In this “ByteCount register”, the data length of the response data for the issued command is set. Thereafter, data transfer of the set transfer data length is performed by the PIO transfer method.

  The DMA controller 32 is realized by an LSI, and controls data transfer between the data buffer 341 and the IDE device 40. Specifically, a read process for storing the data transferred from the IDE device 40 in the data buffer 341 or a write process for transferring the data stored in the data buffer 341 to the IDE device 40 is performed. At this time, data transfer with the IDE device 40 is performed with the transfer data length designated by the CPU 31, and data reading / writing from the data buffer 341 is performed in a predetermined unit (specifically, in units of 2 bytes). .

  The ROM 33 stores a system program for the CPU 31 to control the device controller 30 as a whole, and a program and data for realizing various processes including a transfer control process. In the present embodiment, the ROM 33 stores a transfer control program 331 and a command table 332. The RAM 34 is used as a work area for the CPU and has a data buffer 341 for temporarily storing transfer data.

[Process flow]
FIG. 3 is a flowchart for explaining the flow of the transfer control process performed by the CPU 31. According to the figure, the CPU 31 first generates a packet command in response to a command request from the host device 10 and issues a packet command to be output to the IDE device 40 (step S1). Next, with reference to the command table 332, the transfer mode defined in the command is determined (step S3).

  If it is determined that the transfer mode is “PIO transfer mode” (step S5: “PIO”), the data transfer mode is set to “PIO transfer mode” (step S7). Then, the setting value of the ByteCount register of the IDE device 40 is read and set as the transfer data length (step S9). Then, data transfer with the set transfer data length is performed with the IDE device 40 (step S11).

  On the other hand, if it is determined that the transfer mode is “DMA transfer mode” (step S5: “DMA”), the data transfer mode is set to “DMA transfer mode” (step S13), and the requested data length from the host device 10 is set. The transfer data length is set (step S15). Then, the DMA controller 32 is caused to perform data transfer with the IDE device 40 with the set transfer data length (step S17). When the above processing is performed, the transfer control processing ends.

[Action / Effect]
Thus, according to the present invention, in the electronic device 20, when the device controller 30 receives a command request from the host device 10, the device controller 30 issues a packet command corresponding to the request to the IDE device 40, and each command The command table 332 associated with the transfer mode is referred to, and data transfer with the IDE device 40 is performed in the transfer mode (DMA / PIO transfer mode) corresponding to the issued command. In the command table 332, the DMA transfer mode is set for a command whose transfer data length is fixed and the transfer data length is an even number of bytes, and the PIO transfer mode is set for other commands. In the data transfer by the DMA transfer method, it is necessary to designate the transfer data length to the DMA controller 32, and data reading / writing to the data buffer 341 by the DMA controller 32 is performed in units of 2 bytes. Because. Thereby, the loss of transfer data between the host apparatus 10 and the IDE device 40 is prevented.

The block diagram of an electronic device. Example of data structure of command table. The flowchart of a transfer control process.

Explanation of symbols

10 host device, 20 electronic device, 30 device controller, 31 CPU, 33 ROM, 331 transfer control program, 332 command table, 34 RAM, 341 data buffer, 32 DMA controller, 40 IDE device

Claims (4)

At least a device that reads data from the recording medium is built in, and the data transferred from the device in any one of the DMA transfer mode and the PIO transfer mode is standardized by a predetermined standard. A device control method by a control circuit of an electronic device that outputs to a host device connected to an external bus,
Receiving a request command from the host device;
Issuing a data transfer command in response to the request command to the device;
For each command, as a transfer mode corresponding to the command, the DMA transfer mode is used for a command in which the data length of the transfer data from the device corresponding to the command is fixed and an even number of bytes, and PIO transfer is otherwise performed. A mode is associated in advance and, based on the association, setting a transfer mode corresponding to the issued command;
Performing data transfer according to the issued command in the set transfer mode;
A device control method including:   At least a device that reads data from the recording medium is built in, and the data transferred from the device in any one of the DMA transfer mode and the PIO transfer mode is standardized by a predetermined standard. A program for causing a computer, which is a control circuit of an electronic device to output to a host device connected to an external bus, to execute the device control method according to claim 1. At least a device that reads data from the recording medium is built in, and the data transferred from the device in any one of the DMA transfer mode and the PIO transfer mode is standardized by a predetermined standard. A control circuit for an electronic device that outputs to a host device connected to an external bus,
A request command receiving unit that receives a request command from the host device;
A command issuing unit that issues a data transfer command according to the request command received by the request command receiving unit to the device;
For each command, as a transfer mode corresponding to the command, the DMA transfer mode is used for a command in which the data length of the transfer data from the device corresponding to the command is fixed and an even number of bytes, and PIO transfer is otherwise performed. Modes are associated in advance, and based on the association, a transfer mode setting unit that sets a transfer mode corresponding to the issued command;
A transfer control unit that performs data transfer according to the issue command in the transfer mode set by the transfer mode setting unit;
Control circuit with.   An electronic apparatus comprising at least a device that reads data from a recording medium and the control circuit according to claim 3 that controls the device, and is connected to a host device via an external bus standardized by a predetermined standard .

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