JP2009181443A - Equipment for industrial controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide equipment capable of responding to interlock even in a compile type program, and changing an interlock algorithm according to characteristics of an object program. <P>SOLUTION: The equipment includes an MPU 21 which arithmetically executes a user program containing a function block FB; and an FB instance storage area 23a which stores an interlock operation flag which specifies whether or not to execute a program in the FB in an interlock state. The section between an interlock start instruction and an interlock termination instruction described in the user program corresponds to the interlock area, and this area is laid in the interlock state when input corresponding to the start instruction is NO. The MPU determines, when an OUT instruction is executed, whether the interlock state or not, and sets the output OFF in the interlock state. The FB present in the interlock area of the interlock state performs execution/non-execution of the program based on the interlock operation flag. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to industrial controllers such as PLCs and PACs and industrial controller equipment such as CPU units constituting the industrial controllers.

  A network system in FA (Factory Automation) includes one or more PLCs (Programmable Logic Controllers) that control input devices and output devices in a production facility, and devices whose operations are controlled by the PLCs. Connected to the network. These PLCs and devices communicate with each other cyclically via the network of the control system, thereby sending and receiving IN data and OUT data (hereinafter referred to as I / O data) to control production facilities.

  Recently, a controller called PAC (Programmable Automation Controller) has been developed as a next-generation industrial controller. This PAC has the high accuracy and durability of a PLC in addition to the high speed, high functionality, and function expandability of a personal computer. The PAC, like the PLC, communicates with the equipment of the production facility via the network to transmit / receive I / O data and control the production facility.

Some industrial controllers such as PLC and PAC are configured by connecting a plurality of units. A CPU unit that supervises the control of an industrial controller, which is one of the units, executes a user program created in a ladder language or the like. For example, the CPU unit inputs an ON signal or an OFF signal of the input device as IN data, performs a logical operation on the input ON / OFF information by a user program, and outputs OUT data as a calculation result to the output device. The output becomes an operation instruction for the output device, and the output device operates to control the production facility. One of execution instructions of this user program is an interlock. In this interlock, when a predetermined contact that is one of the targets of IN data is turned OFF, the predetermined contact that is OUT data that is the target of the interlock area is fixed to OFF.
International Publication Number WO97 / 23812

  Since the conventional interlock is usually realized by dedicated hardware such as an ASIC chip, the flexibility of processing corresponding to the interlock is low from the viewpoint of the number of gates of the ASIC. For example, when a function block exists in the program in the interlock area, the function block program is fixed so as not to be executed. For this reason, even if there is a request such as calling a function block and executing a program to turn an internal contact ON / OFF, there are cases where it cannot be handled. Of course, since the original function of the interlock is to turn off the OUT contact in the interlock region, the final output contact may be turned off even if the function block is executed. Of course, there is an idea that it is not necessary to execute a function block (it is not desired to execute it), but there are cases where it is desired to execute it. However, the execution of the interlock by the conventional dedicated hardware cannot respond to the user's request for the execution / non-execution of the function block existing in the interlock area.

  An object of the present invention is to provide an industrial controller device that can flexibly cope with an interlock in a user program and can change an interlock algorithm in accordance with the characteristics of a target program.

  Conventional interlocks are implemented with dedicated hardware and do not assume compiled programs. In the present invention, the user program including flexible function blocks and other POUs can be designed by realizing the interlock by software. For example, when the user individually selects whether the interlock is valid or invalid for a POU such as a function block (FB), even if the interlock area where the POU exists is in the interlock state, Instructions can be executed or not executed. Specifically, the configuration is as follows.

(1) An industrial controller device according to the present invention includes an arithmetic unit that executes a user program including a POU that is a program constituent unit composed of a plurality of instruction words;
A storage unit that stores operation information at the time of interlocking that specifies whether or not to execute an instruction in the POU in the interlock state. When the interlock start instruction and the interlock end instruction that are paired are described, the user program has an interlock area between the two instructions, and the input corresponding to the interlock start instruction is in the interlock state. In the case of the indicated value, the interlock area is set to the interlock state. When executing the OUT instruction in the user program, the arithmetic unit determines whether or not the interlock area including the OUT instruction is in an interlock state, and executes the set interlock process in the case of the interlock state. When the POU existing in the interlock area in the interlock state is executed, the operation information at the time of interlock of the storage unit is confirmed, and the instruction in the POU is executed / not executed based on the confirmation result And a function.

  The industrial controller device may be a single CPU unit 2 according to the embodiment, or a concept including an industrial controller itself such as a PAC including the CPU unit 2. In the case of an industrial controller, not only those configured by connecting a plurality of units as in the embodiment, but also an integrated controller in which necessary functions are incorporated in one housing.

  POU is an abbreviation for “Program Organization Unit” and is also referred to as a program configuration unit. This POU is a minimum unit in program management composed of a plurality of instruction words, and is called a program, function, or function block. The program can be reused in this POU unit.

  The calculation unit corresponds to the MPU 21 in the embodiment. In the embodiment, whether or not the interlock area is in the interlock state can be known by referring to the value of “isInterLock”. As described above, when the identification information for identifying the interlock state / normal state is appropriately set and updated, the arithmetic unit performs normal processing only by referring to the corresponding identification information when executing the OUT instruction. Or whether to perform interlock processing. In the embodiment, the interlock operation information corresponds to an interlock operation flag.

  According to the present invention, each time an OUT instruction is executed, it is checked whether or not it is in an interlock state, and if it is in an interlock state, processing corresponding to that (such as output OFF or instruction non-execution) is performed. If it is in the state, normal arithmetic processing is performed. Thereby, the interlock by software is realizable. Then, by appropriately setting the operation information at the time of interlock, it is possible to individually set whether or not to execute the POU existing in the interlock area in the interlock state. In particular, when the POU has an internal variable such as a function block, it is preferable because the internal variable can be updated by executing the program even in the interlock state.

  (2) The user program is allowed to nest an interlock area in which another interlock start instruction and an interlock end instruction are arranged in an interlock area surrounded by an interlock start instruction and an interlock end instruction. A data area for storing a state determination flag indicating whether the input corresponding to the lock start instruction is an interlock state or a normal state is provided, and the arithmetic unit, for a nested interlock area, includes the nested interlock area. If at least one of the state determination flag corresponding to the state and the state determination flag flag corresponding to another interlock region set so as to include the interlock region indicates the interlock state, the nested state Process the interlock area as an interlock state. Then good. Thereby, interlock nesting can be realized.

  (3) A pair of interlock start instructions and interlock end instructions are described in the POU, and the arithmetic unit may execute a corresponding process depending on whether or not the POU is in the interlock state.

  (4) Furthermore, the present invention is an industrial controller device including an operation unit that performs an operation of a user program including a POU that is a program constituent unit composed of a plurality of instruction words. When an interlock start instruction and an interlock end instruction are described, the section enclosed by both instructions becomes the interlock area, and when the input corresponding to the interlock start instruction is a value indicating the interlock state, the interlock area To be in an interlock state. Then, when executing the OUT instruction in the user program, the arithmetic unit determines whether or not the interlock area including the OUT instruction is in the interlock state, and in the case of the interlock state, the set interlock process May be provided with a function of executing

  According to the present invention, in an industrial controller device, the interlock in the user program can be flexibly dealt with individually, and the interlock algorithm can be set or changed in accordance with the characteristics of the target program.

  FIG. 1 shows one form of a programmable automation controller (abbreviated as PAC) 1 which is a kind of industrial controller to which the present invention is applied. The PAC1 is configured by connecting a plurality of units for realizing various functions, and each unit is connected by an internal bus. The plurality of units have at least one CPU unit 2. Furthermore, in the present embodiment, the PAC 1 includes a power supply unit 3, a motor unit 4, a counter unit 5, an image unit 6, a communication unit 7, and an I / O unit 8. Of course, the units constituting the PAC1 are not limited to those described above, and the necessary units are appropriately selected according to the control to be executed. For example, a combination of “CPU unit + motor unit + counter unit” and “CPU unit + I / O unit” is also effective for PAC. In the present embodiment, PAC1 is described as an example, but the present invention can be similarly applied to PLC.

  Various detailed settings are made in advance for the CPU unit 2 and other units. In that case, as shown in the figure, the user connects a personal computer to the CPU unit 2 and starts a setting tool program which is an application program installed in the personal computer, and uses the setting tool program to control the program (user (Also called a program) is created or edited and stored in the CPU unit, settings relating to inter-unit communication, and various detailed settings for operating various units. The CPU unit 2 is basically a process for fetching IN data via an input unit or a communication unit (IN refresh process), a process for calculating and executing a control program based on the fetched IN data (user program execution process), Processing for outputting OUT data to an output unit or the like (OUT refresh) is performed. The power supply unit 3 converts commercial power / AC voltage into a DC voltage corresponding to each unit, and supplies power to each connected unit. Note that a configuration in which a power supply unit is not connected may be made by directly supplying a DC voltage to each unit. The motor unit 4 can connect one or more servo drives (servo motor and its control device) and controls the servo motor. The counter unit 5 connects one or more rotary encoders, takes a pulse signal from the encoder, and measures the amount of rotation and the amount of movement of the target object. The image unit 6 connects one or more cameras, performs desired image processing on the images from the cameras, and measures the amount of movement of the object to be imaged, the number of parts, and the like. The communication unit 7 transmits / receives data to / from other industrial controllers connected to the network. The I / O unit 8 is an input unit that connects input devices such as sensors and switches in the equipment and takes in the on / off signals as input signals, and an actuator and relay that are controlled by the equipment. An output unit that connects output devices and sends output signals to them. An input / output unit having both an input function and an output function is also included.

  These units are electrically connected by connecting connectors provided on the side surfaces of the units. With this connection, the units are connected to each other using an internal bus (parallel communication), a high-speed serial communication line, and the like, and data is transmitted and received between the units.

  FIG. 2 shows the internal configuration of the CPU unit 2. The CPU unit 2 includes an MPU 21, a peripheral controller 22, a memory 23, and a communication interface 24. The MPU 21 is a high-performance device that is also mounted on a personal computer or the like, and executes predetermined arithmetic processing. The MPU 21 operates by scanning a plurality of tasks divided for each execution cycle at regular intervals. That is, the tasks to be executed by the MPU 21 include, for example, a task that should be executed at a cycle of 1 ms and a task that should be executed at a cycle of 2 ms. Of course, there may be tasks with various periods such as 4 ms, 8 ms, and so on. Therefore, the MPU 21 calculates a task having a cycle to be executed by multitask processing. Each task executes a user program written in, for example, a ladder language. In the case of a conventional PLC, there is no concept of the execution cycle for each task described above, a series of control programs that collectively describe programs corresponding to each task are executed in order from the top, and IO refresh and peripheral processing are performed. One cycle process including the above is cyclically repeated, but the PAC1 of the present embodiment is different in that the multitask process (time division process) is performed as described above. Note that the multi-task processing may not be synchronized with the IN refresh processing and the OUT refresh, or may be synchronized. Further, the PAC does not necessarily perform multitask processing, but may perform processing cyclically as in the past.

  The peripheral controller 22 is also referred to as a chip set, and has a memory 23, an interface 24, and the MPU 21 to perform arbitration and timing adjustment. Thereby, MPU21 can concentrate on a calculation. The memory 23 is used as a work memory when the MPU 21 performs arithmetic processing, for example. The communication interface 24 is an interface for connection with a personal computer constituting a setting tool device. Although not shown, a communication interface for communicating with other slaves (units) is also provided. The communication unit as a slave communicates via a communication medium (internal bus, high-speed serial communication line) mounted in the PAC1.

  In the present embodiment, since description of a program by function blocks (Function Blocks: FB) is allowed, an FB instance storage area 23a that is a data area for storing instances of each function block is provided on the memory 23. . As shown in FIG. 3A, the FB instance storage area 23a set in the memory 23 secures necessary information independently for each function instance, and is mainly composed of three areas. The In other words, a flag that specifies whether or not to call a function block at the time of interlocking (operation flag at the time of interlocking), a data area that stores each data held by the function block instance, and a pointer that indicates processing at the time of function block execution It is. This pointer corresponds to the “procedure” in FIG. The pointer information is a place for storing information for specifying a specific execution process of the FB definition (function block definition) stored in the memory 23. That is, what is pointed by this pointer is a function block definition, which is an area in which a program for specific execution processing (see FIG. 5) is stored.

  Supplementally, a function block is conceptually composed of a type and an entity. A type represents a data type and a procedure, and is a template of an entity. An entity is generated from a template. Corresponding to this, the function block is stored in the memory area as an FB definition and an FB instance area. Necessary information is secured in the FB instance area independently for each function block instance, and information common to the same function block instance is secured in the FB definition. Data is a representative example of the FB instance area, and a procedure is a representative example of the FB definition. Since the procedure is secured in the FB definition, a pointer indicating processing at the time of function block execution represents the FB definition.

  The MPU 21 confirms the interlock operation flag when the function block is called. If it is ON, the MPU 21 calls the function block during the interlock and executes the function block program. If OFF, the function block program is not called during interlocking, and the function block program is not executed.

  Furthermore, in the present embodiment, a data area 23b for storing a state determination flag is provided on the memory 23 in order to realize a nested interlock. As shown in FIG. 3B, in this embodiment, the data area 23b is secured for 8 bits, and each bit corresponds to one level of interlock nesting. When a certain interlock area is in an interlock state, the corresponding bit (state determination flag) is 0, and when a certain interlock area is in a normal state other than the interlock state, the corresponding bit (for state determination) The flag is controlled to be 1. As a result, it is understood that if at least one bit has a state determination flag of 0, it is in an interlock state, and if all bits have a state determination flag of 1, it is in a normal state.

  Next, the interlock of the nested structure that is executed by the CPU unit 2 will be described using a user program described in a specific ladder diagram. FIG. 4 shows a ladder diagram using an interlock instruction. In the figure, “MILH” is an interlock start command, and “MILC” is an interlock end command. Also, the interlock start instruction and the interlock end instruction to be paired are specified by the same interlock number (“0”, “1” in the figure). The area between the interlock start instruction and the interlock end instruction is an interlock area. During the interlock, output contacts ("MILH 0" to "MILC" in the figure) exist in the interlock area. “0002.00” and “H00.00” sandwiched between 0 are OFF (0), and OUT-related commands such as the SET command and the CNT command are not executed.Interlock is an input associated with the interlock start command. Interlocked when the contact ("W000.00", "W000.01" in the figure) is OFF.

  Further, in the present embodiment, nests in which another pair of MILH and MILC are arranged in a nested state are allowed in the interlock region that is a section from the pair of MILH to MILC. In the example shown in the figure, a nested structure is formed in which the interlock regions “MILH 1” to “MILC 1” are arranged in the interlock regions “MILH 0” to “MILC 0”.

  According to this program, when the input contact W000.00 of MILH 0 0100.00 and the input contact W000.01 of MILH 1 0100.01 are both ON, the commands in the interlock area are all executed normally without being interlocked.

  When the input contact W000.00 of MILH 0 0100.00 is OFF, the outputs in the interlock region from MILH 0 to MILC 0 are interlocked. In other words, the nested “MILH 1” and “MILC 1” are input contacts W000 of the interlock start instruction “MILH 1” when the outer “MILH 0” and “MILC 0” are interlocked. Regardless of the value of .01, the output in the region from MILH 1 0100.01 to MILC 1 is also interlocked. Therefore, since the interlock is in progress, the MPU 21 turns off the output contacts 0002.00 and H00.00, and the SET 0002.03 and CNT 1 # 0010 instructions remain at the values of the previous cycle (hold).

  On the other hand, when the input contact W000.00 of MILH 0 0100.00 is ON and the input contact W000.01 of MILH 1 0100.01 is OFF, the interlock start command of “MILH 0” is not interlocked and “MILH 1” The interlock is activated by the interlock start command. Accordingly, the region from MILH 0 0100.00 to MILH 1 0100.01 is executed as usual, and the MPU 21 writes the value (ON / OFF) of the input contact 0000.01 to the output contact 0002.00. Since the output of the interlock area from MILH 1 0100.01 to MILC 1 is interlocked, the MPU 21 turns off the H00.00 contact in that area and keeps SET 0002.03 at the value of the previous cycle. The MILC 1 to MILC 0 area is executed as usual, and the MPU 21 executes the CNT instruction based on the two input contacts (0000.04,0000.05).

  In the present embodiment, it is determined whether or not the interlock state is established, and in the interlock state, the processing during the interlock is performed by software instead of dedicated hardware. ing. As a result, it is possible to flexibly deal with the interlock in the user program, and to deal with a change in the interlock algorithm in accordance with the characteristics of the target program.

  The MPU 21 determines whether it is in the interlock state or the normal state before executing the process at the location where the process differs depending on whether or not it is in the interlock state, such as an output contact or various instructions, and according to the state Execute the process. Specifically, in the case of the program shown in FIG. 4, the MPU 21 executes the following processing.

(1) The MPU 21 reads W000.00, which is a 1-bit value, and writes the read value in a data storage area (Power Flow, hereinafter referred to as PF) called a power flow. Next, the MPU 21 executes the MILH 0 0100.00 instruction. That is, the MPU 21 determines to enter the interlock state if the PF is 0, and to continue the normal state if the PF is 1.

(2) The MPU 21 reads 0000.01 and writes the value to the PF. Next, the MPU 21 executes the OUT 0002.00 instruction. That is, the MPU 21 turns OFF 0002.00 in the interlock state, and writes the PF value in 0002.00 in the normal state.

(3) The MPU 21 reads W000.01 and writes it to the PF. Next, the MPU 21 executes the MILH 1 0100.01 instruction. In other words, the MPU 21 enters an interlock state when the PF is 0, and continues the normal state when the PF is 1.

(4) The MPU 21 reads 0000.02 and writes it to the PF. The MPU 21 executes the OUT H00.00 instruction. That is, the MPU 21 turns off H00.00 in the interlock state, and writes the value of PF in H00.00 in the normal state.

(5) The MPU 21 reads 0000.03 and writes it to the PF. If the MPU 21 is in the interlock state, the SET 0002.03 instruction is not executed and the previous value remains unchanged. If the MPU 21 is in the normal state, the SET 0002.03 instruction is executed. If the PF is ON, 0002.03 is turned ON.

(6) The MPU 21 executes a MILC 1 instruction, that is, an interlock end instruction. A specific processing algorithm of the interlock end instruction will be described later.

(7) The MPU 21 reads 0000.04 and writes it to the PF. The MPU 21 pushes the PF onto the stack, reads 0000.05, and writes it to the PF. Then, the MPU 21 executes the CNT 1 # 0010 instruction.

(8) The MPU 21 executes a MILC 0 instruction which is an interlock end instruction.

  FIG. 5 shows another example of a ladder diagram using a nested interlock instruction. This program is different from FIG. 4 in that the function block 1 is included. FIG. 6 shows an example of the function block 1 program. A function block (Function Block, FB) is a functional component that possesses data for each instance that is the substance of a function block. Even in the case where a function block exists in this manner, each command in all areas is similar to the case of FIG. 4 according to the ON / OFF state of W000.00 and W000.01 which are input contacts for the interlock start command. It is possible to flexibly cope with the normal state in which the process is executed normally, the region from MILH 0 0100.00 to MILC 0 is in the interlock state, or only the region from MILH 1 0100.01 to MILC 1 is in the interlock state. It is like that.

  In the case of the program shown in FIG. 5, the MPU 21 functions so that the process (5) described above executes the process (5) ′ described below.

(5) 'The MPU 21 reads 0000.03 and writes it to the PF. The MPU 21 calls the FB EN instruction and the ENO instruction. In the case of the function block shown in FIG. 6, the MPU 21 reads EN and writes it to the PF. Next, the MPU 21 executes an OUT isRun instruction. That is, the MPU 21 turns off isRun if it is in the interlock state, and writes the value of PF in isRun if it is in the normal state. Here, isRun is a BOOL type local variable defined in the function block. As is clear from FIG. 6, the function block of this embodiment is permitted to use the interlock start instruction MILH and the interlock end instruction MILC in the internal program. Depending on the value of the input contact EN paired with MILH numIL, a predetermined area of the internal program of the function block becomes an interlock state or a normal state.

  The MPU 21 executes the MILH numIL isIL instruction. The MPU 21 enters an interlock state from MILH numIL if the PF is 0, and continues the normal state if the PF is 1.

  The MPU 21 reads P_On, which is an always-on flag, and writes it to the PF. The MPU 21 executes the OUT ENO instruction. The MPU 21 turns off ENO in the interlock state, and writes the value of PF into ENO in the normal state. Then, the MPU 21 executes the MILC numIL instruction. Thereby, the execution of the internal program of the function block is completed.

  Next, when executing the process for the output contact H00.01, the MPU 21 determines whether or not it is in an interlock state. If it is in the interlock state, H00.01 is turned OFF, and if it is in a normal state, the value of PF is set to H00.01. Write.

  FIG. 7 shows a schematic flowchart of cycle processing in PAC1 (MPU 21 of CPU unit 2), and FIG. 8 shows a detailed flowchart of processing for one task and peripheral services.

  First, when the system power is turned on, the MPU 21 performs processing when the power is turned on (S1). This power-on processing includes initialization of hard memory and system work, recognition of mounted units, automatic transfer processing from memory card when power is turned on, verification of mounted units and registered I / O tables, I / O memory There are various processes such as clearing the area and forcibly setting / resetting. This process is the same as in the case of a conventional PLC.

  Next, the MPU 21 generates threads for the number of registered tasks, and executes the threads generated according to appropriate scheduling. Each task can be a plurality of tasks divided for each execution cycle, for example. Then, the MPU 21 operates by scanning each at regular intervals.

  In each thread, the MPU 21 first performs common processing (S2). That is, as shown in FIG. 8, the MPU 21 performs battery abnormality check, memory card attachment / detachment check, dip switch monitoring, I / O bus check, user program memory check, and the like (S2a). Then, the MPU 21 determines whether or not the check result is normal (S2b). If normal, the MPU 21 ends the common process and performs IN refresh for exchanging data with the input unit (S3). When the check result is abnormal, the MPU 21 sets a corresponding abnormal relay (S2c). Along with this, an LED for notifying abnormality is turned on / flashing or an alarm sounds. The MPU 21 determines whether or not the above types can continue operation (S2d). If it can be continued (Yes in S2d), the common process is terminated and IN refresh is performed (S3). In the case of an abnormality that stops the operation (No in S2d), the MPU 21 performs OUT refresh without performing IN refresh and subsequent arithmetic processing (S5).

  After executing the IN refresh, the MPU 21 performs arithmetic processing (S4). That is, the MPU 21 executes the user program in order from the top of the program (S4a), determines whether or not the user program has ended (S4b), and if not, returns the process to the execution of the user program. By repeatedly executing these processing steps S4a and S4b, the MPU 21 executes the user program up to the last line. If the user program has ended (S4b is Yes), the MPU 21 performs a cycle time calculation process (S4c). That is, the time until the next cycle time that is the execution cycle is calculated and set. Then, the MPU 21 stops until the set cycle time is reached (S4d).

  When the set cycle time is reached, the MPU 21 executes OUT refresh for exchanging data with the output unit (S5). Thereafter, the MPU 21 returns to the execution of the common process in process step S2.

  The MPU 21 repeatedly executes the above processing steps S2 to S5 by parallel processing for each task. Further, the MPU 21 generates one task for performing only the peripheral service in addition to the above-described task for performing the calculation, and executes it according to the scheduling. That is, the MPU 21 repeatedly executes the process (S7) for executing the peripheral service after executing the common process (specifically, the process steps S2a to S2c) (S2 '). Peripheral services include, for example, those that are executed only when an event occurs, event services with high-function I / O units, event services with CPU high-function units, RS-232C port services, communication port services, etc. is there.

  Here, the processing / function of the MPU 21 in the case of executing the program shown in FIGS. 5 and 6 will be described for the arithmetic processing (S4), in particular, the execution of the user program (S4b). As shown in FIGS. 9 and 10, the MPU 21 reads W000.00 of the input contact and writes the read value (0/1) to the PF (S11).

  Next, the MPU 21 executes an interlock start command (MILH 0 0100.00) (S12). Specifically, the execution process of the interlock start command executes the flowchart shown in FIG. Here, “n” which is the first operand of “MILH is isInterLock” shown in FIG. 11 represents an interlock number. When the data area 23b shown in FIG. 3B is used, n is 0 or more and less than 8. n may be described as a specific numerical value or may be described as a variable. The second operand (isInterLock) represents a Boolean variable indicating that the interlock is being performed. During interlock, isInterLock is 0, and is 1 in the normal state. N and isInterLock may be described by specific numerical values or may be described by variables. Further, in relation to the three stages (MILH / number / address) of the symbol indicating the interlock start instruction, “n” corresponds to the middle number and “isInterLock” corresponds to the lower address. That is, the value of isInterLock is written to the address specified by the interlock start instruction. The general processing of the interlock start instruction (MILH instruction) is as follows.

  First, the MPU 21 writes the value of the PF in nbit of the data area 23b (S41). In the case of the processing step S12, since the code n is “0”, the read PF (0/1) value is written in the 0-bit position of the data area 23b.

  Next, the MPU 21 checks whether all 8 bits of the data area 23b are 1 (S42). If any one of the bits has 0, this branch determination is No and the interlock state is established. If all the data areas 23b are 1, the normal state is entered (S42 is Yes), and the MPU 21a writes 1 to isInterLock and ends the execution of the MILH instruction (S43). That is, in the case of the processing step S12, 1 is written in the area of the address “0100.00”. On the other hand, when even one 0 exists in 8 bits of the data area 23b (No in S42), the interlock state is set, and the MPU 21a writes 0 to isInterLock and ends the MILH instruction execution (S44). . That is, in the case of the processing step S12, 0 is written in the area of the address “0100.00”.

  When the execution of the interlock start instruction (MILH 1 0100.00) is completed as described above, the MPU 21 reads 0000.01 and writes it to the PF (S13). Next, the MPU 21 executes the OUT2.00 instruction. In other words, the MPU 21 confirms whether or not it is currently in the interlock state (S14). If it is in the interlock state, 2.00 is set to 0 (S16), and if it is in the normal state, PF is written in 2.00 (S15). Whether it is in the interlock state or not can be determined based on the value (1/0) stored in the area of address “0100.00” which is is InterLock.

  Next, the MPU 21 reads W000.01 and writes it in the PF (S17). Then, the MPU 21 executes an interlock start command (MILH 1 0100.01) (S18). That is, the MPU 21 executes the flowchart shown in FIG. Specifically, the MPU 21 writes the value of PF (the value of W000.01 of the input contact) in 1 bit of the data area 23b (S41). Next, the MPU 21 confirms whether all 8 bits of the data area 23b are 1 (S42). If any one of the bits has 0, this branch determination is No and the interlock state is established. If all the data areas 23b are 1, the normal state is entered (S42 is Yes), the MPU 21a writes 1 to isInterLock (0100.01), and ends the MILH instruction execution (S43). On the other hand, if even one 0 exists in 8 bits of the data area 23b (S42: No), the interlock state is entered, and the MPU 21a writes 0 to isInterLock (0100.01) and ends the MILH instruction execution. (S44).

  This interlock start instruction (MILH 1 0100.01) is a nested structure. In the interlock area from the interlock start instruction (MILH 1 0100.01) to the interlock end instruction (MILC 1), as described in FIG. When the paired input contact W000.01 is OFF, the interlock state is established. Even when the input contact W000.01 is ON, if the input contact W000.00 is OFF and the interlock start command (MILH 1 0100.00) is already in the interlock state, the interlock start command (MILH 1 0100.01) to the interlock end command (MILC 1) is in the interlock state. This can be dealt with by appropriately rewriting the state determination flag stored in each bit of the data area 23b. That is, when W000.01 is 0 (OFF), 0 is written to the PF, so 0 is written to the 1-bit (n = 1) area of the data area 23b. Accordingly, since at least the 1-bit portion is 0, the branch determination in processing step S42 is No, and 0 is written in isInterLock (0100.01), so that the interlock state is entered. On the other hand, when W000.01 is 1 (ON), 1 is written to the PF, so 1 is written to the 1 bit (n = 1) area of the data area 23b. At this time, if W000.00 is 0 (OFF), 0 is written in the 0-bit (n = 0) area of the data area 23b as the processing step S12 is executed. Therefore, regardless of the value of the 1-bit area, the branch determination in processing step S42 is No and 0 is written to isInterLock (0100.01), so that the interlock state is entered. When both W000.01 and W000.01 are 1 (ON), 1 is written in the 0-bit and 1-bit areas of the data area 23b, and 1 is still written as the initial value in the other areas. Therefore, all the bits in the data area 23b become 1, and the branch determination in the processing step S42 becomes Yes and the normal state is set.

  When the execution of the interlock start instruction (MILH 1 0100.01) is completed as described above, the MPU 21 reads 0.02 and writes it to the PF (S19). Next, the MPU 21 executes the OUT H0.00 instruction. That is, the MPU 21 confirms whether or not it is currently in the interlock state (S20), and if it is in the interlock state, H0.00 is set to 0 (S22), and if it is in the normal state, PF is written in H0.00 (S21). Whether it is in the interlock state or not can be determined based on the value (1/0) stored in the area of address “0100.01” which is is InterLock.

  Next, the MPU 21 reads 0000.03 and writes it to the PF (S23). Then, the MPU 21 calls a function block (S24). Specifically, the function block calling process executes the flowcharts shown in FIGS.

  The MPU 21 refers to the data area 23b and checks whether all are 1 (S51). Then, the MPU 21 determines that the interlock state is present even if one 0 exists, and determines that the normal state is present when all 0s are present.

  In the normal state, the MPU 21 checks the PF value (0000.03 value) (S52). If PF is 0, the function block call processing is terminated. When PF is 1, the MPU 21 sets the input value of the function block (S53) and executes the function block (FB) (S54). Specifically, the function block execution processing executes the flowcharts shown in FIGS.

  That is, the MPU 21 executes the function block program in order from the top (S61), determines whether or not the program has ended (S62), and if not, returns the process to the execution of the function block program. By repeatedly executing the processing steps S61 and S62, the MPU 21 executes the function block program up to the last line. Then, when the program ends, the function block execution process ends.

  Regarding the execution of the function block program (S61), the processing and function of the MPU 21 when executing the program shown in FIG. 6 will be described. As shown in FIG. 15, the MPU 21 reads EN and writes it into the PF (S71). Next, the MPU 21 performs a write process to isRun. Since isRun is an OUT system, it is checked whether or not it is in an interlock state prior to writing processing (S72). If it is in an interlock state, 0 is written to isRun (S74), and if it is in a normal state, isRun PF is written in (S75). In the function block execution process of process step 54, since it is known that the normal state is determined by the branch determination in S51, the MPU 21 writes the value of PF in isRun.

  Next, the MPU 21 executes an interlock start instruction (MILH numIL isIL) (S75). That is, the MPU 21 executes the flowchart shown in FIG. Specifically, the MPU 21 writes the value of PF (the value of EN of the input contact) in a predetermined bit (bit corresponding to the numerical value specified by numIL) in the data area 23b (S41). Note that numIL is an internal variable of the function block, and is a numerical value from 2 to 7 here. Next, the MPU 21 confirms whether all 8 bits of the data area 23b are 1 (S42). If any one of the bits has 0, this branch determination is No and the interlock state is established. If all the data areas 23b are 1, the normal state is entered (S42 is Yes), and the MPU 21a writes 1 to isInterLock (address specified by isIL), and ends the MILH instruction execution (S43). On the other hand, if even one 0 exists in 8 bits of the data area 23b (S42 is No), the interlock state is set, and the MPU 21a writes 0 to isInterLock (isIL) and ends the execution of the MILH instruction. (S44).

  When the execution of the interlock start instruction (MILH numIL isIL) is completed as described above, the MPU 21 reads P_On and writes it to the PF (S76). Next, the MPU 21 writes to the ENO that is the output of the function block. Prior to this writing, the MPU 21 checks whether or not it is currently in an interlock state (S77). If the interlock state is established, 0 is written to ENO (S79), and if it is a normal state, PF is written to ENO (S78). . Next, the MPU 21 executes an interlock end instruction (MILC numIL) and ends the function block execution process (S80).

  Specifically, the execution process of the interlock end instruction executes the flowchart shown in FIG. Here, “n” which is the first operand of “MILC n” shown in FIG. 12 represents an interlock number. The same interlock number as the interlock start instruction to be paired is described. This MILC n instruction is used to indicate that the interlock region starting with the MILH n second operand is to be terminated. The general processing of the interlock end instruction (MILC instruction) is as follows.

  First, the MPU 21 writes 1 in the nbit of the data area 23b (S45). Then, the MPU 21 checks whether all the data areas 23b are 1 (S46). If all the data areas 23b are 1, the normal state is entered (S46 is Yes), the MPU 21a writes 1 to isInterLock, and ends the MILC instruction execution (S47). That is, in the case of the processing step S80, 1 is written in the area of the address “isIL”. On the other hand, if even one 0 exists in 8 bits of the data area 23b (No in S46), 0 is written in isInterLock, and the MILC instruction execution is terminated while the interlock state is continued (S48). That is, in the case of the processing step S80, 0 is written in the area of the address “isIL”. In the case of processing step 54, since the interlock areas (MILH1 to MILC1) where the function block 1 exists are in the normal state, the execution of the processing step of S45 causes all the bits in the data area 23b to be 1, It becomes a normal state.

  When the execution of the interlock end instruction (MILC numIL) is completed as described above, the processing of step S54 in FIG. 13 is completed, so the MPU 21 sets the output value of the function block (FB), and the function Block call processing is terminated.

  On the other hand, if any one of the data areas has 0 and is in the interlock state (No in S51), the MPU 21 accesses the FB instance area 23 and sets the “operation flag at interlock” of the corresponding function block instance. Confirm (S56). If the flag is ON (indicating that FB execution is effective at interlock), the MPU 21 sets the input value of the function block (FB) as in the normal state (S57) and executes the function block. (S58), the output value of the function block (FB) is set (S59), and the function block call processing is terminated. These processing steps S57, S58, and S59 are the same as S53, S54, and S55, respectively.

  On the other hand, when the “interlock operation flag” is OFF (indicating that the FB execution at the time of interlock is invalid), the function block call processing is terminated as it is. By doing in this way, even if it is a function block in an interlock state, the function block program can be executed or not executed. In addition, since the operation flag at the time of interlock is set for each function block instance, it is possible to individually execute or not execute the function block in the interlock area.

  If the function block calling process (S24) is completed by the above process, the process returns to the process step S25 of FIG. 10, and the MPU 21 executes the OUT H00.01 instruction. That is, the MPU 21 confirms whether or not the interlock state is established (S25). This confirmation can be made based on the written value (1/0) by accessing “0100.01”. Then, the MPU 21 sets H00.01 to 0 in the interlock state (S27), and writes PF to H00.01 in the normal state (S26). Next, the MPU 21 executes an interlock end instruction (MILC 1) (S29). That is, the MPU 21 executes the flowchart shown in FIG.

  Next, the MPU 21 reads 0000.04 and writes it in the PF (S30). Next, the MPU 21 loads the PF on the stack, reads 0000.05, and writes it to the PF (S31, S32). Then, the MPU 21 executes the CNT 1 # 10 instruction based on the PF and the values of 0000.04 and 0000.05 loaded on the stack (S33). Then, the MPU 21 executes an interlock end instruction (MILC 0) (S34). That is, the MPU 21 executes the flowchart shown in FIG. By executing this end instruction, all the bits in the data area 23b return to 1. This completes the arithmetic processing.

  In the above-described embodiment, an example in which a “function block” that is a block having an input / output variable and an internal variable is included in the program has been described. However, the present invention is not limited to a function block. It may be a “function” that does not have internal variables in a block obtained by expanding a combination of operations in an industrial controller such as a PAC, or may be a “program” that is a main program including I / O and global variables. Thus, the present invention can be applied to POU (Program Organization Unit) such as “function block”, “function”, and “program”. In other words, an appropriate set such as a block is associated with a flag (operation flag at interlock) that specifies whether or not to execute at the time of interlocking (calling) or not, and is interlocked at the time of calculation execution. When there is a POU in the interlock area, it is possible to refer to the flag and execute or not execute the calculation of the POU.

It is a figure which shows an example of PAC. It is a figure which shows an example of the internal structure of a CPU unit. It is a figure which shows an example of the internal structure of memory. It is a figure which shows an example of the program for demonstrating an interlock. It is a figure which shows an example of the program containing the function block for demonstrating an interlock. It is a figure which shows an example of the program of a function block. It is a flowchart which shows the function of MPU. It is a flowchart which shows the function of MPU. It is a flowchart (the 1) which shows the function (user program execution function) of MPU. It is a flowchart (the 2) which shows the function (user program execution function) of MPU. It is a flowchart which shows the function (interlock start command execution function) of MPU. It is a flowchart which shows the function (interlock end command execution function) of MPU. It is a flowchart which shows the function (function block call instruction execution function) of MPU. It is a flowchart which shows the function (function block execution function) of MPU. It is a flowchart which shows the function (function block execution function) of MPU.

Explanation of symbols

1 PAC
2 CPU unit 21 MPU (control unit)
23 Memory (storage unit)
23a FB instance storage area 23b Data area

Claims (4)

A computing unit that computes and executes a user program including a POU that is a program constituent unit composed of a plurality of instruction words;
A storage unit that stores operation information at the time of interlocking that specifies whether or not to execute an instruction in the POU in the interlock state;
With
In the user program, when an interlock start instruction and an interlock end instruction to be paired are described, a section surrounded by both instructions becomes an interlock area, and an input corresponding to the interlock start instruction is in an interlock state. In the case of the value shown, the interlock area is set to the interlock state,
The computing unit is
A function for determining whether or not an interlock area including the OUT instruction is in an interlock state when executing the OUT instruction in the user program, and executing a set interlock process in the case of the interlock state; ,
A function of confirming the operation information at the time of interlock of the storage unit when executing the POU existing in the interlock area in the interlock state, and executing / non-executing instructions in the POU based on the confirmation result; ,
Industrial controller equipment characterized by comprising: The user program is allowed to nest an interlock area in which another interlock start instruction and an interlock end instruction are arranged in an interlock area surrounded by an interlock start instruction and an interlock end instruction.
A data area for storing a state determination flag indicating whether the input corresponding to the interlock start command is an interlock state or a normal state;
For the nested interlock area, the calculation unit includes a state determination flag corresponding to the nested interlock area of the data area and another interlock set to include the interlock area. 2. The industrial use according to claim 1, wherein, when at least one of the state determination flags corresponding to the region indicates an interlock state, the nested interlock region is processed as the interlock state. Controller equipment.   2. The interlock start instruction and the interlock end instruction that are paired are described in the POU, and the arithmetic unit executes a corresponding process depending on whether or not the POU is in the interlock state. Or the apparatus for industrial controllers of 2. An industrial controller device comprising a calculation unit for calculating and executing a user program including a POU which is a program constituent unit composed of a plurality of instruction words,
In the user program, when an interlock start instruction and an interlock end instruction to be paired are described, a section surrounded by both instructions becomes an interlock area, and an input corresponding to the interlock start instruction is in an interlock state. In the case of the value shown, the interlock area is set to the interlock state,
When executing the OUT instruction in the user program, the arithmetic unit determines whether or not the interlock area including the OUT instruction is in an interlock state, and in the case of the interlock state, the set interlock process Industrial controller equipment characterized by having a function to execute

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