JP2009177488A - Semiconductor switch circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress reduction of a terminal voltage boosted due to an increase of a gate leak current even when a large power is transmitted when an ambient temperature is high, and to improve a harmonic distortion characteristic. <P>SOLUTION: Upon transmission, a step-up voltage V1 obtained by a step-up circuit 21 is applied to a gate of a first switch element 31 by a decoder circuit 22. On the other hand, 0V is applied to the gate of a second switch element 32, and the first switch element 31 becomes conductive and the second switch element 32 becomes non-conductive. Further, a third switch element 33 becomes conductive, and a diode 39 is set to a reverse-bias state. Therefore, even a gate leak current of the second switch element 32 increases, the reduction of the boosted terminal voltage can be avoided. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor switch circuit used for switching a transmission path of a high-frequency signal in a mobile communication device or a high-frequency device, and particularly relates to a circuit that improves operational characteristics.

In wireless application devices such as mobile phones, semiconductor switches are used for transmission / reception switching, frequency band switching, and antenna switching.
In particular, in recent years, in mobile phones, multimode and multiband such as GSM, WCDMA, and CDMA systems have progressed, and in response to this, a semiconductor that can perform switching between a plurality of paths with lower loss. A switch is needed.
As an important characteristic required for such a semiconductor switch, there is a harmonic distortion characteristic during a transmission operation. Here, the harmonic distortion characteristic indicates a distortion component generated at a frequency that is an integral multiple of the transmission input signal frequency when a high-power transmission signal is input to the semiconductor switch.

Since the harmonic distortion, which is the distortion component, becomes an interference wave for other applications that use the frequency, there is a legal restriction on the amount of generation.
By the way, the harmonic distortion power generally increases in proportion to the square of the input power at the second harmonic and the cube of the input power at the third harmonic with respect to the increase of the input power. For this reason, in particular, when a large power signal of 35 dBm at the maximum is input to the semiconductor switch as in the GSM system, it is required to have a highly difficult technique to suppress the distortion component.

Such a switch for switching between a high-power transmitter and a receiver is particularly called an antenna switch.
FIG. 4 shows a configuration example of a semiconductor switch circuit that functions as an antenna switch. Hereinafter, a conventional antenna switch will be described with reference to FIG.
This semiconductor switch circuit as an antenna switch is the simplest configuration example for selectively selecting and connecting either a transmission terminal or a reception terminal with a control signal from the outside to one antenna terminal. Yes, and has a configuration called SPDT (Single Pole Double Through). A transmitter is connected to the transmission terminal, and a receiver is connected to the reception terminal.

Specifically, the semiconductor switch circuit is roughly divided into a booster circuit 21A, a decoder circuit 22A, and a switch circuit 23A.
In this configuration example, a depletion type FET (hereinafter referred to as “DFET”) 31A is provided between the antenna terminal 13A and the transmission terminal 11A, and switches between passing and non-passing between the antenna terminal 13A and the transmission terminal 11A. It functions as an element.
A DFET 32A is provided between the antenna terminal 13A and the receiving terminal 12A, and functions as a switching element that switches between passing and non-passing between the antenna terminal 13A and the receiving terminal 12A.

Further, a DFET 33A and a capacitor 37A are connected in series between the reception terminal 12A and the ground, and when selecting the transmission terminal 11A through a passage route, a high frequency from the transmission terminal 11A to the reception terminal 12A is provided. It operates as a shunt switch that prevents signal leakage and enhances isolation.
The power supply voltage VDD is supplied from the power supply voltage supply terminal 14A as a power source for operating the DFETs 31A to 33A as the switch elements, and the switch path switching signal input terminal 15A is used for switching between the transmission path and the reception path. An external control signal is supplied.

  The semiconductor switch circuit incorporates a booster circuit 21A, and generates and outputs a voltage V1 (V1> VDD) higher than the power supply voltage VDD. The switch element is driven by the high voltage V1.

  In general, the harmonic distortion characteristics of a semiconductor switch circuit improve as the drive voltage of the switch element increases. On the other hand, an appropriate DC bias voltage is applied to keep the switch element in the OFF state (non-conducting state). However, since the large power signal has a large voltage amplitude, the OFF state is maintained at a voltage amplitude exceeding the DC bias voltage. It ’s gone. In this case, the transfer characteristic of the switch element appears as a non-linear characteristic, and the input high power signal is distorted. When discussing very low distortion characteristics, the operating state of the switch element does not deteriorate so much that the OFF state cannot be maintained, but it can be described as simply having a back-off.

  When the semiconductor switch circuit is used as an antenna switch, a high power signal does not pass through the reception path, and therefore it is not necessary to consider low distortion characteristics. Therefore, at the time of reception, it is preferable to turn off the booster circuit 21A and use a voltage lower than the power supply voltage VDD as the switching voltage of the switch element.

  Here, the relationship between the voltages of the main parts in the semiconductor switch circuit shown in FIG. 4 will be described. First, the highest potential is the output voltage V1 of the booster circuit 21A. The output voltage of the logic value High of the decoder circuit driven using this boosted voltage V1 is substantially the same as the boosted voltage V1. Actually, the voltage drops slightly due to the loss in the decoder circuit 22A. However, in the following description of the circuit operation, it is assumed that there is no such voltage drop.

  First, a circuit operation in the case where the passage between the transmission terminal 11A and the antenna terminal 13A is selected will be described. In this case, the DFET 31A needs to be turned on (conductive state). Therefore, the output voltage V1 corresponding to the logical value High is output from the decoder circuit 22A to the gate of the DFET 31A. In the DFET 31A, when the gate potential becomes V1, the source and the drain are in a forward bias state. In the forward bias state, a slight potential difference Vf is generated between the gate and the source and between the gate and the drain. As a result, the source and drain of the DFET 31A are biased to a voltage VT = V1−Vf lower than the gate. It will be.

This voltage VT is a bias potential for all terminals that can serve as a high-frequency signal passing path, that is, drain and source, regardless of selection or non-selection of the terminals.
Therefore, the sources and drains of the DFET 31A, DFET 32A, and DFET 33A, which are switch elements in the circuit configuration shown in FIG. 4, are all biased to VT.

  Under such a premise, when the passage between the transmission terminal 11A and the antenna terminal 13A is selected as a passing path, the DFET 31A is turned on and at the same time the DFET 32A provided between the receiving terminal 12A and the antenna terminal 13A, which is a non-passing path, is set. Since it is necessary to be in the OFF state, 0 V corresponding to the logic value Low is applied from the decoder circuit 22A to the gate of the DFET 32A. At this time, the gate of the DFET 32A is in a reverse bias state with respect to the drain and the source.

As a result of the reverse-biased DFET 32A being set to the OFF state, the semiconductor switch circuit is in a passing state between the transmission terminal 11A and the antenna terminal 13A, while between the reception terminal 12A and the antenna terminal 13A, Non-passing state.
Such a semiconductor switch circuit is disclosed in, for example, Patent Document 1 and the like.

Japanese Patent Laying-Open No. 2005-354279 (page 4-7, FIGS. 1 to 3)

By the way, the gate leakage current of each of the above-mentioned DFETs 31A to 33A is normally designed so as to be a very small current. In general terms, the leakage current in a semiconductor increases exponentially with increasing voltage and temperature.
In the case of the above-described conventional circuit, since the switch element is driven by the boosted voltage V1 higher than the power supply voltage VDD, the gate leakage current is relatively large and becomes more noticeable when the temperature becomes high. As described above, the increase in the gate leakage current causes a voltage drop between the gate and the drain and between the gate and the source, and the bias voltage VT becomes a voltage reduced by the voltage drop. There is a problem that distortion characteristics at the time of transmission are deteriorated.

  The present invention has been made in view of the above circumstances, and a semiconductor switch circuit that does not cause deterioration of harmonic distortion characteristics even when the gate leakage current at high temperature increases during high power transmission. Is to provide.

In order to achieve the above object of the present invention, a semiconductor switch circuit according to the present invention includes:
A configuration in which a desired passage route can be formed by selectively switching connection between one or a plurality of high power signal terminals, one or a plurality of low power signal terminals, and one or a plurality of output signal terminals. A semiconductor switch circuit comprising:
A decoder circuit that selects a passage path according to a control signal from the outside;
Depending on the output of the decoder circuit, one of the one or more large power signal terminals and one of the one or more output terminals, or one of the one or more small power signal terminals and the one or more A switching circuit having a plurality of switching elements that connect one of the output terminals to the output terminal,
In the switching circuit, field effect transistors are provided in series as switching elements in respective passage paths formed between the high power signal terminal and the output terminal, while the small power signal terminal In each passing path formed between the output terminal, a field-effect transistor and a diode connected in series are respectively connected in series, and the diode is forward from the small power signal terminal to the output terminal. Thus, it is provided on the output terminal side.
In such a configuration, a booster circuit that boosts the power supply voltage supplied from the outside is provided, and the decoder circuit supplies the output voltage of the booster circuit to the switch element to be turned on to drive the switch element. What is comprised in this way is suitable.
Further, in this configuration, the switch circuit includes a field effect transistor as a switch element provided in parallel with the low power signal terminal, and the field effect transistor has a power source supplied to the gate from the outside. What is applied with a voltage is more preferable.

  According to the present invention, the drain and the source of the field effect transistor as a switching element provided to form a passage path between the low power signal terminal and the output terminal are at the time of transmission, that is, the low power signal terminal and the output terminal. When the gap is a non-passing path, it is configured to be DC-blocked from the drain and source of the field-effect transistor that forms the passing path at the time of transmission, so high power transmission is possible when the ambient temperature is high. Even if it is performed, unlike the conventional case, it is surely avoided that the bias voltage VT is lowered due to an increase in the gate leakage current in the field effect transistor provided between the low power signal terminal and the output terminal which are in the non-conductive state. It is possible to provide a semiconductor switch circuit having good harmonic distortion characteristics without deteriorating the harmonic distortion characteristics.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a configuration example of a semiconductor switch circuit according to an embodiment of the present invention will be described with reference to FIG.
A semiconductor switch circuit according to an embodiment of the present invention includes a switch circuit 23 having a transmission terminal 11, a reception terminal 12, and an antenna terminal 13, a decoder circuit (denoted as “DEC” in FIG. 1) 22, and a booster circuit (FIG. 1 is expressed as “BOOST”) 21 as a main component.

The switch circuit 23 is configured by an SPDT (Single Pole Double Through) switch having first to third switch elements 31 to 33 and a diode 39 as main components. In this configuration example, specifically, the first to third switch elements 31 to 33 use depletion type field effect transistors (FETs). Here, the transmitter terminal 11 as a high power signal terminal has a transmitter (not shown), the receiver terminal 12 as a low power signal terminal has a receiver (not shown), and the antenna terminal 13 has an antenna (not shown). Are connected to each other.
In FIG. 1, a portion provided on a semiconductor substrate (not shown) in the switch circuit 23 is surrounded by a dotted line.

  Hereinafter, the circuit configuration will be described in detail. The drain (or source) of the first switch element 31 is connected to the transmission terminal 11 via the first DC cut capacitor 34, while the source (or drain) is Both the cathode of a diode 39 to be described later are connected to the antenna terminal 13 via a third DC cut capacitor 36. A resistor 50 is connected between the anode of the diode 39 and the ground.

Further, the gate of the first switch element 31 is connected to the output stage of the decoder circuit 22 via the first gate resistor 51, and a predetermined gate is selected according to the passage route selected as will be described later. A voltage is applied. A first drain-source resistor 55 is connected between the drain and source of the first switch element 31.
On the other hand, the drain (or source) of the second switch element 32 is connected to the receiving terminal 12 via the second DC cut capacitor 35, while the source (or drain) is connected to the anode of the diode 39. Yes.
As described above, the diode 39 is provided on the output terminal 13 side in the forward direction from the reception terminal 12 to the output terminal 13.

  The gate of the second switch element 32 is connected to the output stage of the decoder circuit 22 via the second gate resistor 52, and a predetermined gate is selected according to the passage route selected as will be described later. A voltage is applied. A second drain-source resistor 56 is connected between the drain and source of the second switch element 32.

The third switch element 33 has a drain (or source) connected to a connection point between the second DC cut capacitor 35 and the drain (or source) of the second switch element 32, while the source (or drain) is connected. It is connected to the ground via a shunt DC cut capacitor 37.
The gate of the third switch element 33 is connected to the power supply voltage supply terminal 14 via the third gate resistor 53, and the power supply voltage is applied as the gate voltage. Note that a third drain-source resistor 57 is connected between the drain and source of the third switch element 33.
Thus, the third switch element 33 is provided in parallel to the reception terminal 12.

The booster circuit 21 is configured to boost the power supply voltage VDD applied via the power supply voltage supply terminal 14 to a predetermined voltage V1 (V1> VDD) and output it. It is a known one.
The output voltage of the booster circuit 21 is applied to the input stage of the decoder circuit 22.

  In response to a control signal input via the switch path switching signal input terminal 15, the decoder circuit 22 selectively turns on one of the first switch element 31 and the second switch element 32. Therefore, each is configured to output a predetermined gate voltage. That is, when a predetermined control signal is input to the decoder circuit 22 so that the first switch element 31 is turned on while the second switch element 32 is turned off, the first switch element 31 is turned on. The voltage V1 obtained by the booster circuit 21 is output to the gate of 31, while 0V is output to the gate of the second switch element 32.

  Also, the decoder circuit 22 makes the first switch element 31 non-conductive while the predetermined control signal is inputted to make the second switch element 32 conductive. Conversely, 0 V is output to the gate of the first switch element 31, while the voltage V1 obtained by the booster circuit 21 is output to the gate of the second switch element 32.

Next, the operation in the above configuration will be described.
First, a transmission state, that is, a case where a predetermined control signal is input to the switch path switching signal input terminal 15 so as to make a path between the transmission terminal 11 and the antenna terminal 13 will be described.
In this case, the booster voltage V1 input from the booster circuit 21 is applied to the gate of the first switch element 31 by the decoder circuit 22, while the gate of the second switch element 32 corresponds to the logic value Low. 0V is applied as the voltage.
The power supply voltage VDD is applied to the gate of the third switch element 33.

  The forward bias of the first switch element 31 causes a slight potential difference Vf between the gate and the source and between the gate and the drain, and the source and drain of the first switch element 31 are more than the gate. It will be biased to a low voltage VT = V1-Vf. As a result, the first switch element 31 is in a conductive state, and therefore, the transmission terminal 11 and the antenna terminal 13 are set as a passage path via the first switch element 31.

  At the same time, the cathode 39 of the diode 39, the source (or drain) of the first switch element 31 and the connection point A of the resistor 50 are also biased to the voltage VT. Since 39 is connected in a reverse bias state, the receiving terminal 12 and the antenna terminal 13 are cut off in a direct current manner, and the drain (or source) of the second switch element 32, the second DC cut capacitor 35, and The connection point between the drains (or sources) of the third switch element 33 does not become the voltage VT.

  On the other hand, the third switch element 33 is forward biased by application of the power supply voltage VDD to the gate, and its source and drain are caused by a slight potential difference Vf generated between the gate and source and between the gate and drain, respectively. Therefore, the voltage is biased to a voltage VS = VDD−Vf lower than that of the gate.

Therefore, the voltage at the connection point between the drain (or source) of the second switch element 32, the second DC cut capacitor 35, and the drain (or source) of the third switch element 33 is VS, and the second As described above, the gate of the switch element 32 is 0 V corresponding to the logic value Low, and the second switch element 32 becomes non-conductive.
Eventually, since the third switch element 33 is in a conductive state, it functions as a shunt switch when the receiving terminal 12 and the antenna terminal 13 are in a non-passing state.

  In such a state, when high power transmission is performed at a high temperature, the gate leakage current of the second switch element 32 in the non-conductive state increases, but the diode 39 is reverse-biased. Due to the increase of the leakage current, the potential of the connection point between the cathode of the diode 39, the source (or drain) of the first switch element 31 and the resistor 50 is decreased, that is, the bias voltage VT is decreased. Is reliably avoided and good low distortion characteristics can be realized.

Next, a reception state, that is, a case where a predetermined control signal is input to the switch path switching signal input terminal 15 so as to make a path between the reception terminal 12 and the antenna terminal 13 will be described.
In this case, the booster voltage V1 input from the booster circuit 21 is applied to the gate of the second switch element 32 by the decoder circuit 22, while the gate of the first switch element 31 corresponds to the logic value Low. 0V is applied as the voltage.
The power supply voltage VDD is applied to the gate of the third switch element 33.

As a result, contrary to the transmission state, the first switch element 31 is turned off, while the second switch element 32 is turned on.
Similarly to the first switch element 31 in the transmission state, the source and drain of the second switch element 32 are biased to a voltage VT = V1−Vf lower than the gate. Therefore, the connection point between the drain (or source) of the second switch element 32, the second DC cut capacitor 35, and the drain (or source) of the third switch element 33 is biased to the voltage VT. It becomes.

Along with this, the drain and source voltages of the third switch element 33 become the voltage VT, but since the power supply voltage VDD lower than the voltage VT is applied to the gate, the third switch element 33 A reverse bias state is established and a non-conduction state is established.
On the other hand, since the gate voltage of the first switch element 31 is 0 V, the voltage VT at the drain and the source of the second switch element 32 is applied to the diode 39 as a forward voltage. Becomes conductive.

Here, when the forward voltage of the diode 39 is Vf, the voltage at the connection point A between the cathode of the diode 39, the source (or drain) of the first switch element 31 and the resistor 50 is VT−Vf. .
Therefore, the source and drain voltages of the first switch element 31 are VT−Vf, and the first switch element 31 is in a non-conductive state.
Eventually, the receiving terminal 12 and the antenna terminal 13 are set as a passing path via the second switch element 32 and the diode 39, and a reception signal input from the antenna terminal 13 is obtained at the receiving terminal 12, and a receiver (not shown) Will be entered.

Next, with respect to an example of a change in terminal voltage on the side opposite to the antenna terminal of the third DC cut capacitor 36 connected to the antenna terminal 13 with respect to the harmonic characteristics with respect to the ambient temperature change in the semiconductor switch circuit of the embodiment of the present invention, This will be described with reference to FIG.
First, in this figure, the axis representing the temperature change is taken as the horizontal axis and viewed from the front, the left vertical axis represents the harmonic level at the antenna terminal 13, and the right vertical axis represents the connection point A (FIG. 1). (See FIG. 4), or the terminal voltage at the connection point A ′ (see FIG. 4).

In the figure, a solid characteristic line with the symbol a indicates a change in the terminal voltage at the connection point A with respect to a change in the ambient temperature of the semiconductor switch circuit in the embodiment of the present invention. The characteristic line shows the change in the terminal voltage at the connection point A ′ with respect to the change in the ambient temperature of the conventional circuit (see FIG. 4).
Comparing these, in the case of the conventional circuit, the terminal voltage gradually decreases as the ambient temperature rises, whereas in the semiconductor switch circuit in the embodiment of the present invention, it is constant. Thus, it can be confirmed that the characteristics are remarkably improved.

Next, in FIG. 3, a solid characteristic line with a symbol b indicates a change in the harmonic level with respect to a change in the ambient temperature in the semiconductor switch circuit according to the embodiment of the present invention, and a dotted line with a symbol d The characteristic line indicates the change in the harmonic level with respect to the change in the ambient temperature in the conventional circuit.
Comparing these, in the case of the conventional circuit, the harmonic level increases proportionally due to the decrease in the terminal voltage as the ambient temperature increases, and at the maximum, it reaches around -67 dBc at the maximum. In the case of the semiconductor switch circuit according to the embodiment of the present invention, although there is a slight increase in the level of harmonics accompanying an increase in the ambient temperature, the maximum is approximately -72 dBc at the maximum, and the harmonic characteristics have been reliably improved. It can be confirmed that.

  Such improvement of the characteristics of the semiconductor switch circuit according to the embodiment of the present invention is achieved by the diode 39 provided in series in the reception path separating the reception terminal 12 and the antenna terminal 13 in a direct current manner at the time of transmission. This is because the voltage of the antenna terminal 13 does not change at the time and at a high temperature, and the deterioration of the harmonic characteristics is suppressed.

FIG. 2 shows another configuration example of the semiconductor switch circuit according to the embodiment of the present invention. Hereinafter, this configuration example will be described with reference to FIG.
The same components as those shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
In this configuration example, the switch element in the reception path is omitted.
That is, in this configuration example, the second switch element 32 shown in FIG. 1 is omitted, and instead of connecting one end of the second gate resistor 52 to the gate of the second switch element 32, This is connected to the connection point between the second DC cut capacitor 35 and the anode of the diode 39.

In such a configuration, the basic operation is the same as that of the configuration example shown in FIG. 1, and thus detailed description thereof is omitted here.
In the case of this configuration example, since the second switch element 32 (see FIG. 1) is omitted, the isolation characteristic at the time of transmission is deteriorated as compared with the configuration example shown in FIG. When the required isolation characteristics are satisfied, there is an advantage that the circuit configuration is simplified as compared with FIG.

In the embodiment of the present invention, the SPDT switch has been described as an example, but the present invention can be similarly applied to a case where there are a plurality of antenna terminals and a plurality of transmission terminals and reception terminals.
Further, it is also preferable that a plurality of the first switch elements 31, the second switch elements 32, and further the third switch elements 33 are connected in series.

It is a circuit diagram which shows the structural example of the semiconductor switch circuit in embodiment of this invention. It is a circuit diagram which shows the other structural example of the semiconductor switch circuit in embodiment of this invention. It is a characteristic diagram which shows the change of the harmonic level with respect to the change of atmospheric temperature in the semiconductor switch circuit of embodiment of this invention, and the DC voltage change in the immediate vicinity of an antenna terminal. It is a circuit diagram which shows the structural example of a conventional circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Transmission terminal 12 ... Reception terminal 13 ... Antenna terminal 14 ... Power supply voltage supply terminal 15 ... Switch path switching signal input terminal 22 ... Decoder circuit 23 ... Switch circuit 31 ... First switch element 32 ... Second switch element 33 ... Third switch element 39... Diode

Claims (3)

A configuration in which a desired passage route can be formed by selectively switching connection between one or a plurality of high power signal terminals, one or a plurality of low power signal terminals, and one or a plurality of output signal terminals. A semiconductor switch circuit comprising:
A decoder circuit that selects a passage path according to a control signal from the outside;
Depending on the output of the decoder circuit, one of the one or more large power signal terminals and one of the one or more output terminals, or one of the one or more small power signal terminals and the one or more A switching circuit having a plurality of switching elements that connect one of the output terminals to the output terminal,
In the switching circuit, field effect transistors are provided in series as switching elements in respective passage paths formed between the high power signal terminal and the output terminal, while the small power signal terminal In each passing path formed between the output terminal, a field-effect transistor and a diode connected in series are respectively connected in series, and the diode is forward from the small power signal terminal to the output terminal. Thus, the semiconductor switch circuit is provided on the output terminal side. A booster circuit for boosting a power supply voltage supplied from the outside;
2. The semiconductor switch circuit according to claim 1, wherein the decoder circuit is configured to supply the output voltage of the booster circuit to the switch element to be turned on to drive the switch element.   The switch circuit has a field effect transistor as a switch element provided in parallel to the small power signal terminal, and the field effect transistor has a power supply voltage supplied from the outside applied to its gate. The semiconductor switch circuit according to claim 2.

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