JP2009170969A - Image processing apparatus, image processing method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a high-accuracy interpolated image by performing accurate edge direction determination considering correlation with peripheral pixels when converting an interlace scanning video signal into a progressive scanning video signal. <P>SOLUTION: An interlace scanning video signal is divided into areas around a notice pixel position, a cluster analysis circuit performs cluster analysis of respective divided areas, a correlation determination circuit determines shapes of the image in respective areas processed by using results of cluster analysis processing and movement of the image between fields, and an interpolation signal generated based on the determined results and an interlace scanning video signal are alternately outputted from a progressive conversion circuit, so that edge direction determination considering correlation with peripheral pixels can be achieved and a high-accuracy interpolated image improving the accuracy of the edge direction determination can be generated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, an image processing method, and a program, and more particularly, to an interpolation technique used when converting an interlaced scanning video signal into a progressive scanning video signal.

  A video signal subjected to interlace scanning has a problem that flicker occurs in very fine horizontal stripes. In order to solve this problem, there is a method of interpolating interlaced scanning lines on the basis of interlaced scanning video signals and outputting them as progressive scanning video signals. This method generally performs motion determination, and mixes the signal of the previous field used when stationary and the signal generated by the signal of the current field used when moving according to the determination result. Generate an interpolation signal.

  Further, a method (conventional method A) has been proposed in which an edge direction of an interpolation pixel is determined to generate an inter-field interpolation value, and an effective interpolation process is also applied to edges and diagonal lines (for example, Patent Document 1). reference.). In this method, the direction of the edge is determined by determining and comparing the absolute value of the difference value from a set of original pixels at point symmetry positions with the interpolation pixel as the center, and the direction in which the difference value is minimum has a high correlation. As the edge direction. Then, by selecting the set of original pixels in the direction that minimizes the difference value as the edge direction and performing interpolation processing, the edge in the diagonal direction is interpolated with the average value in the direction with high correlation, and the edge becomes jagged. Can be prevented.

JP-A-8-163511

  However, the above-described conventional method A has a problem in that it is difficult to understand the correlation with surrounding pixels because the difference value of a set of original pixels that are point-symmetrical with respect to the interpolation pixel is simply compared. In addition, there is a problem that the correct edge direction cannot be determined when there are a plurality of directions having the same difference value.

  For example, in the conventional method A, even when the interpolation pixel is actually an orthogonal angle, the correlation in the oblique direction becomes high, and the interpolation process using the set of original pixels in the oblique direction is performed. The corners will be crushed. Further, when the interpolated pixel is at an orthogonal angle and actually stationary, pixel values having different values for each field appear alternately at the same position, and thus one pixel flicker (dot flicker). It looks like.

  In the present invention, when an interlaced scanning video signal is converted into a progressive scanning video signal, it is possible to perform highly accurate edge direction determination in consideration of correlation with surrounding pixels and generate a high-definition interpolated image. The purpose is to do.

The image processing apparatus according to the present invention includes a holding unit that holds an interlaced scanning video signal for at least one field, and the interlaced scanning video signal is divided into regions centered on a target pixel position to perform cluster analysis processing. Analyzing processing means, determining means for determining the shape of the image of the area subjected to the cluster analysis processing and the movement of the image between fields using the result of the cluster analysis processing by the analyzing processing means, and the determining means A first interpolation signal generating means for generating an intra-field interpolation signal by weighting and adding the pixel value of the reference pixel position according to the distance from the target pixel position based on the result of the determination at On the basis of the result of the determination at, the video signal of the previous field output from the holding means and the image generated by the first interpolation signal generating means. The second interpolation signal generating means for generating an interpolation signal from the intra-field interpolation signal, the interlaced scanning video signal inputted and the interpolation signal generated by the second interpolation signal generating means are alternately arranged. Conversion means for outputting.
The image processing method of the present invention uses an analysis processing step of performing cluster analysis processing by dividing an interlaced scanning video signal into a region centered on a target pixel position, and a cluster analysis processing result. A determination step for determining the shape of the image in the region subjected to the analysis processing and the movement of the image between fields, and the pixel value of the reference pixel position from the target pixel position based on the determination result in the determination step A first interpolation signal generation step that weights and adds according to the distance to generate an intra-field interpolation signal, and holds at least one field of the interlaced scanning video signal based on the determination result in the determination step An interpolation signal is generated from the one-field previous video signal output from the holding means and the intra-field interpolation signal generated in the first interpolation signal generation step. A second interpolation signal generation step, and a conversion step of alternately outputting the input interlaced scanning video signal and the interpolation signal generated in the second interpolation signal generation step. Features.
The program of the present invention includes an analysis processing step for performing cluster analysis processing by dividing an interlaced scanning video signal into a region centered on a target pixel position, and using the result of the cluster analysis processing, A determination step for determining the shape of the image of the region where the image is performed and the motion of the image between fields, and the pixel value of the reference pixel position is set to a distance from the target pixel position based on the determination result in the determination step. A first interpolation signal generation step for generating an intra-field interpolation signal by weighting according to the results, and holding for holding at least one field of the interlaced scanning video signal based on the determination result in the determination step And the intra-field interpolation signal generated in the first interpolation signal generation step. A second interpolation signal generation step for generating an interpolation signal from the input, a conversion for alternately outputting the input interlaced video signal and the interpolation signal generated in the second interpolation signal generation step And causing the computer to execute the steps.

  According to the present invention, the cluster analysis processing is performed by dividing the region into the region centered on the target pixel position, and the result is used to determine the shape of the image of the region subjected to the cluster analysis processing and the movement of the image between fields. Then, an interpolation signal related to the video signal of the interlace scanning is generated. This makes it possible to determine the edge direction in consideration of the correlation with surrounding pixels, improve the accuracy of edge direction determination, perform more accurate edge direction determination, and generate a high-definition interpolated image Can do. Therefore, it is possible to perform smooth interpolation along the edge direction, and it is possible to generate an image with good progressive scanning.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described.
FIG. 1 is a block diagram illustrating a configuration example of an image processing apparatus 1 according to the first embodiment. FIG. 1 illustrates an example of an imaging system to which the image processing apparatus 1 according to the first embodiment is applied.

  The imaging system shown in FIG. 1 includes a charge coupled device (CCD) 11, an analog-digital (A / D) converter 12, a camera signal processing circuit 13, and an image processing apparatus 1. The image processing apparatus 1 includes a field memory 14, cluster analysis circuits 15 and 16, a correlation determination circuit 17 </ b> A, an intra-field interpolation signal generation circuit 18, a selector 19, and a progressive conversion circuit 20.

  An interlaced scanning video signal obtained by photoelectric conversion by the CCD 11 is subjected to analog-digital conversion (AD conversion) by an A / D converter 12. The camera signal processing circuit 13 performs imaging system signal processing such as aperture correction, gamma correction, and white balance on the interlaced scanning video signal converted into a digital signal by the A / D converter 12.

  The image processing apparatus 1 according to the first embodiment uses an interlaced scanning video signal S11, which is an output signal of the camera signal processing circuit 13, as an input signal, and performs processing such as progressive conversion to generate a progressive scanning video signal S21. Output. Specifically, the image processing apparatus 1 generates an interpolated image by performing edge direction determination using cluster analysis and the like, and converts the input interlaced scanning video signal S11 into a progressive scanning video signal S21. To do.

Hereinafter, each functional unit in the image processing apparatus 1 will be described.
The field memory (holding means) 14 is a memory that holds an input interlaced scanning video signal S11 for at least one field. The interlaced scanning video signal S11 input to the field memory 14 is held in the field memory 14 and delayed by one field.

  The cluster analysis circuit (first analysis processing means) 15 receives the interlaced scanning video signal S11. The cluster analysis circuit 15 divides the input interlaced scanning video signal S11 into regions centered on the pixel position of interest which is an interpolation point, performs cluster analysis processing, and outputs classified pixel information as an output signal. In S12, the classification number is output as an output signal S13.

  The cluster analysis circuit (second analysis processing means) 16 receives the output signal S14 of the field memory 14, that is, the interlaced scanning video signal S11 delayed by one field. The cluster analysis circuit 16 divides the output signal S14 of the field memory 14 into regions centered on the target pixel position, performs cluster analysis processing, sets the classified pixel information as the output signal S15, and outputs the classification number Output as signal S16.

  That is, the cluster analysis circuit 15 performs cluster analysis on the current field and outputs classified pixel information and the number of classifications related to the video signal of the current field. The cluster analysis circuit 16 performs cluster analysis on the previous field, and outputs classified pixel information and the number of classifications related to the video signal of the previous field. The cluster analysis processing in the cluster analysis circuits 15 and 16 may be performed for each pixel or in units of blocks, and there is no restriction on the block size.

  The correlation determination circuit (determination means) 17A receives the output signals S12 and S13 of the cluster analysis circuit 15 and the output signals S15 and S16 of the cluster analysis circuit 16. The correlation determination circuit 17A determines the shape of the edge and the motion between fields from the cluster analysis results indicated by the output signals S12 and S13 and the output signals S15 and S16. Based on the determination result, the correlation determination circuit 17A outputs the interpolation method control signal S17A to the selector 19, and outputs the position information of the reference pixel used to calculate the interpolation value to the intra-field interpolation signal generation circuit 18 as an output signal. (Position signal) Output as S18.

  The intra-field interpolation signal generation circuit (first interpolation signal generation means) 18 receives the interlaced scanning video signal S11 and the output signal S18 of the correlation determination circuit 17A, and generates an intra-field interpolation signal. Specifically, the intra-field interpolation signal generation circuit 18 obtains pixel information to be referred to by the output signal S18 of the correlation determination circuit 17A, and obtains a weighted average taking into account the distance from the interpolation point, thereby performing intra-field interpolation. A signal is generated and output as an output signal S19. In other words, the intra-field interpolation signal generation circuit 18 generates an intra-field interpolation signal by weighting and adding the pixel value at the reference pixel position according to the distance from the target pixel position as an interpolation point.

  The selector (second interpolation signal generation means) 19 receives the output signal S19 of the intra-field interpolation signal generation circuit 18, the output signal S14 of the field memory 14, and the control signal S17A of the interpolation method from the correlation determination circuit 17A. . The selector 19 selects either the output signal S19 of the intra-field interpolation signal generation circuit 18 or the output signal S14 of the field memory 14 in units of pixels in accordance with the interpolation method control signal S17A, and outputs the selected signal as an output signal S20.

  Specifically, when the interpolation method control signal S17A is "1", the selector 19 outputs the output signal S14 of the field memory 14 as the output signal S20 because the interpolation process is performed using the value of the previous field. . Further, when the interpolation method control signal S17A is “0”, the interpolation process is performed using the signal generated from the data in the field, so that the selector 19 outputs the output signal S19 of the intra-field interpolation signal generation circuit 18. Is output as an output signal S20.

  The progressive conversion circuit (conversion means) 20 receives the interlaced scanning video signal S11 and the output signal S20 of the selector 19. The progressive conversion circuit 20 outputs a progressively converted video signal (progressive scanning video signal) S21 by alternately outputting signals S11 and S20 in units of scanning lines (horizontal scanning period) in interlace scanning. .

Next, the cluster analysis circuits 15 and 16 will be described.
Hereinafter, the cluster analysis circuit 15 will be described as an example. The cluster analysis circuit 16 is different from the cluster analysis circuit 15 in the input signal, but the cluster analysis process to be executed is the same. In the present embodiment, pixel values of an image are used as data for classification in cluster analysis. Note that the method of using the pixel values of the image is an example, and two-dimensional cluster analysis may be performed in consideration of the pixel values and the distance from the interpolation point.

  The cluster analysis processing in the cluster analysis circuit 15 is performed by hierarchical cluster analysis processing. In the hierarchical cluster analysis processing, cluster merging processing and distance recalculation processing are repeated. In the process of merging clusters, “distance” which means a difference value between data to be compared is obtained, and data having a short distance are collected as data of the same cluster. In the distance recalculation process, the cluster merge process is performed, and then the distance from the merged cluster to another cluster is recalculated. In the hierarchical cluster analysis process, the process is basically repeated until the number of clusters becomes 1, that is, until all the clusters are merged. In this embodiment, the cluster is analyzed until the distance between the clusters exceeds a certain value. Control to repeat the merge.

The hierarchical cluster analysis process will be described with reference to a specific example shown in FIG.
In FIG. 2, 6A (PA, PB, PC, PD, PE, PF) as shown in FIG. 2A is a schematic diagram showing pixel positions, and FIG. 2B is a line segment diagram showing pixel values of each pixel. The example of the cluster analysis processing using is shown.

  In the hierarchical cluster analysis process, first, the difference value of the pixel values of all the pixels PA to PF is obtained as a distance and held as a table (see FIG. 2C). Next, a group having the shortest distance is searched from among them, and a cluster merging process for collecting the same cluster is performed. Subsequently, after performing cluster merge processing, recalculation of distance from the merged cluster is performed, and a table is created again. The cluster merging process and the distance recalculation process are repeated, and the process is terminated when the minimum distance value in the table exceeds a certain value or when the number of clusters becomes 1.

  FIG. 2D shows a case where the cluster of the pixel PA and the cluster of the pixel PD are merged as one cluster, and FIG. 2E shows the cluster of the pixel PB and the cluster of the pixel PE after the merge. Is shown as a single cluster.

FIG. 3 is a flowchart showing the flow of hierarchical cluster analysis processing by the cluster analysis circuit 15.
When the cluster analysis circuit 15 starts the cluster analysis process, first, the difference values of the pixel values of all the pixels are obtained as distances and held as a table (S101). Here, when starting the cluster analysis process, it can be considered that all the pixels are one cluster.

  Next, the cluster analysis circuit 15 checks the number of clusters and determines whether or not the number of clusters is 1 (S102). As a result of the determination, when the number of clusters is 1, the cluster cannot be merged any more. Therefore, the cluster analysis circuit 15 outputs the classified pixel information (classification information) and the classification number as output signals S12 and S13. And finish the cluster analysis process.

  On the other hand, if the result of determination in step S102 is that the number of clusters is other than 1, the cluster analysis circuit 15 searches the distance table for the minimum value and determines whether the minimum value is greater than the constant α. (S103). The constant α is set in advance by obtaining a difference value between pixel values when it is determined to be an edge by experiment or the like.

  If the minimum value is larger than the constant α as a result of the determination in step S103, it means that the difference value is too large. Therefore, the cluster analysis circuit 15 determines that the portion becomes an edge and merges the clusters. Cancel. Then, the cluster analysis circuit 15 outputs the classified pixel information (classification information) at that time as the output signal S12 and the classification number as the output signal S13, and ends the cluster analysis processing.

  On the other hand, if the result of determination in step S103 is that the minimum value is less than or equal to the constant α, the difference between the compared pixel values is small and the values are similar, and cluster merging can still be performed. Therefore, the cluster analysis circuit 15 merges the pixels having the smallest difference value as the same cluster (S104). When the clusters are merged, the cluster analysis circuit 15 recalculates the distance between the clusters after merging to reconstruct the table (S105), and returns to step S102. And the process after step S102 mentioned above is performed repeatedly.

Here, the recalculation of the distance from the merged cluster after the merge of the clusters is obtained using, for example, the Ward method as shown below.
<Ward method>
Assume that cluster a and cluster b are merged to form cluster c. Further, the distance between the cluster a and the cluster b before the merge of the cluster a and the cluster b is d _ab , the distance between the cluster a and the cluster x is d _xa , and the distance between the cluster b and the cluster x is d _xb . Note that the cluster x is another cluster different from the cluster a and the cluster b. At this time, the distance between cluster c and cluster x after merging is obtained by the following equation.
d ² _xc = α _a d ² _xa + α _b d ² _xb + βd ² _ab
α _a : (n _x + n _a ) / (n _x + n _c )
α _b : (n _x + n _b ) / (n _x + n _c )
β: −n _x / (n _x + n _c )
Here, _nx is the number of individuals included in the cluster x. n _a, n _b, The same is true for n _c.

  Note that the method of recalculating the distance to the merged cluster is not limited to the Ward method, and may be another method such as the shortest distance method used in the cluster analysis method.

  In the above description, the cluster analysis processing in the cluster analysis circuits 15 and 16 uses hierarchical cluster analysis processing, but may use non-hierarchical cluster analysis processing. Even when the non-hierarchical cluster analysis process is used, the difference value between the data is obtained as the distance, as in the hierarchical cluster analysis process.

Non-hierarchical cluster analysis processing will be described with reference to a specific example shown in FIG.
In FIG. 4, as shown in the schematic diagram of the pixel position in (A), the cluster analysis process using 6 pixels (PA, PB, PC, PD, PE, PF), and the number of clusters to be classified is 2. An example is shown. In the line segment diagrams shown in (B) to (E), the pixel values of the respective pixels are shown.

  In the non-hierarchical cluster analysis process, first, a pixel to be a classification starting point is randomly selected. In the example shown in FIG. 4, processing is performed starting from the pixels PA and PF (see FIG. 4B). Next, the difference value between the pixel values of each pixel to be classified and the starting point is calculated as a distance, and classification is temporarily performed on a cluster having a shorter distance (see FIG. 4C). In the example shown in FIG. 4C, the pixel PA and the pixel PD are classified into the same cluster, and the pixel PB, the pixel PC, the pixel PE, and the pixel PF are classified into the same cluster.

  When classification is completed, the center of gravity in each cluster is obtained. As the center of gravity, for example, an average value of pixel values of pixels in the cluster can be used. Subsequently, after obtaining the center of gravity, the calculation of the distance between each pixel and the center of gravity is performed again. If the center of gravity of another cluster is closer to the center of gravity of another cluster, the cluster is moved. When the movement between the clusters occurs, the center of gravity of the cluster changes, so that the process of obtaining the center of gravity again and obtaining the distance between each pixel and the center of gravity is performed again. If movement between clusters does not occur, the result is not changed even if the process is repeated any more, so the process ends (see FIGS. 4D and 4E).

FIG. 5 is a flowchart showing the flow of non-hierarchical cluster analysis processing.
In the example shown in FIG. 5, the processing is performed with the number of clusters being two. However, the processing is not limited to this, and the processing may be performed by classifying into three or more clusters.

  Since the cluster analysis circuit 15 first aims to classify into two clusters, it selects two pixels (for example, pixels that exist in the upper left and lower right positions) as the starting point of the classification, Classify into clusters (S201). Next, the cluster analysis circuit 15 obtains the distance from the starting point for all the pixels, and classifies each of the pixels into a cluster having a shorter distance (S202). The distance here is a difference value of pixel values.

  Next, the cluster analysis circuit 15 obtains the center of gravity in the classified cluster (S203). In the present embodiment, as an example, an average value of pixel values is obtained as the center of gravity in the cluster. Subsequently, the cluster analysis circuit 15 obtains the obtained distance from the center of gravity with respect to all the pixels, and classifies it again into a cluster having a shorter distance (S204). Here, when the center of gravity of a cluster different from the cluster to which it belongs is closer, the cluster is moved.

  If movement between clusters occurs in the processing in step S204 (Yes in S205), it means that the optimum classification has not been performed, and the cluster analysis circuit 15 returns to step S203. That is, the cluster analysis circuit 15 obtains the center of gravity in the cluster again (S203) and performs cluster reclassification processing (S204). This process is repeated until no movement between clusters occurs.

  On the other hand, if no movement between clusters has occurred in the process in step S204 (No in S205), there is no change even if the reclassification process is further performed. This process is terminated.

After finishing the process related to the cluster classification, the cluster analysis circuit 15 determines whether or not the preset cluster classification number 2 is valid.
First, the cluster analysis circuit 15 determines whether the distance between the centroids of the classified clusters is larger than the constant β (S206). For the constant β, a value obtained in advance through experiments or the like is used.

  As a result of the determination in step S206, if the distance between the centroids of the classified clusters is equal to or less than the constant β, it means that the distance between the two clusters is close, and therefore it should not be classified into another cluster. I can judge. Therefore, the cluster analysis circuit 15 outputs the classification number “1” as the output signal S13 (S207), and ends the cluster analysis process.

  On the other hand, as a result of the determination in step S206, if the distance between the centroids of the classified clusters is larger than the constant β, the cluster analysis circuit 15 determines whether or not classification into finer clusters can be performed. Specifically, the cluster analysis circuit 15 calculates the maximum value of the distance in the cluster for each classified cluster, and determines whether the maximum value is larger than the constant γ (S208). The constant γ uses a value obtained in advance by experiments or the like.

  As a result of the determination in step S208, when the maximum value of the distance in the classified cluster is larger than the constant γ, it is said that the pixels that are separated from each other and are considered to be edges are classified into the same cluster. Therefore, it can be determined that the number of classifications is three or more. Therefore, the cluster analysis circuit 15 outputs the classification number “3” as the output signal S13 (S209), and ends the cluster analysis process.

  On the other hand, as a result of the determination in step S208, when the maximum value of the distance in the classified cluster is equal to or smaller than the constant γ, it can be determined that 2 is the optimum number of classifications. Therefore, the cluster analysis circuit 15 outputs the classification number “2” as the output signal S13 (S210), and ends the cluster analysis process.

  Note that the cluster analysis technique in the present embodiment described above is an example, and the present invention is not limited to this.

Next, the correlation determination process by the correlation determination circuit 17A will be described.
FIG. 6 is a flowchart showing the flow of the correlation determination process in the first embodiment. In the correlation determination process in the present embodiment, the process is divided according to the number of divided clusters in the current field. The number of clusters divided in the current field can be determined from the output signal S13 of the cluster analysis circuit 15 indicating the number of cluster classifications.

  FIG. 6 described below shows, as an example, a case where pattern matching processing is performed when the number of clusters in the current field is 2, but the present invention is not limited to this. For example, pattern matching processing may be performed even when the number of clusters in the current field is three or more, and pattern matching may not be performed when the number of clusters is more than a certain number.

  When the correlation determination circuit 17A starts the correlation determination process, the correlation determination circuit 17A first determines how many clusters are divided in the current field based on the output signal S13 from the cluster analysis circuit 15 (S301).

  As a result of the determination in step S301, when the number of divided clusters is 1, it means that the area subjected to the cluster analysis processing has been merged into one cluster, and therefore it can be determined that the plane does not include an edge. it can. Therefore, the correlation determination circuit 17A sets “0” as the control signal S17A for the interpolation method so that the value obtained by performing the intra-field interpolation processing in the selector 19 (the output signal S19 of the intra-field interpolation signal generation circuit 18) is selected. Output. Further, the correlation determination circuit 17A obtains information on all the pixels in the region subjected to the cluster analysis process so that all the plane data is used as reference pixels when the intra-field interpolation signal generation circuit 18 performs the intra-field interpolation process. The output signal S18 is output (S302).

  As a result of the determination in step S301, when the number of divided clusters is 2, the correlation determination circuit 17A compares with a previously prepared pattern to determine the edge shape and the motion between fields. The information of the divided area of the current field can be determined by the output signal S12 of the cluster analysis circuit 15 indicating the cluster classification information.

  An example of patterns prepared in advance is shown in FIG. For each pattern of the current field, pattern information of the previous field that is expected when stationary is also prepared. The prepared patterns include “a position that must be completely matched” and “a position that does not have to be matched” when determining an edge.

  When the number of divided clusters is 2, the correlation determination circuit 17A first acquires information on the divided areas of the current field from the output signal S12 of the cluster analysis circuit 15. Then, the correlation determination circuit 17A sequentially compares the acquired information on the divided areas of the current field and the prepared pattern, and all the classifications of “positions that must be completely matched” match. A pattern is detected (S303).

  Next, the correlation determination circuit 17A acquires a pattern for comparison with the cluster analysis result of the previous field from the pattern detected in step S303 (S304). Then, the correlation determination circuit 17A acquires information on the divided area of the previous field from the output signal S15 of the cluster analysis circuit 16 indicating the cluster classification information, and compares it with the pattern of the previous field acquired previously. This is performed (S305).

  As a result of the comparison in step S305, when all the classifications of “positions that must be completely matched” match (Yes in S306), it is determined that the divided area is a stationary edge. can do. Accordingly, the correlation determination circuit 17A outputs “1” as the control signal S17A of the interpolation method so that the value of the previous field (output signal S14 of the field memory 14) is selected by the selector 19 (S307). At this time, since intra-field interpolation processing is not performed, the output signal S18 is not particularly limited.

  On the other hand, as a result of the comparison in step S305, if the classification of “positions that must be completely matched” does not match (No in S306), it is determined that the divided area is a moving edge. can do. Therefore, the correlation determination circuit 17A sets “0” as the control signal S17A for the interpolation method so that the value obtained by performing the intra-field interpolation processing in the selector 19 (the output signal S19 of the intra-field interpolation signal generation circuit 18) is selected. Output. The reference pixel position when performing the intra-field interpolation processing acquires the position information of the cluster including the interpolation point from the pattern of the current field, and uses the intra-field interpolation signal generation circuit as the output signal S18 of the correlation determination circuit 17A. 18 (S308).

  As a result of the determination in step S301, when the number of divided clusters is 3 or more, it can be determined that the area subjected to the cluster analysis process is a chaotic area including a plurality of edges. Therefore, the correlation determination circuit 17A sets “0” as the control signal S17A for the interpolation method so that the value obtained by performing the intra-field interpolation processing in the selector 19 (the output signal S19 of the intra-field interpolation signal generation circuit 18) is selected. Output. Further, since the reference pixel position when performing the intra-field interpolation processing is a region where the edge direction cannot be determined, information on the pixels above and below the interpolation point is output as the output signal S18 of the correlation determination circuit 17A ( S309).

  According to the first embodiment, the cluster analysis process is performed, and the shape of the image of the area subjected to the cluster analysis process and the movement of the image between fields are determined based on the result. Then, according to the determination result, either the output signal S19 of the intra-field interpolation signal generation circuit 18 or the output signal S14 of the field memory 14 is output to the progressive conversion circuit 20 as an interpolation signal.

  As a result, the edge direction can be determined in consideration of the correlation with the surrounding pixels, the accuracy of the edge direction determination can be improved, and smooth interpolation can be performed along the edge direction. Accordingly, it is possible to accurately determine the edge direction and generate a high-definition interpolated image, and to output a video signal of good progressive scanning.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 8 is a block diagram illustrating a configuration example of the image processing apparatus 2 according to the second embodiment. FIG. 8 illustrates an example of an imaging system to which the image processing apparatus 2 according to the second embodiment is applied. 8, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  The imaging system shown in FIG. 8 includes a CCD 11, an A / D converter 12, a camera signal processing circuit 13, and an image processing device 2. The image processing apparatus 2 includes a field memory 14, cluster analysis circuits 15 and 16, a correlation determination circuit 17 </ b> B, an intra-field interpolation signal generation circuit 18, an interpolation signal generation circuit 21, and a progressive conversion circuit 20. The image processing apparatus 2 uses the interlaced scanning video signal (the output signal of the camera signal processing circuit 13) S11 as an input signal, generates an interpolated image by performing edge direction determination using cluster analysis, etc., and performs progressive scanning. The video signal S21 is output.

  The correlation determination circuit (determination means) 17B receives the output signals S12 and S13 of the cluster analysis circuit 15 and the output signals S15 and S16 of the cluster analysis circuit 16. The correlation determination circuit 17B determines the shape of the edge and the movement between fields from the results of cluster analysis indicated by the output signals S12 and S13 and the output signals S15 and S16. Based on the determination result, the correlation determination circuit 17B outputs an interpolation method control signal S17B to the interpolation signal generation circuit 21, and the intra-field interpolation signal generation circuit 18 uses reference pixel position information to calculate an interpolation value. Is output as an output signal (position signal) S18.

  The interpolation signal generation circuit (second interpolation signal generation means) 21 includes an output signal S19 from the intra-field interpolation signal generation circuit 18, an output signal S14 from the field memory 14, and an interpolation method control signal S17B from the correlation determination circuit 17B. Entered. The interpolation signal generation circuit 21 generates an interpolation signal by linearly synthesizing the output signal S19 of the intra-field interpolation signal generation circuit 18 and the output signal S14 of the field memory 14, and outputs it as an output signal S22. In this linear synthesis, as the interpolation method control signal S17B is closer to "0", a value closer to the output signal S19 of the intra-field interpolation signal generation circuit 18 is output as the output signal S22. The output signal S22 of the interpolation signal generation circuit 21 corresponds to the signal S20 in the first embodiment and is input to the progressive conversion circuit 20.

The correlation determination process by the correlation determination circuit 17B will be described.
FIG. 9 is a flowchart showing the flow of the correlation determination process in the second embodiment. In the correlation determination processing in this embodiment, the number of clusters divided in the current field is determined by the output signal S13 of the cluster analysis circuit 15, and the processing is divided according to the number of clusters.

  FIG. 9 described below shows, as an example, a case where pattern matching processing is performed when the number of clusters in the current field is 2, but the present invention is not limited to this. For example, pattern matching processing may be performed even when the number of clusters in the current field is three or more, and pattern matching may not be performed when the number of clusters is more than a certain number.

  When the correlation determination circuit 17B starts the correlation determination process, it first determines how many clusters the current field has been divided based on the output signal S13 from the cluster analysis circuit 15 (S401).

  As a result of the determination in step S401, when the number of divided clusters is 1, it means that the area subjected to the cluster analysis processing has been merged into one cluster, and therefore it can be determined that the plane does not include an edge. it can. Therefore, the correlation determination circuit 17B uses the value obtained by performing the intra-field interpolation processing in the interpolation signal generation circuit 21 (the output signal S19 of the intra-field interpolation signal generation circuit 18) as the interpolation method control signal S17B. 0 ”is output. In addition, the information of all the pixels in the region subjected to the cluster analysis processing is output as the output signal S18 so that all the plane data is used as the reference pixels when the intra-field interpolation signal generation circuit 18 performs the intra-field interpolation processing. (S402).

  As a result of the determination in step S401, when the number of divided clusters is 2, the correlation determination circuit 17B performs comparison with a pattern prepared in advance as shown in FIG. Judge the movement of the image between fields. Information on the divided area of the current field can be determined by the output signal S12 of the cluster analysis circuit 15.

  For each pattern in the current field, there is also prepared pattern information of the previous field that is expected when still, and pattern information that must be excluded in the previous field. The pattern that must be excluded in the previous field means a pattern in which the direction of the edge is reversed or the shape of the edge is completely different. The prepared patterns include “a position that must be completely matched” and “a position that does not have to be matched” when determining an edge.

  When the number of divided clusters is 2, the correlation determination circuit 17B acquires information on the divided areas of the current field from the output signal S12 of the cluster analysis circuit 15. Then, the correlation determination circuit 17B sequentially compares the acquired information on the divided areas of the current field and the prepared pattern, and the classification of “positions that must be completely matched” matches. The detected pattern is detected (S403).

  Next, the correlation determination circuit 17B acquires information on the pattern that should be excluded from the patterns to be compared with the cluster analysis result of the previous field from the pattern detected in step S403 (S404). Then, the correlation determination circuit 17B acquires information on the divided area of the previous field from the output signal S15 of the cluster analysis circuit 16, and compares it with the pattern of the previous field acquired in step S404 (S405).

  As a result of the comparison in step S405, if all the classifications of “positions that must be completely matched” match (Yes in S406), the process proceeds to step S407. Then, the correlation determination circuit 17B outputs “0” as the control signal S17B of the interpolation method so as not to perform the correlation determination process with the current field, and ends the correlation determination process. The reference pixel position when performing the intra-field interpolation processing acquires the position information of the cluster including the interpolation point from the pattern of the current field, and uses the intra-field interpolation signal generation circuit as the output signal S18 of the correlation determination circuit 17B. 18 (S407). In this process, when counting the number of matching pixels, which will be described later, the value may increase even when counting is performed for an edge having a completely different shape. This is to enable determination by another process.

  On the other hand, as a result of the comparison in step S405, if the classification of “positions that must be completely matched” does not match (No in S406), the process proceeds to step S408. The correlation determination circuit 17B acquires pattern information for determining whether the pattern is stationary among the patterns for comparison with the result of cluster analysis in the previous field from the pattern detected in step S403 (S408). Then, the correlation determination circuit 17B acquires information on the divided area of the previous field from the output signal S15 of the cluster analysis circuit 16, and compares it with the pattern of the previous field acquired in step S408 (S409).

  The correlation determination circuit 17B counts how many pixels at “positions that must be completely matched” when performing the comparison in step S409, and determines the ratio of the matched pixels as a control signal for the interpolation method. Output as S17B. The reference pixel position when performing the intra-field interpolation processing acquires the position information of the cluster including the interpolation point from the pattern of the current field, and uses the intra-field interpolation signal generation circuit as the output signal S18 of the correlation determination circuit 17B. 18 (S410).

  As a result of the determination in step S401, when the number of divided clusters is 3 or more, it can be determined that the area subjected to the cluster analysis process is a chaotic area including a plurality of edges. Accordingly, the correlation determination circuit 17B selects “a value (the output signal S19 of the intra-field interpolation signal generation circuit 18) subjected to the intra-field interpolation processing in the interpolation signal generation circuit 21 as the control signal S17B for the interpolation method”. 0 ”is output. In addition, since the reference pixel position when performing the intra-field interpolation processing is a region where the edge direction cannot be determined, information on pixels above and below the interpolation point is output as the output signal S18 of the correlation determination circuit 17B ( S411).

  According to the second embodiment, the cluster analysis process is performed, and the shape of the image of the region subjected to the cluster analysis process and the movement of the image between fields are determined based on the result. Then, according to the determination result, the output signal S19 of the intra-field interpolation signal generation circuit 18 and the output signal S14 of the field memory 14 are linearly synthesized to generate an interpolation signal, which is output to the progressive conversion circuit 20. This makes it possible to determine the edge direction in consideration of the correlation with surrounding pixels, improve the accuracy of the edge direction determination, generate a high-definition interpolated image, and generate a good progressive scan video signal. Can be output.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 10 is a block diagram illustrating a configuration example of the image processing apparatus 3 according to the third embodiment. FIG. 10 illustrates an example of an imaging system to which the image processing device 3 according to the third embodiment is applied. 10, constituent elements having the same functions as those shown in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted.

  The imaging system shown in FIG. 10 includes a CCD 11, an A / D converter 12, a camera signal processing circuit 13, and an image processing device 3. The image processing apparatus 3 includes a field memory 14, a cluster analysis circuit 15, a shape determination circuit 31A, an intra-field interpolation signal generation circuit 32A, a motion determination circuit 33, an interpolation signal generation circuit 34, and a progressive conversion circuit 20. The image processing device 3 receives an interlaced scanning video signal (output signal from the camera signal processing circuit 13) S11 as an input signal, generates an interpolated image by performing shape determination using cluster analysis, and the like, and performs progressive scanning video. The signal S21 is output.

  The shape determination circuit (determination unit, shape determination unit) 31A receives the output signals S12 and S13 of the cluster analysis circuit 15, and receives an image of a region where cluster analysis processing has been performed based on the results of cluster analysis indicated by the output signals S12 and S13. Determine the edge shape. Based on the determination result, the shape determination circuit 31A outputs an output signal S31A for calculating the intra-field interpolation value to the intra-field interpolation signal generation circuit 32A.

  Specifically, the shape determination circuit 31A determines the number of clusters divided by the output signal S13 of the cluster analysis circuit 15 indicating the number of cluster classifications, and the shape of the region subjected to the cluster analysis processing based on the number of clusters. Determine.

  When the number of divided clusters is 1, it means that the area subjected to the cluster analysis process has been merged into one cluster, so the shape determination circuit 31A determines that the area subjected to the cluster analysis process is a plane. be able to. In this case, the shape determination circuit 31A uses all the plane data as reference pixels when the intra-field interpolation signal generation circuit 32A performs the intra-field interpolation processing, so that all the pixels in the region subjected to the cluster analysis processing are used. Is output as an output signal S31A.

  In addition, when the number of divided clusters is 2, it means that the area where the cluster analysis processing has been performed has been accurately divided into two areas, and therefore the shape determination circuit 31A has the position information (refer to reference) of the clusters including the interpolation points. The pixel position information) is output as the output signal S31A.

  Further, when the number of divided clusters is 3 or more, it can be determined that the area where the cluster analysis process is performed is a chaotic area including a plurality of edges. In this case, the shape determination circuit 31A cannot perform edge determination, and therefore outputs information on pixels above and below the interpolation point as the output signal S31.

  The intra-field interpolation signal generation circuit (first interpolation signal generation means) 32A receives the interlaced scanning video signal S11 and the output signal S31A of the shape determination circuit 31A, and generates an intra-field interpolation signal. The intra-field interpolation signal generation circuit 32A acquires pixel information to be referred to by the output signal S31A of the shape determination circuit 31A, and generates an intra-field interpolation signal by obtaining a weighted average taking into account the distance from the interpolation point. And output as an output signal S32A. In other words, the intra-field interpolation signal generation circuit 32A generates an intra-field interpolation signal by weighting and adding the pixel value at the reference pixel position according to the distance from the target pixel position that is the interpolation point.

  The motion determination circuit (determination means, motion determination means) 33 receives the output signal S14 of the field memory 14 and the output signal S32A of the intra-field interpolation signal generation circuit 32A. The motion determination circuit 33 determines whether or not the region (interpolation point region) subjected to the cluster analysis processing is moving based on the input signals S14 and S32A. The motion determination circuit 33 obtains an absolute value of a difference value between the output signal S14 of the field memory 14 and the output signal S32A of the intra-field interpolation signal generation circuit 32A, and further divides the absolute value by the maximum value of the assigned bit length. Thus, it is normalized and output as an output signal S33.

  When the difference between the output signal S14 of the field memory 14 and the output signal S32A of the intra-field interpolation signal generation circuit 32A is small, it can be determined that the motion of the interpolation point region is small, and as the output signal S33 of the motion determination circuit 33 A value close to “0” is output. On the other hand, when the difference between the input output signal S14 and the output signal S32A is large, it is possible to determine that the area of the interpolation point is moving because the relevance with the previous value is low, and the motion determination circuit 33 A value close to “1” is output as the output signal S33.

  The interpolation signal generation circuit (second interpolation signal generation means) 34 receives the output signal S14 of the field memory 14, the output signal S32A of the intra-field interpolation signal generation circuit 32A, and the output signal S33 of the motion determination circuit 33. The interpolation signal generation circuit 34 generates an interpolation signal to be output as the value of the interpolation point by linearly synthesizing the output signal S14 of the field memory 14 and the output signal S32A of the intra-field interpolation signal generation circuit 32A, and outputs it as an output signal S34. To do.

  In the linear synthesis in the interpolation signal generation circuit 34, the closer the output signal S33 of the motion determination circuit 33 is to "1", the closer the output signal S32A of the intra-field interpolation signal generation circuit 32A is to be output as the output signal S34. On the other hand, as the output signal S33 of the motion determination circuit 33 is closer to “0”, a value closer to the output signal S14 of the field memory 14 is output as the output signal S34. The output signal S34 of the interpolation signal generation circuit 34 corresponds to the signal S20 in the first embodiment and is input to the progressive conversion circuit 20.

  According to the third embodiment, the shape of the image and the movement of the image between fields are determined using cluster analysis processing, and the output signal S32A and the output signal S14 are linearly synthesized and interpolated according to the result. A signal is generated and output to the progressive conversion circuit 20. As a result, the edge direction can be determined in consideration of the correlation with the surrounding pixels, the accuracy of the edge direction determination can be improved, and smooth interpolation can be performed along the edge direction. Accordingly, it is possible to accurately determine the edge direction and generate a high-definition interpolated image, and to output a video signal of good progressive scanning.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
FIG. 11 is a block diagram illustrating a configuration example of the image processing apparatus 4 according to the fourth embodiment. FIG. 11 illustrates an example of an imaging system to which the image processing device 4 according to the fourth embodiment is applied. 11, constituent elements having the same functions as those shown in FIGS. 1 and 9 are given the same reference numerals, and redundant descriptions are omitted.

  The imaging system shown in FIG. 11 includes a CCD 11, an A / D converter 12, a camera signal processing circuit 13, and an image processing device 4. The image processing apparatus 4 includes a field memory 14, a cluster analysis circuit 15, a shape determination circuit 31B, an edge direction determination circuit 41, an intra-field interpolation signal generation circuit 32B, a motion determination circuit 33, an interpolation signal generation circuit 34, and a progressive conversion circuit 20. Have The image processing device 4 uses the interlaced scanning video signal (output signal of the camera signal processing circuit 13) S11 as an input signal, generates an interpolated image by performing edge direction determination using cluster analysis, etc., and performs progressive scanning. The video signal S21 is output.

  The shape determination circuit (determination means, shape determination means) 31B receives the output signals S12 and S13 of the cluster analysis circuit 15, and the shape of the region where the cluster analysis processing has been performed based on the result of the cluster analysis indicated by the output signals S12 and S13. Determine. The shape determination circuit 31B outputs an output signal S31B for controlling the operation of the edge direction determination circuit 41 to the edge direction determination circuit 41 according to the determination result.

  Specifically, the shape determination circuit 13B detects an edge shape of an orthogonal corner that causes a problem in the edge direction determination processing in the edge direction determination circuit 41. When the shape of the area subjected to the cluster analysis process includes an edge shape with an orthogonal angle, the output signal S35 of the edge direction determination circuit 41 is controlled. An example of the edge shape of the orthogonal corner is shown in FIG. Note that the shape shown in FIG. 12 is an example, and includes a shape obtained by rotating and inverting this shape.

The shape determination circuit 31B determines the number of clusters divided by the output signal S13 of the cluster analysis circuit 15, and performs processing according to the number of clusters.
When the number of divided clusters is 1, it means that the area where the cluster analysis processing has been performed has been merged into one cluster, so that it can be determined to be a plane. Accordingly, the shape determination circuit 31B outputs “0” as the output signal S31B because it is not the corresponding pattern (the shape of the edge of the orthogonal corner).

  When the number of divided clusters is 2, the shape determination circuit 31B compares the edge shape between the region subjected to the cluster analysis process and the corresponding pattern. The shape determination circuit 31B outputs “1” as the output signal S31B when the edge shapes match, and outputs “1” as the output signal S31B. If the edge shapes do not match, the shape determination circuit 31B outputs the corresponding pattern. Therefore, “0” is set as the output signal S31B.

  Further, when the number of divided clusters is 3 or more, it can be determined that the area where the cluster analysis process is performed is a chaotic area including a plurality of edges. Therefore, the shape determination circuit 31B cannot determine the shape of the edge and cannot determine whether the pattern is the corresponding pattern, and therefore outputs “0” as the output signal S31B.

  The edge direction determination circuit 41 receives the interlaced scanning video signal S11 and the output signal S31B of the shape determination circuit 31B, determines the direction of the edge at the interpolation point based on them, and outputs the determination result as an output signal S35. . Details of the edge direction determination processing in the edge direction determination circuit 41 will be described later.

  The intra-field interpolation signal generation circuit (first interpolation signal generation means) 32B receives the interlaced scanning video signal S11 and the output signal S35 of the edge direction determination circuit 41, and generates an intra-field interpolation signal. Here, the intra-field interpolation signal generation circuit 32B of the present embodiment uses the average value of pixels in the direction indicated by the output signal S35 of the edge direction determination circuit 41 as the intra-field interpolation signal in the upper and lower lines of the interpolation point.

The edge direction determination process by the edge direction determination circuit 41 will be described.
FIG. 13 is a conceptual diagram showing edge direction determination processing in the present embodiment, and schematically illustrates pixels used when edge direction determination is performed. In the following description, a case where edge direction determination is performed in three directions will be described as an example, but the present invention is not limited to this.

  In FIG. 13, three pixels that are continuous in the horizontal direction of the line above the interpolation point centered on the point of interest x that is the interpolation point are defined as f, d, and g, and continuous in the horizontal direction of the line below the interpolation point. Let these three pixels be h, e, and i. The edge direction determination circuit 41 outputs “0” as the output signal S35 when it is determined that the edge direction is the vertical direction (pixel d−pixel e direction) as a result of the edge direction determination processing. Similarly, when it is determined that the edge direction is the diagonal direction and the direction of the pixel f-pixel i, “1” is output as the output signal S35, and the edge direction is determined to be the diagonal direction and the direction of the pixel g-pixel h. In this case, “2” is output as the output signal S35.

FIG. 14 is a flowchart illustrating a flow of edge direction determination processing according to the fourth embodiment.
When the processing starts, the edge direction determination circuit 41 first performs initial setting processing of data to be used (S501). FIG. 15 is a flowchart showing the initial setting process in step S501 shown in FIG. The edge direction determination circuit 41 calculates the absolute value of the difference value between the pixel f and the pixel i as the difference value in the oblique direction, and sets it as difX1 (S601). Similarly, the absolute value of the difference value between the pixel g and the pixel h is calculated as the difference value in the diagonal direction, and is set as difX2 (S602). Further, the absolute value of the difference value between the pixel d and the pixel e is calculated as the difference value in the vertical direction, and is set as difX (S603).

  Next, the edge direction determination circuit 41 compares difX1 and difX2 (S502, S503).

  As a result of comparison, if difX1 is greater than difX2 (Yes in S502), the minimum value of the difference value in the diagonal direction is difX2, so the edge direction determination circuit 41 sets difX2 as difmin (S504). In addition, the edge direction determination circuit 41 sets and holds 2 indicating the direction at that time as difsel (S505).

  On the other hand, when difX2 is greater than difX1 (No in S502 and No in S503), the minimum value of the difference value in the diagonal direction is difX1, and therefore the edge direction determination circuit 41 sets difX1 as difmin (S506). ). Further, the edge direction determination circuit 41 sets and holds 1 indicating the current direction as difsel (S507).

  Further, when the values of difX1 and difX2 are equal (No in S502 and Yes in S503), the correlation in the diagonal direction is equal, and therefore the edge direction determination circuit 41 determines that both directions are the edge direction. Does not judge. Then, the edge direction determination circuit 41 outputs “0” as the output signal S35 (S508).

  Next, when difsel is not 0, the edge direction determination circuit 41 compares difX that is the difference value in the vertical direction with difmin that is the minimum value of the difference value in the oblique direction (S509).

  As a result, if difX is larger than difmin (Yes in S509), the edge direction determination circuit 41 selects a value set in difsel (S510). On the other hand, when difX is smaller than difmin or when the values of difX and difmin are equal (No in S509), the edge direction determination circuit 41 outputs “0” as the output signal S35 (S508).

  Next, the edge direction determination circuit 41 determines whether the output signal S31B of the shape determination circuit 31B is “1” or “0” (S511). As a result, when the output signal S31B is “1”, it means that the shape of the edge of the interpolation point is not an orthogonal angle, so the edge direction determination circuit 41 outputs difsel as the output signal S35. (S512). On the other hand, when the output signal S31B is “0”, it means that the edge shape of the interpolation point is an orthogonal angle, so the edge direction determination circuit 41 determines the edge direction as the vertical direction determination result. Therefore, “0” is output as the output signal S35 (S508).

  According to the fourth embodiment, the shape of the edge of the image and the movement of the image between fields are determined using cluster analysis processing, and the output signal S32A and the output signal S14 are linearly synthesized according to the result. Then, an interpolation signal is generated and output to the progressive conversion circuit 20. This makes it possible to determine the edge direction in consideration of the correlation with surrounding pixels, improve the accuracy of the edge direction determination, generate a high-definition interpolated image, and generate a good progressive scan video signal. Can be output.

(Other embodiments of the present invention)
For realizing the functions of the above-described embodiment for a computer (CPU or MPU) in an apparatus or system connected to the various devices so that the various devices are operated to realize the functions of the above-described embodiments. Supply software programs. And what was implemented by operating the said various devices according to the program stored in the computer of the system or the apparatus is also contained under the category of this invention.
In this case, the software program itself realizes the functions of the above-described embodiments, and the program itself constitutes the present invention. Further, means for supplying the program to the computer, for example, a recording medium storing the program constitutes the present invention. As a recording medium for storing such a program, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.
In addition, such a program is also included in the embodiment of the present invention when the function of the above-described embodiment is realized in cooperation with an operating system running on a computer or other application software. Needless to say.
Further, after the supplied program is stored in a memory provided in a function expansion board or a function expansion unit related to the computer, a CPU or the like provided in the function expansion board or the like based on an instruction of the program may be a part of actual processing or Do everything. Needless to say, the present invention includes the case where the functions of the above-described embodiments are realized by the processing.

For example, the image processing apparatuses shown in the first to fourth embodiments have a computer function 700 as shown in FIG. 16, and the CPU 701 performs operations in the embodiments.
As shown in FIG. 16, the computer function 700 includes a CPU 701, a ROM 702, and a RAM 703. Further, a controller (CONSC) 705 of the operation unit (CONS) 709 and a display controller (DISPC) 706 of a display (DISP) 710 as a display unit such as a CRT or LCD are provided. Furthermore, a hard disk (HD) 711, a controller (DCONT) 707 of a storage device (STD) 712 such as a flexible disk, and a network interface card (NIC) 708 are provided. These functional units 701, 702, 703, 705, 706, 707, and 708 are configured to be communicably connected to each other via a system bus 704.
The CPU 701 comprehensively controls each component connected to the system bus 704 by executing software stored in the ROM 702 or the HD 711 or software supplied from the STD 712. That is, the CPU 701 reads out from the ROM 702, the HD 711, or the STD 712 and executes a processing program for performing the above-described operation, thereby performing control for realizing the operation in each of the above-described embodiments. The RAM 703 functions as a main memory or work area for the CPU 701.
The CONSC 705 controls an instruction input from the CONS 709. The DISPC 706 controls the display of the DISP 710. The DCONT 707 controls access to the HD 711 and the STD 712 that store a boot program, various applications, user files, a network management program, the processing program in each embodiment, and the like. The NIC 708 exchanges data with other devices on the network 713 in both directions.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is a figure which shows the structural example of the image processing apparatus which concerns on 1st Embodiment. It is a figure which shows the specific example of a hierarchical cluster analysis process. It is a flowchart which shows the hierarchical cluster analysis process in 1st Embodiment. It is a figure which shows the specific example of a non-hierarchical cluster analysis process. It is a flowchart which shows the non-hierarchical cluster analysis process in 1st Embodiment. It is a flowchart which shows the correlation determination process in 1st Embodiment. It is a figure which shows an example of the pattern used for a correlation determination process. It is a figure which shows the structural example of the image processing apparatus which concerns on 2nd Embodiment. It is a flowchart which shows the correlation determination process in 2nd Embodiment. It is a figure which shows the structural example of the image processing apparatus which concerns on 3rd Embodiment. It is a figure which shows the structural example of the image processing apparatus which concerns on 4th Embodiment. It is a figure which shows an example of the pattern used for a shape determination process. It is a conceptual diagram which shows the edge direction determination process in 4th Embodiment. It is a flowchart which shows the edge direction determination process in 4th Embodiment. It is a flowchart which shows the initial data setting process shown in FIG. It is a figure which shows the computer function which can implement | achieve the image processing apparatus in this embodiment.

Explanation of symbols

1-4 Image processing device 14 Field memory 15, 16 Cluster analysis circuit 17A, 17B Correlation determination circuit 18, 32A, 32B Inter-field interpolation signal generation circuit 19 Selector 20 Progressive conversion circuit 21, 34 Interpolation signal generation circuit 31A, 31B Shape determination Circuit 33 Motion determination circuit 41 Edge direction determination circuit

Claims (12)

Holding means for holding interlaced scanning video signals for at least one field;
Analysis processing means for performing cluster analysis processing by dividing the interlaced scanning video signal into a region centered on the pixel position of interest;
Using the result of cluster analysis processing by the analysis processing means, determination means for determining the shape of the image of the area where the cluster analysis processing has been performed and the movement of the image between fields,
First interpolation signal generation means for generating an intra-field interpolation signal by weighting and adding the pixel value of the reference pixel position according to the distance from the target pixel position based on the determination result of the determination means;
Based on the result of the determination by the determination means, an interpolation signal is generated from the video signal of one field before output from the holding means and the intra-field interpolation signal generated by the first interpolation signal generation means. Second interpolation signal generating means;
An image processing apparatus comprising: a conversion unit that alternately outputs the input interlaced video signal and the interpolation signal generated by the second interpolation signal generation unit. The analysis processing means includes a first analysis processing means for performing a cluster analysis process on the input interlaced video signal, and a cluster analysis for the one-field previous video signal output from the holding means. Second analysis processing means for performing processing,
The determination means compares the pattern prepared in advance using the result of the cluster analysis processing by the first analysis processing means and the second analysis processing means, and the edge of the image of the area subjected to the cluster analysis processing The image processing apparatus according to claim 1, wherein it is determined whether or not the shapes match. The determination means determines whether or not the shape of the edge of the image of the area where cluster analysis processing has been performed and the pattern prepared in advance match,
The second interpolation signal generation means is a video signal one field before output from the holding means, or a field generated by the first interpolation signal generation means, depending on the result of determination by the determination means. 3. The image processing apparatus according to claim 2, wherein any one of the inner interpolation signals is selected and output in units of pixels. The determination means determines the proportion of pixels in which the shape of the edge of the image of the area in which the cluster analysis process has been performed and the pattern prepared in advance match,
The second interpolation signal generation unit is configured to output a one-field previous video signal output from the holding unit and a field generated by the first interpolation signal generation unit according to the ratio obtained by the determination unit. The image processing apparatus according to claim 2, wherein the interpolation signal is generated by synthesizing the interpolation signal. The determination unit includes a shape determination unit that determines the shape of the edge of the image of the area subjected to the cluster analysis process, and a motion determination unit that determines the movement of the image between fields.
The second interpolation signal generation unit is configured to output a one-field previous video signal output from the holding unit and a field generated by the first interpolation signal generation unit according to the determination result of the motion determination unit. The image processing apparatus according to claim 1, wherein the interpolation signal is generated by synthesizing with an inner interpolation signal.   The motion determination unit determines a motion of an image between fields based on the video signal of one field before output from the holding unit and the intra-field interpolation signal generated by the first interpolation signal generation unit. The image processing apparatus according to claim 5.   The image processing apparatus according to claim 5, wherein the shape determination unit determines whether or not the image of the region subjected to the cluster analysis process includes an orthogonal angle.   The analysis processing means ends the cluster analysis processing when the difference value of the pixel values between the compared clusters reaches a certain value or more. The image processing apparatus described.   8. The cluster analysis process according to claim 1, wherein the analysis processing unit terminates the cluster analysis process when a distance between clusters obtained from a pixel value and a distance from the target pixel position is equal to or greater than a predetermined value. The image processing apparatus according to any one of the above.   8. The determination unit according to claim 1, wherein when the number of divided clusters is equal to or greater than a predetermined value, the determination unit does not compare the classification information pattern of the cluster analysis process. 9. Image processing device. An analysis processing step for performing cluster analysis processing by dividing the interlaced scanning video signal into a region centered on the target pixel position;
Using the result of the cluster analysis process, a determination step of determining the shape of the image of the area subjected to the cluster analysis process and the movement of the image between fields,
A first interpolation signal generation step of generating an intra-field interpolation signal by weighting and adding the pixel value of the reference pixel position according to the distance from the target pixel position based on the determination result in the determination step;
Based on the result of the determination in the determination step, the video signal of one field before output from the holding means for holding the video signal of the interlace scan for at least one field, and the first interpolation signal generation step A second interpolation signal generation step of generating an interpolation signal from the generated intra-field interpolation signal;
An image processing method comprising: a conversion step of alternately outputting the input interlaced video signal and the interpolation signal generated in the second interpolation signal generation step. An analysis processing step for performing cluster analysis processing by dividing the interlaced scanning video signal into a region centered on the target pixel position;
Using the result of the cluster analysis process, a determination step of determining the shape of the image of the area subjected to the cluster analysis process and the movement of the image between fields;
A first interpolation signal generation step of generating an intra-field interpolation signal by weighting and adding the pixel value of the reference pixel position according to the distance from the target pixel position based on the determination result in the determination step;
Based on the result of the determination in the determination step, the video signal of one field before output from the holding means for holding the video signal of the interlace scan for at least one field, and the first interpolation signal generation step A second interpolation signal generation step of generating an interpolation signal from the generated intra-field interpolation signal;
A program for causing a computer to execute a conversion step of alternately outputting the input interlaced video signal and the interpolation signal generated in the second interpolation signal generation step.

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