JP2009164220A - Electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component having a passive element formed on a multi-layer ceramics substrate having a penetrating electrode and internal wiring, curving of the multi-layer ceramics substrate being suppressed. <P>SOLUTION: The present invention relates to the electronic component having the multi-layer ceramics substrate 20 having the penetrating electrode and internal wiring; an upper insulating film 26 provided on a top surface of the multi-layer ceramics substrate 20; a lower insulating film 28, provided on the lower surface of the multi-layer ceramics substrate 20 and made of the same material as that of the upper insulating film; and passive elements 120 and 140 provided on the upper insulating film 26. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electronic component, and more particularly to an electronic component in which a passive element is provided on a multilayer ceramic substrate.

  When performing phase matching of a high frequency circuit, an inductor or a capacitor is used. For example, in a radio frequency (RF) system such as a mobile phone or a wireless local area network (LAN), the same applies to devices mounted in the same manner due to demands for miniaturization, cost reduction, and high performance of the system itself. The request is sought. In order to satisfy this requirement, electronic components such as integrated passive elements in which passive elements are integrated are used.

  As one of the methods for satisfying these requirements, an integrated passive element that uses a low temperature co-fired ceramic (LTCC) technique and has a passive element built in a multilayer ceramic substrate has been developed. In addition, an integrated passive element in which a passive element is formed on a multilayer ceramic substrate has been developed. However, since the relative permittivity of the ceramic substrate is larger than that of the quartz substrate, there is a problem that, for example, the Q value of the inductor is lowered and a high Q value passive element cannot be manufactured.

Patent Documents 1 and 2 disclose a technique in which a coating layer is provided on a ceramic substrate and a passive element is formed on the coating layer.
JP 2007-123468 A JP 2007-31242 A

  When a passive element such as an inductor is formed on a multilayer ceramic substrate, the passive element is formed on an insulating film having a relative dielectric constant smaller than that of the multilayer ceramic substrate. Thereby, the dielectric loss of a passive element can be suppressed. In the manufacturing process for forming the passive element, the multilayer ceramic substrate is heated to a high temperature of 200 ° C. to 300 ° C. Therefore, it is preferable to use a resin-based insulating film such as PBO (Polybenzoxazole) or BCB (Benzocyclobutene) having low heat resistance. Absent. As the insulating film, an insulating film having high heat resistance such as SOG is preferable. However, the insulating film tends to generate internal stress. On the other hand, since the multilayer ceramic substrate has through electrodes and internal wiring, stress imbalance is likely to occur and warp easily. On such a multilayer ceramic substrate, an oxide having a film thickness that can suppress induction loss of passive elements. When the film is formed, the multilayer ceramic substrate is greatly warped. This hinders subsequent formation of passive elements.

  The present invention has been made in view of the above problems, and an object thereof is to suppress warping of a multilayer ceramic substrate in an electronic component in which a passive element is formed on a multilayer ceramic substrate having a through electrode and internal wiring.

  The present invention provides a multilayer ceramic substrate having a through electrode and an internal wiring, an upper insulating film provided on the upper surface of the multilayer ceramic substrate, and a lower portion of the same material as the upper insulating film provided on the lower surface of the multilayer ceramic substrate. An electronic component comprising: an insulating film; and a passive element provided on the upper insulating film. According to the present invention, the warpage of the multilayer ceramic substrate can be suppressed by forming the insulating films of the same material on the upper surface and the lower surface of the multilayer ceramic substrate.

  In the above configuration, the upper insulating film and the lower insulating film may be formed of an SOG oxide film. In the above structure, the upper insulating film and the lower insulating film may be formed of a photosensitive SOG oxide film.

  In the above structure, the upper insulating film and the lower insulating film may have the same film thickness. According to this configuration, warpage of the multilayer ceramic substrate can be further suppressed.

  In the above structure, a lower passive element provided under the lower insulating film may be provided. According to this configuration, the mounting density of passive elements can be increased.

  The said structure WHEREIN: The said upper insulating film can be set as the structure which has an opening part which exposes the upper surface of the said penetration electrode.

  In the above configuration, the upper passive element is an inductor, or an inductor and a capacitor, and the inductor is spaced apart from a spiral first coil provided on the insulating film via a gap above the first coil. And a spiral second coil provided.

  According to the present invention, the warp of the multilayer ceramic substrate can be suppressed by forming the insulating films on the upper surface and the lower surface of the multilayer ceramic substrate.

First, a method for manufacturing a multilayer ceramic substrate will be described with reference to FIGS. Referring to FIGS. 1 (a) and 1 (b), for example, a metal such as alumina (Al ₂ O ₃ ), silicon oxide (SiO ₂ ), titanium oxide (TiO ₂ ), or calcium oxide (CaO). The grease sheet 10 made of oxide is formed and cut into a desired shape. With reference to FIG. 2A and FIG. 2B, the sheet 10 is punched to form the through holes 11. 3A and 3B, a metal such as Ag, Au, or Cu is embedded in the through hole 11. Thereby, the through electrode 12 is formed. 4A and 4B, a metal wiring 13 made of, for example, Ag, Au, or Cu is formed on the surface of the sheet 10. With reference to FIG. 5A and FIG. 5B, a plurality of sheets 10a to 10c formed in this way are stacked. For example, in FIG.5 (b), it laminate | stacks so that the penetration electrode 12a of the sheet | seat 10a and the penetration electrode 12b of the sheet | seat 10b may connect. The laminated sheets 10a to 10c can be further shaped into a desired shape. For example, a wafer shape may be used so that subsequent passive elements can be easily formed.

  With reference to FIG. 6, the laminated sheets 10 a to 10 b are fired to form a multilayer ceramic substrate 20. Furthermore, in order to set the thickness and surface roughness of the multilayer ceramic substrate 20 to desired values, the surface of the multilayer ceramic substrate 20 is polished using loose abrasive grains or fixed abrasive grains. Since the sheets 10a to 10c contract during firing, the upper surface of the through electrode protrudes. Further, during the polishing, the sheet 10a is easily polished, but the through electrode made of metal is difficult to polish, so that the through electrode 12a further protrudes. Thus, the upper surface of the through electrode is higher than the upper surface of the multilayer ceramic substrate 20. The protruding amount t1 of the through electrode 12a from the surface of the sheet 10a is, for example, about 0.5 μm to 10 μm.

  With reference to FIGS. 7A to 9D, a method of manufacturing an integrated passive element according to the first embodiment will be described. Referring to FIG. 7A, the multilayer ceramic substrate 20 is manufactured by the method described with reference to FIGS. The multilayer ceramic substrate 20 is provided with through electrodes 12 and internal wirings 16.

  Referring to FIG. 7B, the electroless plating method is used on the surface of the through electrode 12 to protect from the multilayer ceramic substrate 20 side, for example, a Ni film having a thickness of 1 μm to 3 μm and an Au film having a thickness of 0.1 μm to 3 μm. Films 22 and 24 are formed. A Pd film having a thickness of, for example, 0.1 μm to 0.3 μm may be provided between the Au film and the Ni film of the protective films 22 and 24. The protective films 22 and 24 have a function of protecting the surface of the through electrode 12 and suppress diffusion of atoms of the connection terminal and the through electrode 12 to each other.

  As shown in FIG. 7C, the upper surface of the multilayer ceramic substrate 20 is spin-coated using a photosensitive SOG (spin on glass) as the upper insulating film 26. For example, XC3380i manufactured by Sliecs is used as the photosensitive SOG. The upper insulating film 26 may be formed by an immersion method other than the spin coating method. Spin coating may be performed a plurality of times, and the SOG film thickness may be set to a desired value. For example, heat treatment is performed at 120 ° C. With reference to FIG. 7D, the opening 25 of the upper insulating film 26 is formed so that the upper surface of the through electrode 12 is opened by exposure and development. For example, curing is performed at 250 ° C. As a result, an SOG oxide film is formed as the upper insulating film 26.

  Referring to FIG. 8A, photosensitive SOG is applied to the lower surface of the multilayer ceramic substrate 20 as the lower insulating film 28 in the same manner as FIG. 7C. Similarly to FIG. 7D, an opening 27 is formed in the lower insulating film 28 so that the lower surface of the through electrode 12 is exposed. With reference to FIG. 8B, a metal layer 30 is formed on the upper insulating film 26. The metal layer 30 is made of, for example, a Cr film having a thickness of 20 nm, an Au film having a thickness of 1000 nm, and a Ti film having a thickness of 20 nm. The Au film may be a Cu film. The metal layer 30 may be a Ti film having a thickness of 20 nm, a Cu film having a thickness of 800 nm, a Ti film having a thickness of 200 nm, and an Au film having a thickness of 20 nm from the bottom. In order to reduce electrical resistance, the metal layer 30 preferably includes Al, Au, and Cu films as main films. Referring to FIG. 8C, a predetermined region of the metal layer 30 is removed using, for example, an ion milling method. Thereby, the lower electrode 41 of the capacitor is formed from the metal layer 30.

With reference to FIG. 9A, a dielectric film 42 is formed on the lower electrode 41. The dielectric film 42 is formed by using, for example, a sputtering method or PECVD (Plasma enhanced chemical vapor deposition), and an SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ or Ta ₂ O ₃ film can be used. The film thickness of the dielectric film 42 can be, for example, 195 nm to 500 nm.

  Referring to FIG. 9B, on the upper insulating film 26 and the metal layer 30, for example, a Ti film with a film thickness of 50 nm and an Au film with a film thickness of 200 nm, or a Ti film with a film thickness of 50 nm and a film thickness of 200 nm. A seed layer (not shown) made of a Cu film is formed. For example, a plating layer 184 made of Cu having a thickness of 10 μm is formed in a predetermined region on the seed layer by using an electrolytic plating method. The seed layer is removed using the plating layer 184 as a mask. As described above, the upper electrode 43 is formed from the plating layer 184. A capacitor 40 is formed by the lower electrode 41, the dielectric film 42 and the upper electrode 43. A coil of the inductor 50 is formed from the plating layer 184. Further, a lower layer of the connection terminal is formed from the plating layer 184.

  Referring to FIG. 9C, a low dielectric film 60 is formed on the multilayer ceramic substrate 20 so as to cover the plating layer 184. As the low dielectric film 60, PBO, BCB, or the like can be used.

  Referring to FIG. 9D, a predetermined region of the low dielectric film 60 is removed, and the upper surface of the plating layer 184 on which the upper plating layer is to be formed is exposed. A plating layer 186 made of Cu having a thickness of 10 μm, for example, is formed using an electrolytic plating method so as to be in contact with the plating layer 184. When forming the plating layer 186, a seed layer is used as in the description in FIG. 9A, but the description is omitted. A pad layer 193 made of, for example, an Au film and a Ni film is formed on the plating layer 186. On the through electrode 12, a connection terminal 92 including plating layers 184 and 186 and a pad layer 193 is formed. Thus, an integrated passive element using the multilayer ceramic substrate 20 is completed.

  FIG. 10 is a view in which a chip is flip-chipped on an integrated passive element, and is a cross-sectional view different from FIGS. 9 (a) to 9 (d). Passive elements such as capacitors and inductors are not shown. Referring to FIG. 10, bumps 194 made of metal such as solder or Au are formed on connection terminals 92. A chip 199 on which an electronic element such as a surface acoustic wave filter or an IC is formed is flip-chip mounted on the connection terminal 92 using the bump 194. Thus, the electronic component according to Example 1 is completed.

  According to the first embodiment, the upper insulating film 26 and the lower insulating film 28 made of the same material are provided on both surfaces of the multilayer ceramic substrate 20. As a result, when the upper insulating film 26 and the lower insulating film 28 use the same insulating material to compensate for the stress, and the insulating film is formed on the multilayer ceramic substrate 20 having the through electrode 12 and the internal wiring 16. Can be suppressed.

  As the upper insulating film 26 and the lower insulating film 28, it is preferable to use an SOG oxide film formed using SOG. The relative dielectric constant of the film made of SOG is about 2.5 to 4, and the relative dielectric constant of the multilayer ceramic substrate 20 is about 7 to 12. Therefore, the loss of the passive element can be reduced. A film made of SOG can be formed by coating. In addition, heat resistance is high. In order to form a passive element as shown in FIGS. 9A to 9D, a temperature of 200 ° C. to 300 ° C. is applied. Since a resin such as BCB does not have heat resistance, a manufacturing method for forming a passive element on the multilayer ceramic substrate 20 is limited. According to the first embodiment, by using films made of SOG as the upper insulating film 26 and the lower insulating film 28, a passive element can be formed more easily.

  Further, a photosensitive SOG oxide film is preferably used as the upper insulating film 26 and the lower insulating film 28. Thereby, as shown in FIG. 7D, the openings 25 and 27 can be easily formed in the upper insulating film 26 and the lower insulating film 28, respectively.

  The film thickness of the upper insulating film 26 and the lower insulating film 28 is preferably the same. Thereby, the curvature of the multilayer ceramic substrate 20 can be further suppressed.

  The upper insulating film has an opening 25 that exposes the upper surface of the through electrode 12. Thereby, the through electrode 12 and the passive element can be electrically connected via the opening 25.

  Example 2 is an example in which a photosensitive SOG oxide film is not used. The method of the multilayer ceramic substrate of Example 2 will be described with reference to FIGS. 11 (a) to 12 (c). Referring to FIG. 11A, the same multilayer ceramic substrate 20 as that of FIG. Referring to FIG. 11B, protective films 32 and 34 are formed on the upper and lower surfaces of the multilayer ceramic substrate 20 by sputtering. As the protective films 32 and 34, for example, a Ti film having a thickness of 0.1 μm to 0.5 μm and a TiW film having a thickness of 0.5 μm to 3 μm can be used from the multilayer ceramic substrate 20 side. Further, a Cu film having a film thickness of, for example, 0.3 μm to 3 μm can be provided on the Ti film. Further, as the protective films 32 and 34, a Ti film having a film thickness of 0.1 μm to 0.5 μm and an Au film having a film thickness of 0.5 μm to 3 μm can be used. Referring to FIG. 11C, the protective films 32 and 34 in a predetermined region are easily removed so that the protective films 32 and 34 on the through electrode 12 remain.

  Referring to FIG. 12A, SOG is applied to the upper and lower surfaces of the multilayer ceramic substrate 20 as the upper insulating film 26 and the lower insulating film 28 so as to cover the through electrodes 12 and the protective films 32 and 34, respectively. The upper surfaces of the upper insulating film 26 and the lower insulating film 28 are preferably flat. As SOG, for example, LNT-025 manufactured by Catalytic Activity may be used. Thereafter, the upper insulating film 26 and the lower insulating film 28 are cured at 400 ° C., for example. Referring to FIG. 12B, the upper insulating film 26 on the through electrode 12 and the lower insulating film 28 under the through electrode 12 are removed using an HF aqueous solution. Referring to FIG. 12C, the same process as that of FIG. 8B and FIG. 8C of Example 1 is performed to form a metal layer 30 on the upper insulating film 26. Thereafter, the same steps as those in FIGS. 9A to 9D of the first embodiment are performed, and the integrated passive element according to the second embodiment is completed.

  As in Embodiment 2, non-photosensitive SOG can be used for the upper insulating film 26 and the lower insulating film 28.

  Example 3 is an example having an inductor in which two coils are stacked with a gap as a passive element. FIG. 13 is a perspective view of the integrated passive element according to the third embodiment, and FIG. 14 is a top view (the first coils 111 and 121 are not shown). Referring to FIG. 13 and FIG. 14, on the upper insulating film 26 formed on the multilayer ceramic substrate 20, the inductor 110 including the first coil 111 and the second coil 112, and the first coil 121 and the second coil 122 are included. An inductor 120 is formed. The inner ends (ends of the innermost circumference) of the first coil 111 and the second coil 112 of the inductor 110 are electrically connected to each other by the connection portion 165, and the first coil 111 has a wiring 152 at the outer ends (ends of the outermost circumference). The second coil 112 is electrically connected to the wiring 151 through the connection portion 160 at the outer end.

  The inner ends of the first coil 121 and the second coil 122 of the inductor 120 are connected to each other by a connection portion 175, the first coil 121 is connected to the wiring 154 at the outer end, and the second coil 122 is connected to the connection portion 170 at the outer end. And is connected to the wiring 153. The wirings 151 to 154 are formed on the upper insulating film 26 formed on the multilayer ceramic substrate 20 and are connected to the connection terminals 131 to 134. The connection terminals 132 and 133 are connected by a wiring 157. A capacitor 140 including a lower electrode 141, a dielectric film 142, and an upper electrode 143 is connected between the connection terminals 131 and 134. The upper electrode 143 and the wiring 151 are connected by the upper wiring 156. The integrated passive element 100 forms a π-type LCL circuit between the connection terminals 131 and 134 by connecting the connection terminal 131 as input, connecting terminal 134 as output, and connecting terminals 132 and 133 as ground.

  Next, a method for manufacturing an integrated passive element according to Example 3 will be described with reference to FIGS. FIGS. 15A to 15D are schematic cross-sectional views corresponding to the AA cross section of FIG. 15A to 15D show connection terminals 198 for strengthening the mechanical connection between the chip and the multilayer ceramic substrate 20, but they are not shown in FIGS. Absent.

  Referring to FIG. 15A, the steps up to FIG. 8C of Example 1 are performed. The metal layer 30 is illustrated as a metal layer 180, and the capacitor lower electrode 41 is illustrated as a lower electrode 141. As in FIG. 9A, a capacitor dielectric film 142 is formed.

  Referring to FIG. 15B, a seed layer (not shown) for electrolytic plating is formed. A photoresist 200 having an opening for plating is formed. Electrolytic plating is performed in the opening to form a plating layer 184 made of Cu having a thickness of 10 μm, for example. Thus, the first coil 121, the upper electrode 143, the wirings 153 and 154, and the lower portion of the connection terminal are formed from the plating layer 184. The MIM capacitor 140 is formed from the lower electrode 141, the dielectric film 142, and the upper electrode 143.

  Referring to FIG. 15C, the photoresist 200 is removed. A photoresist 202 having an opening for plating is formed. Electrolytic plating is performed in the opening to form a plating layer 186 made of Cu having a thickness of 10 μm, for example. As a result, the strut portions 174 and 176 and the intermediate portion of the connection terminal are formed from the plating layer 186.

  Referring to FIG. 15D, the photoresist 202 is removed. A sacrificial layer photoresist 204 is applied. The upper surface of the sacrificial layer photoresist 204 is substantially flat with the upper surfaces of the support columns 174 and 176. A seed layer (not shown) for electrolytic plating is formed on the entire surface of the sacrificial layer photoresist 204. A photoresist 206 having an opening for plating is formed on the seed layer. Electrolytic plating is performed in the opening to form a plating layer 188 made of Cu having a thickness of 10 μm, for example. Thus, the second coil 122, the wiring 156, and the upper part of the pad are formed from the plating layer 188. A connection part 170 and a connection part 175 are formed from the plating layers 184, 186 and 188.

  Referring to FIG. 16A, a photoresist 208 having an opening is formed. An Ni layer 190 and an Au layer 192 are formed on the plating layer 188. Referring to FIG. 16B, the photoresist 208, the seed layer (not shown), the photoresist 206, and the sacrificial layer photoresist 204 are removed. Connection terminals 131, 133, and 198 are formed from the metal layer 180, the plating layers 184, 186, 188, the Ni layer 190, and the Au layer 192. Thus, the integrated passive element according to Example 3 is formed.

  A mounting method of the chip 199 will be described with reference to FIG. Referring to FIG. 16C, the chip 199 is flip-chip mounted on the connection terminals 131, 133 and 198 using bumps 194.

  FIG. 17 is a cross-sectional view corresponding to the BB cross section of FIG. 14 of the integrated passive element according to the third embodiment in which the chip 199 is flip-chip mounted. Referring to FIG. 17, chip 199 is flip-chip mounted on connection terminals 132 and 133.

  As in the third embodiment, the spiral first coils 111 and 121 provided on the upper insulating film 26 and the spiral second coil provided above the first coils 111 and 121 with a gap therebetween. The present invention can also be applied to an integrated passive element in which an inductor having 112 and 122 is formed.

  Example 4 is an example in which a lower electronic element is formed under the lower insulating film 28. Referring to FIG. 21, after FIG. 16C of the third embodiment, the lower passive layer is provided below the lower insulating layer 28 of the multilayer ceramic substrate 20, as in FIGS. 15A to 16C of the third embodiment. An element is formed. A metal layer 180a, plating layers 184a to 188a, a Ni film 190a, and an Au film 192a are formed. As a result, an inductor 120a is formed under the lower insulating film 28 as a lower passive element. A capacitor or a resistor can be used as the lower passive element. Similarly to FIG. 17 of the third embodiment, the chip 199a is flip-chip mounted on the lower passive element.

  As in the fourth embodiment, a lower passive element can be formed under the lower insulating film 28. According to the fourth embodiment, since the lower passive element is formed via the lower insulating film 28, the induction loss can be suppressed. Moreover, since the passive elements are formed above and below the multilayer ceramic substrate 20, the mounting density of the passive elements can be increased.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

FIGS. 1A and 1B are views (No. 1) illustrating a method for manufacturing a multilayer ceramic substrate, in which FIG. 1A is a top view and FIG. 1B is a cross-sectional view. FIGS. 2A and 2B are views (part 2) illustrating the method of manufacturing the multilayer ceramic substrate, in which FIG. 2A is a top view and FIG. 2B is a cross-sectional view. FIG. 3A and FIG. 3B are views (No. 3) showing the method for manufacturing a multilayer ceramic substrate, FIG. 3A is a top view, and FIG. 3B is a cross-sectional view. FIGS. 4A and 4B are views (part 4) illustrating the method for manufacturing a multilayer ceramic substrate, FIG. 4A is a top view, and FIG. 4B is a cross-sectional view. 5 (a) and 5 (b) are views (No. 5) showing the method for manufacturing the multilayer ceramic substrate, FIG. 5 (a) is a top view, and FIG. 5 (b) is a sectional view. FIG. 6 is a view (No. 6) illustrating the method for manufacturing the multilayer ceramic substrate. FIG. 7A to FIG. 7D are cross-sectional views (part 1) showing the method for manufacturing the integrated passive element according to the first embodiment. 8A to 8C are cross-sectional views (part 2) illustrating the method for manufacturing the integrated passive element according to the first embodiment. FIG. 9A to FIG. 9D are cross-sectional views (part 3) illustrating the method for manufacturing the integrated passive element according to the first embodiment. FIG. 10 is a diagram in which a chip is mounted on the integrated passive element according to the first embodiment. FIG. 11A to FIG. 11C are cross-sectional views (No. 1) showing the method for manufacturing the integrated passive element according to the second embodiment. 10A to 12C are cross-sectional views (part 2) illustrating the method for manufacturing the integrated passive element according to the second embodiment. FIG. 13 is a perspective view of an integrated passive element according to the third embodiment. FIG. 14 is a top view of the integrated passive element according to the third embodiment. FIG. 15A to FIG. 15D are cross-sectional views (part 1) illustrating the method for manufacturing the integrated passive element according to the third embodiment. 16A to 16C are cross-sectional views (part 2) illustrating the method for manufacturing the integrated passive element according to the third embodiment. FIG. 17 is a diagram in which a chip is mounted on an integrated passive element according to the third embodiment. FIG. 18 is a diagram in which a chip is mounted on an integrated passive element according to the fourth embodiment.

Explanation of symbols

10 Sheet 12 Through Electrode 20 Multilayer Ceramic Substrate 22, 32 Protective Film 26 Upper Insulating Film 28 Lower Insulating Film 40, 140 Capacitor 50, 110, 120 Inductor

Claims (7)

A multilayer ceramic substrate having through electrodes and internal wiring;
An upper insulating film provided on the upper surface of the multilayer ceramic substrate;
A lower insulating film provided on the lower surface of the multilayer ceramic substrate, made of the same material as the upper insulating film;
A passive element provided on the upper insulating film;
An electronic component comprising:   2. The electronic component according to claim 1, wherein the upper insulating film and the lower insulating film are made of SOG oxide films.   2. The electronic component according to claim 1, wherein the upper insulating film and the lower insulating film are made of a photosensitive SOG oxide film.   4. The electronic component according to claim 1, wherein the upper insulating film and the lower insulating film have the same film thickness. 5.   5. The electronic component according to claim 1, further comprising a lower passive element provided under the lower insulating film.   The electronic component according to claim 1, wherein the upper insulating film has an opening that exposes an upper surface of the through electrode. The upper passive element is an inductor, or an inductor and a capacitor;
The inductor includes a spiral first coil provided on the insulating film,
The electronic component according to claim 1, further comprising: a spiral second coil provided above the first coil with a gap therebetween.

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