JP2009163061A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device, not exerting any influence on correction of a threshold voltage of a TFT by suitably setting time constants of a wiring resistance and a parasitic capacity generated in a cathode wiring. <P>SOLUTION: This display device includes a pixel array part having row-like scanning lines, column-like data lines, pixels having light emitting elements disposed in a matrix at portions where the scanning lines and the data lines intersect, and adapted to perform spontaneous light emitting according to quantity of a current, power supply lines disposed corresponding to the respective rows of the pixels. The pixel array part includes a scanning line, a data line, and first wiring and second wiring, which form the power supply line. In the case of using either the first wiring or the second wiring as the cathode wiring of the light emitting element, the time constants of the wiring resistance and the parasitic capacity between the power supply line and the cathode wiring are set under the time for correcting the threshold voltage of a second transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to an active matrix display device using a light emitting element that emits light according to a current amount as a pixel.

  As flat and thin display devices, liquid crystal display devices using liquid crystals, plasma display devices using plasma, and the like have been put into practical use.

  The liquid crystal display device is a display device that displays an image by providing a backlight and changing the arrangement of liquid crystal molecules by applying a voltage so as to allow or block light from the backlight. In addition, the plasma display device enters a plasma state by applying a voltage to the gas sealed in the substrate, and the phosphor is irradiated with ultraviolet rays generated by energy generated when returning from the plasma state to the original state. This is a display device that displays visible light.

  On the other hand, in recent years, a self-luminous display device using an organic EL (electroluminescence) element that emits light when a voltage is applied has been developed. When receiving energy by electrolysis, the organic EL element changes from a ground state to an excited state, and emits differential energy as light when returning from the excited state to the ground state. The organic EL display device is a display device that displays an image using light emitted from the organic EL element.

  Unlike a liquid crystal display device that requires a backlight, the self-luminous display device does not require a backlight because the element emits light by itself, and thus can be made thinner than a liquid crystal display device. In addition, since the moving image characteristics, viewing angle characteristics, color reproducibility, and the like are superior to the liquid crystal display device, the organic EL display device has attracted attention as a next-generation flat thin display device.

Among the flat self-luminous display devices using organic EL elements as pixels, the development of an active matrix flat self-luminous display device in which thin film transistors (TFTs) are integrated in each pixel as a driving element, in particular. Has been actively conducted. For example, Patent Documents 1 to 5 describe active matrix type flat self-luminous display devices.

JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A Japanese Patent Laid-Open No. 2004-093682

  However, in the conventional active matrix type flat self light emitting display device, the threshold voltage and mobility of the TFT for driving the light emitting element vary due to process variations. In addition, the characteristics of the organic EL element also vary with time. Such variations in TFT characteristics and fluctuations in the characteristics of organic EL elements affect the light emission luminance of the screen. Therefore, in order to uniformly control the light emission luminance over the entire screen, it is necessary to correct variations in TFT characteristics and fluctuations in organic EL element characteristics in each pixel, and an active matrix type plane having such a correction function for each pixel. A self-luminous display device has been proposed.

  Conventionally, when an auxiliary capacitor is formed in a pixel circuit to determine a time for correcting the mobility of the TFT (mobility correction time), the auxiliary capacitor is connected via a fixed potential such as a power supply voltage or an auxiliary electrode. The cathode connection was made. In addition, a low-resistance material was selected for the cathode wiring, but the first wiring was used as the cathode wiring due to layout restrictions. The first wiring has a problem that the resistance is higher than that of the second wiring and the cathode potential fluctuates. Further, there is a problem in that the correction of the threshold voltage of the TFT for driving the light emitting element is affected by the fluctuation of the cathode potential.

  Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to appropriately set the time constant between the wiring resistance and the parasitic capacitance generated in the cathode wiring, thereby making the threshold of the TFT. It is an object of the present invention to provide a new and improved display device capable of not affecting voltage correction.

  In order to solve the above-described problem, according to one aspect of the present invention, a row-shaped scanning line, a column-shaped data line, and a scanning line and a data line are arranged in a matrix at the intersection, and the current amount is A display device including a pixel array unit including a pixel including a light-emitting element that emits light in response and a power supply line arranged corresponding to each row of the pixel, wherein the pixel array unit includes a scanning line and a data line , And a first wiring and a second wiring for forming a power supply line, and when either the first wiring or the second wiring is used as a cathode wiring of the light emitting element, the wiring resistance is between the power supply line and the cathode wiring. A display device is provided in which the time constant with respect to the parasitic capacitance is less than the time for correcting the threshold voltage of the second transistor.

  According to this configuration, the display device is arranged in a matrix at a portion where the row-shaped scanning lines, the column-shaped data lines, and the scanning lines and the data lines intersect, and emits light by itself according to the amount of current. The pixel array unit includes pixels including elements and power supply lines arranged corresponding to the respective rows of pixels. In such a configuration, the pixel array section includes a first wiring and a second wiring that form a scanning line, a data line, and a power supply line, and either the first wiring or the second wiring is used as a cathode wiring of the light emitting element. When used, the time constant of the wiring resistance and the parasitic capacitance between the power supply line and the cathode wiring is set to be less than the time for correcting the threshold voltage of the second transistor. As a result, the threshold voltage of the TFT can be corrected without affecting the correction of the threshold voltage of the TFT by appropriately setting the time constant between the wiring resistance and the parasitic capacitance generated in the cathode wiring.

  The time constant may be less than 0.1 microseconds. As a result, by setting the time constant between the wiring resistance and the parasitic capacitance generated in the cathode wiring so as to be less than 0.1 microsecond, the TFT threshold voltage is not affected, and the TFT threshold voltage is not affected. The voltage can be corrected.

  As described above, according to the present invention, the time constant between the wiring resistance and the parasitic capacitance generated in the cathode wiring can be appropriately set so as not to affect the correction of the threshold voltage of the TFT. An improved display device can be provided.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  First, a display device 100 according to an embodiment of the present invention will be described. FIG. 1 is an explanatory diagram illustrating the configuration of a display device 100 according to an embodiment of the present invention. Hereinafter, the configuration of the display device 100 according to an embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, a display device 100 according to an embodiment of the present invention includes a pixel array unit 102 including a plurality of pixels 101 arranged in a matrix, a horizontal selector (HSEL) 103, a light scanner ( (WSCN) 104 and power supply scanner (DSCN) 105.

  The pixel array unit 102 includes a plurality of (m in this embodiment) scanning lines WSL1 to WSLm extending from the light scanner 104 and a plurality (n in this embodiment) data lines DTL1 to DTLn extending from the horizontal selector 103. A plurality of (m × n in this embodiment) pixels (PXLC) 101 arranged in a matrix at the intersection of the scanning line and the data line, and the power supply scanner 105 corresponding to each row of the pixels 101. Power supply lines DSL1 to DSLm extending from the line. The write scanner 104 is an example of the scanning signal control unit of the present invention, and sequentially supplies the control signals to the scanning lines WSL1 to WSLm to scan the pixels 101 line by line. In this embodiment, a sequential scanning method is employed as the scanning method, but in the present invention, scanning may be performed by interlaced scanning. The power supply scanner 105 is an example of a power supply control unit according to the present invention. A first potential and a second potential lower than the first potential are applied to the power supply lines DSL1 to DSLm in accordance with the line sequential scanning performed by the write scanner 104. The power supply voltage that is switched at is supplied. The horizontal selector 103 is an example of a video signal control unit according to the present invention, and controls the supply of a signal potential that becomes a video signal and a reference potential to the data lines DTL1 to DTLn according to line sequential scanning by the write scanner 104. To do.

  For example, one pixel 101 may be configured by any one of a red light emitting subpixel that emits red light, a green light emitting subpixel that emits green light, and a blue light emitting subpixel that emits blue light. Further, the light-emitting elements constituting each pixel are driven line-sequentially, and the display frame rate is FR (times / second). In other words, the light emitting elements constituting each of the pixels 101 arranged in a certain row are driven simultaneously. In other words, in each light emitting element constituting one row, the light emission / non-light emission timing is controlled in units of rows to which each light emitting element belongs. The process of writing a video signal for each pixel constituting one row may be a process of writing a video signal for all the pixels at the same time, or may be a process of sequentially writing a video signal for each pixel. Which write processing is adopted may be appropriately selected according to the circuit configuration.

  As described above, the threshold voltage and mobility of the TFT for driving the light emitting element vary due to process variations, and the characteristics of the organic EL element also vary with time, so that the emission luminance is uniformly controlled over the entire screen. Therefore, variations in TFT characteristics and fluctuations in characteristics of organic EL elements are corrected in each pixel. That is, the threshold voltage correction process, the video signal writing process, and the mobility correction process of the TFTs that drive the light emitting elements are performed before the end of the horizontal scanning period of each light emitting element arranged in a row. Note that the video signal writing process and the mobility correction process need to be performed within the horizontal scanning period of each light emitting element arranged in a certain row. On the other hand, the threshold voltage correction processing of the TFT and the preprocessing associated with the threshold voltage correction processing may be performed prior to the horizontal scanning period.

  Then, after all of the above-described TFT threshold voltage correction processing, video signal writing processing, and mobility correction processing are completed, the light emitting units constituting the light emitting elements arranged in a row are caused to emit light. The light emitting unit may emit light immediately after the above-described processing ends, or the issuing unit may emit light after a predetermined period (for example, a horizontal scanning period of a predetermined number of rows) has elapsed. The predetermined period may be set as appropriate depending on the specifications of the display device 100, the configuration of a drive circuit that drives the pixel 101, and the like. In the present embodiment, for convenience of explanation, it is assumed that the light emitting unit emits light immediately after the above-described processes are completed, but it goes without saying that the present invention is not limited to such an example.

  Then, the light emission of the light emitting units constituting each light emitting element arranged in a certain row (for example, the xth row) is continued until immediately before the start of the horizontal scanning period of each light emitting device arranged in the (x + x ′) th row. The Here, x ′ is a parameter that can be determined according to the design specifications of the display device 100. That is, the light emission of the light emitting units constituting the light emitting elements arranged in the xth row of a certain display frame is continued until the (x + x′−1) th horizontal scanning period. On the other hand, the video signal writing process and the mobility correction process are completed within the x-th horizontal scanning period in the next display frame from the beginning of the horizontal scanning period of each light emitting element arranged in the (x + x ′)-th row. Until this is done, the light-emitting portions constituting the light-emitting elements arranged in the x-th row are basically kept in the non-light-emitting state. By providing the above-described non-light emitting period (also simply referred to as “non-light emitting period”), the afterimage blur caused by active matrix driving is reduced, and the moving image quality can be further improved. However, the light emission state / non-light emission state of each pixel is not limited to this example. The time length of the horizontal scanning period is a time length of less than (1 / FR) × (1 / m) seconds. If the value of (x + x ′) exceeds m, the excess horizontal scanning period is processed in the display frame next to the display frame.

  The configuration of the display device 100 according to the embodiment of the present invention has been described above with reference to FIG. Next, the configuration of the pixel 101 according to an embodiment of the present invention will be described.

  FIG. 2 is an explanatory diagram illustrating the configuration of the pixel 101 according to the embodiment of the present invention. Hereinafter, the configuration of the pixel 101 according to the embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 2, a pixel 101 according to an embodiment of the present invention includes transistors 1A and 1B, a capacitor 1C, and an organic EL element 1D. In the following description, the transistors 1A and 1B are described as enhancement type field effect transistors (FETs), but the present invention is not limited to this. A depletion type transistor may be used for the transistors 1A and 1B. The transistors 1A and 1B may be a single gate type or a dual gate type (double gate type). Furthermore, the source / drain regions of the transistors 1A and 1B can be made of a conductive material such as polysilicon or amorphous silicon containing impurities, as well as metals, alloys, conductive particles, and their laminated structures. Alternatively, a layer made of an organic material (conductive polymer) may be used.

  As shown in FIG. 2, the transistor 1A has a gate connected to the scanning line WSL1 extending from the write scanner 104, one of the source and the drain connected to the data line DTL1 extending from the horizontal selector 103, and the other connected to the transistor 1B. Connected to the gate. The transistor 1A is turned on in response to a signal supplied from the scanning line.

In the transistor 1B, either the source or the drain is connected to the organic EL element 1D, and the other is connected to the power supply line DSL1 extending from the power supply scanner 105. In the present embodiment, the source of the transistor 1B is connected to the anode of the organic EL element 1D, and the drain is connected to the power supply line DSL1 extending from the power supply scanner 105. Here, the transistor 1B is driven so that the light emission current _Ids flows according to the following Equation 1 in the light emitting state in which the organic EL element 1D emits light. In Equation 1, each term indicates the following.
μ: Effective mobility of transistor 1B _Vgs : _Potential difference between gate and source of transistor 1B _Vth : Threshold voltage of transistor 1B k: (1/2) · (W / L) · Cox
L: channel length W: channel width Cox: (relative permittivity of gate insulating layer) · (dielectric constant of vacuum) / (thickness of gate insulating layer)

I _ds = k · μ · (V _gs −V _th ) ²
... (Formula 1)

When the light emission current _Ids flows through the organic EL element 1D, the organic EL element 1D emits light by itself. Furthermore, the light emission luminance of the organic EL element 1D changes depending on the value of the light emission current _Ids .

  As shown in FIG. 2, the capacitor 1C is provided between one of the source and drain of the transistor 1B connected to the anode of the organic EL element 1D and the gate of the transistor 1B. In the present embodiment, since the source of the transistor 1B is connected to the anode of the organic EL element 1D, the capacitor 1C is provided between the source and gate of the transistor 1B.

  The organic EL element 1D is an example of a light emitting element that emits light according to the amount of current. The anode of the organic EL element 1D is connected to the source of the transistor 1B, and the cathode is connected to the ground wiring 1H. Although details of the operation will be described later, in the configuration of the pixel 101 illustrated in FIG. 2, the capacitor 1C holds the signal potential supplied from the data line DTL1 by the conduction of the transistor 1A. The transistor 1B receives the supply of current from the power supply line DSL1, thereby causing a driving current to flow through the organic EL element 1D in accordance with the potential held in the capacitor 1C. The organic EL element 1D emits light by passing a driving current through the organic EL element 1D. Needless to say, the present invention is not limited to such an example. For example, the cathode of the organic EL element 1D may be connected to the ground (GND).

In the configuration of the pixel 101 shown in FIG. 2, the power supply scanner 105 determines the potential of the power supply line DSL1 while the horizontal selector 103 supplies the reference potential to the data line DTL1 after the transistor 1A is turned on. By switching between the first potential and the second potential lower than the first potential, a voltage corresponding to the threshold voltage _Vth of the transistor 1B is held in the capacitor 1C. In this way, by holding the voltage corresponding to the threshold voltage _Vth of the transistor 1B in the capacitor 1C, the threshold voltage of the transistor 1B can be corrected, and the influence of the threshold voltage of the transistor 1B that causes variation among pixels is canceled. can do.

  In this embodiment, the horizontal selector 103 sets two types of reference potentials to be supplied to the data line DTL1, and corrects the threshold voltage of the transistor 1B by supplying two reference potentials to the data line DTL1. It is said.

  Although details of the operation will be described later, in the configuration of the pixel 101 shown in FIG. 2, the horizontal selector 103 switches the potential of the data line DTL1 to the signal potential at the timing when the transistor 1A is non-conductive, and then the write scanner. 104 applies a control signal to the scanning line WSL1 to turn on the transistor 1A, and then the write scanner 104 stops applying the control signal to the scanning line WSL1. By controlling the application of the control signal in this way, the source potential of the transistor 1B can be controlled, that is, the mobility of the transistor 1B can be corrected.

  As described above, the configuration of the pixel 101 according to the embodiment of the present invention has been described with reference to FIG. 2. In the present invention, the circuit configuring the pixel 101 is not limited to the example illustrated in FIG. 2. Next, the relationship between the signal input to the pixel 101 according to the embodiment of the present invention and the potential of the transistor 1B will be described.

  FIG. 3 is an explanatory diagram illustrating a relationship between a signal input to the pixel 101 according to an embodiment of the present invention and the potential of the transistor 1B. Hereinafter, the relationship between the signal input to the pixel 101 according to the embodiment of the present invention and the potential of the transistor 1B will be described with reference to FIG. In the subsequent timing charts, the length of the horizontal axis (time length) indicating each period is a schematic one and does not necessarily match the ratio of the time length of each period.

FIG. 3 shows changes in the scanning line potential supplied to the scanning line, the power supply line potential supplied to the power supply line, the data line potential supplied to the data line, and the gate of the transistor 1B. and also it shows the change in the potential V _g and the source potential V _s.

First, in the light emission period (A), the first potential is supplied from the power supply scanner 105 to the power supply line DSL1, and the current flows through the organic EL element 1D, so that the organic EL element 1D emits light. When the potential supplied from the power scanner 105 transitions to a second potential lower than the first potential, the light emission period is completed. Potential supplied from the power supply scanner 105 to the power supply line DSL1 is that the transition to the second potential, the gate potential V _g and the source potential V _s of the transistor 1B both reduced.

Thereafter, the scanning line potential supplied from the scanning line WSL1 transitions from LOW (low potential side) to HIGH (high potential side) at the boundary between the period (B) and the period (C). When the potential supplied to the scanning line WSL1 transitions to the high potential side, the transistor 1A becomes conductive. Accordingly, the gate potential V _g of the transistor 1B is slightly increased, the source potential V _s is further reduced. The source potential V _s at this time is set to V _{cc_L} . The period (B) and the period (C) are combined to form a threshold correction preparation period.

Complete the threshold value correction preparation period, the potential supplied from the power supply scanner 105 to the power supply line DSL1 is, when the transition from the second potential to the first potential, the the gate electric potential V _g of the transistor 1B remains constant, the source The potential V _s begins to rise slowly. This period is defined as a threshold correction period (D). This threshold correction period (D), between the gate potential V _g and the source potential V _s of the transistor 1B, so that the potential difference corresponding to the threshold voltage V _th of the transistor 1B is maintained. In the pixel 101 in this embodiment, the potential difference corresponding to the threshold voltage _Vth of the transistor 1B is held in the capacitor 1C.

Thereafter, the potential supplied to the scanning line WSL1 is that changes from LOW to HIGH, the gate potential _{V g} and the source potential _{V s} of the transistor 1B starts to rise together. This period is a sampling period and a mobility correction period (E). By sampling period and the mobility correction period (E) is started, the data line potential rises to V _in. Therefore, the gate electric potential V _g of the transistor 1B rises in the form of potential corresponding to the data line potential V _in is added up. Note in the pixel 101 in the present embodiment, together with the potential difference corresponding to a potential corresponding to the potential is added up to the data line potential V _in the threshold voltage V _th of the transistor 1B is held in the capacitor 1C, movement of the transistor 1B A voltage ΔV for correcting the degree is subtracted from the capacitor 1C. Note that the voltage ΔV is large when the mobility of the transistor 1B is large, and is small when the mobility is small.

Thereafter, the potential supplied to the scanning line WSL1 changes from HIGH to LOW, so that the sampling period and the mobility correction period (E) end. Furthermore, at a luminance corresponding to the video signal potential V _in by the data line potential transitions to a reference potential V _o organic EL element 1D starts emitting light. This period is defined as a light emission period (F). At this time, the video signal potential V _in the voltage corresponding to the threshold voltage V _th of the transistor 1B, is adjusted by a voltage ΔV for correcting the mobility, emission luminance of the organic EL element 1D is the threshold of transistor 1B It is not affected by variations in voltage _Vth and mobility μ. A so-called bootstrap operation is performed at the beginning of the light emission period (F). The gate potential V _g and the source potential V _{s of} the transistor 1B rise while the gate-source voltage V _gs of the transistor 1B is kept constant at V _gs = V _th + V _in −ΔV. Thereby, in the light emission period (F), the light emission luminance of the organic EL element 1D can be kept constant.

  The relationship between the signal input to the pixel 101 according to the embodiment of the present invention and the potential of the transistor 1B has been described above with reference to FIG. Next, the operation of the pixel 101 described above will be specifically described. The operation of the pixel 101 described above is described in, for example, Japanese Patent Application Laid-Open No. 2007-310311, and will be described in detail below with reference to the drawings.

  4A and 4B are explanatory diagrams for specifically explaining the operation of the pixel 101 according to the embodiment of the present invention. Hereinafter, the operation of the pixel 101 according to the embodiment of the present invention will be specifically described with reference to FIGS. 4A and 4B. 4A and 4B also show the parasitic capacitance 1I of the organic EL element 1D.

4A shows the operation of the pixel 101 in the light emission period (A) of FIG. In the emission period (A), to the power supply line DSL1 is supplied with a first potential _{V cc - H} from the power supply scanner 105 flows current _{I ds} to the transistor 1B. FIG. 4A shows an operation of the pixel 101 in the period (B). In the period (B), the second potential V _{cc_L} is supplied from the power scanner 105 to the power line _DSL1 .

FIG. 4C shows the operation of the pixel 101 in the period (C). In the period (C), the scanning line potential supplied from the scanning line WSL1 changes from LOW (low potential side) to HIGH (high potential side), and the transistor 1A is turned on. At this time, the reference potential _{V o} is applied to the data line DTL1. Therefore, the potential V _g of the gate g of the transistor 1B is V _o . The potential V _s of the source s of the transistor 1B is V _{cc_L} . Accordingly, the gate-source voltage V _gs of the transistor 1B at this time is V _o −V _{cc_L} . V _o and V _{cc_L} are set so that the gate-source voltage V _{gs at} this time becomes equal to or higher than the threshold voltage V _{th of the} transistor 1B. When the threshold voltage _Vth of the transistor 1B is exceeded, the transistor 1B becomes conductive.

FIG. 4A (d) shows the operation of the pixel 101 during the threshold correction period (D). In the threshold value correction period (D), to the power supply line DSL1 is supplied with a first potential _{V cc - H} from the power supply scanner 105, the potential _{V s} of the source s of the transistor 1B starts to gradually rise. When the gate-source voltage V _gs of the transistor 1B reaches the threshold voltage V _th , the transistor 1B is turned off.

FIG. 4B (e) shows the operation of the pixel 101 after the threshold correction period (D). When the scanning line potential supplied from the scanning line WSL1 transitions from HIGH (high potential side) to LOW (low potential side) after the threshold correction period (D), the transistor 1A is turned off. At this time, the gate-source voltage _Vgs of the transistor 1B maintains the threshold voltage _Vth . (F) in FIG. 4B, after the (e) in FIG. 4B, the data lines DTL1 is an explanatory view showing operation of the pixel 101 when the video signal potential _{V in} is applied.

FIG. 4B (g) shows the operation of the pixel 101 in the sampling period and the mobility correction period (E). In the sampling period and the mobility correction period (E), the scanning line potential supplied from the scanning line WSL1 changes from LOW (low potential side) to HIGH (high potential side), and the transistor 1A is turned on. Thus, the video signal potential V _in applied to the data line DTL1 is applied to the gate g of the transistor 1B, the potential of the potential V _in only the gate g increases. On the other hand, the coupling between the parasitic capacitance 1I of the capacitor 1C and the organic EL element 1D, also rises the source potential _{V s} of the source s of the transistor 1B. More specifically, since the organic EL element 1D is in a cut-off state (high impedance), the light emission current I _ds (drain-source current) flowing through the transistor 1B flows through the parasitic capacitance 1I. When the light emission current _Ids flows, the parasitic capacitance 1I is charged, and the source potential Vs of the transistor 1B rises. The gate-source voltage V _gs of the transistor 1B is “V _in + V _th −ΔV”. Here, ΔV is a mobility correction term for correcting the mobility of the transistor 1B in the pixel 101.

FIG. 4B (h) shows the operation of the pixel 101 in the light emission period (F). In the light emission period (F), the scanning line potential supplied from the scanning line WSL1 transits from HIGH (high potential side) to LOW (low potential side), and the transistor 1A is turned off. Since the transistor 1A is turned off, the gate g of the transistor 1B is disconnected from the data line DTL1. Then, the light emission current _Ids flowing through the transistor 1B starts to flow through the organic EL element 1D. Therefore, the anode potential of the organic EL element 1D, that is, the potential of the source s of the transistor 1B rises according to the light emission current _Ids . By the bootstrap operation of the capacitor 1C, the potential of the gate g of the transistor 1B starts to increase as the potential of the source s of the transistor 1B increases. Moreover, since the potential of the source s of the transistor 1B rises and exceeds the threshold voltage _Vel of the organic EL element 1D, the organic EL element 1D starts to emit light.

  FIG. 5 is an explanatory diagram for explaining a circuit configuration in the case where the capacitor 1J is arranged as an auxiliary capacitor in the display device 100 shown in FIG. 2, and FIG. 6 shows a layout that embodies the circuit configuration shown in FIG. It is explanatory drawing explaining an example.

  The cathode wiring 1H to which the organic EL element 1D and the capacitor 1J are connected is preferably a low resistance material. The second wiring is often used when a circuit is formed of low-temperature polysilicon. Further, an auxiliary electrode formed of an anode electrode may be used for the cathode wiring 1H. However, for pixels with high definition, it is difficult to use the second wiring and the auxiliary wiring as the cathode wiring 1H due to the layout area limitation.

  FIG. 7A is an explanatory diagram showing a general low-temperature polysilicon TFT structure. As shown in FIG. 7A, a general low-temperature polysilicon TFT 11 includes a first wiring 12, a gate oxide film 13 formed so as to cover the first wiring 12, and a part of the upper portion of the gate oxide film 13. Polysilicon 14 to be formed, oxide film 15 formed to cover gate oxide film 13 and polysilicon 14, and second film formed on top of oxide film 15 and connected to polysilicon 14 The wiring 16 includes a planarization film 17 formed so as to cover the oxide film 15 and the second wiring 16, and an organic EL anode electrode 18 formed on a part of the top of the planarization film 17. The

  The TFT 11 shown in FIG. 7A shows a structure when the second wiring 16 is used as the wiring of the organic EL anode electrode 18. In this case, although not shown in FIG. 7A, the first wiring 12 is used for the wiring of the organic EL cathode electrode.

  FIG. 7B is an explanatory diagram showing another example of a general low-temperature polysilicon TFT structure. As shown in FIG. 7B, a general low-temperature polysilicon TFT 21 includes a first wiring 22, a gate oxide film 23 formed so as to cover the first wiring 22, and a part of the upper portion of the gate oxide film 23. Polysilicon 24 to be formed, oxide film 25 formed so as to cover gate oxide film 23 and polysilicon 24, formed on top of oxide film 25, and connected to polysilicon 24 and first wiring 22 A second wiring 26 formed, a planarization film 27 formed so as to cover the oxide film 25 and the second wiring 26, an organic EL anode electrode 28 formed on a part of the upper part of the planarization film 27, An organic EL cathode electrode 29, an organic EL 30 formed on a part of the organic EL anode electrode 28, and a planarizing film 31 are configured.

  The TFT 21 shown in FIG. 7B uses the second wiring 26 for the wiring of the organic EL anode electrode 28. The first wiring 22 is used for the wiring of the organic EL cathode electrode 29. The organic EL 30 emits light by passing a current between the organic EL anode electrode 28 and the organic EL cathode electrode 29.

  FIG. 8 is an explanatory diagram for explaining an equivalent circuit of the pixel 101 when the first wiring is used as the cathode wiring in the display device 100 according to the embodiment of the present invention. When the first wiring is used as the cathode wiring, since the first wiring is generally made of a material having a higher resistance than the second wiring, the pixel 101 is equivalent to the cathode resistance 1K entering the cathode side of the organic EL element 1D. It becomes a circuit. FIG. 8 also shows the parasitic capacitance Cp between the power supply line DSL1 and the cathode wiring (first wiring).

  FIG. 9 shows the potential fluctuations (cathodes) of each potential and the node at point a in FIG. 8 when driving is performed at the timing shown in FIG. 3 in the case where the pixel 101 is configured as shown in FIG. It is explanatory drawing explaining the fluctuation | variation of an electric potential. The pixel 101 in FIG. 8 is in a state where an integration circuit is formed by the parasitic capacitance Cp and the cathode resistance 1K. Therefore, as shown in FIG. 9, at the point a in FIG. 8, the cathode potential rises as the threshold correction period (D) starts, and the cathode potential returns to the original potential with the time constant of the circuit of the pixel 101. .

  However, when the resistance value of the cathode resistance 1K increases, it takes time for the cathode potential to return to the original potential as shown by the broken line in FIG. If the cathode potential does not return to the original potential by the end of the threshold correction period (D), the threshold voltage of the transistor 1B cannot be corrected.

Therefore, in the present embodiment, when the first wiring is used as the cathode wiring, the time constant based on the parasitic capacitance Cp and the resistance value R _cath of the cathode resistance 1K is set so as to consider the threshold correction period _tvth. Thus, the correction of the threshold voltage of the transistor 1B is not affected.

Specifically, the time constant based on the parasitic capacitance Cp and the resistance value R _cath of the cathode resistance 1K is set to be less than the threshold correction period _tvth . That means
t _vth > Cp × R _cath
Set the time constant so that By setting in this way, it is possible not to affect the correction of the threshold voltage of the transistor 1B. Here, the time required for threshold correction is preferably about 5 microseconds. From this, it is desirable that the time constant of the parasitic capacitance Cp and the resistance value R _cath of the cathode resistance 1K is within 0.5 micron.

In consideration of the high frame rate, the time constant may be set so that Cp × R _path <0.1 microseconds. By setting the time constant based on the parasitic capacitance Cp and the resistance value R _cath of the cathode resistance 1K to be less than 0.1 microsecond, the correction of the threshold voltage of the transistor 1B is not affected. The threshold voltage can be corrected.

  As above, the setting in the case where the first wiring is used as the cathode wiring in the display device 100 according to the embodiment of the present invention has been described.

  As described above, according to one embodiment of the present invention, the time constant between the wiring resistance and the parasitic capacitance generated in the cathode wiring is appropriately set so as not to affect the correction of the threshold voltage of the TFT. Can be.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  The present invention can be applied to a display device, and in particular, can be applied to an active matrix display device using a light-emitting element that emits light according to a current amount as a pixel.

It is explanatory drawing explaining the structure of the display apparatus 100 concerning one Embodiment of this invention. It is explanatory drawing explaining the structure of the pixel 101 concerning one Embodiment of this invention. FIG. 10 is an explanatory diagram illustrating a relationship between a signal input to a pixel 101 and a potential of a transistor 1B. FIG. 6 is an explanatory diagram specifically explaining an operation of the pixel 101 according to the embodiment of the present invention. FIG. 6 is an explanatory diagram specifically explaining an operation of the pixel 101 according to the embodiment of the present invention. FIG. 3 is an explanatory diagram illustrating a circuit configuration when a capacitor 1J is disposed as an auxiliary capacitor in the display device 100 illustrated in FIG. FIG. 6 is an explanatory diagram illustrating an example of a layout that embodies the circuit configuration illustrated in FIG. 5. It is explanatory drawing shown about the TFT structure of a general low temperature polysilicon. It is explanatory drawing shown about the TFT structure of a general low temperature polysilicon. FIG. 7 is an explanatory diagram illustrating an equivalent circuit of the pixel 101 in the case where the first wiring is used as the cathode wiring in the display device 100 according to the embodiment of the present invention. FIG. 9 is an explanatory diagram for explaining each potential and potential fluctuation of a node at point a in FIG. 8 in the pixel 101 shown in FIG. 8.

Explanation of symbols

11, 21 TFT
12, 22 First wiring 13, 23 Gate oxide film 14, 24 Polysilicon 15, 25 Oxide film 16, 26 Second wiring 17, 27, 31 Planarization film 18, 28 Organic EL anode electrode 29 Organic EL cathode electrode 30 Organic EL
DESCRIPTION OF SYMBOLS 100 Display apparatus 101 Pixel 102 Pixel array part 103 Horizontal selector 104 Write scanner 105 Power supply scanner DTL1-DTLn Data line DSL1-DSLm Power supply line WSL1-WSLm Scanning line

Claims (2)

A pixel having a light emitting element which is arranged in a matrix at a portion where a scanning line in a row, a columnar data line, and the scanning line and the data line intersect, and which emits light according to a current amount; A power supply line arranged corresponding to each row of the display device including a pixel array unit,
The pixel array unit includes a first wiring and a second wiring that form the scanning line, the data line, and the power supply line,
When either the first wiring or the second wiring is used as the cathode wiring of the light emitting element, the time constant of the wiring resistance and the parasitic capacitance between the power supply line and the cathode wiring is set to the second wiring. A display device characterized in that the threshold voltage of a transistor is less than the time for correction. The display device according to claim 1, wherein the time constant is less than 0.1 microseconds.

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