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JP2009159811A - Battery condition monitoring circuit and battery device - Google Patents

Battery condition monitoring circuit and battery device Download PDF

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Publication number
JP2009159811A
JP2009159811A JP2008288088A JP2008288088A JP2009159811A JP 2009159811 A JP2009159811 A JP 2009159811A JP 2008288088 A JP2008288088 A JP 2008288088A JP 2008288088 A JP2008288088 A JP 2008288088A JP 2009159811 A JP2009159811 A JP 2009159811A
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battery
voltage
charge
circuit
nmos transistor
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Inventor
Tomoyuki Koike
智幸 小池
Atsushi Sakurai
敦司 桜井
Kazusuke Sano
和亮 佐野
Yoshihisa Taya
良久 田家
Muneharu Kawana
宗治 川名
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Seiko Instruments Inc
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Seiko Instruments Inc
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Priority to JP2008288088A priority Critical patent/JP2009159811A/en
Priority to TW097146384A priority patent/TW200941017A/en
Priority to US12/327,097 priority patent/US20090179617A1/en
Priority to KR1020080122443A priority patent/KR20090060170A/en
Publication of JP2009159811A publication Critical patent/JP2009159811A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/396—Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/382—Arrangements for monitoring battery or accumulator variables, e.g. SoC
    • G01R31/3835—Arrangements for monitoring battery or accumulator variables, e.g. SoC involving only voltage measurements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/392—Determining battery ageing or deterioration, e.g. state of health

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Secondary Cells (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a battery condition monitoring circuit which reduces the manufacturing cost of a battery device, and its battery device. <P>SOLUTION: A charge/discharge control transistor is structured to be operated by a low-level signal based on a high-level signal and a ground voltage VSS based on the voltage of a voltage regulator which is lower than a power supply voltage VDD based on a battery voltage. Accordingly, the charge/discharge control transistor can use an element with low resistance to pressure because the voltage applied to a gate becomes low. The cost of the charge/discharge transistor becomes low, and the manufacturing cost of the battery device also becomes low. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、複数個のバッテリの状態を監視するバッテリ状態監視回路、及び、バッテリ状態監視回路を備えたバッテリ装置に関する。   The present invention relates to a battery state monitoring circuit that monitors the states of a plurality of batteries, and a battery device including the battery state monitoring circuit.

従来のバッテリ装置について説明する。図２は、バッテリ装置を示すブロック図である。   A conventional battery device will be described. FIG. 2 is a block diagram illustrating the battery device.

バッテリ状態監視回路６０は、バッテリ７１の状態を監視する。検出回路６１は、バッテリ７１の過充電状態及び過放電状態を検出する。遅延回路６２は、検出回路６１から信号が入力すると、所定の遅延時間経過後に、その信号を出力する。制御回路６４は、所定の時、充電経路が遮断されるよう動作する。充電制御トランジスタ８１は、オフすることにより、充電器（図示せず）からバッテリ７１への充電経路を遮断する。また、制御回路６４は、所定の時、放電経路が遮断されるよう動作する。放電制御トランジスタ８２は、オフすることにより、バッテリ７１から負荷（図示せず）への放電経路を遮断する（例えば、特許文献１参照）。
特開２００７−１９５３０３号公報 The battery state monitoring circuit 60 monitors the state of the battery 71. The detection circuit 61 detects an overcharge state and an overdischarge state of the battery 71. When a signal is input from the detection circuit 61, the delay circuit 62 outputs the signal after a predetermined delay time has elapsed. The control circuit 64 operates so that the charging path is interrupted at a predetermined time. The charge control transistor 81 shuts off the charging path from the charger (not shown) to the battery 71 by turning off. The control circuit 64 operates so that the discharge path is interrupted at a predetermined time. The discharge control transistor 82 shuts off a discharge path from the battery 71 to a load (not shown) by turning off (see, for example, Patent Document 1).
JP 2007-195303 A

ここで、バッテリ装置は、図２ではバッテリを１個有しているが、バッテリを複数個有することがある。この時、制御回路６４に電源として供給される電圧は、複数個のバッテリの電圧に基づいた電源電圧ＶＤＤになり、制御回路６４は、その電源電圧ＶＤＤに基づいたハイレベル信号及び接地電圧ＶＳＳに基づいたローレベル信号を充電制御トランジスタ８１及び放電制御トランジスタ８２のゲートに出力することになる。   Here, the battery device has one battery in FIG. 2, but may have a plurality of batteries. At this time, the voltage supplied to the control circuit 64 as the power supply becomes the power supply voltage VDD based on the voltages of the plurality of batteries, and the control circuit 64 generates the high level signal and the ground voltage VSS based on the power supply voltage VDD. The low level signal is output to the gates of the charge control transistor 81 and the discharge control transistor 82.

また、充電制御トランジスタ８１及び放電制御トランジスタ８２の耐圧は、ゲートに印加される電圧に基づいて回路設計されている。   The breakdown voltage of the charge control transistor 81 and the discharge control transistor 82 is designed based on the voltage applied to the gate.

よって、充電制御トランジスタ８１及び放電制御トランジスタ８２は、ゲートに印加される電圧が高くなるので、高耐圧用の素子が使用されることになる。よって、充電制御トランジスタ８１及び放電制御トランジスタ８２の製造コストが高くなり、バッテリ装置の製造コストも高くなってしまう。   Therefore, since the voltage applied to the gates of the charge control transistor 81 and the discharge control transistor 82 is high, a high withstand voltage element is used. Therefore, the manufacturing cost of the charge control transistor 81 and the discharge control transistor 82 increases, and the manufacturing cost of the battery device also increases.

本発明は、このような点に鑑みてなされ、バッテリ装置の製造コストが低くなるバッテリ状態監視回路及びそのバッテリ装置を提供する。   This invention is made in view of such a point, and provides the battery state monitoring circuit which the manufacturing cost of a battery apparatus becomes low, and its battery apparatus.

本発明は、上記課題を解決するため、バッテリの充放電状態を検出し、その状態を示す検出信号を出力する検出回路と、検出信号を入力し、所定の遅延時間経過後に、検出信号を出力する遅延回路と、複数個のバッテリの電圧に基づいた電源電圧を入力し、電源電圧よりも低い定電圧を出力するボルテージレギュレータと、検出信号が入力すると、接地電圧に基づいたローレベル信号と、前記ボルテージレギュレータが出力する定電圧に基づいたハイレベル信号とを、充放電制御用トランジスタのゲートに出力する制御回路と、を備えることを特徴とするバッテリ状態監視回路を提供する。   In order to solve the above-mentioned problems, the present invention detects a charge / discharge state of a battery, outputs a detection signal indicating the state, inputs a detection signal, and outputs a detection signal after a predetermined delay time has elapsed. A delay circuit, a voltage regulator that inputs a power supply voltage based on the voltages of a plurality of batteries, outputs a constant voltage lower than the power supply voltage, and a detection signal is input, a low level signal based on the ground voltage, A battery state monitoring circuit comprising: a control circuit that outputs a high level signal based on a constant voltage output from the voltage regulator to a gate of a charge / discharge control transistor.

また、本発明は、上記バッテリ状態監視回路を備えたバッテリ装置を提供する。   Moreover, this invention provides the battery apparatus provided with the said battery state monitoring circuit.

本発明では、充電制御トランジスタ及び放電制御トランジスタは、複数個のバッテリの電圧に基づいた電源電圧よりも低いボルテージレギュレータの出力電圧に基づいたハイレベル信号に基づいて動作する。従って、充電制御トランジスタ及び放電制御トランジスタは、ゲートに印加される電圧が低くなるので、低耐圧用の素子を使用することが出来る。よって、充電制御トランジスタ及び放電制御トランジスタの製造コストが低くなり、バッテリ装置の製造コストも低くなる。   In the present invention, the charge control transistor and the discharge control transistor operate based on a high level signal based on the output voltage of the voltage regulator that is lower than the power supply voltage based on the voltages of the plurality of batteries. Therefore, since the voltage applied to the gate of the charge control transistor and the discharge control transistor is low, an element for low withstand voltage can be used. Therefore, the manufacturing cost of the charge control transistor and the discharge control transistor is reduced, and the manufacturing cost of the battery device is also reduced.

以下、本発明の実施形態を、図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

まず、バッテリ装置の構成について説明する。図１は、バッテリ装置を示すブロック図である。   First, the configuration of the battery device will be described. FIG. 1 is a block diagram illustrating a battery device.

バッテリ装置は、バッテリ２１〜２４、バッテリ状態監視回路１０、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２を備えている。また、バッテリ装置は、外部端子ＥＢ＋及び外部端子ＥＢ−を備えている。   The battery device includes batteries 21 to 24, a battery state monitoring circuit 10, a charge control NMOS transistor 31, and a discharge control NMOS transistor 32. Further, the battery device includes an external terminal EB + and an external terminal EB−.

バッテリ状態監視回路１０は、検出回路１１、遅延回路１２、ボルテージレギュレータ１３及び制御回路１４を有している。また、バッテリ状態監視回路１０は、モニタ端子Ｖ１〜Ｖ５、制御端子ＣＯ及び制御端子ＤＯを有している。   The battery state monitoring circuit 10 includes a detection circuit 11, a delay circuit 12, a voltage regulator 13, and a control circuit 14. The battery state monitoring circuit 10 has monitor terminals V1 to V5, a control terminal CO, and a control terminal DO.

バッテリ２１〜２４は直列接続され、バッテリ２１は外部端子ＥＢ＋に接続され、バッテリ２４は放電制御ＮＭＯＳトランジスタ３２に接続されている。バッテリ２１の＋端子はモニタ端子Ｖ１に接続され、バッテリ２２の＋端子はモニタ端子Ｖ２に接続され、バッテリ２３の＋端子はモニタ端子Ｖ３に接続され、バッテリ２４の＋端子はモニタ端子Ｖ４に接続され、バッテリ２４の−端子はモニタ端子Ｖ５に接続されている。充電制御ＮＭＯＳトランジスタ３１は、放電制御ＮＭＯＳトランジスタ３２と外部端子ＥＢ−との間に設けられている。充電制御ＮＭＯＳトランジスタ３１のゲートは制御端子ＣＯに接続され、放電制御ＮＭＯＳトランジスタ３２のゲートは制御端子ＤＯに接続されている。   The batteries 21 to 24 are connected in series, the battery 21 is connected to the external terminal EB +, and the battery 24 is connected to the discharge control NMOS transistor 32. The positive terminal of the battery 21 is connected to the monitor terminal V1, the positive terminal of the battery 22 is connected to the monitor terminal V2, the positive terminal of the battery 23 is connected to the monitor terminal V3, and the positive terminal of the battery 24 is connected to the monitor terminal V4. The negative terminal of the battery 24 is connected to the monitor terminal V5. The charge control NMOS transistor 31 is provided between the discharge control NMOS transistor 32 and the external terminal EB−. The gate of the charge control NMOS transistor 31 is connected to the control terminal CO, and the gate of the discharge control NMOS transistor 32 is connected to the control terminal DO.

検出回路１１は、モニタ端子Ｖ１〜Ｖ５及び遅延回路１２に接続されている。遅延回路１２は、モニタ端子Ｖ１、モニタ端子Ｖ５及び制御回路１４に接続されている。ボルテージレギュレータ１３は、モニタ端子Ｖ１、モニタ端子Ｖ５及び制御回路１４に接続されている。制御回路１４は、モニタ端子Ｖ５、制御端子ＣＯ及び制御端子ＤＯに接続されている。   The detection circuit 11 is connected to the monitor terminals V1 to V5 and the delay circuit 12. The delay circuit 12 is connected to the monitor terminal V1, the monitor terminal V5, and the control circuit 14. The voltage regulator 13 is connected to the monitor terminal V1, the monitor terminal V5, and the control circuit. The control circuit 14 is connected to the monitor terminal V5, the control terminal CO, and the control terminal DO.

ここで、バッテリ状態監視回路１０は、バッテリ２１〜２４の状態を監視する。検出回路１１は、バッテリ２１〜２４の過充電状態及び過放電状態を検出する。遅延回路１２は、検出回路１１から信号が入力すると、所定の遅延時間経過後に、その信号を出力する。ボルテージレギュレータ１３は、一定の出力電圧を出力する。制御回路１４は、所定の時、充電経路が遮断されるよう動作する。充電制御ＮＭＯＳトランジスタ３１は、オフすることにより、充電器（図示せず）からバッテリ２１〜２４への充電経路を遮断する。また、制御回路１４は、所定の時、放電経路が遮断されるよう動作する。放電制御ＮＭＯＳトランジスタ３２は、オフすることにより、バッテリ２１〜２４から負荷（図示せず）への放電経路を遮断する。   Here, the battery state monitoring circuit 10 monitors the states of the batteries 21 to 24. The detection circuit 11 detects the overcharge state and the overdischarge state of the batteries 21 to 24. When a signal is input from the detection circuit 11, the delay circuit 12 outputs the signal after a predetermined delay time has elapsed. The voltage regulator 13 outputs a constant output voltage. The control circuit 14 operates so that the charging path is interrupted at a predetermined time. When the charge control NMOS transistor 31 is turned off, the charge path from the charger (not shown) to the batteries 21 to 24 is interrupted. The control circuit 14 operates so that the discharge path is interrupted at a predetermined time. The discharge control NMOS transistor 32 shuts off a discharge path from the batteries 21 to 24 to a load (not shown) by turning off.

また、ボルテージレギュレータ１３の出力電圧は、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２の耐圧電圧未満に回路設計されている。   The output voltage of the voltage regulator 13 is designed to be less than the withstand voltage of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32.

次に、バッテリ装置の動作について説明する。   Next, the operation of the battery device will be described.

［充電器がバッテリを充電し、バッテリが過充電状態になる場合］充電器がバッテリ装置に接続され、充電が開始される。ボルテージレギュレータ１３は、バッテリ２１〜２４の電圧に基づいた電源電圧ＶＤＤに基づき、電源電圧ＶＤＤよりも低い一定の出力電圧を出力する。   [When the charger charges the battery and the battery is overcharged] The charger is connected to the battery device, and charging is started. The voltage regulator 13 outputs a constant output voltage lower than the power supply voltage VDD based on the power supply voltage VDD based on the voltages of the batteries 21 to 24.

バッテリ２１〜２４の中のいずれか１個のバッテリが過充電状態になると、検出回路１１は、そのバッテリの過充電状態を検出してその旨を示す過充電検出信号を遅延回路１２に出力する。遅延回路１２は、所定の遅延時間経過後に、過充電検出信号を制御回路１４に出力する。すると、制御回路１４はボルテージレギュレータ１３の出力電圧に基づいたハイレベル信号を放電制御ＮＭＯＳトランジスタ３２のゲートに出力し、放電制御ＮＭＯＳトランジスタ３２はオンする。また、制御回路１４は接地電圧ＶＳＳに基づいたローレベル信号を充電制御ＮＭＯＳトランジスタ３１のゲートに出力し、充電制御ＮＭＯＳトランジスタ３１はオフする。充電制御ＮＭＯＳトランジスタ３１がオフすると、寄生ダイオードによって放電電流は流れるが、充電電流は流れなくなる。よって、充電器からバッテリ２１〜２４への充電経路が遮断され、充電が禁止される。   When any one of the batteries 21 to 24 is overcharged, the detection circuit 11 detects the overcharge state of the battery and outputs an overcharge detection signal indicating that to the delay circuit 12. . The delay circuit 12 outputs an overcharge detection signal to the control circuit 14 after a predetermined delay time has elapsed. Then, the control circuit 14 outputs a high level signal based on the output voltage of the voltage regulator 13 to the gate of the discharge control NMOS transistor 32, and the discharge control NMOS transistor 32 is turned on. Further, the control circuit 14 outputs a low level signal based on the ground voltage VSS to the gate of the charge control NMOS transistor 31, and the charge control NMOS transistor 31 is turned off. When the charge control NMOS transistor 31 is turned off, the discharge current flows through the parasitic diode, but the charge current does not flow. Therefore, the charging path from the charger to the batteries 21 to 24 is blocked, and charging is prohibited.

［バッテリが負荷に放電し、バッテリが過放電状態になる場合］負荷がバッテリ装置に接続され、放電が開始される。ボルテージレギュレータ１３は、バッテリ２１〜２４の電圧に基づいた電源電圧ＶＤＤに基づき、電源電圧ＶＤＤよりも低い一定の出力電圧を出力している。   [When the battery is discharged to the load and the battery is in an overdischarged state] The load is connected to the battery device, and discharge is started. The voltage regulator 13 outputs a constant output voltage lower than the power supply voltage VDD based on the power supply voltage VDD based on the voltages of the batteries 21 to 24.

バッテリ２１〜２４の中のいずれか１個のバッテリが過放電状態になると、検出回路１１は、そのバッテリの過放電状態を検出してその旨を示す過放電検出信号を遅延回路１２に出力する。遅延回路１２は、所定の遅延時間経過後に、過放電検出信号を制御回路１４に出力する。すると、制御回路１４はハイレベル信号を充電制御ＮＭＯＳトランジスタ３１のゲートに出力し、充電制御ＮＭＯＳトランジスタ３１はオンする。また、制御回路１４はローレベル信号を放電制御ＮＭＯＳトランジスタ３２のゲートに出力し、放電制御ＮＭＯＳトランジスタ３２はオフする。放電制御ＮＭＯＳトランジスタ３２がオフすると、寄生ダイオードによって充電電流は流れるが、放電電流は流れなくなる。よって、バッテリ２１〜２４から負荷への放電経路が遮断され、放電が禁止される。   When any one of the batteries 21 to 24 is in an overdischarged state, the detection circuit 11 detects the overdischarged state of the battery and outputs an overdischarge detection signal indicating that to the delay circuit 12. . The delay circuit 12 outputs an overdischarge detection signal to the control circuit 14 after a predetermined delay time has elapsed. Then, the control circuit 14 outputs a high level signal to the gate of the charge control NMOS transistor 31, and the charge control NMOS transistor 31 is turned on. The control circuit 14 outputs a low level signal to the gate of the discharge control NMOS transistor 32, and the discharge control NMOS transistor 32 is turned off. When the discharge control NMOS transistor 32 is turned off, the charging current flows through the parasitic diode, but the discharging current does not flow. Therefore, the discharge path from the batteries 21 to 24 to the load is blocked, and discharge is prohibited.

このようにすると、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２は、バッテリ２１〜２４の電圧に基づいた電源電圧ＶＤＤでなくてボルテージレギュレータ１３の出力電圧に基づいたハイレベル信号及び接地電圧ＶＳＳに基づいたローレベル信号に基づいて動作する。よって、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２は、ゲートに印加される電圧が低くなるので、耐圧が低くても良くなり、高耐圧用の素子が使用されなくても良くなる。よって、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２の製造コストが低くなり、バッテリ装置の製造コストも低くなる。   In this way, the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 are not set to the power supply voltage VDD based on the voltages of the batteries 21 to 24 but to the high level signal and the ground voltage VSS based on the output voltage of the voltage regulator 13. It operates based on the low level signal based on it. Therefore, since the voltage applied to the gates of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 is low, the breakdown voltage may be low, and an element for high breakdown voltage may not be used. Therefore, the manufacturing cost of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 is reduced, and the manufacturing cost of the battery device is also reduced.

また、制御回路１４は、電源電圧ＶＤＤでなくてボルテージレギュレータ１３の出力電圧が供給され、電源として供給される電圧が低くなるので、耐圧が低くても良くなり、高耐圧用の素子が使用されなくても良くなり、面積が小さくなる。また、制御回路１４は、電源として供給される電圧が低くなるので、消費電力が少なくなる。   Further, the control circuit 14 is supplied with the output voltage of the voltage regulator 13 instead of the power supply voltage VDD, and the voltage supplied as the power supply becomes low, so that the withstand voltage may be low, and an element for high withstand voltage is used. It is not necessary and the area is reduced. Further, the control circuit 14 consumes less power because the voltage supplied as a power source is low.

また、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２のゲートに印加される電圧は、ボルテージレギュレータ１３の出力電圧であるので、一定である。よって、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２のオン抵抗が一定になる。   The voltage applied to the gates of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 is constant because it is the output voltage of the voltage regulator 13. Therefore, the on-resistances of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 are constant.

また、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２のゲートに印加される電圧は、ボルテージレギュレータ１３の出力電圧であるので、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２の耐圧電圧未満である。よって、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２の耐圧を保護するための部品がバッテリ装置に不要になるので、バッテリ装置の製造コストが低くなる。   Further, the voltage applied to the gates of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 is the output voltage of the voltage regulator 13, and therefore is less than the withstand voltage of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32. This eliminates the need for the battery device to protect the breakdown voltage of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32, thereby reducing the manufacturing cost of the battery device.

なお、充電経路を遮断する素子及び放電経路を遮断する素子は、バッテリ２４と外部端子ＥＢ−との間に設けられる充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２であるが、バッテリ２１と外部端子ＥＢ＋との間に設けられる充電制御ＰＭＯＳトランジスタ（図示せず）及び放電制御ＰＭＯＳトランジスタ（図示せず）でもよい。ここで、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２のゲートにボルテージレギュレータ１３の出力電圧と接地電圧ＶＳＳとの間の電圧が印加され、充電制御ＰＭＯＳトランジスタ（図示せず）及び放電制御ＰＭＯＳトランジスタ（図示せず）のゲートに電源電圧ＶＤＤとボルテージレギュレータ１３の出力電圧との間の電圧が印加されるように、制御回路１４は適宜回路設計される。   The elements that cut off the charge path and the elements that cut off the discharge path are the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 provided between the battery 24 and the external terminal EB−. It may be a charge control PMOS transistor (not shown) and a discharge control PMOS transistor (not shown) provided between EB +. Here, a voltage between the output voltage of the voltage regulator 13 and the ground voltage VSS is applied to the gates of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32, and a charge control PMOS transistor (not shown) and a discharge control PMOS transistor are applied. The control circuit 14 is appropriately designed so that a voltage between the power supply voltage VDD and the output voltage of the voltage regulator 13 is applied to the gate (not shown).

また、遅延回路１２に電源として供給される電圧は、電源電圧ＶＤＤと接地電圧ＶＳＳとの間の電圧であるが、ボルテージレギュレータ１３の出力電圧と接地電圧ＶＳＳとの間の電圧でもよいし、電源電圧ＶＤＤとボルテージレギュレータ１３の出力電圧との間の電圧でもよい。   The voltage supplied to the delay circuit 12 as a power supply is a voltage between the power supply voltage VDD and the ground voltage VSS, but may be a voltage between the output voltage of the voltage regulator 13 and the ground voltage VSS. It may be a voltage between the voltage VDD and the output voltage of the voltage regulator 13.

すると、遅延回路１２は、電源として供給される電圧が低くなるので、耐圧が低くても良くなり、高耐圧用の素子が使用されなくても良くなり、面積が小さくなる。また、遅延回路１２は、電源として供給される電圧が低くなるので、消費電力が少なくなる。   As a result, the voltage supplied as the power source of the delay circuit 12 is low, so that the withstand voltage may be low and an element for high withstand voltage may not be used, and the area is reduced. In addition, the delay circuit 12 consumes less power because the voltage supplied as a power source is lower.

また、バッテリ装置のバッテリ数は、４個になっているが、４個未満でも５個以上でも良い。   The number of batteries in the battery device is four, but it may be less than four or five or more.

また、バッテリ状態監視回路１０は１個の半導体装置であって充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２はＦＥＴであるが、バッテリ状態監視回路１０、充電制御ＮＭＯＳトランジスタ３１及び放電制御ＮＭＯＳトランジスタ３２が１個の半導体装置であってもよい。   The battery state monitoring circuit 10 is a single semiconductor device, and the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 are FETs, but the battery state monitoring circuit 10, the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 May be one semiconductor device.

バッテリ装置を示すブロック図である。It is a block diagram which shows a battery apparatus. 従来のバッテリ装置を示すブロック図である。It is a block diagram which shows the conventional battery apparatus.

符号の説明Explanation of symbols

１０ バッテリ状態監視回路
１１ 検出回路
１２ 遅延回路
１３ ボルテージレギュレータ
１４ 制御回路
２１〜２４ バッテリ
３１ 充電制御ＮＭＯＳトランジスタ
３２ 放電制御ＮＭＯＳトランジスタ
ＥＢ＋ 外部端子
ＥＢ− 外部端子
Ｖ１〜Ｖ５ モニタ端子
ＣＯ 制御端子
ＤＯ 制御端子
ＶＤＤ 電源電圧
ＶＳＳ 接地電圧 DESCRIPTION OF SYMBOLS 10 Battery state monitoring circuit 11 Detection circuit 12 Delay circuit 13 Voltage regulator 14 Control circuit 21-24 Battery 31 Charge control NMOS transistor 32 Discharge control NMOS transistor EB + External terminal EB- External terminal V1-V5 Monitor terminal CO Control terminal DO Control terminal VDD Power supply voltage VSS Ground voltage

Claims (2)

直列に接続された複数個のバッテリの状態を監視するバッテリ状態監視回路において、
前記バッテリの充放電状態を検出し、その状態を示す検出信号を出力する検出回路と、
前記検出信号を入力し、所定の遅延時間経過後に、前記検出信号を出力する遅延回路と、
前記複数個のバッテリの電圧に基づいた電源電圧を入力し、前記電源電圧よりも低い定電圧を出力するボルテージレギュレータと、
前記検出信号が入力すると、接地電圧に基づいたローレベル信号と、前記ボルテージレギュレータが出力する定電圧に基づいたハイレベル信号とを、充放電制御用トランジスタのゲートに出力する制御回路と、
を備えることを特徴とするバッテリ状態監視回路。 In a battery status monitoring circuit that monitors the status of a plurality of batteries connected in series,
A detection circuit that detects a charge / discharge state of the battery and outputs a detection signal indicating the state;
A delay circuit that inputs the detection signal and outputs the detection signal after a predetermined delay time;
A voltage regulator that inputs a power supply voltage based on the voltages of the plurality of batteries and outputs a constant voltage lower than the power supply voltage;
A control circuit that outputs a low level signal based on a ground voltage and a high level signal based on a constant voltage output from the voltage regulator to a gate of a charge / discharge control transistor when the detection signal is input;
A battery state monitoring circuit comprising: 複数個のバッテリと、
充放電制御用トランジスタと、
前記複数個のバッテリの充放電状態を監視し、前記充放電制御用トランジスタを制御する請求項１に記載のバッテリ状態監視回路と、
を備えることを特徴とするバッテリ装置。 A plurality of batteries;
A charge / discharge control transistor;
The battery state monitoring circuit according to claim 1, wherein charge / discharge states of the plurality of batteries are monitored, and the charge / discharge control transistor is controlled.
A battery device comprising:
JP2008288088A 2007-12-06 2008-11-10 Battery condition monitoring circuit and battery device Pending JP2009159811A (en)

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JP2008288088A JP2009159811A (en) 2007-12-06 2008-11-10 Battery condition monitoring circuit and battery device
TW097146384A TW200941017A (en) 2007-12-06 2008-11-28 Battery state monitoring circuit and battery device
US12/327,097 US20090179617A1 (en) 2007-12-06 2008-12-03 Battery state monitoring circuit and battery device
KR1020080122443A KR20090060170A (en) 2007-12-06 2008-12-04 Battery state monitoring circuit and battery apparatus

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US10333317B2 (en) 2016-12-28 2019-06-25 Ablic Inc. Charge/discharge control circuit and battery device
CN116853057A (en) * 2023-08-04 2023-10-10 小米汽车科技有限公司 Charging method, device, storage medium and vehicle

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JP5462046B2 (en) * 2010-03-26 2014-04-02 セイコーインスツル株式会社 Battery state monitoring circuit and battery device
JP6030817B2 (en) * 2010-06-04 2016-11-24 エスアイアイ・セミコンダクタ株式会社 Battery state monitoring circuit and battery device
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JP4101816B2 (en) * 2005-05-16 2008-06-18 日本テキサス・インスツルメンツ株式会社 Battery protection circuit
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KR20180077009A (en) 2016-12-28 2018-07-06 에이블릭 가부시키가이샤 Charging/discharging control circuit and battery device
US10333317B2 (en) 2016-12-28 2019-06-25 Ablic Inc. Charge/discharge control circuit and battery device
CN116853057A (en) * 2023-08-04 2023-10-10 小米汽车科技有限公司 Charging method, device, storage medium and vehicle
CN116853057B (en) * 2023-08-04 2024-04-02 小米汽车科技有限公司 Charging method, device, storage medium and vehicle

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