JP2009147297A - Semiconductor device having soi substrate and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can cope with the case when various circuits such as a signal processing circuit and a high power circuit are mixed and mounted in one chip, and can suppress thickening of a SOI (Silicon On Insulator) layer. <P>SOLUTION: A SOI substrate 4 is used, and a SOI layer 1 is formed as a low power circuit portion R1 and a support layer 2 is formed as a high power circuit portion R2. Accordingly, the thickness of the SOI layer 1 is determined in consideration of formation of the low power circuit portion R1 without considering the withstand voltage and the like of the high power circuit portion R2. Consequently, well layers have no boundary, compared with a case where a well layer is formed in a thick SOI layer, so that a parasitic capacitor can be eliminated and the increase in energy consumption and the reduction in calculation speed caused by the parasitic capacitor can be prevented. On the other hand, since the high power circuit portion R2 is formed in the support layer 2 having sufficient thickness, the withstand voltage and the like can be secured. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which an SOI (Silicon on insulator) layer and a support substrate are bonded to each other through a buried insulating film, and semiconductor devices are formed on the SOI layer and the support substrate, respectively. It relates to the manufacturing method.

  In recent years, as advanced functions of in-vehicle equipment and industrial robots have advanced, images, sound, acceleration, etc. are calculated from signals obtained from various sensors, etc., and actuators are driven and airbag operations are performed by generating outputs accordingly. The use of the system to do etc. is increasing. In order to realize a semiconductor device used in such a system on a single chip, there are devices in which various types of devices are mixed by junction isolation or oxide film isolation, and are generally called composite elements (for example, , See Patent Document 1).

As an element isolation structure for realizing such a composite element, a junction isolation for forming a PN junction around the element portion and an oxide film in a trench reaching the buried oxide film formed in the SOI layer of the SOI substrate are arranged. Oxide film isolation is effective in that the oxide film isolation is superior to surge isolation because it does not have a parasitic element and can be downsized as compared with the case of junction isolation.
JP-A-8-182111

  However, in order to incorporate various types of circuits, it is necessary to increase the thickness of the SOI layer. For example, if a high-power circuit including a logic circuit equipped with a CMOS or the like in charge of computation and a diode for LDMOS or ESD (Electro static discharge) that handles high power is mounted on the same substrate, ensuring the breakdown voltage in the high-power circuit For example, the SOI layer must be thickened. Therefore, for example, in a logic circuit, a well layer is formed in a thick SOI layer, and a device is formed in the well layer. Therefore, a parasitic capacitance is formed at the boundary of the well layer, and the parasitic capacitance is not sufficiently reduced. In addition, the power consumption is increased and the calculation speed is reduced.

  In view of the above points, the present invention provides a semiconductor device having a structure that can cope with a single chip even when various circuits such as a signal processing circuit and a high-power circuit are mixedly mounted and can suppress the increase in the thickness of the SOI layer. The purpose is to provide.

  In order to achieve the above object, according to the first aspect of the present invention, a plurality of SOI substrates (4) having a SOI layer (1) formed on a support layer (2) via a buried insulating film (3) are provided. A semiconductor device in which circuit portions (R1, R2) are mixedly mounted. In the SOI substrate (4), an SOI layer (4) is left on a support layer (2) through a buried insulating film (3). A first region (R1) and a second region (R2) in which the buried insulating film (3) and the SOI layer (4) are not formed on the support layer (2), and the SOI layer (1) The first region (1) and the second region (R2) are insulated and separated by the trench isolation portion (7) formed so as to penetrate the buried insulating film (3) and the support layer (2). In the first region (1), an element is formed in the SOI layer (1), and in the second region (R2), an element is formed in the support layer (2). To have.

  In the semiconductor device having such a structure, the SOI layer (1) is the first region (R1) and the support layer (2) is the second region (R2) while using the SOI substrate (4). Therefore, a semiconductor device having a structure that can cope with a single chip even when various circuits are mixedly mounted in the first region (R1) and the second region (R2) and can suppress the increase in the thickness of the SOI layer (1). It becomes possible to do. The semiconductor device having such a structure includes, for example, an SOI layer (1) and a buried oxide between the first region (R1) and the second region (R2). A step corresponding to the thickness of the film (3) is formed.

  Further, as in the invention described in claim 3, as the SOI substrate (4), the buried insulating film (3) is formed only in the first region (R1), and the buried insulating film is formed in the second region (R2). A partial SOI substrate on which the film (3) is not formed can also be used. In this case, a step is not formed between the first region (R1) and the second region (R2). Further, if the SOI substrate (4) is constituted by a partial SOI substrate in this way, a plurality of buried insulating films (3) are provided in the first region (R1) as described in claim 4. It can also be a structure.

  For example, as described in claim 5, a signal processing circuit is formed in the first region (R1), and a high power circuit having a higher power than the signal processing circuit is formed in the second region (R2). It is preferable to apply to such a semiconductor device.

  As a high power circuit, for example, a power element (20) can be formed as described in claim 6. In this case, as described in claim 7, the second region (R2) is divided into a plurality of regions by the trench isolation part (7), and the power element (20) is formed in each of the divided regions. Thus, it is possible to make a multi-channel.

  Further, as described in claim 8, when the trench isolation portion (7) for insulating and isolating the power element (20) is a multiple trench, it becomes possible to perform insulation isolation from other elements, and the power element ( It is possible to suppress potential interference that causes the high voltage used in 20) to interfere with other elements.

  According to a ninth aspect of the present invention, the power element (20) is a vertical element through which current flows so as to penetrate the front and back of the support layer (2). A structure can be adopted in which the sense cell is divided into currents proportional to the current flowing through the cells.

  In this case, as described in claim 10, the support layer (2) in the second region (R2) includes a temperature sensor (60) for detecting the temperature of the power element (20), and the power element (20) It is preferable that the trench isolation part (7) is also arranged between the temperature sensor (60). In this way, since the temperature of the power element (20) can be detected at a closer location, the temperature of the power element (20) can be detected more correctly.

  In addition, as described in claim 11, in the support layer (2) in the second region (R 2), an insulating film (2) is formed on the surface of the support layer (2) at the place where the power element (20) is disposed. 63), a temperature sensor (60) for detecting the temperature of the power element (20) may be provided. In this way, not only the same effect as in claim 10 can be obtained, but also the temperature sensor (60) can be brought closer to the power element (20), and the temperature of the power element (20) can be detected more correctly. It becomes possible to do.

  In the invention described in claim 12, in the first region (R1), the CMOS (10) is formed in the SOI layer (1), and the support layer (2) at a position corresponding to the first region (R1) The threshold adjustment electrode (40) of the CMOS (10) is electrically connected.

  By providing such a threshold adjustment electrode (40), the potential applied to the support layer (2) corresponding to the back surface of the CMOS (10) can be changed, and the operation threshold of the CMOS (10) can be changed. It becomes possible to adjust. For this reason, the characteristics of the CMOS (10) can be set to a desired value, such as speeding up by setting the operation threshold of the CMOS (10) low.

  In the invention described in claim 13, in the first region (R1), the CMOS (10) is formed in the SOI layer (1) and penetrates the SOI layer (1) and the buried insulating film (3). Then, the threshold adjustment electrode (40) of the CMOS (10) electrically connected to the support layer (2) is formed, and the CMOS (10) and the threshold adjustment electrode (40) are formed on the SOI layer (1). Insulating separation is performed by the insulating film (41).

  With such a structure, since it can be electrically connected to the support layer (2) through the threshold adjustment electrode (40) provided on the surface side of the semiconductor device, the operation threshold of each CMOS (10) can be adjusted. Thus, an effect similar to that of the twelfth aspect can be obtained.

  In this case, as described in claim 14, a PN junction composed of a p-type layer (2a) and an n-type layer (2b) is formed on the support layer (2) electrically connected to the threshold adjustment electrode (40). Preferably, the threshold adjustment electrode (40) is formed so as to be electrically connected to the p-type layer (2a). By doing in this way, it is also possible to suppress voltage propagation through the support layer (2).

  Further, when the threshold adjustment electrode (40) is provided as described in claims 13 to 14, as described in claim 15, the SOI layer (1) and the support layer (2) in the first region (R1) are provided. The plurality of regions are insulated and separated, and the SOI layer (1) of each of the plurality of regions is provided with a CMOS (10), and the threshold adjustment electrode (40) is provided to the support layer (2) of each of the plurality of regions. Each can be provided. Thereby, the operation threshold value of the CMOS (10) can be adjusted in each of the plurality of regions.

  In the invention described in claim 16, the SOI substrate (4) is provided with a thin film structure (50) composed of an SOI layer (1) and a buried insulating film (3), and the thin film structure. (50) is surrounded by the first region (R1) and the second region (R2).

  Thus, a thin film structure (50) can also be provided. In this case, it is possible to prevent the thin film structure (50) from being damaged by surrounding the thin film structure (50) with the first region (R1) and the second region (R2). It becomes.

  As such a thin film structure (50), as described in claim 17, for example, a recess (51) in which an SOI layer (1) is recessed, a bottom surface of the recess (51), and a buried insulating film And a sensor or a microphone having a diaphragm (52) constituted by (3).

  The invention described in claims 18 and 19 relates to the manufacturing method of the invention described in claim 1.

  Specifically, in the invention described in claim 18, a step of preparing an SOI substrate (4) and penetrating the SOI layer (1) and the buried insulating film (3) with respect to the SOI substrate (4). After forming a trench (5) that reaches the support layer (2), an insulating film (6) is buried in the trench (5) to separate at least the first region (R1) and the second region (R2). A step of forming a trench isolation portion (7), a step of forming an element for the first region (R1) in the SOI substrate (4), an SOI layer (1) and a buried insulating film in the second region (R2) The method includes a step of removing (3) and a step of forming an element on the support layer (2) in the second region (R2). According to such a manufacturing method, the semiconductor device according to claim 1, specifically, the semiconductor device according to claim 2 can be manufactured.

  According to the nineteenth aspect of the present invention, the buried insulating film (3) is formed on the silicon substrate (8) by performing a heat treatment process after implanting oxygen ions into the bulk silicon substrate (8). Forming a partial SOI substrate constituting the SOI substrate (4) by forming and forming an SOI structure including the SOI layer (1) and the support substrate (2) with the buried insulating film (3) interposed therebetween Then, a trench (5) that penetrates the SOI layer (1) and the buried insulating film (3) to reach the support layer (2) is formed in the SOI substrate (4), and then the trench (5) By embedding the insulating film (6), the trench isolation part is separated into the first region (R1) disposed at the position where the SOI structure is formed and the second region (R2) disposed at the position where the SOI structure is not formed. (7) forming step and SOI substrate (4 Is characterized by comprising the steps of element formation, the step of element formation relative to the support layer (2) in the second region (R2), against the first region (R1) in the. Also by such a manufacturing method, the semiconductor device according to claim 1, specifically, the semiconductor device according to claim 3 can be manufactured.

  In this case, as in the invention described in claim 20, in the step of preparing the partial SOI substrate, the energy at the time of implanting oxygen ions into the silicon substrate (8) is controlled to be different in a plurality of stages. By implanting oxygen ions to a depth, a plurality of buried insulating films (3) can be formed.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment. With reference to this figure, the configuration of the semiconductor device of this embodiment will be described. In the following description, the upper side in FIG. 1 is described as the front side of the semiconductor device, and the lower side in FIG. 1 is described as the back side of the semiconductor device.

  As shown in FIG. 1, the semiconductor device of this embodiment includes an SOI substrate 4 in which an SOI layer 1 and a support layer 2 made of, for example, n-type silicon are bonded via a buried oxide film (BOX) 3. It is formed using.

  The SOI layer 1 is disposed on the surface side of the semiconductor device, and is configured by grinding a silicon substrate to a film thickness of about 10 nm to 10 μm. The SOI layer 1 is configured with a signal processing circuit such as a logic circuit driven with low power. Hereinafter, the region where the signal processing circuit is formed is referred to as a low power circuit portion R1.

The small power circuit portion R1 is isolated from other portions of the semiconductor device by the trench 5 and the trench isolation portion 7 formed of the insulating film 6 disposed in the trench 5. The low-power circuit unit R1 includes various elements that constitute a signal processing circuit such as the CMOS 10. Specifically, the SOI layer 1 is element-isolated by an element isolation insulating film 11 such as STI (Shallow Trench Isolation) or LOCOS oxide film, and each element-isolated region is divided into an n-well layer 12a or p The well layer 12b is formed. A p ⁺ type source region 13a and a p ⁺ type drain region 14a are formed in the n well layer 12a, and an n ⁺ type source region 13b and an n ⁺ type drain region 14b are formed in the p well layer 12b. The surface of the n well layer 12a located between the p ⁺ type source region 13a and the p ⁺ type drain region 14a and the p well layer located between the n ⁺ type source region 13b and the n ⁺ type drain region 14b. Gate electrodes 16a and 16b are formed on the surface of 12b via gate insulating films 15a and 15b. Thus, a CMOS 10 composed of an n-channel MOSFET and a p-channel MOSFET is configured.

  Incidentally, on the surface side of the SOI layer 1, gate electrodes 16a and 16b constituting the CMOS 10, wiring portions electrically connected to the source regions 13a and 13b or the drain regions 14a and 14b, an interlayer insulating film, and the like are formed. However, the illustration is omitted here. In addition to the CMOS 10, a bipolar transistor, a diffused resistor, and a memory are also provided. Since these structures are well known, only the CMOS 10 is shown here as a representative.

  On the other hand, in the portion of the SOI substrate 4 other than the small power circuit portion R1, the SOI layer 1 and the buried oxide film 3 are removed, and the support layer 2 is exposed on the surface side of the semiconductor device. Therefore, a step corresponding to the thickness of the SOI layer 1 and the buried oxide film 3 is formed between the small power circuit portion R1 and the region where the support layer 2 is exposed. In the present embodiment, various high power elements are provided with the region of the support layer 2 exposed on the surface side of the semiconductor device as the high power circuit portion R2.

  The large power circuit portion R2 is also element-isolated at the trench isolation portion 7 by the trench 5 and the insulating film 6. In the case of the semiconductor device of this embodiment, a power MOSFET 20 having a trench gate structure is provided in one isolated region. In the other region, a protection diode 30 is provided.

The power MOSFET 20 corresponds to a power element. In the present embodiment, the power MOSFET 20 is a vertical element that allows current to pass through the front and back of the support layer 2. A p-type base region 21 is formed in the surface layer portion of the support layer 2 constituting the power MOSFET 20, and an n ⁺ -type source region 22 is formed so as to terminate in the p-type base region 21. . A trench 23 is formed so as to penetrate the n ⁺ -type source region 22 and the p-type base region 21 and reach the n-type support layer 2, and the inside of the trench 23 is formed so as to cover the inner wall surface of the trench 23. The gate insulating film 24 and the gate electrode 25 formed on the surface of the gate insulating film 24 are embedded. An n ⁺ type drain region 26 is formed on the back surface side of the support layer 2, and a drain electrode 27 ohmically connected to the n ⁺ type drain region 26 is provided. With such a structure, a power MOSFET is configured.

Note that a wiring portion and an interlayer insulating film electrically connected to the gate electrode 25 or the n ⁺ -type source region 22 and the p-type base region 21 are formed on the surface side of the support layer 2. Is omitted.

  In addition, a p-type anode layer 31 and an n-type cathode layer 32 terminating in the p-type anode layer 31 are formed on the surface layer portion of the support layer 2 in which the protective diode 30 is formed. The protection diode 30 is configured by a PN junction formed by the n-type cathode layer 32. Since the protection diode 30 is a horizontal element that allows current to flow in a direction parallel to the surface of the semiconductor device, the back surface side of the support layer 2 in which the protection diode 30 is formed is covered with an insulating film 33.

  Note that, on the surface side of the protective diode 30, wiring portions and interlayer insulating films that are electrically connected to the p-type anode layer 31 and the n-type cathode layer 32 are formed, but the illustration is omitted here. is there.

  The semiconductor device of this embodiment is configured by such a structure. In the semiconductor device having such a structure, the SOI layer 1 is used as the small power circuit portion R1 and the support layer 2 is used as the high power circuit portion R2 while using the SOI substrate 4.

  Therefore, the thickness of the SOI layer 1 may be set in consideration of the small power circuit portion R1, and may not be set in consideration of the breakdown voltage of the high power circuit portion R2. Therefore, it becomes possible to eliminate the boundary of the well layer as in the case where the well layer is formed in the thick SOI layer, and it is possible to eliminate the parasitic capacitance and to increase the power consumption and the calculation speed due to the parasitic capacitance. It becomes possible to prevent.

  On the other hand, since the high power circuit portion R2 is formed on the support layer 2 having a sufficient thickness, it is possible to ensure a withstand voltage and the like. Therefore, even when various circuits such as the small power circuit portion R1 constituted by the signal processing circuit and the large power circuit portion R2 including the power MOSFET 20 are mounted together, it is possible to cope with one chip.

  Therefore, when a variety of circuits such as the low-power circuit portion R1 and the high-power circuit portion R2 are mixedly mounted, a semiconductor device having a structure that can cope with one chip and can suppress the thickening of the SOI layer 1 is provided. It becomes possible.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described. 2 to 4 are cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment. This will be described with reference to these drawings.

[Step shown in FIG. 2 (a)]
First, an SOI substrate 4 in which an SOI layer 1 made of n-type silicon and a support layer 2 are bonded with a buried oxide film 3 is prepared. There are various methods for manufacturing the SOI substrate 4, but since they are well known in the art, description thereof is omitted here.

[Step shown in FIG. 2 (b)]
Next, a trench 5 is formed in the SOI substrate 4. For example, after a mask such as a silicon oxide film, a silicon nitride film, or a resist is disposed on the surface of the SOI layer 1, a portion where the trench 5 is to be formed is opened in the mask. Using this mask, the SOI layer 1, the buried oxide film 3 and the support layer 3 are etched to form a trench 5 having a depth that does not penetrate through the support layer 3. At this time, it is necessary to change the etching material between the SOI layer 1 and the support layer 2 made of silicon and the buried oxide film 3 made of an insulating film such as a silicon oxide film. Thereafter, thermal oxidation is performed to form a thermal oxide film on the inner wall surface of the trench 5, and then the interior of the trench 5 is buried by disposing Poly-Si on the surface of the thermal oxide film. Then, by removing Poly-Si formed on the surface of the SOI layer 1 or a mask by CMP polishing or the like, a trench isolation portion 7 in which the trench 5 is filled with the insulating film 6 is configured.

[Step shown in FIG. 3 (a)]
A signal processing circuit including the CMOS 10 in a desired region of the SOI layer 1 is formed by a well-known formation method (an element isolation step by STI or the like, a step of forming an n well layer 12a or a p well layer 12b by ion implantation and activation heat treatment, ion implantation And a step of forming source regions 13a and 13b and drain regions 14a and 14b by activation heat treatment, a step of forming gate insulating films 15a and 15b by thermal oxidation, etc., gate electrodes 16a and 16b by deposition and patterning of doped Poly-Si And the like. Thereby, the low power circuit portion R1 is formed.

  Then, after arranging a mask so as to cover the small power circuit portion R1, the SOI layer 1 and the buried oxide film 3 are removed in the large power circuit portion R2 by etching. Thereby, the surface side of the support layer 2 can be exposed in the high power circuit portion R2.

[Step shown in FIG. 3B]
A well-known formation technique (p-type base region 21 or n ⁺ -type source region 22 by p-type ion implantation and activation heat treatment, p-type) Step of forming anode layer 31 and n-type cathode layer 32, step of forming trench 23, step of forming gate insulating film 24 by thermal oxidation or stacking of silicon nitride films, gate electrode 25 by embedding doped Poly-Si and etch back And the like.

[Step shown in FIG. 4 (a)]
With the support layer 2 side facing upward, the support layer 2 is ground from the back side by CMP polishing or the like, so that at least the trench isolation portion 7 is exposed. After that, after n-type impurities are ion-implanted from the back surface of the support layer 2, an activation heat treatment is performed to form the n ⁺ -type drain region 26. Subsequently, an insulating film 33 is formed on the back surface of the support layer 2, and is then patterned and left on the back surface of the protection diode 30.

[Step shown in FIG. 4B]
An electrode layer made of Al or the like is formed on the back surface side of the support layer 2, and then patterned and left on the back surface of the power MOSFET 20 to form the drain electrode 27.

  Although the subsequent steps are not shown, the semiconductor device of this embodiment is completed through an interlayer insulating film forming step, a wiring forming step, a protective film forming step, and the like.

  As described above, in the semiconductor device of this embodiment, the SOI layer 1 is used as the small power circuit unit R1 and the support layer 2 is used as the high power circuit unit R2 while using the SOI substrate 4. Thereby, even when various circuits such as the low-power circuit portion R1 and the high-power circuit portion R2 are mixedly mounted, a semiconductor device having a structure that can cope with one chip and can suppress the increase in the thickness of the SOI layer 1 is provided. Is possible.

(Second Embodiment)
A second embodiment of the present invention will be described. The semiconductor device of this embodiment is obtained by separating the power MOSFET 20 and the protection diode 30 into a plurality of parts with respect to the first embodiment, and is otherwise the same as the first embodiment.

FIG. 5 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in FIG. 5, each cell constituting the power MOSFET 20 is element-isolated by the trench isolation section 7, and a plurality of n ⁺ -type drain regions 26 and drain electrodes 27 are provided for each cell. . Further, the protection diode 30 is also element-isolated by the trench isolation part 7 for each cell.

  In this way, the power MOSFET 20 and the protection diode 30 can be divided into a plurality of pieces. The power MOSFET 20 can be divided into a plurality of channels, and the power MOSFET 20 can be multi-channeled by providing a plurality of drain electrodes 27.

As for the semiconductor device having such a structure, the pattern for forming the trench isolation portion 7 and the patterning for forming the n ⁺ -type drain region 26 and the drain electrode 27 are changed with respect to the first embodiment. Can be manufactured.

(Third embodiment)
A third embodiment of the present invention will be described. The semiconductor device of the present embodiment is such that threshold adjustment of the CMOS 10 or the like in the low-power circuit unit R1 is performed with respect to the first embodiment, and the others are the same as those of the first embodiment.

  FIG. 6 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, a threshold adjustment electrode 40 is provided on the back surface of the support layer 2 corresponding to the CMOS 10 provided in the low power circuit portion R1. FIG. 6 shows a case where a plurality of CMOSs 10 are provided in the low-power circuit part R1. Each CMOS 10 is divided by the trench isolation part 7, and a threshold adjustment electrode 40 is provided corresponding to each CMOS 10. I have to. In FIG. 6, the two CMOSs 10 on the left side of the drawing are omitted, but the CMOSs 10 are actually formed.

  By providing such a threshold adjustment electrode 40, the potential applied to the support layer 2 corresponding to the back surface of the CMOS 10 can be changed, and the operation threshold of the CMOS 10 can be adjusted. For this reason, the characteristics of the CMOS 10 can be set to desired values, such as speeding up by setting the operation threshold of the CMOS 10 low.

  A semiconductor device having such a structure can be manufactured by simply increasing the number of steps for forming the threshold adjustment electrode 40. Since the threshold adjustment electrode 40 can be formed at the same time as the drain electrode 27 is formed, the semiconductor device of this embodiment can be manufactured without increasing the number of manufacturing steps compared to the first embodiment. .

(Fourth embodiment)
A fourth embodiment of the present invention will be described. Similarly to the third embodiment, the semiconductor device of this embodiment also performs threshold adjustment of the CMOS 10 or the like in the low-power circuit unit R1, and the other aspects are the same as those of the first embodiment.

  FIG. 7 is a cross-sectional view of the semiconductor device according to the present embodiment. This figure shows a case where a plurality of CMOSs 10 are provided in the low-power circuit unit R1, and each CMOS 10 is divided by the trench isolation unit 7. Then, the SOI layer 1 and the buried oxide film 3 are partially removed around each CMOS 10, and a threshold adjustment electrode 40 electrically connected to the support layer 2 is formed at the removed place. An insulating film 41 is disposed between each CMOS 10 and the threshold adjustment electrode 40 so that each CMOS 10 and the threshold adjustment electrode 40 are insulated and separated. In FIG. 7, the two CMOSs 10 on the left side of the drawing are omitted, but the CMOSs 10 are actually formed.

  In the low power circuit portion R1, the support layer 2 has a p-type layer 2a in the upper layer portion and an n-type layer 2b in the lower layer portion to form a PN junction. The structure is covered with 33.

  With such a structure, since it can be electrically connected to the support layer 2 through the threshold adjustment electrode 40 provided on the surface side of the semiconductor device, it is possible to adjust the operation threshold of each CMOS 10, which is the third embodiment. The same effect can be obtained. Further, if a PN junction is formed in the support layer 2 as in the present embodiment, voltage propagation through the support layer 2 can be suppressed.

A semiconductor device having such a structure can be manufactured by simply increasing the number of steps for forming the threshold adjustment electrode 40 and increasing the number of steps for forming the p-type layer 2a or the n-type layer 2b on the support layer 2. . Regarding the threshold adjustment electrode 40, when removing the SOI layer 1 and the buried oxide film 3 when forming the trench isolation portion 7, the portion where the threshold adjustment electrode 40 is disposed is also removed. The support layer 2 is prevented from being removed under the threshold adjustment electrode 40 by covering with a mask, and the threshold is formed when forming the wiring layers connected to the gate electrodes 16a and 16b or the source regions 13a and 13b and the drain regions 14a and 14b. The adjustment electrode 40 may be formed at the same time. Further, the step of forming the p-type layer 2a or the n-type layer 2b is a stage before the support layer 2 and the SOI layer 1 are bonded together via the buried oxide film 3 when the support layer 2 is composed of n-type. in, it is possible to form a p-type layer 2a by performing such pre-ion implantation into the support layer 2, when forming the support layer 2 a p-type, at the same time n-type when forming the n ⁺ -type drain region 26 Layer 2b can be formed.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. The semiconductor device of this embodiment is a combination of a thin film structure such as a sensor with respect to the first embodiment, and the other parts are the same as those of the first embodiment, and therefore only different parts will be described.

  FIG. 8 is a cross-sectional view of the semiconductor device according to the present embodiment. 9A is a top layout view of the semiconductor device shown in FIG. 8, and FIG. 9B is a partially enlarged view of FIG. 9A. FIG. 8 corresponds to the AA cross section of FIG.

  As shown in FIG. 8, a thin film structure 50 constituted by the SOI layer 1 and the buried oxide film 3 by removing the support layer 2 between the low power circuit portion R1 and the high power circuit portion R2. Is provided. The thin film structure 50 is, for example, a sensor or a microphone. Specifically, in the thin film structure 50, the SOI layer 1 is further recessed by forming the recess 51 by recessing the SOI layer 1 from the surface side, and the thinned SOI layer 1 and the embedded oxidation are formed. A diaphragm 52 composed of the membrane 3 is provided. As shown in FIG. 9B, the diaphragm 52 is formed with a piezoresistor 53 composed of a p-type diffusion layer or the like, and when the diaphragm 52 is distorted due to application of pressure or sound, the distortion is reduced. Accordingly, the resistance value of the piezoresistor 53 is changed. For this reason, the thin film structure 50 can be a sensor that detects pressure or the like based on a change in the resistance value of the piezoresistor 53 or a microphone that captures sound.

  Each piezoresistor 53 is electrically connected to the low power circuit portion R1 in a region where the signal processing circuit is formed through the wiring 54, and the resistance value change of each piezoresistor 53 is connected to the signal processing circuit through the wiring 54. By being transmitted, the thin film structure 50 can be made to function as a sensor or a microphone as described above.

  As shown in FIG. 9A, such a thin film structure 50 is formed, for example, at the center position of the chip on which the semiconductor device is formed. For this reason, the periphery of the thin film structure 50 is surrounded by the remaining portion of the support layer 2, and the thin film structure 50 can be prevented from being damaged.

  Here, the case where the thin-film structure 50 is configured with the buried oxide film 3 remaining is described. However, the buried oxide film 3 is thinned or removed in accordance with a desired sensor sensitivity or the like. May be.

(Sixth embodiment)
A sixth embodiment of the present invention will be described. The semiconductor device of this embodiment is configured to more reliably perform isolation of the power MOSFET 20 with respect to the first embodiment, and is otherwise the same as the first embodiment.

  FIG. 10 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, a multiple trench structure is formed by providing a plurality of trench isolation portions 7 formed between the power MOSFET 20 and other elements, that is, the low power circuit portion R1 and the protection diode 30.

  As described above, the trench isolation portion 7 for insulating and isolating the power MOSFET 20 has a multi-trench structure, so that it is possible to perform isolation and isolation from other elements, and the high voltage used in the power MOSFET 20 is different from that of other elements. Potential interference that interferes with the element can be suppressed.

(Seventh embodiment)
A seventh embodiment of the present invention will be described. The semiconductor device of this embodiment is obtained by dividing the power MOSFET into a main cell and a sense cell with respect to the first embodiment, and is otherwise the same as that of the first embodiment.

  FIG. 11 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, the power MOSFET 20 is divided into a main cell and a sense cell by the trench isolation part 7. Each element constituting the main cell and the sense cell has basically the same structure, but the main cell is composed of a large number of cells, and the sense cell is composed of a smaller number of cells. A large current flowing in the main cell can be detected by flowing a current proportional to the large current flowing in the main cell to the sense cell side and detecting the current on the sense cell side. Such a semiconductor device is applied to, for example, a load driving device that supplies a large current flowing to the main cell side to a load.

  Thus, even when the power MOSFET 20 is divided into the main cell and the sense cell, the same effect as that of the first embodiment can be obtained. In the semiconductor device according to the present embodiment, the protection diode 30 is not provided. However, the protection device 30 may be provided as necessary.

(Eighth embodiment)
An eighth embodiment of the present invention will be described. The semiconductor device of the present embodiment is further provided with a temperature sensor with respect to the semiconductor device shown in the seventh embodiment, and the others are the same as those of the seventh embodiment.

  FIG. 12 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in the figure, a temperature sensor 60 is provided in the large power circuit R2 so as to be adjacent to the power MOSFET 20. The temperature sensor 60 is composed of, for example, a plurality of PN diodes including a p-type layer 61 and an n-type layer 62, and detects the temperature of the power MOSFET 20 based on the temperature characteristics of the PN diode. Then, based on the temperature detected by the temperature sensor 60, for example, various calculations are performed by the signal processing circuit provided in the small power circuit unit R1, and the driving state of the power MOSFET 20 is controlled to prevent overheating. Perform the process.

  Since the temperature sensor 60 is not an element that consumes a large amount of power, the temperature sensor 60 can be provided on the small power circuit unit R1 side. However, by providing the temperature sensor 60 on the large power circuit unit R2 side, the temperature of the power MOSFET 20 is closer. Therefore, the temperature of the power MOSFET 20 can be detected more correctly.

  Thus, even in a structure including the temperature sensor 60 that detects the temperature of the power MOSFET 20, the same effect as that of the first embodiment can be obtained.

(Ninth embodiment)
A ninth embodiment of the present invention will be described. The semiconductor device according to the present embodiment is obtained by changing the location of the temperature sensor 60 shown in the eighth embodiment, and is otherwise the same as that of the eighth embodiment.

  FIG. 13 is a cross-sectional view of the semiconductor device according to the present embodiment. FIG. 14 is a top layout view of the semiconductor device according to FIG. As shown in these drawings, a temperature sensor 60 is provided on the surface of the support layer 2 provided with the power MOSFET 20 in the large power circuit portion R2. The temperature sensor 60 is formed on the surface of the support layer 2 via an insulating film 63 such as an oxide film.

  Thus, the temperature sensor 60 can also be formed on the surface of the support layer 2 on which the power MOSFET 20 is formed. In this way, not only the same effects as in the eighth embodiment can be obtained, but also the temperature sensor 60 can be brought closer to the power MOSFET 20 and the temperature of the power MOSFET 20 can be detected more correctly.

(10th Embodiment)
A tenth embodiment of the present invention will be described. The semiconductor device of the present embodiment has the same structure as that of the semiconductor device shown in the first embodiment, but the SOI substrate 4 is not the whole substrate having the SOI structure, but the one having a partially formed SOI structure. The other components are the same as those in the first embodiment.

  FIG. 15 is a cross-sectional view of the semiconductor device according to the present embodiment. In the first embodiment, the SOI substrate 4 is formed by forming an SOI structure in which the SOI layer 1 is formed on the entire surface of the support layer 2 via the buried oxide film 3. Then, as shown in FIG. 15, only the low power circuit portion R1 has an SOI structure. For this reason, no step is formed between the small power circuit portion R1 and the large power circuit portion R2, and the respective surfaces are in the same plane. As described above, a so-called partial SOI substrate in which an SOI structure is partially configured can be used as the SOI substrate 4.

  16 and 17 are cross-sectional views showing manufacturing steps of the semiconductor device of this embodiment shown in FIG. The semiconductor device manufacturing method of the present embodiment is generally the same as the semiconductor device manufacturing method of the first embodiment, but differs in the following points.

Specifically, in the step shown in FIG. 16A, a bulk silicon substrate 8 is prepared, and then the same process as that in FIG. Form. In the step shown in FIG. 16B, after covering the portions other than the low power circuit portion R1 with a mask (not shown), oxygen ions are implanted from above the mask. For example, the dose is about 1 to 10 × 10 ¹⁷ cm ⁻³ and the implantation energy is 50 to 500 eV. Thereby, in the low power circuit portion R1, oxygen ions are implanted at a predetermined depth from the surface of the silicon substrate 8.

  Subsequently, a heat treatment step is performed in the step shown in FIG. For example, heating is performed at a temperature of 1200 to 1400 ° C. for about 5 hours. By this heat treatment step, oxygen ions implanted into the small power circuit portion R1 in the silicon substrate 8 are oxidized with nearby silicon to form the buried oxide film 3, and the buried oxide film 3 forms the silicon substrate 8 into the buried oxide film 3. Separated up and down. Among these, the upper side is the SOI layer 1, and the lower side and the high-power circuit unit R 1 function as the support substrate 2.

  Thereafter, by performing each manufacturing process from FIG. 3 shown in the first embodiment, the semiconductor device of this embodiment is completed as shown in FIG. 17B. In the present embodiment, as shown in FIGS. 16A and 16B, the case where the buried insulating film 3 is formed after the trench isolation portion 7 is formed has been described. Alternatively, the trench isolation portion 7 may be formed after the buried insulating film 3 is formed.

(Eleventh embodiment)
An eleventh embodiment of the present invention will be described. The semiconductor device of the present embodiment is obtained by forming a plurality of buried oxide films 3 with respect to the tenth embodiment, and is otherwise the same as the tenth embodiment.

  FIG. 18 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, in this embodiment, the buried oxide film 3 is formed in two layers. The thickness of each layer is arbitrary, but if the total film thickness is the same as that of the single buried oxide film 3 shown in the tenth embodiment, an equivalent breakdown voltage can be obtained in terms of breakdown voltage design. .

  Thus, a plurality of buried oxide films 3 may be formed. The formation of the buried oxide film 3 having a plurality of layers changes the ion implantation energy described in the step shown in FIG. 16B of the tenth embodiment and changes the implantation depth. This can be done by controlling the thickness.

(Twelfth embodiment)
A twelfth embodiment of the present invention will be described. The semiconductor device of the present embodiment is obtained by changing the structure of the power MOSFET 20 with respect to the first embodiment, and is otherwise the same as that of the tenth embodiment.

FIG. 19 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, in this embodiment, at the position where the power MOSFET 20 is formed, the support layer 2 has a super junction structure, specifically, n ⁺ -type layer 28a and p-type layer 28b are alternately arranged in order. The structure is arranged in The n ⁺ type layer 28a is formed at a position corresponding to the trench gate structure, that is, at a position below the n ⁺ type source region 22, and the p type layer 28b is formed between the trench gate structures. With such a super junction structure, when the power MOSFET 20 is not in operation, the current path can be pinched off by the depletion layer extending to the PN junction formed by the n ⁺ -type layer 28a and the p-type layer 28b. The withstand voltage can be increased. Further, when the power MOSFET is operated, the depletion layer is reduced, and a current can flow through the high concentration n ⁺ -type layer 28a, so that a low on-resistance can be achieved.

(13th Embodiment)
A thirteenth embodiment of the present invention will be described. In the present embodiment, a wiring structure when various elements are formed in the small current circuit portion R1 and the large current circuit portion R2 as in the above embodiments will be described.

  FIG. 20 is a cross-sectional view showing an example of a wiring structure in a structure provided with a temperature sensor 60 while being divided into a main cell and a sense cell of the power MOSFET 20 as in the eighth embodiment. However, in the present embodiment, the temperature sensor 60 is provided in the low power circuit unit R1.

As shown in this figure, the electrical connection between each part separated by the trench isolation part 7 and the signal processing circuit provided in the small power circuit part R1 is made of a conductor made of metal such as Al. The wiring layer 70 and the interlayer insulating film 71 formed thereon are used as a set, and at least one set of the wiring layer 70 and the interlayer insulating film 71 is used. In the case of this embodiment, three sets of a set connecting the temperature sensor 60 and the signal processing circuit, a set connecting the sense cell of the power MOSFET 20 and the signal processing circuit, and a set connecting the main cell and the signal processing circuit are stacked. The set of wiring layers 70 connected to the uppermost main cell is formed on almost the entire region where the power MOSFET 20 is formed, and is electrically connected to the n ⁺ -type source region 22. The structure also works as a source electrode. A protective film 73 is formed on the wiring layer 70. The protective film 73 is partially opened so that the wiring layer 70 is exposed, and the wiring layer 70 exposed from the opened portion is used as a pad. The structure can be electrically connected to the outside by bonding or the like.

  Thus, even if various elements are formed in the small current circuit portion R1 and the large current circuit portion R2, each element and the signal processing circuit can be securely connected to each other.

(14th Embodiment)
A fourteenth embodiment of the present invention will be described. In this embodiment, the wiring structure when various elements are formed in the small current circuit portion R1 and the large current circuit portion R2 as in the above embodiments will be described.

  In the case of the present embodiment, each element and the signal processing circuit are electrically connected by only one set rather than a structure in which a plurality of sets of wiring layers 70 and interlayer insulating films 71 are stacked as in the thirteenth embodiment.

  FIG. 21 is a layout diagram showing an example of a wiring structure in a structure in which the power MOSFET 20 is divided into a main cell and a sense cell and the thin film structure 50 and the temperature sensor 60 are provided.

  As shown in this figure, the region R1b in which the temperature sensor 60 is formed is disposed adjacent to the region R1a provided with the signal processing circuit in the low-power circuit unit R1, and so as to be adjacent to the region R1a. A region R2a where the sense cell of the power MOSFET 20 is formed and a region R2b where the main cell is formed are formed. In addition, a structure in which a region R1c in which the thin film structure 50 is formed is disposed on the opposite side of the region R1a in which the signal processing circuit is formed across the region R1b in which the temperature sensor 60 is formed and the region R2a in which the sense cell is formed. It is said.

  In such a structure, the layout is such that the wiring layer 70 extended from the region R1b, the region R1c, the region R2a, and the region R2b does not overlap with the region R1a. As a result, each element and the signal processing circuit can be electrically connected only by one set of the wiring layer 70 of the conductor and the interlayer insulating film 71 formed thereon.

  In the drawing, a portion surrounded by a broken line in the region R2b is a region to be a source electrode in the wiring layer 70. A protective film 72 is opened at the center of this region, and electrical connection with the outside is possible. In addition, a portion of the region R2b that is not surrounded by a broken line is a wiring layer 70 that is electrically connected to each gate electrode 25.

(Other embodiments)
(1) In each of the above embodiments, a CMOS is shown as an example of an element constituting a signal processing circuit provided in the small power circuit unit R1, but as described above, other elements such as a bipolar transistor may be formed. . Similarly, the trench gate structure MOSFET has been described as an example of the element provided in the high-power circuit unit R2, but other elements may be used. Of course, this is particularly effective when the element is a power element. In addition, the other element may be another vertical element or a horizontal element.

  (2) In the first embodiment, in the step shown in FIG. 3A, after the element formation of the small power circuit portion R1, the SOI layer 1 and the buried oxide film 3 of the large power circuit portion R2 are removed. However, the order of these steps may be changed.

  In the first embodiment, the back side is ground after the steps shown in FIGS. 3A and 3B. However, after the back side is ground, the back side is shown in FIGS. 3A and 3B. You may make it perform a process.

  (3) The above embodiments may be combined as appropriate. For example, as shown in the second embodiment, the power MOSFET 20 or the like has a multi-channel structure (see FIG. 5), and as shown in the third and fourth embodiments, the structure includes the threshold adjustment electrode 40 of the CMOS 10 (FIG. 6). , See FIG. 7). In addition to the structure of the first embodiment, the thin film structure 50 shown in the fifth embodiment with respect to the structure of the second to fourth embodiments or a structure combining these embodiments (see FIGS. 8 and 9). ) May be provided. Furthermore, the element isolation structure (see FIG. 10) using multiple trenches shown in the sixth embodiment may be applied to the first to fifth embodiments or a structure in which these embodiments are combined.

  (4) The materials constituting the SOI substrate 4 and the materials constituting the elements formed on the SOI substrate 4 shown in the above embodiments can be appropriately changed. For example, in each of the above embodiments, the buried oxide film 3 is used as the buried insulating film of the SOI substrate 4, but another insulating film may be used.

  (5) In each of the above embodiments, in the high-power circuit portion R2, the structure in which the element is formed from the front surface side of the support layer 2 is described as an example. However, the element is formed from the back surface side of the support layer 2. It does not matter as a structure. In addition, when the element is formed from the back side of the support layer 2 as described above, the element can be formed from the back side of the support layer 2 even in the low-power circuit portion R1.

  (6) In each of the above-described embodiments, the low power circuit unit R1 is used as the first region and the high power circuit unit R2 is used as the second region. However, these must always be a low power circuit and a high power circuit. is not. However, it is particularly preferable to apply to a form in which a small power circuit is formed in the SOI layer 1 and a large power circuit is formed in the support layer 2.

  (7) In the tenth and eleventh embodiments, the case where the SOI substrate 4 is a partial SOI substrate in configuring the semiconductor device having the same structure as that of the first embodiment has been described. Even in the form, only a region where the small power circuit portion R1 is formed may be an SOI structure, and a region where the high power circuit portion R2 is formed may be a partial SOI substrate including only the support substrate 2.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 2; FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3; It is sectional drawing of the semiconductor device concerning 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 4th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 5th Embodiment of this invention. FIG. 9 is a top layout view of the semiconductor device shown in FIG. 8. It is sectional drawing of the semiconductor device concerning 6th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 7th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 8th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 9th Embodiment of this invention. FIG. 14 is a top layout view of the semiconductor device shown in FIG. 13. It is sectional drawing of the semiconductor device concerning 10th Embodiment of this invention. FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 15. FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; It is sectional drawing of the semiconductor device concerning 11th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 12th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 13th Embodiment of this invention. It is a layout diagram of a semiconductor device according to a fourteenth embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... SOI layer, 2 ... Support layer, 2a ... p-type layer, 2b ... n-type layer, 3 ... Embedded oxide film,
3 ... support layer, 4 ... SOI substrate, 7 ... trench isolation part, 8 ... silicon substrate,
10 ... CMOS, 20 ... power MOSFET, 30 ... protection diode,
40 ... threshold adjustment electrode, 50 ... thin film structure, 60 ... temperature sensor, 70 ... wiring layer,
71 ... Interlayer insulating film, 72 ... Protective film, R1 ... Low power circuit part, R2 ... High power circuit part

Claims (20)

A semiconductor device in which a plurality of circuit portions (R1, R2) are mixedly mounted on an SOI substrate (4) having an SOI layer (1) formed on a support layer (2) via a buried insulating film (3). And
The SOI substrate (4) includes a first region (R1) in which the SOI layer (4) is left on the support layer (2) via the buried insulating film (3), and the support layer (2). ) On the buried insulating film (3) and the second region (R2) where the SOI layer (4) is not formed. The SOI layer (1), the buried insulating film (3), and The first region (1) and the second region (R2) are insulated and separated by a trench isolation portion (7) formed so as to penetrate the support layer (2).
In the first region (1), an element constituting a part of the plurality of circuit portions (R1, R2) is formed in the SOI layer (1), and in the second region (R2), the support layer ( 2) In 2), an element constituting a part of the plurality of circuit portions (R1, R2) is formed.   A step corresponding to the thickness of the SOI layer (1) and the buried oxide film (3) is formed between the first region (R1) and the second region (R2). The semiconductor device according to claim 1.   In the SOI substrate (4), the buried insulating film (3) is formed only in the first region (R1), and the buried insulating film (3) is formed in the second region (R2). 2. The semiconductor device according to claim 1, wherein the semiconductor device is a partial SOI substrate that has not been formed.   The semiconductor device according to claim 3, wherein the buried insulating film (3) is provided in a plurality of layers in the first region (R1).   A signal processing circuit is formed in the first region (R1), and a high power circuit having a higher power than the signal processing circuit is formed in the second region (R2). The semiconductor device according to any one of claims 1 to 4.   6. The semiconductor device according to claim 5, wherein a power element (20) is formed as the high power circuit.   The second region (R2) is divided into a plurality of regions by the trench isolation part (7), and the power element (20) is formed in each of the divided regions, thereby increasing the number of channels. The semiconductor device according to claim 6, wherein the semiconductor device is formed.   8. The semiconductor device according to claim 6, wherein the trench isolation part (7) for insulatingly isolating the power element (20) is a multiple trench.   The power element (20) is a vertical element that allows a current to pass through the front and back of the support layer (2), and a current flowing in the main cell and the main cell in the trench isolation part (7). 7. The semiconductor device according to claim 6, wherein the semiconductor device is divided into sense cells through which a current proportional to the current flows.   The support layer (2) in the second region (R2) is provided with a temperature sensor (60) for detecting the temperature of the power element (20), and the power element (20) and the temperature sensor ( 60. The semiconductor device according to claim 9, wherein the trench isolation portion (7) is also insulated and isolated from the semiconductor device 60).   In the support layer (2) in the second region (R2), the power element (20) is disposed on the surface of the support layer (2) via an insulating film (63) at the place where the power element (20) is disposed. The semiconductor device according to claim 9, further comprising a temperature sensor (60) for detecting the temperature of (20).   In the first region (R1), a CMOS (10) is formed in the SOI layer (1). The support layer (2) at a position corresponding to the first region (R1) includes the CMOS (10). The semiconductor device according to any one of claims 5 to 11, wherein the threshold adjustment electrode (40) of (10) is electrically connected.   In the first region (R1), a CMOS (10) is formed in the SOI layer (1), and the support layer penetrates the SOI layer (1) and the buried insulating film (3). The threshold adjustment electrode (40) of the CMOS (10) electrically connected to (2) is formed, and the CMOS (10) and the threshold adjustment electrode (40) are formed on the SOI layer (1). The semiconductor device according to claim 5, wherein the semiconductor device is insulated and separated by the formed insulating film (41).   The support layer (2) electrically connected to the threshold adjustment electrode (40) has a PN junction formed by a p-type layer (2a) and an n-type layer (2b), and the threshold adjustment electrode ( The semiconductor device according to claim 13, wherein 40) is electrically connected to the p-type layer (2a).   The SOI layer (1) and the support layer (2) in the first region (R1) are insulated and separated into a plurality of regions, and the CMOS (10) is formed on the SOI layer (1) in each of the plurality of regions. The threshold adjustment electrode (40) is provided for the support layer (2) in each of the plurality of regions, respectively, and the threshold adjustment electrode (40) is provided. Semiconductor device.   The SOI substrate (4) is provided with a thin film structure (50) composed of the SOI layer (1) and the buried insulating film (3), and the thin film structure (50) is the first thin film structure (50). 16. The semiconductor device according to claim 1, wherein the semiconductor device is surrounded by one region (R1) and the second region (R2).   The thin film structure (50) includes a diaphragm (52) configured by a recess (51) in which the SOI layer (1) is recessed, a bottom surface of the recess (51), and the embedded insulating film (3). The semiconductor device according to claim 16, wherein the semiconductor device is a sensor or a microphone including Manufacture of a semiconductor device in which a plurality of circuit portions (R1, R2) are mixedly mounted on an SOI substrate (4) in which an SOI layer (1) is bonded onto a support layer (2) via a buried insulating film (3). A method,
Preparing the SOI substrate (4);
A trench (5) that reaches the support layer (2) through the SOI layer (1) and the buried insulating film (3) is formed in the SOI substrate (4), and then the trench (5 ) Embedding the insulating film (6) in the step of forming a trench isolation portion (7) that separates at least the first region (R1) and the second region (R2);
Forming an element for the first region (R1) in the SOI substrate (4);
Removing the SOI layer (1) and the buried insulating film (3) in the second region (R2);
Forming a device on the support layer (2) in the second region (R2). Manufacturing of a semiconductor device in which a plurality of circuit portions (R1, R2) are mixedly mounted on an SOI substrate (4) in which an SOI layer (1) is formed on a support layer (2) via a buried insulating film (3). A method,
After implanting oxygen ions into the bulk silicon substrate (8), a heat treatment process is performed to form a buried insulating film (3) on the silicon substrate (8). The buried insulating film (3) Preparing a partial SOI substrate constituting the SOI substrate (4) by configuring an SOI structure including an SOI layer (1) and a support substrate (2) with a sandwiched therebetween,
A trench (5) that reaches the support layer (2) through the SOI layer (1) and the buried insulating film (3) is formed in the SOI substrate (4), and then the trench (5 ) Is embedded into the first region (R1) disposed at the position where the SOI structure is formed and the second region (R2) disposed at the position where the SOI structure is not formed. Forming a trench isolation (7) to be performed;
Forming an element for the first region (R1) in the SOI substrate (4);
Forming a device on the support layer (2) in the second region (R2).   In the step of preparing the partial SOI substrate, the oxygen ions are implanted at different depths by controlling energy when the oxygen ions are implanted into the silicon substrate (8). The method of manufacturing a semiconductor device according to claim 19, wherein the buried insulating film is formed in a plurality of layers.

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