JP2009146553A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of preventing the deterioration of cell disturbance characteristics caused by a data line capacity and being operated by a low voltage. <P>SOLUTION: This device is provided with a memory cell array 1 including a plurality of word lines WL, a plurality of bit line pairs BL intersecting the word lines WL and a plurality of memory cells MC connected to intersections of the plurality of word lines WL and the plurality of bit line pairs BL, a row decoder 3 for selecting a word line WL, a read/write circuit 13 reading and writing data of the memory cell array 1, and a column decoder 4 having a multiplexer circuit 12 constituted of transfer gates G1 and G2 for selectively connecting the plurality of bit line pairs BL and the read/write circuit 13. In access to a memory cell , when the column decoder 4 selects a word line WL, the column decoder turns on the transfer gates G1, G2 after keeping the transfer gates G1, G2 in off-states for a prescribed time. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor device such as an SRAM that operates at a low voltage.

  In LSIs used in mobile devices such as mobile phones, it is required to lower the power supply voltage in order to reduce power consumption. In particular, LSIs that dynamically change the operating frequency and power supply voltage to reduce power consumption require that the power supply voltage be kept as low as possible when the processing load is light. Therefore, an SRAM that is frequently used as a memory in an LSI is required to operate at a lower voltage.

  A conventional SRAM circuit has a memory cell array composed of a plurality of memory cells connected to respective intersections of a plurality of word lines and a plurality of bit line pairs, a row decoder for selecting the word lines, and a bit line for selecting the memory cells. It includes a column decoder that reads / writes data and a controller that controls the row decoder and the column decoder in accordance with an external address signal and control signal.

  The column decoder selects an arbitrary column by address selection of a multiplexer circuit using a transfer gate composed of an NMOS transistor and a PMOS transistor, and a read / write circuit. At the time of access, an arbitrary word line is selected by the row decoder and at the same time an arbitrary transfer gate is opened, and a read / write circuit is further selected, thereby accessing a memory cell at an arbitrary address.

  The SRAM memory cell is widely used as a six-transistor type memory cell comprising four NMOS transistors and two PMOS transistors because it is easy to manufacture and can be highly integrated. It is known that as the power supply voltage decreases, the disturb margin decreases and it is difficult to reduce the voltage. The 6-transistor type memory cell becomes unstable because the “L” level node of the flip-flop is pulled up by the charge flowing from the bit line when the word line is opened. For this reason, a method of stabilizing the cell by reducing the amount of charge from the bit line is employed. Specifically, there is a method of reducing the bit line capacity by reducing the number of cells connected per bit line as much as possible (Non-Patent Document 1).

  However, if the number of cells connected per bit line is reduced as much as possible in order to reduce the voltage, the bit line capacity decreases, but the influence of the data line capacity from the transfer gate gradually becomes impossible to ignore. . Therefore, there arises a problem that the total capacity is not sufficiently reduced even if the number of cells per bit line is reduced.

Furthermore, the data line capacity is a transfer gate junction capacity, wiring capacity, etc., and increases as the number of multiplexers in the column increases. When the number of cells per bit line is limited, when an SRAM having the same capacity is to be configured, the number of column multiplexers tends to increase, and the influence of the data line capacity is further increased. Therefore, there is a problem that the total capacity cannot be sufficiently reduced and the voltage cannot be lowered.
M. Khellah et.al., 2007 Symp. VLSI Circuits, pp76-77

  An object of the present invention is to provide a semiconductor memory device that prevents cell disturb characteristics from being deteriorated due to data line capacitance and operates at a low voltage.

  A semiconductor memory device according to an aspect of the present invention includes a plurality of word lines and a plurality of bit line pairs intersecting the word lines, and at each intersection of the plurality of word lines and the plurality of bit line pairs. A memory cell array including a plurality of connected memory cells, a row decoder for selecting the word line, a read / write circuit for reading data from and writing data to the memory cell array, and the plurality of bit line pairs. A column decoder having a multiplexer circuit composed of a transfer gate for selectively connecting the read / write circuit, and the column decoder selects the transfer line when selecting the word line in accessing the memory cell. After the gate is kept off for a predetermined time, the transfer gate is turned on. Characterized in that it in.

  According to the present invention, it is possible to provide a semiconductor memory device that prevents cell disturb characteristics from being deteriorated due to data line capacitance and operates at a low voltage.

  Hereinafter, embodiments of a semiconductor memory device according to the present invention will be described in detail with reference to the drawings.

[First embodiment]
FIG. 1 is a circuit diagram showing a schematic configuration of the semiconductor memory device according to the first embodiment of the present invention, and FIG. 2 is a circuit diagram showing details of the column decoder shown in FIG.

  The semiconductor memory device according to this embodiment includes a memory cell array 1, a row decoder 3 and a column decoder 4 that select memory cells MC from the memory cell array 1, and a controller 2 that controls the row decoder 3 and column decoder 4. It is prepared for.

  The memory cell array 1 includes a plurality of word lines WL, a bit line pair BL including a plurality of bit lines BLt and BLc, and a plurality of memory cells MC provided at the intersections of the word line WL and the bit line pair BL. ing. Here, the memory cell MC is a 6-transistor type memory cell as shown in FIG. That is, the 6-transistor type memory cell includes a first inverter IV1 having a PMOS transistor Q1 and an NMOS transistor Q2 that are connected to a power supply line VDD and a ground line VSS, respectively, and are connected in a complementary pair. And a second inverter IV2 including a PMOS transistor Q3 and an NMOS transistor Q4 connected to the ground line VSS and connected in a complementary pair. The inputs and outputs of these inverters IV1 and IV2 are connected to each other. A first transfer transistor Q5 is connected between the bit line BLt and the output terminal of the first inverter IV1, and a second transfer transistor is connected between the bit line BLc and the output terminal of the second inverter IV2. Transistor Q6 is connected. The gates of the first and second transfer transistors Q5 and Q6 are connected to the word line WL. Note that the write operation using the 6-transistor type memory cell is performed on both the bit lines BLt and BLc, but the read operation may be single-ended read performed only on one bit line BLt.

  The controller 2 generates a row address signal RA and first and second column address signals CA from an address signal ADD given from the outside, and transfers them to the row decoder 3 and the column decoder 4, respectively. Further, the write enable signal WE is transferred to the column decoder 4 in accordance with a control signal CNT given from the outside.

  The row decoder 3 selects the word line WL based on the row address signal RA given from the controller 2.

  The column decoder 4 includes a plurality of precharge circuits 11, a multiplexer circuit 12, and a read / write circuit 13. The column decoder 4 converts the column address signal CA supplied from the controller 2 into first and second column address signals Ya (Ya1,..., Yam) and Yb (Yb1,..., Ybm). Data is read from and written to the memory cells MC in the column selected by the second column address signals Ya and Yb by the write enable signal WE supplied from the controller 2.

  The precharge circuit 11 is connected between the bit line pair BL. The precharge circuit 11 is a circuit for precharging the bit lines BLt and BLc in advance when data is read from the memory cell MC. The precharge circuit 11 is controlled to be activated / deactivated by the precharge signal pc_b, and the power supply VDD− It is composed of three PMOS transistors Q11, Q12, and Q13 that connect between the bit lines BLt, between the power supply VDD and the bit line BLc, and between the bit lines BLt and BLc, respectively.

  The multiplexer circuit 12 includes a plurality of column transfer gate circuits 12a. Each column transfer gate circuit 12a includes two transfer gates G1 and G2 and one inverter IV3 for one set of bit line pairs BL. The source and drain terminals of the transfer gates G 1 and G 2 are connected to the bit lines BLt and BLc of the memory cell array 1 and the data lines DLt and DLc of the column decoder 4. The first column address signal Ya is input to the gate terminal of the NMOS transistor constituting the transfer gates G1 and G2, and the first column address signal Ya is also input to the gate terminal of the PMOS transistor via the inverter IV3. Is entered. The column transfer gate circuit 12a is turned on when the first column address signal Ya is “H”, and the source terminal and the drain terminal are brought into conduction. A plurality of column transfer gate circuits 12a connected to a bit line pair BL sharing one read / write circuit 13 is a data line pair (hereinafter referred to as DL) composed of data lines DLt and DLc connected to source or drain terminals. .) Is selectively connected to the plurality of bit line pairs BL of the memory cells MC and the data line pairs DL of the column decoder 4.

  The read / write circuit 13 includes a sense amplifier, a write buffer, and the like. The read / write circuit 13 is selected by the second column address signal Yb supplied from the controller 2, and the operation is switched by the write enable signal WE to transfer data to the memory cell MC. Perform a read or write operation. A plurality of read / write circuits 13 are provided, and a plurality of bit line pairs BL are selectively connected to each other via the multiplexer circuit 12.

  The operation of the semiconductor memory device having the above configuration will be described below.

  At the time of reading, the first column address signal Ya is set to “L” and the transfer gates G1 and G2 are turned off in advance. Next, after the precharge circuit 11 precharges the bit line pair BL to a predetermined level, when the row decoder 3 selects the word line WL, the drive NMOS transistor Q2 connected to the “L” node of the selected memory cell MC. Alternatively, since the charge of the bit line BLt or BLc is discharged via Q4, the potential of the bit line BLt or BLc to which the charge has been discharged decreases, and the other potential maintains the charge potential. In the present embodiment, the transfer gate is maintained in the off state for a predetermined time until the potential difference between the bit lines BLt and BLc becomes the predetermined potential difference, and then the transfer gates G1 and G2 are turned on. As a result, even if there is a slight voltage variation due to the connection between the bit line pair BL and the data line pair DL, a predetermined potential difference (disturb margin) between the bit lines BLt and BLc so as to exceed the variation value. Therefore, it is possible to prevent deterioration of disturb characteristics.

  FIG. 4 is a graph showing the relationship between the number of memory cells per bit line, the bit line capacitance C_bl, and the data line capacitance C_data in the semiconductor memory device according to this embodiment.

  As is apparent from FIG. 4, the bit line capacitance C_bl increases in proportion to the increase in the number of connected memories. On the other hand, the data line capacitance C_data is constant without depending on the number of memory cells. Therefore, even when the number of memory cells is sufficiently reduced, the total capacity is not sufficiently reduced due to the influence of the data line capacity C_data. However, according to the present embodiment, data can be read from the memory cell MC without being affected by the data line capacitance C_data, so that errors during data reading can be reduced.

  Next, writing will be described. Since the data is overwritten in the selected memory cell MC at the time of writing, the deterioration of the disturbance does not become a problem. However, in the configuration in which a plurality of bit line pairs BL are connected to each of a plurality of read / write circuits 13 as in the present embodiment, a column transfer gate in a selected state connected to a non-selected read / write circuit 13. A problem similar to that at the time of reading occurs in the bit line pair BL connected to the circuit 12a. For example, when data is written in the memory cell MC connected to the bit line pair BL connected to the i-th column transfer gate circuit 12a connected to the j-th read / write circuit 13, the read / write circuit 13 other than the j-th In the memory cell MC connected to the bit line pair BL connected to the i-th column transfer gate circuit 12a connected to, write data is not supplied even though the column transfer gate circuit 12a is opened, so that the read state The same problem occurs.

  For this reason, even at the time of writing, a reading operation is performed prior to writing. That is, with the transfer gates G1 and G2 turned off in advance, the bit line pair BL is precharged, and the row decoder 3 selects the word line WL. Then, the transfer gate is maintained in the off state for a predetermined time until the potential difference between the bit lines BLt and BLc becomes the predetermined potential difference, and thereafter, the transfer gates G1 and G2 are turned on. Subsequently, the read / write circuit 13 selected to the bit line pair BL to which data is written supplies the data to write the data to the selected memory cell MC.

  Thereby, it is possible to prevent the deterioration of the disturb characteristic for the memory cell MC to which no data is written.

[Second Embodiment]
FIG. 5 is a circuit diagram showing a configuration of the column decoder 4A of the semiconductor memory device according to the second embodiment of the present invention.

  The column decoder 4A according to the present embodiment is different from the column decoder 4 according to the first embodiment in that a latch circuit 24 is further added.

  The latch circuit 24 is connected between a pair of bit lines BL, and is configured by cross coupling of two inverters IV4 and IV5 including transistors Q21 and Q22 and Q23 and Q24. A control switch Q25 for activating / deactivating the latch circuit 24 is connected to the source terminals of the inverters IV4 and IV5, and is controlled by a latch enable signal lat supplied from the controller 2. When the latch enable signal lat is “H”, the latch circuit 24 is activated and the data on the bit line pair BL is latched. On the other hand, when the latch enable signal lat is “L”, the latch circuit 24 is inactivated.

  The operation of the semiconductor memory device having the above configuration will be described below.

  According to the present embodiment, after sufficient amplitude is obtained for the bit lines BLt and BLc, the latch circuit 24 is further activated by the latch enable signal lat from the controller 2 to latch the data of the bit line pair BL. The semiconductor memory device according to the first embodiment is different in that the transfer gates G1 and G2 are turned on.

  According to the first embodiment, at the moment when the transfer gates G1 and G2 are turned on, the charge on the bit line BLt or BLc at the “H” level is charge-shared between the bit line capacitance C_bl and the data line capacitance C_data. Thus, the level of the bit line BLt or BLc at the “L” level may rise instantaneously and disturb may occur. However, according to the present embodiment, the level of the bit line pair BL is held by the latch circuit 24. Therefore, this phenomenon can be further prevented.

  Next, the write operation will be described. FIG. 6 is a waveform diagram showing an operation during writing.

  After a predetermined time when the word line WL is selected and the potential difference between the bit lines BLt and BLc reaches a predetermined potential difference, the latch enable signal lat rises and the latch circuit 24 holds the potentials of the bit lines BLt and BLc. Thereafter, the first column address signal Ya rises to turn on the transfer gates G1 and G2, and simultaneously, writing is started. As a result, it is possible to prevent the deterioration of the disturb characteristics of the memory cells MC not written to the memory cells MC connected to the bit line pair BL connected to the transfer gates G1 and G2 that are turned on.

[Third Embodiment]
FIG. 7 is a circuit diagram showing a configuration of the column decoder 4B of the semiconductor memory device according to the third embodiment of the present invention.

  The latch circuit 34 of the column decoder 4B according to this embodiment is different from the second embodiment in that the control switch Q25 included in the latch circuit 34 is controlled by the latch enable signal lat_n output from each read / write circuit 13. And different.

  The latch enable signal lat_n is a signal that becomes “H” only when the second column address signal Yb is “H” and the write enable signal WE is “H”. That is, when the read / write circuit 13 selected by the second column address signal Yb performs a data write operation, all the latch circuits 34 connected to the read / write circuit 13 are deactivated. The data on the bit lines BLt and BLc is not latched.

  In the second embodiment, as shown in FIG. 6, at the time of writing, data is latched for each bit line pair BL, and then the read / write circuit 13 operates to write back. In this case, the latch circuit 24 is An extra current consumption occurs due to the inversion, so that the driving force of the read / write circuit 13 may not be sufficiently obtained. In this case, the latch circuit 24 is not inverted, and there is a risk that data writing will fail. In this regard, according to the third embodiment, the occurrence of the above-described problem can be prevented by making the latch circuit 34 connected to the memory cell MC into which data is written deactivated to facilitate writing. .

[Fourth Embodiment]
The semiconductor memory device according to the fourth embodiment of the present invention has the same configuration as that of the semiconductor memory device according to the first to third embodiments, and the write and read operations are set to the first operation mode. A second operation mode different from the operation mode is added.

  The second operation mode is to turn on the transfer gates G1 and G2 of the column decoder 4 simultaneously with the selection of the word line WL by the row decoder 3 when reading and writing data in the memory cell MC.

  FIG. 8 shows an operation waveform in the second operation mode in the present embodiment.

  In the first operation mode, as can be seen from FIG. 6, after the word line WL becomes “H”, the first column address signal Ya becomes “H”. As described above, the influence of the data line capacitance C_data. Therefore, sufficient amplitudes of the bit lines BLt and BLc appear quickly. On the other hand, in the second operation mode, as can be seen from FIG. 8, at the same time as the word line WL becomes “H”, the first column address signal Ya becomes “H”, and the transfer gates G1 and G2 are turned on. Therefore, the data line capacitance C_data is affected, and the amplitudes of the bit lines BLt and BLc appear more slowly than in the first operation mode. However, when a power supply voltage that can sufficiently shorten the transition time of the amplitude of the bit lines BLt and BLc can be secured, there is no time for data reading as a premise of data writing as in the first operation mode. It is possible to ensure an operating speed comparable to that of the conventional technology. That is, according to the present embodiment, in the case of processing that does not require a high operating frequency, the first operation mode that can operate at a low voltage is selected, and in the case of processing that requires a fast operating frequency, the operation is performed at a high voltage. By selecting the second operation mode to be performed, it is possible to cope with different operation environments.

  FIG. 9 is a schematic diagram of an LSI system using a semiconductor memory device according to an embodiment of the present invention.

  The LSI system 40 includes a DVS (Dynamic Voltage Scaling) control unit 41 and an SRAM 42 which is a semiconductor storage device. Here, DVS control refers to a control method for reducing power consumption by dynamically changing the drive voltage. In the case of this system, the drive voltage VDD of the SRAM 42 and the operation mode selection signal Mode for determining the operation mode of the SRAM 42 are generated by the DVS control unit 41 and given to the SRAM 42.

  By using this system, it is possible to suppress the occurrence of cell disturbance and reduce power consumption.

1 is a circuit diagram showing a schematic configuration of a semiconductor memory device according to a first embodiment of the present invention. 3 is a circuit diagram showing details of a column decoder of the semiconductor memory device. FIG. 2 is a circuit diagram showing a 6-transistor type memory cell of the semiconductor memory device. FIG. 4 is a graph showing the relationship between the number of memory cells per bit line, the bit line capacity, and the data line capacity of the semiconductor memory device. FIG. 5 is a circuit diagram showing a configuration of a column decoder of a semiconductor memory device according to a second embodiment of the present invention. It is a wave form diagram which shows the operation | movement at the time of writing of the same semiconductor memory device. It is a circuit diagram which shows the structure of the column decoder of the semiconductor memory device concerning the 3rd Embodiment of this invention. FIG. 10 is a waveform diagram in a second operation mode of the semiconductor memory device. 1 is a schematic diagram of an LSI system using a semiconductor memory device according to an embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Controller, 3 ... Row decoder, 4, 4A, 4B ... Column decoder, 11 ... Precharge circuit, 12 ... Multiplexer circuit, 12a ... Column transfer gate circuit, 13... Read / write circuit, 24, 34.

Claims (5)

A plurality of word lines, a plurality of first and second bit line pairs crossing these word lines, and a plurality of memories connected to each intersection of the plurality of word lines and the plurality of bit line pairs A first and second inverter comprising a PMOS transistor and an NMOS transistor, and an output terminal of the first inverter and the first bit. A first transfer transistor connected between the lines and a gate connected to the word line, and an output terminal of the second inverter and the second bit line, and a gate connected to the word line. A memory cell array comprising a second transfer transistor;
A row decoder for selecting the word line;
A column decoder having a read / write circuit for reading data from the memory cell array and writing data to the memory cell array, and a multiplexer circuit composed of a transfer gate for selectively connecting the plurality of bit line pairs to the read / write circuit When,
With
In the access to the memory cell, the column decoder maintains the transfer gate in an off state for a predetermined time when selecting the word line, and then turns on the transfer gate. The column decoder has a latch circuit connected between the bit line pair,
In accessing the memory cell, when the word line is selected, the transfer gate is maintained in an off state for a predetermined time, and then the data of the bit line pair is latched in the latch circuit, and then the transfer gate is in an on state. The semiconductor memory device according to claim 1, wherein: The column decoder, when writing data to the memory cell, maintains the transfer gate in an off state for a predetermined time when the word line is selected, and then turns on the transfer gate. 3. The semiconductor memory device according to 1 or 2. The column decoder includes a plurality of the read / write circuits shared by a plurality of the bit line pairs,
3. The semiconductor memory device according to claim 2, wherein in writing data to the memory cell, a latch circuit between the bit line pairs sharing a read / write circuit for performing a data write operation is deactivated. 4. . The column decoder has first and second operation modes,
In the first operation mode, in the access to the memory cell, after the word line is selected, the transfer gate is turned on after a predetermined time has elapsed,
5. The semiconductor memory device according to claim 1, wherein, in the second operation mode, the transfer gate is turned on simultaneously with selection of the word line in accessing the memory cell. 6.

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