JP2009033878A - Dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a recovery time from a temporary variation of an output voltage caused by a load variation, and to quickly switch an operation mode between a step-down operation mode and a step-up operation mode. <P>SOLUTION: A first voltage comparator CMP_H, a second voltage comparator CMP_L, pull-up circuits I<SB>PU</SB>, SW<SB>PU</SB>, and pull-down circuits I<SB>PD</SB>, SW<SB>PD</SB>are connected to an error amplifier EA of a back-boost (step-down, boosting) DC-DC converter. When a feedback voltage V<SB>FB</SB>generated from the output voltage V<SB>OUT</SB>of an output terminal T<SB>2</SB>becomes higher than a first reference voltage V<SB>CNT</SB>+V<SB>α</SB>, or becomes lower than a second reference voltage V<SB>CNT</SB>-V<SB>β</SB>, a voltage V<SB>OE</SB>of an error amplifying output terminal of the error amplifier EA is pulled down or pulled up. In the other DC-DC converter, a noninverting input terminal, an inverting input terminal, and the output terminal of a first error amplifier are maintained at a voltage level of a first intermediate reference voltage by a first switch. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a DC / DC converter, and is particularly suitable for shortening a recovery time from a temporary fluctuation of an output voltage and improving an operation mode switching speed between a step-down operation mode and a step-up operation mode. Regarding technology.

  With the widespread use of portable devices having various functions, an effective power saving solution for extending battery life has become an important issue.

  In Non-Patent Document 1 below, a single inductor buck-boost converter is suitable for realizing a cost-effective integrated solution with a small number of inductors and capacitance, although it is complicated. It is described as being suitable. Non-Patent Document 1 below describes the design and implementation of an integrated circuit (IC) of a dual-mode, buck-boost (step-down / boost) converter that achieves high efficiency under a wide load condition. This converter is designed as a dynamic adaptive power supply for RF power amplifier (PA) in code division multiple access (CDMA) mobile phones.

A smoothing inductor is connected to two external terminals of an integrated circuit (IC) described in Non-Patent Document 1 below, and a smoothing capacitor is connected between the output terminal of the integrated circuit and a ground potential. Four switches for buck-boost are formed inside the integrated circuit. The four switches include a first P-channel MOS transistor (hereinafter referred to as PMOS), a first N-channel MOS transistor (hereinafter referred to as NMOS), a second PMOS, and a second NMOS. A first PMOS is connected between the battery voltage _VIN and one end of the smoothing inductor, and a first NMOS is connected between one end of the smoothing inductor and the ground potential. A second PMOS is connected between the other end of the smoothing inductor and the output terminal, and a second NMOS is connected between the output terminal and the ground potential. In the buck (buck) mode, the output terminal voltage is generated by the on / off operation of the first PMOS and the first NMOS, and in the boost (boost) mode, the second PMOS and the second NMOS are turned on / off. In operation, a voltage at the output terminal is generated. The integrated circuit (IC) includes an error amplifier and two voltage comparators, the input of the error amplifier being responsive to the voltage at the output terminal. The two voltage comparators are supplied with the output of the error amplifier and a triangular wave for pulse width modulation (PWM).

  Non-Patent Document 2 below describes an integrated synchronous buck-boost DC / DC converter for an RF power amplifier (PA) for WCDMA applications similar to the buck-boost converter described in Non-Patent Document 1 below. Is described. The integrated internal circuit of the integrated DC / DC converter described in Non-Patent Document 2 below is also similar to the internal circuit of the converter integrated circuit described in Non-Patent Document 1 below.

Two voltage-dividing resistors connected in series are connected between the output terminal of the integrated DC / DC converter described in Non-Patent Document 2 below and the ground potential. The connection node of the two voltage dividing resistors is connected to the inverting input terminal of the error amplifier via the feedback terminal, and a reference voltage of 1.22 volts is supplied to the non-inverting input terminal of the error amplifier. The two voltage comparators are supplied with the output of the error amplifier and a triangular wave for pulse width modulation (PWM). By supplying a battery voltage V _IN of 2.7 to 5.5 volts, an output voltage V _{OUT in} the range of 0.5 to 5.0 volts can be generated.

A control voltage V _CONTROL from the output of the digital-to-analog converter (DAC) is supplied to the connection node of the two voltage _dividing resistors through the resistors. By changing the control voltage V _CONTROL from a high level of 2.36 volts to a low level of 0.28 volts, the output voltage _VOUT changes from a low level of 0.8 volts to a high level of 4.2 volts. It is. Further, when the control voltage V _CONTROL is increased from 0.5 volt to 2.5 volt, the output voltage V _OUT is reduced from approximately 4.2 volt to 0.5 volt in inverse proportion. High-speed error amplifier and integrated loop compensation circuit change voltage level for RF power amplifier from standby to transmit and transmit to standby in less than 25μs, reducing output overshoot and undershoot It is intended to provide the fast transition response necessary to do this.

Biranchinath Sahu et al, “A High-Efficiency, Dual Mode, Dynamic, Buck-Boost Power Supply IC for Portable Applications”, Proceedings of the 18th International Conference on VLSI Design, 3-7 Jan 2005, PP. 858 ~ 861, Product name LTC3444 Data sheet “LTC3444 Micropower Synchronous Buck-Boost DC / DC Converter for WCDMA Applications” pp. 1-10, Linear Technology Corporation, California, USA, http: // pdf. chinaecnet. com / pdf1 / pdf. newpro2005 / Linear / 3444. pdf [Search March 20, 2007]

  Prior to the present invention, the inventors engaged in the development of an integrated DC / DC converter mounted on an RF power amplifier module of a multiband transmission system such as a GSM system or a mixed installation of a GSM system and a CDMA system.

As described in Non-Patent Document 2, this integrated DC / DC converter also needs to generate an output voltage V _OUT that is equal to, higher than, or lower than the supplied battery voltage V _IN. is there.

The buck function of the integrated buck-boost (step-down / boost) DC / DC converter mounted on the RF power amplifier module adds power by lowering the collector / drain voltage of the power transistor when transmitting low transmission power. Effective to improve efficiency (PAE). Further, the boosting function of this converter is effective when transmitting a high transmission power because the output voltage _VOUT can be increased when the battery voltage _VIN decreases due to the battery life.

  In both the step-down and step-up cases, the on / off operation of the four switches connected to the smoothing inductor increases the voltage due to the accumulation of the electromagnetic energy of the smoothing inductor and the release of the energy of the inductor by charging the smoothing capacitor. Conversion efficiency can be realized. Further, in both cases of step-down and step-up, the feedback voltage by the two voltage dividing resistors of the output voltage of the DC / DC converter is compared with the reference voltage by the error amplifier, so that the output voltage of the DC / DC converter is It is maintained at a stable voltage.

However, the consumption current of the RF power amplifier, which is the output load of the integrated buck-boost (step-down / boost) DC / DC converter mounted on the RF power amplifier module, varies greatly depending on the transmission power level from the RF power amplifier. For example, when a user of a mobile phone having a built-in RF power amplifier module moves at a high speed to a place where the radio wave environment is not good due to movement by transportation such as an automobile, the transmission power level from the RF power amplifier is increased at a high speed. There must be. However, the voltage between the terminals of the smoothing inductor increases due to a sudden increase in current consumption supplied from the DC / DC converter to the RF power amplifier, and the output voltage V _{OUT of the} converter supplied to the RF power amplifier that is the output load is It will decline temporarily. A temporary decrease in the output voltage V _OUT causes a decrease in the transmission power level from the RF power amplifier. A decrease in the output voltage V _OUT of the converter is a decrease in the feedback voltage V _FB due to the voltage _dividing resistor. A decrease in the feedback voltage V _FB is detected by the error amplifier, and the temporarily decreased output voltage _VOUT returns to the value before the load condition. However, it has been clarified that wireless communication in a place where the radio wave environment is not good becomes difficult due to a decrease in the transmission power level of the RF power amplifier during this return time.

It has also been clarified that it is necessary to improve the switching between the step-down / low transmission power mode and the step-up / high transmission power mode and when switching from the step-up / high transmission power mode to the step-down / low transmission power mode. It was. That is, in the step-down / low transmission power mode, the high battery voltage _VIN is converted to a low power supply voltage by the step-down function of the DC / DC converter in order to improve the power added efficiency (PAE) when the RF power amplifier transmits low transmission power. And supply. In order to increase the transmission power of the RF power amplifier at a high speed from this state, it is necessary to quickly switch the DC / DC converter from the step-down operation to the step-up operation. Also, when the battery voltage V _IN drops due to the battery life, the RF power amplifier can transmit high transmission power by converting the low battery voltage V _IN into a high power supply voltage by the DC / DC converter boosting function and supplying it. It becomes possible. In order to reduce the transmission power of the RF power amplifier at a high speed from this state, it is necessary to quickly switch the DC / DC converter from the step-up operation to the step-down operation.

  The present invention has been made as a result of the study of the present inventors prior to the present invention as described above.

  Accordingly, an object of the present invention is to provide a DC / DC converter capable of shortening a recovery time from a temporary fluctuation of an output voltage due to a sudden fluctuation of a consumption current of a load.

  Another object of the present invention is to provide a DC / DC converter capable of improving the switching speed of the operation mode between the step-down operation mode and the step-up operation mode.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, in one typical DC / DC converter of the present invention, the error amplifier (EA) includes a first voltage comparator (CMP_H), a second voltage comparator (CMP_L), and a pull-up circuit (I _PU , SW _PU ) And a pull-down circuit (I _PD , SW _PD ) are connected. The feedback voltage (V _FB ) generated from the output voltage (V _OUT ) of the converter output terminal (T ₂ ) is higher than the first reference voltage (V _CNT + V _α ) or the second reference voltage (V _CNT −V _β The voltage (V _OE ) at the error amplification output terminal of the error amplifier (EA) is pulled down or pulled up (see FIGS. 1 and 4).

  In another typical DC / DC converter according to the present invention, the first controller (SW1) is used for the buck controller (101) for the step-down operation (Bck_Op) during the step-up operation (Bst_Op). The non-inverting input terminal, the inverting input terminal, and the output terminal of the one error amplifier (EA1) are maintained at the voltage level of the first intermediate reference voltage (Ref_Dn). During the step-down operation (Bck_Op), in the boost controller (102) for the step-up operation (Bst_Op), the second switch (SW2) causes the non-inverting input terminal, the inverting input terminal, and the output terminal of the second error amplifier (EA2). Is maintained at the voltage level of the second intermediate reference voltage (Ref_Up) (see FIGS. 5, 6, and 7).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to one exemplary embodiment of the present invention, it is possible to shorten the recovery time from a temporary fluctuation of the output voltage due to a sudden fluctuation of the consumption current of the load.

  According to another exemplary embodiment of the present invention, it is possible to improve the operation mode switching speed between the step-down operation mode and the step-up operation mode.

<Typical embodiment>
First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A DC / DC converter (IC) according to a typical embodiment of the present invention includes a buck converter (11), a boost converter (12), and a controller (10).

An input voltage (V _IN ) can be supplied to the input terminal (T ₁ ) of the buck converter (11), and the output node (T ₆ ) of the buck converter (11) and the input node of the boost converter (12) ( A smoothing inductor (L ₁₂ ) can be connected to T ₇ ).

The buck converter (11) includes a first switch (MP ₁ ) connected between the input terminal (T ₁ ) and the output node (T ₆ ), the output node (T ₆ ), and a ground voltage. A second switch (MN ₁ ) connected to (GND), and a back driver (110) for driving the first switch (MP ₁ ) and the second switch (MN ₁ ). .

The boost converter (12) includes a third switch (MP ₂ ) connected between the input node (T ₇ ) and an output terminal (T ₂ ), the input node (T ₇ ), and a ground voltage ( a fourth switch connected between the GND) (MN _2), comprising a third switch (MP ₂₎ and said fourth switch (MN ₂₎ drives the boost driver (120).

The controller (10) includes an error amplifier (EA), a pulse control circuit (CMP1, CMP2, OSC, 100), a first voltage comparator (CMP_H), a second voltage comparator (CMP_L), and a pull-up A circuit (I _PU , SW _PU ) and a pull-down circuit (I _PD , SW _PD ) are included.

The error amplifier (EA) is responsive to a control input voltage (V _CNT ) and a feedback voltage (V _FB ) generated from the output voltage (V _OUT ) of the output terminal (T ₂ ), and an error amplification output terminal An error amplification output voltage (V _OE ) is generated.

The pulse control circuit (CMP1, CMP2, OSC, 100) responds to the error amplification output voltage (V _OE ) generated from the error amplifier (EA), and the back driver (110) and the boost driver ( 120) is controlled.

The feedback voltage (V _FB ) can be supplied to one input terminal of the first voltage comparator (CMP_H), and the control input voltage (V _CNT ) is supplied to the other input terminal of the first voltage comparator (CMP_H). ) Higher than the first reference voltage (V _CNT + V _α ).

The feedback voltage (V _FB ) can be supplied to one input terminal of the second voltage comparator (CMP_L), and the control input voltage (V _CNT ) is supplied to the other input terminal of the second voltage comparator (CMP_L). ) Lower than the second reference voltage (V _CNT −V _β ).

When the feedback voltage (V _FB ) becomes higher than the first reference voltage (V _CNT + V _α ), the pull-down circuit (I _PD , SW _PD ) responds to the output of the first voltage comparator (CMP_H). The voltage at the error amplification output terminal is pulled down.

When the feedback voltage (V _FB ) is lower than the second reference voltage (V _CNT −V _β ), in response to the output of the second voltage comparator (CMP_L), the pull-up circuit (I _PU , SW _PU ) Pulls up the voltage of the error amplification output terminal (see FIGS. 1 and 4).

  According to the embodiment, it is possible to shorten the recovery time from the temporary fluctuation of the output voltage due to the sudden increase in the current consumption of the load by the operation of the pull-down circuit and the pull-up circuit.

  In the DC / DC converter according to a preferred embodiment, the buck converter (11), the boost converter (12), and the controller (10) are integrated in a semiconductor integrated circuit (IC) constituting the DC / DC converter. It has become.

In a DC / DC converter according to a more preferred embodiment, the first switch (MP ₁ ) of the buck converter (11) and the third switch (MP ₂ ) of the boost converter (12) are P It is a channel MOS transistor. Further, the second switch (MN ₁ ) of the buck converter (11) and the fourth switch (MN ₂ ) of the boost converter (12) are N-channel MOS transistors.

In a specific embodiment, the output voltage (V _OUT ) of the output terminal (T ₂ ) is an operating power supply voltage of an RF power amplifier mounted on a battery-operated mobile phone (FIG. 9).

In a most specific embodiment, the output voltage (V _OUT ) of the output terminal (T ₂ ) is an operating power supply voltage of a CPU or processor mounted on a battery-operated mobile device.

  [2] A DC / DC converter (IC) according to a representative embodiment of another aspect of the present invention includes a buck converter (11), a boost converter (12), and a controller (10).

An input voltage (V _IN ) can be supplied to the input terminal (T ₁ ) of the buck converter (11), and the output node (T ₆ ) of the buck converter (11) and the input node of the boost converter (12) ( A smoothing inductor (L ₁₂ ) can be connected to T ₇ ).

The buck converter (11) includes a first switch (MP ₁ ) connected between the input terminal (T ₁ ) and the output node (T ₆ ), the output node (T ₆ ), and a ground voltage. A second switch (MN ₁ ) connected to (GND), and a back driver (110) for driving the first switch (MP ₁ ) and the second switch (MN ₁ ). .

The boost converter (12) includes a third switch (MP ₂ ) connected between the input node (T ₇ ) and an output terminal (T ₂ ), the input node (T ₇ ), and a ground voltage ( a fourth switch connected between the GND) (MN _2), comprising a third switch (MP ₂₎ and said fourth switch (MN ₂₎ drives the boost driver (120).

  The controller (10) includes a buck controller (101) for the buck converter (11) and a boost controller (102) for the boost converter (12).

  The buck controller (101) includes a first switch (SW1), a first error amplifier (EA1), a first pulse control circuit (PWM1), and a first reference voltage generator (Ref_Dn).

  The boost controller (102) includes a second switch (SW2), a second error amplifier (EA2), a second pulse control circuit (PWM2), and a second reference voltage generator (Ref_Up).

During the step-down operation (Bck_Op) by the buck controller (101) and the buck converter (11), the first error amplifier (EA1) includes a control input voltage (V _CNT ) and the output terminal (T ₂ ). The first error amplification output voltage (V _OE _EA1) is generated in response to the feedback voltage (V _FB ) generated from the output voltage (V _OUT ).

During the step-down operation (Bck_Op), the first pulse control circuit (PWM1) is responsive to the first error amplification output voltage (V _OE _EA1) generated from the first error amplifier (EA1). By controlling the back driver (110), the output voltage (V _OUT ) by the step-down operation (Bck_Op) is generated from the output terminal (T ₂ ).

During the boost operation (Bst_Op) by the boost controller (102) and the boost converter (12), the second error amplifier (EA2) has the control input voltage (V _CNT ) and the output terminal (T _2). The second error amplification output voltage (V _{OE —} EA2) is generated in response to the feedback voltage (V _FB ) generated from the output voltage (V _OUT ).

During the boost operation (Bst_Op), the second pulse control circuit (PWM2) is responsive to the second error amplification output voltage (V _OE _EA2) generated from the second error amplifier (EA1). By controlling the boost driver (120), the output voltage (V _OUT ) by the boost operation (Bst_Op) is generated from the output terminal (T ₂ ).

During the boost operation (Bst_Op), from the first reference voltage generator (Ref_Dn) of the buck controller (101), the output voltage (V _OUT ) and the ground voltage (GND) by the boost operation (Bst_Op). A first intermediate reference voltage between is generated.

  During the step-up operation (Bst_Op), the first switch (SW1) causes the non-inverting input terminal, the inverting input terminal, and the output terminal of the first error amplifier (EA1) to be at the voltage level of the first intermediate reference voltage. Maintained.

During the step-down operation (Bck_Op), from the second reference voltage generator (Ref_Up) of the boost controller (102), the output voltage (V _OUT ) and the ground voltage (GND) by the step-down operation (Bck_Op). A second intermediate reference voltage between is generated.

  During the step-down operation (Bck_Op), the second switch (SW2) causes the non-inverting input terminal, the inverting input terminal, and the output terminal of the second error amplifier (EA2) to be at the voltage level of the second intermediate reference voltage. Maintained (see FIGS. 5, 6, and 7).

  According to the embodiment of the another aspect, the switching speed between the switching from the step-down operation mode to the step-up operation mode and the switching from the step-up operation mode to the step-down operation mode can be improved.

  In the DC / DC converter according to a preferred embodiment, during the step-up operation (Bst_Op), the non-inverting input terminal of the first error amplifier (EA1) is connected to the first intermediate reference by the first switch (SW1). Set to the voltage level of the voltage. During the boosting operation (Bst_Op), the first switch (SW1) connects the inverting input terminal and the output terminal of the first error amplifier (EA1). During the step-down operation (Bck_Op), the second switch (SW2) sets the non-inverting input terminal of the second error amplifier (EA2) to the voltage level of the second intermediate reference voltage. During the step-down operation (Bck_Op), the inverting input terminal and the output terminal of the second error amplifier (EA2) are connected by the second switch (SW2).

  In a DC / DC converter according to another more preferred embodiment, the controller (10) includes a step-down / step-up switch circuit (Hys_Cmp) that switches between the step-up operation (Bst_Op) and the step-down operation (Bck_Op). Including. The first switch (SW1) of the buck controller (101) and the second switch (SW2) of the boost controller (102) are controlled by the output of the step-down / boost switch circuit (Hys_Cmp).

In a DC / DC converter according to a more preferred embodiment, the step-down / boost switch circuit (Hys_Cmp) is supplied with a non-inverting input terminal to which the feedback voltage (V _FB ) is supplied and the control input voltage (V _CNT ). And an inverting input terminal.

  In a DC / DC converter according to another even more preferred embodiment, the buck controller (101) is connected between the output of the first pulse control circuit (PWM1) and the input of the buck driver (110). The first gate circuit (NAND) is included. The boost controller (102) includes a second gate circuit (NOR) connected between the output of the second pulse control circuit (PWM2) and the input of the boost driver (120).

  During the step-up operation (Bst_Op), the output of the step-down / step-up switch circuit (Hys_Cmp) causes the back driver (110) from the output of the first pulse control circuit (PWM1) by the first gate circuit (NAND). Signal transmission to the input is prohibited.

  During the step-down operation (Bck_Op), from the output of the second pulse control circuit (PWM2) by the second gate circuit (NOR) by the output of the step-down / step-up switch circuit (Hys_Cmp), the boost driver (120) Signal transmission to the input is prohibited.

  In the DC / DC converter according to a specific embodiment, the buck converter (11), the boost converter (12), and the controller (10) are included in a semiconductor integrated circuit (IC) that constitutes the DC / DC converter. It is integrated.

In the DC / DC converter according to a more specific embodiment, the first switch (MP ₁ ) of the buck converter (11) and the third switch (MP ₂ ) of the boost converter (12) are: P-channel MOS transistor. Further, the second switch (MN ₁ ) of the buck converter (11) and the fourth switch (MN ₂ ) of the boost converter (12) are N-channel MOS transistors.

In another more specific embodiment, the output voltage (V _OUT ) of the output terminal (T ₂ ) is an operating power supply voltage of an RF power amplifier mounted on a battery-operated mobile phone. Yes (see FIG. 9).

In a most specific embodiment, the output voltage (V _OUT ) of the output terminal (T ₂ ) is an operating power supply voltage of a CPU or processor mounted on a battery-operated mobile device.

<< Description of Embodiment >>
Next, the embodiment will be described in more detail.

<< Configuration of Integrated DC / DC Converter According to First Embodiment >>
FIG. 1 is a diagram showing a configuration of an integrated DC / DC converter according to a first embodiment of the present invention mounted on an RF power amplifier module of a GSM transmission system.

The integrated DC / DC converter of FIG. 1 is composed of an integrated circuit (IC). When the input voltage V _{IN in} the voltage range of 2.3 to 4.7 volts is supplied from the lithium ion battery BT to the input terminal T ₁ of the integrated DC / DC converter, the output terminal T ₂ to 0.5 V is supplied. An output voltage V _{OUT in} the voltage range of ~ 5 volts is generated. A ground terminal T ₃ is connected to the ground potential, the control input terminal T ₄ is supplied to control input voltage V _CNT, the feedback voltage V _FB is supplied to the feedback terminal T _5. Between the terminal T _6, T ₇ is connected a smoothing inductor L _12, the shutdown control input terminal T ₈ is shutdown control input signal Shut_Down supplied. The input terminal T ₁ is connected an input smoothing capacitor C _IN, to the output terminal T ₂ is connected to the output smoothing capacitor C _{OUT. Two} voltage-dividing resistors R ₁ and R ₂ connected in series are connected between the output terminal T ₂ and the ground voltage. The feedback voltage V _{FB at} the connection node of the _two voltage _dividing resistors R ₁ and R ₂ is supplied to the feedback terminal T ₅ . The output voltage V _OUT from the output terminal T ₂ is supplied as a power supply voltage to an RF power amplifier (not shown). Note that by setting the resistance values of the _two voltage _dividing resistors R ₁ and R ₂ to the same value, the feedback voltage V _FB of the feedback terminal T ₅ becomes half of the voltage of the output voltage _VOUT of the output terminal T _2. Become. In addition, the two voltage dividing resistors R ₁ and R ₂ can be integrated inside an integrated circuit (IC) of an integrated DC / DC converter.

The integrated DC / DC converter (IC) of FIG. 1 includes a controller 10, a buck (step-down) converter 11, and a boost (step-up) converter 12. In response to the level of the control input voltage V _CNT of the control input terminal T _4, the controller 10, buck converter 11, a boost converter 12, the input voltage V _IN to the output terminal T ₂ of the input terminal T ₁ The output voltage is converted to _VOUT . Under the control of the controller 10, the level of the output voltage V _OUT at the output terminal T ₂ follows in direct proportion to the level of the control input voltage V _{CNT at} the control input terminal T ₄ . The level of the feedback voltage V _{FB at} the feedback terminal T ₅ follows the level of the output voltage V _{OUT at} the output terminal T ₂ .

As shown in the lower part of FIG. 1, the control input voltage _VCNT and the feedback voltage _VFB are supplied to the non-inverting input terminal + and the inverting input terminal − of the error amplifier EA of the controller 10. The error of the feedback voltage V _FB with respect to the control input voltage V _CNT is amplified by the error amplifier EA of the controller 10, and an error amplified output voltage V _OE is generated. The error amplification output voltage V _OE and the reference triangular wave signal of the triangular wave reference oscillator OSC are compared by the comparators CMP1 and CMP2, and the comparison output signals of the comparators CMP1 and CMP2 are supplied to the pulse width modulation control logic 100. The buck converter 11 and the boost converter 12 are controlled by a PWM output control signal of the pulse width modulation control logic 100 of the controller 10. When the integrated DC / DC converter (IC) of FIG. 1 converts the input voltage V _IN at the input terminal T ₁ into the output voltage V _OUT at the output terminal T ₂ , the levels of the feedback voltage V _FB and the output voltage V _OUT are It is accurately controlled by the level of the control input voltage V _CNT of the control input terminal T _4. The buck converter 11 includes a buck driver 110, a first PMOS (MP ₁ ), and a first NMOS (MN ₁ ), and the boost converter 12 includes a boost driver 120, a second PMOS (MP ₂ ), and a first PMOS (MP ₂ ). 2 NMOSs (MN ₂ ).

<< Step-Down Operation of Integrated DC / DC Converter According to First Embodiment >>
Input voltage V _IN of the voltage level of 4.0 volts from the battery BT of Lithium ions are supplied, the control input voltage V _CNT of the voltage level of the control input terminal T ₄ to 1.0 volts is assumed to be supplied. Accordingly, the buck converter 11 of the integrated DC / DC converter (IC) of FIG. 1 down-converts the 4.0 volt voltage level input voltage V _IN to the 2.0 volt voltage level output voltage _VOUT. To do. The voltage conversion rate of the PWM-controlled buck converter 11 is determined by the on period T _ON and the off period T _OFF . The on period T _ON is a period in which the first PMOS (MP ₁ ) of the buck converter 11 is on and the first NMOS (MN ₁ ) is off, and the off period T _OFF is the first period of the buck converter 11. This is a period in which the first PMOS (MP ₁ ) is off and the first NMOS (MN ₁ ) is on. The output voltage V _OUT by the PWM-controlled buck converter 11 becomes a value lower than the input voltage V _IN as shown in the following equation depending on the ON period T _ON and the OFF period T _OFF .

V _OUT = V _IN · T _ON / (T _ON + T _OFF ) (1) When the ON period T _ON and OFF period T _OFF are set to the same period, the input voltage V _IN is 4.0 volts. An output voltage V _{OUT at} a level of 2.0 volts, which is half of the output voltage, is generated.

During the step-down operation by the buck converter 11, the second PMOS (MP ₂ ) of the boost converter 12 is always kept on, and the output voltage _VOUT due to the step-down operation of the buck converter 11 is the output terminal. it can be fed to T _2.

<< Boosting Operation of Integrated DC / DC Converter According to First Embodiment >>
Input voltage V _IN of the voltage level of 2.0 volts from the battery BT of Lithium ions are supplied, the control input voltage V _CNT of the voltage level of the control input terminal T ₄ to 2.0 volts is assumed to be supplied. Accordingly, the boost converter 12 of the integrated DC / DC converter (IC) of FIG. 1 up-converts the input voltage V _IN at a voltage level of 2.0 volts to the output voltage V _OUT at a voltage level of 4.0 volts. To do. The voltage conversion rate of the PWM controlled boost converter 12 is determined by the _ON period T _ON and the OFF period T _OFF . The on period T _ON is a period in which the second NMOS (MN ₂ ) of the boost converter 12 is on and the second PMOS (MP ₂ ) is off, and the off period T _OFF is the first period of the boost converter 12. This is a period during which the second NMOS (MN ₂ ) is off and the second PMOS (MP ₂ ) is on. The output voltage V _OUT generated by the PWM-controlled boost converter 12 is higher than the input voltage V _IN by the _ON period T _ON and the OFF period T _OFF as shown in the following equation.

V _OUT = V _IN · (T _ON + T _OFF ) / T _OFF (2) Equation During the boost operation by the boost converter 12, the first PMOS (MP ₁ ) of the buck converter 11 is always on. is maintained, input voltage V _iN from the battery BT is supplied to one terminal of the smoothing inductor L _12.

<< Through Operation of Integrated DC / DC Converter According to First Embodiment >>
Supplied input voltage V _IN of the voltage level of approximately 3.6 volts from the battery BT of Lithium ions, the control input voltage V _CNT voltage level of approximately 1.8 volts is assumed to be supplied to the control input terminal T ₄ . Accordingly, the buck converter 11 and the boost converter 12 of the integrated DC / DC converter (IC) of FIG. 1 have an input voltage V _IN of approximately 3.6 volts and a voltage level of approximately 3.6 volts. _Performs voltage slew conversion to output voltage _VOUT .

_< Responding to a drop in output voltage V _OUT >
On the other hand, the integrated DC / DC converter (IC) shown in FIG. 1 has a stable output voltage by the voltage conversion operation by any one of the voltage down conversion, the voltage up conversion, and the voltage through conversion of the expression (2). _Assume that a temporary decrease in the output voltage V _OUT occurs due to a rapid increase in the consumption current of the RF power amplifier while V _OUT is being generated. A temporary decrease in the level of the feedback voltage V _FB due to a temporary decrease in the output voltage V _OUT is detected by the error amplifier EA, and the level of the error amplification output voltage V _OE increases. The ON period T _ON of the PWM control of the buck converter 11 becomes longer due to the rise in the level of the error amplification output voltage V _OE , and the output voltage V _OUT that has temporarily decreased can be raised.

To shorten the recovery time of the output voltage _VOUT , it is assumed that the voltage gain of the error amplifier EA is increased. However, if the voltage gain of the error amplifier EA is set higher than necessary, the phase margin of the negative feedback control loop is reduced. Thus, there is a problem that the negative feedback control loop becomes unstable.

_< Structure against decrease in output voltage _VOUT >
In the integrated DC / DC converter (IC) of FIG. 1, to avoid this problem, the controller 10 has two voltage comparators CMP_H, CMP_L, a pull-up current source I _PU , a pull-down current source I _PD , and a pull-up. A switch SW _PU and a pull-down switch SW _PD are included. The control input voltage V _CNT is applied to the non-inverting input terminal + of the two voltage comparators CMP_H and CMP_L, and one reference voltage V _CNT + V _α is applied to the inverting input terminal − of one voltage comparator CMP_H, The other reference voltage V _CNT −V _β is applied to the inverting input terminal − of the other voltage comparator CMP_L. Further, the control input voltage _VCNT is applied to the non-inverting input terminal + of the error amplifier EA, and the feedback voltage _VFB is applied to the inverting input terminal − of the error amplifier EA. A pull-up current source I _PU and a pull-up switch SW _PU are connected in series between the output voltage _VOUT as the power supply voltage level and the output terminal of the error amplifier EA, and the output terminal of the error amplifier EA and the ground voltage GND are connected. A pull-down switch SW _PD and a pull-down current source I _PD are connected in series between them.

2 shows an error amplifier EA, pull-up current source I _PU , pull-down current source I _PD , pull-up switch SW _PU , pull-down switch SW _PD and reference in the controller 10 of the integrated DC / DC converter (IC) of FIG. It is a figure which shows the structure of a voltage generator. The reference voltage generator includes a resistor R _3, R ₄ and diode-connected NMOS (QN ₀₎ and a diode-connected PMOS (QP _0), connection of the diode connected NMOS and (QN ₀₎ and a diode-connected PMOS (QP ₀₎ A control input voltage _VCNT is applied to the node. Resistor R ₃ and a diode connected NMOS (QN ₀₎ one of the reference voltage V _CNT + V _alpha from a connection node between is generated from the connection node between the diode-connected PMOS (QP ₀₎ and a resistor R ₄ other reference voltage V _CNT -V _β is generated. The error amplifier EA includes a differential pair NMOS (QN ₁ , QN ₂ ) and a constant current source NMOS (QN ₃ ). A diode-connected NMOS (QN ₄ ) is connected to the constant current source NMOS (QN ₃ ), and a bias current (I ₀ ) is supplied to the diode-connected NMOS (QN ₄ ). A current mirror load PMOS (QP ₁ , QP ₂ ) is connected to the differential pair NMOS (QN ₁ , QN ₂ ). The drain output signal of _one differential pair NMOS (QN ₁ ) drives the gate of the output PMOS (QP ₄ ) and the gate of the PMOS (QP ₅ ) as the pull-up current source _IPU , and the other differential pair NMOS The gate of the PMOS (QP ₃ ) is driven by the drain output signal of (QN ₂ ). PMOS (QP ₃₎ drain diode connected NMOS (QN ₅₎ is connected to the, NMOS as a gate and a pull-down current source I _PD output by the gate-source voltage of the diode-connected _{NMOS (QN 5) NMOS (QN} 6) The gate of (QN ₇ ) is driven. The gate of the NMOS (QN ₈ ) as the pull-down switch SW _PD is driven by the output signal of one voltage comparator CMP_H, and the output of the PMOS (QP ₆ ) as the pull-up switch SW _PU is driven by the output signal of the other voltage comparator CMP_L. The gate is driven. A resistor R ₅ and a capacitor C ₀ for phase compensation are connected in series between the gate and drain of the output PMOS (QP ₄ ).

_< Operation corresponding to decrease in output voltage _VOUT >
FIG. 3 is a diagram showing an operation of a general integrated DC / DC converter, and FIG. 4 is a diagram showing an operation of the integrated DC / DC converter shown in FIG.

As described above, it is assumed that the output voltage V _OUT is temporarily reduced due to a rapid increase in the consumption current of the RF power amplifier. A temporary decrease in the level of the feedback voltage V _FB due to a temporary decrease in the output voltage V _OUT is detected by the error amplifier EA, and the level of the error amplification output voltage V _OE increases as shown in FIG. The ON period T _ON of the PWM control of the buck converter 11 or the boost converter 12 becomes longer due to the increase in the level of the error amplification output voltage V _OE , and the output voltage _VOUT that has temporarily decreased is increased. Can not be set high unnecessarily voltage gain of the error amplifier EA, recovery time of output voltage V _OUT for the temporary increase in output voltage V _OUT having a reduced there is a problem that long.

On the other hand, in the operation of the integrated DC / DC converter of FIG. 1 shown in FIG. 4, the temporary decrease in the level of the feedback voltage V _FB due to the temporary decrease in the output voltage _VOUT is caused by the other voltage comparator. It is detected by comparing the other reference voltage V _CNT −V _β by CMP_L with the feedback voltage V _FB . As the feedback voltage V _FB drops below the other reference voltage V _CNT −V _β , the output of the other voltage comparator CMP_L changes from the high level to the low level. As a result, the PMOS (QP ₆ ) as the pull-up switch SW _PU is controlled to be turned on by the low level output signal of the other voltage comparator CMP_L, and the drain current of the PMOS (QP ₅ ) as the pull-up current source I _PU As a result, the level increase of the error amplification output voltage V _OE of the error amplifier EA is accelerated. Accordingly, the time during which the ON period T _ON of the PWM control of the buck converter 11 is lengthened is advanced, and the time during which the temporarily reduced output voltage _VOUT rises is also advanced.

Further, when the feedback voltage V _FB rises higher than one reference voltage V _CNT + V _α , the output of one voltage comparator CMP_H changes from low level to high level. As a result, the NMOS (QN ₈ ) as the pull-down switch SW _PD is turned on by the high level output signal of one voltage comparator CMP_H, and the drain current of the NMOS (QP ₇ ) as the pull-down current source I _PD The level drop of the error amplification output voltage V _OE of the error amplifier EA is accelerated. Accordingly, the time during which the ON period T _ON of the PWM control of the buck converter 11 is shortened is shortened, and the time during which the temporarily increased output voltage _VOUT is decreased is also shortened.

<< Configuration of Integrated DC / DC Converter According to Second Embodiment >>
FIG. 5 is a diagram showing a configuration of an integrated DC / DC converter according to the second embodiment of the present invention mounted on the RF power amplifier module of the GSM transmission system.

Compared to the integrated DC / DC converter of FIG. 1, the controller 10 of the integrated DC / DC converter of FIG. 5 includes a buck controller 101 for the buck converter 11 and a boost controller 102 for the boost converter 12. And a step-down / boost switch circuit (Hys_Cmp). The buck controller 101 includes a switch SW1 for step-down operation, an error amplifier EA1, a pulse width modulation control logic PWM1, a NAND circuit, and a reference voltage generator Ref_Dn. Similarly, the boost controller 102 includes a switch SW2 for a boost operation, an error amplifier EA2, a pulse width modulation control logic PWM2, a NOR circuit, a reference voltage generator Ref_Dn, and an inverter Inv. Two voltage-dividing resistors R ₁ and R ₂ connected in series are integrated in an integrated DC / DC converter (IC). The feedback voltage V _FB and the control input voltage V _CNT are respectively supplied to one pair of selection input terminals A of the switch SW1 for the step-down operation, and the other pair of selection input terminals B of the switch SW1 is a reference voltage generator. Ref_Dn is connected to the output terminal of the error amplifier EA1. A feedback voltage _VFB and a control input voltage _VCNT are respectively supplied to one pair of selection input terminals A of the switch SW2 for boosting pressure operation, and a reference voltage is generated at the other pair of selection input terminals B of the switch SW2. Ref_Up and the output terminal of the error amplifier EA2 are respectively connected.

The feedback voltage V _FB and the control input voltage V _CNT are respectively applied to the non-inverting input terminal + and the inverting input terminal − of the step-down / boost switch circuit (Hys_Cmp) configured by a hysteresis comparator. During the step-up operation, the reference voltage generator Ref_Dn of the buck controller 101 supplies the intermediate reference voltage Ref_Dn to the other selection input terminal B of the switch SW1 connected to the non-inverting input terminal + of the error amplifier EA1. . The intermediate reference voltage Ref_Dn is set to a level between the high level feedback voltage V _FB and the low level ground voltage GND. At this time, since the output terminal of the error amplifier EA1 is connected to the inverting input terminal − of the error amplifier EA1 through the switch SW1, the error output voltage V _OE _EA1 at the output terminal of the error amplifier EA1 is also at the level of the intermediate reference voltage Ref_Dn. Is maintained. During the step-down operation, the reference voltage generator Ref_Up of the boost controller 102 supplies the intermediate reference voltage Ref_Up to the other selection input terminal B of the switch SW2 connected to the non-inverting input terminal + of the error amplifier EA2. Yes. The intermediate reference voltage Ref_Up is also set to a level between the high level feedback voltage _VFB and the low level ground voltage GND. At this time, since the output terminal of the error amplifier EA2 is connected to the inverting input terminal − of the error amplifier EA2 through the switch SW2, the error output voltage V _OE _EA2 at the output terminal of the error amplifier EA2 is also at the level of the intermediate reference voltage Ref_Up. Is maintained.

<Operation for switching from step-up operation to step-down operation>
FIGS. 6A and 6B are diagrams showing the switching operation from the step-up operation Bst_Op to the step-down operation Bck_Op of the general integrated DC / DC converter and the integrated DC / DC converter shown in FIG. 5, respectively. .

While the integrated DC / DC converter in FIG. 5 is performing the boosting operation, both the output voltage V _OUT and the feedback voltage V _FB are maintained at stable values. When the integrated DC / DC converter of FIG. 5 is switched from the step-up operation to the step-down operation, the control input voltage _VCNT changes from a relatively high level to a relatively low level. As a result, the output terminal of the step-down / boost switch circuit (Hys_Cmp) configured by the hysteresis comparator changes from the low level “0” to the high level “1”. Accordingly, the step-down / boost switch circuit (Hys_Cmp) switches the switch SW1 of the buck controller 101 from the other selection input terminal B in the standby state to the one selection input terminal A in the active state. The step-down / boost switch circuit (Hys_Cmp) switches the switch SW2 of the boost controller 102 from one selection input terminal A in the active state to the other selection input terminal B in the standby state. At this time, since the error output voltage V _{OE —} EA1 at the output terminal of the error amplifier EA1 of the buck controller 101 is also maintained at the level of the intermediate reference voltage Ref_Dn, the buck controller 101 boosts as shown in FIG. It is possible to quickly shift from the standby state in operation to the step-down operation. Further, when the output terminal of the step-down / step-up switch circuit (Hys_Cmp) changes to high level “1”, the NAND circuit of the buck controller 101 inverts the output signal of the pulse width modulation control logic PWM1 and the buck converter 11 To the input of the back driver 110. However, since the output of the NOR circuit of the boost controller 102 is maintained at a low level “0”, the output signal of the pulse width modulation control logic PWM2 cannot be transmitted to the input of the boost driver 120 of the boost converter 12 .

In contrast, while the general integrated DC / DC converter is performing the boosting operation Bst_Op, the buck converter 11 is maintained in the standby state. While the buck converter 11 is maintained in the standby state, the feedback voltage V is applied to the inverting input terminal − and the non-inverting input terminal + of the error amplifier EA1 of the buck controller 101 of a general integrated DC / DC converter. _FB and a ground voltage GND at a low voltage level or an output voltage _VOUT at a high voltage level are applied. Therefore, during the boosting operation Bst_Op, the error output voltage V _{OE —} EA1 of the error amplifier EA1 of the buck controller 101 of a general integrated DC / DC converter is grounded at a low voltage level as shown in FIG. Maintained at voltage GND or output voltage _VOUT at high voltage level. When the operation of a general integrated DC / DC converter is switched from the step-up operation Bst_Op to the step-down operation Bck_Op, the control input voltage V _CNT at the intermediate voltage level is applied to the non-inverting input terminal + of the error amplifier EA1 of the buck controller 101. And the error output voltage V _{OE —} EA1 also changes to the intermediate voltage level. Since the error output voltage V _OE _EA1 is maintained at the ground voltage GND at the low voltage level or the output voltage _VOUT at the high voltage level, the error output voltage V _OE _EA1 reaches the intermediate voltage level of the error output voltage V _OE _EA1 as shown in FIG. The change time becomes longer.

<Switching operation from step-down operation to step-up operation>
FIGS. 7A and 7B are diagrams showing the switching operation from the step-down operation Bck_Op to the step-up operation Bst_Op of the general integrated DC / DC converter and the integrated DC / DC converter shown in FIG. 5, respectively. .

When the integrated DC / DC converter of FIG. 5 is switched from the step-down operation to the step-up operation, the control input voltage _VCNT changes from a relatively low level to a relatively high level. As a result, the output terminal of the step-down / boost switch circuit (Hys_Cmp) configured by the hysteresis comparator changes from the high level “1” to the low level “0”. Therefore, the step-down / boost switch circuit (Hys_Cmp) switches the switch SW2 of the boost controller 102 from the other selection input terminal B in the standby state to the one selection input terminal A in the active state, and switches the switch SW1 of the buck controller 101. Switching from one selection input terminal A in the active state to the other selection input terminal B in the standby state. At this time, since the error output voltage V _{OE —} EA2 at the output terminal of the error amplifier EA2 of the boost controller 102 is also maintained at the level of the intermediate reference voltage Ref_Up, the boost controller 102 steps down as shown in FIG. It is possible to quickly shift from the standby state of the operation to the step-up operation. Further, when the output terminal of the step-down / boost switch circuit (Hys_Cmp) changes to low level “0”, the NOR circuit of the boost controller 102 inverts the output signal of the pulse width modulation control logic PWM2 and the boost driver 120 Input. However, since the output of the NAND circuit of the buck controller 101 is maintained at the high level “1”, the output signal of the pulse width modulation control logic PWM1 cannot be transmitted to the input of the back driver 110 of the buck converter 11. .

In contrast, while the general integrated DC / DC converter is performing the step-down operation Bck_Op, the boost converter 12 is maintained in a standby state. While the boost converter 12 is maintained in the standby state, the feedback voltage V is applied to the inverting input terminal − and the non-inverting input terminal + of the error amplifier EA2 of the boost controller 102 of a general integrated DC / DC converter. _FB and a ground voltage GND at a low voltage level or an output voltage _VOUT at a high voltage level are applied. Therefore, during the step-down operation Bck_Op, the error output voltage V _{OE —} EA2 of the error amplifier EA2 of the boost controller 102 of a general integrated DC / DC converter is set to the low voltage level ground as shown in FIG. Maintained at voltage GND or output voltage _VOUT at high voltage level. When the operation of a general integrated DC / DC converter is switched from the step-down operation Bck_Op to the step-up operation Bst_Op, the control input voltage V _CNT at the intermediate voltage level is applied to the non-inverting input terminal + of the error amplifier EA2 of the boost controller 102. And the error output voltage V _{OE —} EA2 also changes to the intermediate voltage level. Since the error output voltage V _OE _EA2 is maintained at the low voltage level ground voltage GND or the high voltage level output voltage V _OUT , the error output voltage V _OE _EA2 reaches the intermediate voltage level of the error output voltage V _OE _EA2 as shown in FIG. The change time becomes longer.

<< Configuration of Integrated DC / DC Converter According to Third Embodiment >>
FIG. 8 is a diagram showing a configuration of an integrated DC / DC converter according to the third embodiment of the present invention mounted on the RF power amplifier module of the GSM transmission system.

  The integrated DC / DC converter of FIG. 8 includes the integrated DC / DC converter (high-speed switching between step-up operation and step-down operation) of FIG. 5 according to the second embodiment of the present invention and the first embodiment of the present invention. 1 is a combination of the integrated DC / DC converter of FIG. 1 (reduction of recovery time from temporary fluctuation of output voltage) according to the embodiment.

  With the integrated DC / DC converter of FIG. 8, the recovery time from the temporary fluctuation of the output voltage due to the sudden increase in the current consumption of the load is shortened, and when switching from the step-down operation mode to the step-up operation mode and the step-up operation It is possible to improve the switching speed when switching from the operation mode to the step-down operation mode.

<Cellular phone with RF power amplifier module for GSM transmission system>
FIG. 9 is a diagram showing a configuration of a mobile phone incorporating an RF power amplifier module of a GSM transmission system equipped with an integrated DC / DC converter according to the first, second or third embodiment of the present invention.

The antenna ANT receives an RF reception signal from the base station and outputs an RF transmission signal to the base station so that the mobile phone terminal device performs a reception operation from the base station and a transmission operation to the base station. This antenna ANT is connected to the RF power amplifier module (RF_PA_MD) 2. The RF power amplifier module (RF_PA_MD) 2 has an antenna switch (Ant_SW) 23. When the antenna switch 23 is connected to the upper side, an RF reception signal received by the antenna ANT is supplied to a reception filter (SAW) 24 using, for example, a surface acoustic wave device. The reception filter 24 passes the desired frequency signal and attenuates the interference frequency signal. On the other hand, when the antenna switch 23 is connected to the lower side, the antenna switch 23 is connected to the output of the transmission RF power amplifier (RF_PA) 22. Accordingly, an RF transmission signal from the antenna ANT to the base station is output by the RF power output of the transmission RF power amplifier (RF_PA) 22. The antenna switch 23 of the RF power amplifier module 2 is connected to the upper side in the time slot for the TDMA (time division multiple access) reception operation, and is connected to the lower side in the time slot for the transmission operation. The RF power amplifier module 2 includes the integrated DC / DC converter 21 according to the first, second, or third embodiment of the present invention described with reference to FIG. 1, FIG. 5, and FIG. The integrated DC / DC converter 21 supplies an output voltage V _OUT generated by voltage conversion of the input voltage V _IN from the battery BT to the transmission RF power amplifier 22 as a power supply voltage.

The RF reception signal output from the reception filter 24 of the RF power amplifier module 2 is supplied to the reception frequency down converter (Rx_Down_Conv) 31 of the RF analog signal processing integrated circuit (RFIC) 3. Since the reception RF local signal is supplied from the PLL frequency synthesizer (PLL_Synth) 33 to the reception frequency down converter 31, the reception baseband signal Rx_I / Q is generated from the reception frequency downconverter 31, and the baseband signal processing LSI (BaseBandLSI) Supplied to 4. Since the transmission baseband signal Tx_I / Q generated from the baseband signal processing LSI (4) and the transmission RF local signal from the PLL frequency synthesizer 33 are supplied to the transmission frequency upconverter (Tx_Up_Conv) 32, the transmission frequency upconverter From 32, an RF transmission signal is formed. The RF transmission signal is amplified by the transmission RF power amplifier 22 of the RF power amplifier module 2 and then transmitted from the antenna ANT to the base station via the antenna switch 23. A digital control signal is supplied from the baseband signal processing LSI (4) to the control circuit (Cntl) 34 and the digital-analog converter (DAC) 35 of the RFIC (3). A control input signal V _CNT from the shutdown control input signal Shut_Down and digital-to-analog converter 35 from the control circuit 34 is supplied to the integrated DC / DC converter 21 of the RF power amplifier module 2.

  The baseband signal processing LSI (4) is connected to the memory 5 and the application processor 6 via an external bus. The memory 5 includes an SRAM used as a work memory for the baseband signal processing LSI (4) and a non-volatile flash memory for storing an operation program for the baseband signal processing LSI (4). The operation program stored in the non-volatile flash memory is used for phase demodulation related to GSM reception baseband signals and phase modulation related to transmission baseband signals by a digital signal processor (DSP) in the baseband signal processing LSI (4). Including programs. The application processor 6 is connected to an external memory, a liquid crystal display device, and an operation key input device (not shown) via an external bus.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the integrated DC / DC converter according to the first, second, or third embodiment of the present invention described with reference to FIGS. 1, 5, and 8 described above is a CPU or audio of a mobile device that operates on a battery voltage. An operating power supply voltage can also be supplied to a multimedia processor LSI that processes signals and video signals. By adopting the integrated DC / DC converter according to the present invention, it is possible to shorten the recovery time from the temporary fluctuation of the operating power supply voltage due to the sudden fluctuation of the current consumption of the CPU or multimedia processor LSI. Further, by adopting the integrated DC / DC converter according to the present invention, it is possible to improve the switching speed between the switching from the step-down operation mode to the step-up operation mode and the switching from the step-up operation mode to the step-down operation mode. It becomes.

  Also, the pulse width modulation control logic 100 in FIG. 1 and the pulse width modulation control logics PWM1 and PWM2 in FIGS. 5 and 8 can be replaced with pulse frequency modulation control logic for controlling pulse frequency modulation (PFM).

FIG. 1 is a diagram showing a configuration of an integrated DC / DC converter according to a first embodiment of the present invention mounted on an RF power amplifier module of a GSM transmission system. FIG. 2 is a diagram showing a configuration of an error amplifier, a pull-up current source, a pull-down current source, a pull-up switch, a pull-down switch, and a reference voltage generator inside the controller of the integrated DC / DC converter of FIG. FIG. 3 is a diagram illustrating the operation of a general integrated DC / DC converter. FIG. 4 is a diagram showing an operation of the integrated DC / DC converter shown in FIG. FIG. 5 is a diagram showing a configuration of an integrated DC / DC converter according to the second embodiment of the present invention mounted on the RF power amplifier module of the GSM transmission system. FIG. 6 is a diagram showing a switching operation from the step-up operation to the step-down operation of the general integrated DC / DC converter and the integrated DC / DC converter shown in FIG. FIG. 7 is a diagram showing a switching operation from the step-down operation to the step-up operation of the general integrated DC / DC converter and the integrated DC / DC converter shown in FIG. FIG. FIG. 9 is a diagram showing a configuration of a mobile phone incorporating an RF power amplifier module of a GSM transmission system equipped with an integrated DC / DC converter according to the first, second or third embodiment of the present invention.

Explanation of symbols

BT battery
C _IN input smoothing capacity
T ₁ input terminal
V _IN input voltage
IC integrated DC / DC converter
10 Controller
11 Buck converter
110 Back driver
MP ₁ first PMOS
MN ₁ first NMOS
12 Boost converter
120 boost driver
MP ₂ 2nd PMOS
MN ₂ second NMOS
T ₂ output terminal
V _OUT output voltage
T ₃ Ground terminal
T ₄ Control input terminal
V _CNT control input voltage
T ₅ feedback terminal
V _FB feedback voltage
T ₆ terminal
T ₇ terminal
L ₁₂ smoothing inductor
R ₁ and R ₂ voltage dividing resistors
C _OUT output smoothing capacity
EA error amplifier
V _OE error amplification output voltage
CMP1, CMP2 comparator
100 pulse width modulation control logic
OSC Triangular wave reference oscillator
CMP_H, CMP_L Voltage comparator
V _CNT + V _α One reference voltage
V _CNT −V _{β The} other reference voltage
I _PU pull-up current source
I _PD pull-down current source
SW _PU pull-up switch
SW _PD pull-down switch
101 Buck controller
SW1 switch
EA1 error amplifier
PWM1 pulse width modulation control logic
NAND NAND circuit
Ref_Dn Reference voltage generator
102 Boost controller
SW1 switch
EA2 error amplifier
PWM2 pulse width modulation control logic
NOR NOR circuit
Ref_Up reference voltage generator
Hys_Cmp Buck / Boost switch circuit
ANT antenna
2 RF power amplifier module
21 DC / DC converter
22 RF power amplifier
23 Antenna switch
24 Receive filter
3 RF analog signal processing integrated circuit
31 Receive frequency down converter
32 Transmit frequency up-converter
33 PLL frequency synthesizer
34 Control circuit
35 Digital-to-analog converter
4 Baseband signal processing LSI
5 memory
6 Application processor

Claims (14)

With a buck converter, boost converter and controller,
An input voltage can be supplied to an input terminal of the buck converter, and a smoothing inductor can be connected between an output node of the buck converter and an input node of the boost converter,
The buck converter includes a first switch connected between the input terminal and the output node, a second switch connected between the output node and a ground voltage, and the first switch. A back driver for driving the second switch;
The boost converter includes a third switch connected between the input node and an output terminal, a fourth switch connected between the input node and a ground voltage, the third switch, and the Including a boost driver that drives a fourth switch;
The controller includes an error amplifier, a pulse control circuit, a first voltage comparator, a second voltage comparator, a pull-up circuit, and a pull-down circuit,
The error amplifier generates an error amplification output voltage at an error amplification output terminal in response to a control input voltage and a feedback voltage generated from the output voltage of the output terminal;
The pulse control circuit controls the buck driver and the boost driver in response to the error amplification output voltage generated from the error amplifier,
The feedback voltage can be supplied to one input terminal of the first voltage comparator, and a first reference voltage higher than the control input voltage can be supplied to the other input terminal of the first voltage comparator,
The feedback voltage can be supplied to one input terminal of the second voltage comparator, and a second reference voltage lower than the control input voltage can be supplied to the other input terminal of the second voltage comparator,
In response to the output of the first voltage comparator when the feedback voltage becomes higher than the first reference voltage, the pull-down circuit pulls down the voltage of the error amplification output terminal,
A DC / DC converter in which the pull-up circuit pulls up the voltage of the error amplification output terminal in response to the output of the second voltage comparator when the feedback voltage becomes lower than the second reference voltage.   The DC / DC converter according to claim 1, wherein the buck converter, the boost converter, and the controller are integrated in a semiconductor integrated circuit that constitutes the DC / DC converter. The first switch of the buck converter and the third switch of the boost converter are P-channel MOS transistors,
The DC / DC converter according to claim 2, wherein the second switch of the buck converter and the fourth switch of the boost converter are N-channel MOS transistors.   4. The DC / DC converter according to claim 3, wherein the output voltage of the output terminal is an operating power supply voltage of an RF power amplifier mounted on a battery-operated mobile phone.   4. The DC / DC converter according to claim 3, wherein the output voltage of the output terminal is an operating power supply voltage of a CPU or a processor mounted on a battery-operated mobile device. With a buck converter, boost converter and controller,
An input voltage can be supplied to an input terminal of the buck converter, and a smoothing inductor can be connected between an output node of the buck converter and an input node of the boost converter.
The buck converter includes a first switch connected between the input terminal and the output node, a second switch connected between the output node and a ground voltage, and the first switch. A back driver for driving the second switch;
The boost converter includes a third switch connected between the input node and an output terminal, a fourth switch connected between the input node and a ground voltage, the third switch, and the Including a boost driver that drives a fourth switch;
The controller includes a buck controller for the buck converter and a boost controller for the boost converter;
The buck controller includes a first switch, a first error amplifier, a first pulse control circuit, a first reference voltage generator,
The boost controller includes a second switch, a second error amplifier, a second pulse control circuit, a second reference voltage generator,
During the step-down operation by the buck controller and the buck converter, the first error amplifier is responsive to a control input voltage and a feedback voltage generated from the output voltage of the output terminal, and a first error amplification output Generate voltage,
During the step-down operation, the first pulse control circuit controls the buck driver in response to the first error amplification output voltage generated from the first error amplifier, thereby reducing the step-down from the output terminal. The output voltage due to operation is generated,
During the boosting operation by the boost controller and the boost converter, the second error amplifier is responsive to the control input voltage and the feedback voltage generated from the output voltage of the output terminal. Generate error amplified output voltage
During the boosting operation, the second pulse control circuit controls the boost driver in response to the second error amplification output voltage generated from the second error amplifier, thereby boosting the boost from the output terminal. The output voltage due to operation is generated,
During the boost operation, a first intermediate reference voltage between the output voltage and the ground voltage by the boost operation is generated from the first reference voltage generator of the buck controller,
During the step-up operation, the first switch maintains the non-inverting input terminal, the inverting input terminal, and the output terminal of the first error amplifier at the voltage level of the first intermediate reference voltage,
During the step-down operation, a second intermediate reference voltage between the output voltage and the ground voltage by the step-down operation is generated from the second reference voltage generator of the boost controller,
During the step-down operation, the second switch maintains a non-inverting input terminal, an inverting input terminal, and an output terminal of the second error amplifier at a voltage level of the second intermediate reference voltage by the second switch. During the boosting operation, the non-inverting input terminal of the first error amplifier is set to the voltage level of the first intermediate reference voltage by the first switch,
During the boosting operation, the inverting input terminal and the output terminal of the first error amplifier are connected by the first switch,
During the step-down operation, the non-inverting input terminal of the second error amplifier is set to the voltage level of the second intermediate reference voltage by the second switch,
The DC / DC converter according to claim 6, wherein the inverting input terminal and the output terminal of the second error amplifier are connected by the second switch during the step-down operation. The controller includes a step-down / step-up switch circuit that switches between the step-up operation and the step-down operation.
8. The DC / DC converter according to claim 7, wherein the first switch of the buck controller and the second switch of the boost controller are controlled by an output of the step-down / boost switch circuit.   9. The DC / DC converter according to claim 8, wherein the step-down / boost switch circuit includes a comparator having a non-inverting input terminal to which the feedback voltage is supplied and an inverting input terminal to which the control input voltage is supplied. The back controller includes a first gate circuit connected between an output of the first pulse control circuit and an input of the back driver;
The boost controller includes a second gate circuit connected between an output of the second pulse control circuit and an input of the boost driver;
During the step-up operation, the output of the step-down / step-up switch circuit prohibits signal transmission from the output of the first pulse control circuit by the first gate circuit to the input of the back driver,
10. The signal transmission from the output of the second pulse control circuit to the input of the boost driver by the second gate circuit is prohibited by the output of the step-down / boost switch circuit during the step-down operation). The DC / DC converter described in 1.   The DC / DC converter according to claim 10, wherein the buck converter, the boost converter, and the controller are integrated in a semiconductor integrated circuit that constitutes the DC / DC converter. The first switch of the buck converter and the third switch of the boost converter are P-channel MOS transistors,
12. The DC / DC converter according to claim 11, wherein the second switch of the buck converter and the fourth switch of the boost converter are N-channel MOS transistors.   13. The DC / DC converter according to claim 12, wherein the output voltage of the output terminal is an operating power supply voltage of an RF power amplifier mounted on a battery-operated mobile phone.   13. The DC / DC converter according to claim 12, wherein the output voltage of the output terminal is an operating power supply voltage of a CPU or a processor mounted on a battery-operated mobile device.

Images