JP2009033399A - Equalizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an equalizer capable of generating a clock phase from a node by shortening a delay time of a signal in a feedback route and making the node that succeeds in equalization exist. <P>SOLUTION: The equalizer includes: a signal determining device 3 for sequentially determining whether a data signal Sin is 0 or 1; a feedback circuit for generating a feedback signal S1_O(E) corresponding to the latest determination result by the signal determining device 3 and generating second feedback signals 2_E(O) and S3O(E) corresponding to respective past determination results from the latest determination result; and correcting parts 51(52) which is provided between a transmission path and the signal determining device 3 and have a first adder E1(O1) for correcting the data signal Sin on the basis of the second feedback signals S2_E(O) and S3O(E) and a second adder E2(O2) for correcting the data signal corrected by the first adder E1(O1) on the basis of the first feedback signal S1_O(E). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an equalizing apparatus that equalizes waveforms of input signals sequentially input via a transmission line.

  Conventionally, a data transfer technique that enables data communication between semiconductor elements such as IC chips has been used. In this data transfer technology, semiconductor elements are connected to each other through conductors such as cables and PC (Printed Circuit) boards, and data signals corresponding to “0” or “1” are sequentially transmitted using these conductors as transmission paths. Transferred.

  In these transmission lines, generally, high-frequency components included in the data signal are attenuated by the skin effect and dielectric loss of the conductor. For example, when high-speed data transfer such as 5 Gbps or 10 Gbps is performed on one transmission line (two in the case of differential signals), the Nyquist frequency (simply, half the data transfer rate, for example, data transfer) At 5 Gbps at 10 Gbps, the signal attenuation level exceeds 10 dB.

  Therefore, a method has been proposed in which the signal is waveform-equalized in consideration of such signal attenuation in the transmission path, that is, a data signal that is as close as possible to the data signal before attenuation is generated on the receiving circuit side. The following three methods are generally known as such methods.

  First, there is a method in which an A / D converter is provided in a receiving circuit, and a signal waveform is equalized when digital processing of the output signal is performed. Second, there is a method in which a signal is waveform-equalized by combining a high-pass filter in the receiving circuit and using an amplifier having a higher gain for a frequency with a greater attenuation in the signal path. Third, the data is subjected to 0/1 determination (determination of whether it is “0” or “1”), and the result is fed back to equalize the waveform of the signal. There is a method of using a decision circuit (DFE (Decision Feedback Equalizer)).

  As a typical example of the decision feedback equalization circuit used in the third method, for example, there is a circuit announced at ISSCC-2006 (see Non-Patent Document 1). This circuit feeds back signals corresponding to the respective determination results of the data signal up to five times (ie, five cycles before). This number of returning cycles is called a tap. That is, this circuit is a 5-tap circuit.

  In general, the upper limit of the operating frequency of the decision feedback equalizer is determined because the decision result of the input signal of each cycle is fed back to the input signal of the next cycle (hereinafter referred to as “Tap1”). This is the delay time.

  This will be described with reference to FIG. FIG. 7 is an explanatory diagram showing a circuit configuration of a general conventional decision feedback equalizer 100.

  As shown in FIG. 7, the conventional decision feedback equalizer 100 includes an adder 102, a signal determiner 103, flip-flop circuits 105 and 107, multipliers 104 and 106, and the like. A data signal and a feedback signal to be described later are input from the transmission path 101, and an adder 102 inputs a signal equalized in waveform by adding the feedback signal to the data signal to the signal determiner 103. The signal determiner 103 performs 0/1 determination in synchronization with the clock signal. The signal output from the signal determiner 103 is multiplied by the coefficient K1 by the multiplier 104 and output to the adder 102 as a feedback signal. The signal output from the signal determiner 103 is sequentially shifted by the plurality of flip-flop circuits 105 and 107 in synchronization with the clock signal, and the outputs of the flip-flop circuits 105 and 107 are also given a predetermined coefficient by the multiplier 106 and the like. The signals are multiplied by K2 or the like and input to the adder 102 as a feedback signal.

  The 0/1 determination by the signal determiner 103 is generally performed in the vicinity of the center of the cycle where the opening of the input signal is maximized as shown in FIG. At the timing shown).

  Since this determination result needs to be reflected in the output of the adder 102 in the next cycle, it is necessary to finish the feedback to the adder 102 by the timing indicated by the symbol T2 in FIG.

  Here, a case is considered in which a high-speed operation with a transfer speed of 10 Gbps is performed on the decision feedback equalizer 100 using, for example, a 90 nm size CMOS Process. At this time, one cycle is 100 ps, and therefore the time for completing the feedback to the adder 102 is 50 ps. However, since the output signal of the adder 102 has a small amplitude (50 mV to 100 mV differential), it is difficult to perform feedback between 50 ps.

  Thus, there is a decision feedback type equalizer that realizes an increase in transfer speed by using a method of performing an interleave operation or a method of performing speculative feedback.

  For example, Non-Patent Document 1 discloses an embodiment of a decision feedback type equalizer using an interleave operation (see Figure 4.1.3 of Non-Patent Document 1). In this embodiment, there are two sets of an even cycle processing circuit for performing even cycle data determination and an odd cycle processing circuit for performing odd cycle data determination, and the data determination is latched as a signal determiner. A circuit is used. When the timing T1 in FIG. 8 is an even cycle, for example, the next cycle is an odd cycle, so the determination result at the timing T1 is used in an odd cycle processing system circuit.

  At this time, since the data determination is performed by the latch operation by the latch circuit, feedback from the even cycle processing system to the odd cycle processing system can be started before the timing T1 (the latch circuit that performs the data determination is The transmission state is set before the timing T1, and the holding state is set after the timing T1). Therefore, the delay time of the signal in the feedback path can be shortened, and a time margin can be provided in the feedback loop.

  In practice, however, this alone is not sufficient for 10 Gbps data transfer in the 90 nm CMOS process. Therefore, the decision feedback type equalizer described in Non-Patent Document 1 uses a speculative feedback technique in addition to the interleave operation (see Figure 4.1.3 of Non-Patent Document 1). Here, speculative feedback means that there are only two combinations of Tap1 of “0” and “1”, so the data in both cases before the determination result of Tap1 is determined. The determination is performed, and later, when the result of Tap1 is found, the data corresponding to the result of Tap1 is selected.

  In the decision feedback type equalizer described in Non-Patent Document 1, two signal determiners are connected to the even-cycle processing system adder and the odd-cycle processing system adder, respectively, and the data of Tap1 is “0” or “ In order to cope with “1”, speculation is realized by supplying different comparison voltages to the two signal determination devices. In this technique, it is only necessary to be able to determine data before two cycles, so determination and feedback may be performed within two cycles (200 ps for 10 Gbps), and 10 Gbps operation is possible even with a 90 nm CMOS process.

  However, in the decision feedback type equalizer using speculative feedback, there remains a problem that there is no node that has been equalized as a side effect. In other words, speculative feedback means that there are two types of signal determiners connected to the adder as described above, one for data “0” and one for data “1”. For example, in a signal determiner for data of “1”, this means that equalization succeeds in one cycle and does not succeed in another cycle.

  Thus, in the technique using speculative feedback, since there is no completed node, as will be described below, the phase determination that is as important as the data determination is adversely affected.

  That is, in general, in a high-speed receiving circuit that receives a data signal of 10 Gbps, the phase variation of the clock signal caused by a temperature change or a voltage change in the circuit cannot be allowed. Therefore, an input data signal (hereinafter referred to as “input signal”) It is necessary to always adjust the phase to the optimum value for the input signal using the information of the above. However, in speculative feedback, since there is no node that has succeeded in equalization, information of the input signal cannot be used, and an optimal clock signal cannot be generated. If there is a node that has succeeded in equalization, the antinodes and nodes of the waveform are clearly separated, so that the phase of the clock signal can be optimized to the node that has succeeded in equalization. A technique for generating an optimal clock signal from a signal that has been successfully equalized is generally known as a clock data recovery circuit (for example, http: //bwrc.eecs.berkeley.Edu/ classes / ee290c_s04 / lectures.html Lecture15).

Thus, in speculative feedback, since there is no node that has succeeded in equalization, the antinodes and nodes of the waveform are not clear, and an optimal clock signal cannot be generated. Therefore, in the technology announced at ISSCC2006, simple equalization is performed in a phase detector separately from the decision feedback type equalizer.
ISSCC-2006 Digest, p-80, “A 10Gb / s 5-Tap-DFE / 4-Tap-FFE Transceiver in 90nm CMOS”

  As described above, the decision feedback type equalizer using speculative feedback can reduce the delay time of the signal in the feedback path, but an extra circuit such as an equalizer for the phase detector must be provided. Don't be. In addition, since the clock phase is generated by a signal that passes through a circuit different from the signal contained in the signal determiner, there is a possibility that the optimum clock phase may not be achieved.

  Therefore, the present invention can reduce the delay time of a signal in the feedback path without using speculative feedback technology, and can generate a clock phase from a node that has been successfully equalized. An object is to provide an equalization apparatus.

  In order to achieve the above object, an equalizer according to claim 1 is an equalizer for waveform equalizing an input signal sequentially input via a transmission line, and the input signal is zero. A signal determination unit that sequentially determines whether the signal is 1 or a signal corresponding to the latest determination result by the signal determination unit is generated as a first feedback signal, and corresponds to each past determination result from the latest determination result. A feedback circuit that generates a signal as a second feedback signal; a first arithmetic unit that is provided between the transmission line and the signal determination unit; and that corrects the input signal based on the second feedback signal; And a correction unit having a second calculator for correcting the input signal corrected by one calculator based on the first feedback signal.

  The equalization apparatus according to claim 2 is an equalization apparatus according to claim 1, wherein the signal output from the first arithmetic unit is amplified between the first arithmetic unit and the second arithmetic unit. And an amplifier for inputting to the second arithmetic unit.

  The equalizer according to claim 3 is the equalizer according to claim 1 or 2, wherein the amplifier has a non-linear amplification characteristic.

  The equalizer according to claim 4 is the equalizer according to any one of claims 1 to 3, wherein the signal determiner determines the even-numbered input signal. And a second signal determiner that determines the odd-numbered input signal, and the correction unit is provided between the transmission path and the first signal determiner, and the first arithmetic unit and the A first correction unit having a second arithmetic unit; and a second correction unit provided between the transmission line and the second signal determination unit, the first arithmetic unit and the second arithmetic unit. The feedback circuit outputs a first feedback signal corresponding to a latest determination result by the second signal determiner to a second calculation of the first correction unit when the even-numbered input signal is determined by the first signal determiner. The latest signal by the first signal determiner and the second signal determiner. From the result, a second feedback signal corresponding to a past determination result is input to the first computing unit of the first correction unit, and the first signal determination is performed when the second signal determination unit determines the odd-numbered input signal. The first feedback signal corresponding to the latest determination result by the detector is input to the second calculator of the second correction unit, and the past determination result by the first signal determiner and the second signal determiner is past. The second feedback signal corresponding to the determination result is input to the first calculator of the second correction unit.

  According to the present invention, the correction unit, which is provided between the transmission line and the signal determination unit and corrects the input signal based on the feedback signal, corresponds to the past determination result corresponding to each past determination result from the latest determination result. (2) a first arithmetic unit that corrects based on the feedback signal, and a second arithmetic unit that corrects the input signal corrected by the first arithmetic unit based on the first feedback signal corresponding to the latest determination result by the signal determiner Therefore, it is possible to minimize the load capacity with the arithmetic unit that feeds back the first feedback signal, thereby reducing the delay time of the signal in the feedback path and increasing the speed of the equalization apparatus. be able to. In addition, a node having succeeded in equalization can exist and a clock phase can be generated from the node.

  Also, an amplifier for amplifying the signal output from the first arithmetic unit and inputting it to the second arithmetic unit is provided between the first arithmetic unit and the second arithmetic unit, and the amplitude is reduced by the correction by the first arithmetic unit. By amplifying the input signal with an amplifier and inputting it to the second arithmetic unit, the operation of the signal decision unit can be increased, and the speed of the equalizer can be further increased.

  Moreover, since an amplifier having a high amplification factor and a nonlinear amplification characteristic can be used as the amplifier, it is easy to provide an amplifier between the first arithmetic unit and the second arithmetic unit.

  Further, by performing the interleaving operation, it is possible to further increase the speed of the equalizer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a schematic configuration of an equalization apparatus 1 according to an embodiment of the present invention. This equalization apparatus 1 is, for example, a decision feedback type waveform equalization apparatus (provided on the receiving side) for equalizing the waveform of a data signal serially transferred through a transmission line provided between two or more semiconductor elements ( A decision feedback equalizer). Data signals “0” or “1” serially transferred through the transmission path are sequentially input. Note that this data signal is actually a differential signal.

    As shown in FIG. 1, the equalization apparatus 1 according to the present embodiment determines the data of even-numbered signals among the data signals Sin input as input signals in order to improve the operating frequency. And a set of circuits (processing system indicated by Odd in FIG. 1) used for determination of odd-numbered input data and the like (a processing system indicated by Even in FIG. 1). It has a so-called interleave configuration. Hereinafter, in the equalization apparatus 1, a period in which even-numbered data is determined is referred to as “even-numbered cycle”, and a period in which odd-numbered data is determined is referred to as “odd-numbered cycle”. Further, the processing system indicated by Even in FIG. 1 is referred to as “even cycle processing system Even”, and the processing system indicated by Odd in FIG. 1 is referred to as “odd cycle processing system Odd”.

    In the equalization apparatus 1 according to the present embodiment, the first adder E1, O1 (corresponding to the first arithmetic unit) and the second adder E2, O2 (second) are respectively used for the even cycle processing system Even and the odd cycle processing system Odd. And a correction unit 5 having amplifiers E and O between the first adder E1 and O1 and the second adder E2 and O2. The apparatus 1 achieves high speed.

    That is, in the conventional equalization apparatus, as shown in FIG. 7, the data signal input using one adder 102 is fed back. However, in the equalization apparatus 1 in this embodiment, the signal determination unit is used. 3 is fed back to the first adder E1, O1 from the past determination results (Tap2_E, TapO_3, Tap2_O, TapE_3) than the latest determination results Tap1_O, Tap1_E. Return to 2 adders E2 and O2. That is, the second adders E2 and O2 that perform feedback of the latest determination results Tap1_O and Tap1_E by the signal determiner 3 do not perform addition of other Taps, and the second adders E2 and O2 that feed back Tap1_O and Tap1_E. By minimizing the load capacity, the speed is increased.

  Further, by providing an amplifier E and an amplifier O between the first adder E1 and the second adder E2 and between the first adder O1 and the second adder O2, respectively, the second adders E2 and O2 The output signal is given a sufficient amplitude so that the operation of the signal decision unit 3 composed of a latch circuit is made faster. This is because the latch circuit can be operated at high speed by giving the input signal a sufficient amplitude. For example, if the second adders E2 and O2 are composed of CMOS CML (Current Mode Logic) circuits, if a signal is input to the second adders E2 and O2 with an amplitude greater than or equal to a difference voltage of 200 mV, The signal output from the two adders E2 and O2 can have a sufficient amplitude. Therefore, the input signal corrected by the first adders E1 and O1 and having a reduced amplitude is amplified by the amplifiers E and O and input to the second adders E2 and O2, thereby speeding up the operation of the signal determiner 3. Yes.

  Hereinafter, the configuration and operation of the equalization apparatus 1 will be specifically described with reference to the drawings. As described above, the equalization apparatus 1 is configured by connecting the even cycle processing system Even and the odd cycle processing system Odd in parallel, and has a so-called interleave configuration.

  The even cycle processing system Even is configured by connecting a first correction unit 51 and latch circuits E3, E4, and E5 in series from the input side of the data signal Sin that is an input signal. The odd cycle processing system Odd is configured by connecting the second correction unit 52 and the latch circuits O3, O4, and O5 in series in order from the input side of the data signal Sin that is an input signal. In the present embodiment, the latch circuit E3 corresponds to the first signal determiner, and the latch circuit O3 corresponds to the second signal determiner. The latch circuits E4, E5, O4, and O5 constitute feedback circuits with multipliers 51a to 51c and 52a to 52c described later.

    The first correction unit 51 includes a first adder E1 as a first arithmetic unit, an amplifier E, and a second adder E2 as a second arithmetic unit, and the second correction unit 52 is a first arithmetic unit as a first arithmetic unit. 1 adder O1, an amplifier O, and a second adder O2 as a second computing unit.

    When the outputs of the latch circuits E3 to E5 are Tap1_E, Tap2_E, and Tap3_E, respectively, and the outputs of the latch circuits O3 to O5 are Tap1_O, Tap2_O, and Tap3_O, respectively, the latch circuits E3 to E5 and O3 to O5 have inputs. When the clock signal is low level, the input data passes through as it is, the input data is latched at the rising edge of the clock signal, and the input data is held while the clock signal is high level. The latch circuits E3, E5, and O4 receive a clock signal having a predetermined cycle from a clock generation circuit (not shown), and the latch circuits E4, O3, and O5 that are circled at the clock input unit include the latch circuits E3 and E3. An inverted clock signal of the clock signal input to E5 and O4 is input.

    In the even cycle processing system Even, the output Tap1_O of the latch circuit O3, which is the second signal determiner, is input to the second adder E2 as the first feedback signal through the multiplier 51c, and the output Tap2_E of the latch circuit E4 is input. Is input to the first adder E1 as the second feedback signal S2_E via the multiplier 51b, and the output Tap3_O of the latch circuit O5 is input to the first adder E1 as the second feedback signal S3_O via the multiplier 51a. Therefore, the data signal Sin is corrected by the first adder E1 and the second adder E2 based on the first feedback signal S1_O and the second feedback signals S2_E and S3_O. The multipliers 51a, 51b, and 51c are set with predetermined coefficients, respectively.

    Similarly, the odd cycle processing system Odd inputs the output Tap1_E of the latch circuit E3, which is the first signal determiner, to the second adder O2 as the first feedback signal S1_E via the multiplier 52c, and the latch circuit O4 The output Tap2_O is input to the first adder O1 as the second feedback signal S2_O via the multiplier 52b, and the output Tap3_E of the latch circuit E5 is input to the first adder O1 as the second feedback signal S3_E via the multiplier 52a. Thus, the data signal Sin input based on the first feedback signal S1_E and the second feedback signals S2_O and S3_E is corrected by the first adder O1 and the second adder O2. The multipliers 52a, 52b, and 52c are set with predetermined coefficients, respectively.

FIG. 2 shows a timing chart of signals in the equalizer 1. At the top of FIG. 2, there is a data signal Sin corresponding to serial bit data (..., D ₀ , D ₁ , D ₂ , D ₃ , D ₄ ,...) Input to the equalizer 1. It is shown. D ₀ , D ₁ , D ₂ , D ₃ , D ₄ ,... Correspond to either “0” or “1”, respectively. If the subscript value is an even number, it is the even-numbered data input, and if the subscript value is an odd-number, it is the odd-numbered data input. In the chart of FIG. 2, a period in which the signal level is indefinite is indicated by X.

  In FIG. 2, the clock signals input to the latch circuits E3, O4, E5 are shown next. An inverted signal of this clock signal is input to the latch circuits O3, E4, and O5.

  Next, the output SumE of the first correction unit 51 is shown. Next, the output Tap1_O of the latch circuit O3 input to the second adder E2 is shown. Next, the output Tap2_E of the latch circuit E4 input to the first adder E1 is shown. Next, the output Tap3_O of the latch circuit O5 that is input to the first adder E1 is shown. These Tap1_O, Tap2_E, and Tap3_O are used in the even cycle processing system as described above.

As shown in FIG. 1, the output Tap2_E of the latch circuit E4 is multiplied by a predetermined coefficient by the multiplier 51b, and is input to the first adder E1 as the second feedback signal S2_E. As shown in FIG. 2, Tap2_E is a signal corresponding to data before two cycles corresponding to a determination result one cycle before the latest determination result (one cycle before) by the signal determination unit 3 in an even cycle. For example, D ₋₂ ) with respect to D ₀ . In the first adder E1, a signal component corresponding to Tap2E is subtracted from the data signal Sin input from the outside. That is, the residual component of the data two cycles before is subtracted from the data signal Sin.

As shown in FIG. 1, a signal corresponding to the output Tap3_O of the latch circuit O5 is also input to the first adder E1. That is, the output Tap3_O of the latch circuit O5 is multiplied by a predetermined coefficient by the multiplier 51a and input as the second feedback signal S3_O. As shown in FIG. 2, this Tap3_O is a signal corresponding to the data before three cycles corresponding to the determination result two cycles before the latest determination result (one cycle before) by the signal determiner 3 in the even cycle. (For example, D _{−3 with} respect to D ₀ ). In the first adder E1, a signal component corresponding to Tap3_O is also subtracted from the data signal Sin input from the outside. That is, the residual component of the data three cycles before is also subtracted from the data signal Sin.

Further, as shown in FIG. 1, the output Tap1_O of the latch circuit O3 is multiplied by a predetermined coefficient by the multiplier 51c, and is input to the second adder E2 as the first feedback signal S1_O. In the second adder E2, a signal component corresponding to Tap1_O is subtracted from the signal output from the amplifier E. As shown in FIG. 2, Tap1_O is a signal (for example, D _{−1 with} respect to D ₀ ) corresponding to data of the previous cycle that is a signal corresponding to the latest determination result by the signal determiner 3 in the even cycle. It becomes. Therefore, in the even number cycle, the input data signal Sin is subtracted by the first adder E1 from the residual component of the data two or three cycles before, amplified by the amplifier E, and then one cycle by the second adder E2. The residual component of the previous data is subtracted.

  In FIG. 2, the output SumO of the second correction unit 52 is shown next. Further, the output Tap1_E of the latch circuit E3 input to the second adder O2 is shown next, and the output Tap2_O of the latch circuit O4 input to the first adder O1 is shown next. Next, the output Tap3_E of the latch circuit E5 input to the first adder O1 is shown. These Tap1_E, Tap2_O, and Tap3_E are used in the odd cycle processing system as described above.

As shown in FIG. 1, the output Tap2_O of the latch circuit O4 is multiplied by a predetermined coefficient by the multiplier 52b and input to the first adder O1 as the second feedback signal S2_O. As shown in FIG. 2, this Tap2_O is a signal corresponding to the data before two cycles corresponding to the determination result one cycle before the latest determination result (one cycle before) by the signal determiner 3 in the odd cycle. (e.g. D _-1 relative to _{D 1)} is. In the first adder O1, the signal component Tap2_O is subtracted from the data signal Sin input from the outside. That is, the residual component of the data two cycles before is subtracted from the data signal Sin.

Further, as shown in FIG. 1, the first adder O1 also receives a signal corresponding to the output Tap3_E of the latch circuit E5. That is, the output Tap3_E of the latch circuit E5 is multiplied by a predetermined coefficient by the multiplier 52a and input as the second feedback signal S3_E. As shown in FIG. 2, this Tap3_E is a signal corresponding to the data before three cycles corresponding to the determination result two cycles before the latest determination result (one cycle before) by the signal determiner 3 in the odd cycle. (For example, D _{-2 with} respect to D ₁ ). In the first adder O1, a signal component corresponding to Tap3_E is also subtracted from the data signal Sin input from the outside. That is, the residual component of the data three cycles before is also subtracted from the data signal Sin.

Further, as shown in FIG. 1, the output Tap1_E of the latch circuit E3 is multiplied by a predetermined coefficient by the multiplier 52c and input to the second adder O2 as the first feedback signal S1_E. In the second adder O2, a component corresponding to Tap1_E is subtracted from the data signal Sin input from the amplifier O. As shown in FIG. 2, Tap1_E, in odd cycle, (D ₀ relative to example D ₁₎ signal corresponding by the signal determination unit 3 to the latest determination result of the previous cycle the corresponding signal data and Become. Therefore, in the odd cycle, the input data signal Sin is subtracted by the first adder O1 from the residual component of the data two or three cycles before, amplified by the amplifier O, and then one cycle by the second adder O2. The residual component of the previous data is subtracted.

  Since it is configured in this way, in the even number cycle, the critical path of determination from the feedback of Tap1_E is the second adder E2 → the latch circuit E3 → the second adder O2 → the latch circuit O3 → the second adder E2. One loop is formed in two cycles (200 ps if 10 Gbps).

    Here, when the equalizer 1 is a 90 nm CMOS process, the standard delay time in the adder, amplifier, and signal determiner is about 20 ps, so two adders E1, E2 (O1, O2), 1 The feedback delay when the two amplifiers E (O) and the signal determination unit (latch circuit E3 (O3)) are connected in series is not a problem at all.

    Note that another stage of amplifier may be added between the second adder E2 (O2) and the signal determiner 3 in order to increase the input amplitude of the latch circuit E3 (O3) as a signal determiner. . This is because there is still a margin even if a delay time of about 20 ps is further added by the amplifier.

  FIG. 3A shows an example of the circuit configuration of the second adder E2, and FIG. 3B shows an example of the circuit configuration of the first adder E1. The second adder O2 has the same circuit configuration as that of the second adder E2, and the first adder O1 has the same circuit configuration as that of the first adder E1, and thus detailed description thereof is omitted.

  As shown in FIG. 3A, the second adder E2 according to the present embodiment employs a differential method, and an input data signal is also a differential signal. This differential signal is input to the two data signal lines L1 and L2 of the second adder E2. A data signal input unit 91 and one determination feedback input unit 92 are connected to the two data signal lines L1 and L2.

The data signal input unit 91 is provided with a constant current source 61 ₁ , NMOSs 62 ₁ and 63 ₁ , and resistors 64 ₁ and 65 ₁ . These constitute a data signal differential input circuit. The positive differential voltage signal D + of the data signals differentially amplified by the amplifier E is input to the gate voltage of the NMOS 62 ₁ . Further, the negative differential voltage signal D− of the data signal differentially amplified by the amplifier E is input to the gate voltage of the NMOS 63 ₁ . Therefore, a current I + flowing on the data signal line L1 and a current I− flowing on the data signal line L2 according to the voltage difference between the differential voltage signals D + and D− input to the NMOSs 62 ₁ and 63 ₁ are obtained. It is determined.

The decision feedback input unit 92 includes a constant current source 61 ₂ and NMOS pair circuits (62 ₂ , 63 ₂ ). The first signal obtained by multiplying the output Tap1_O (+, −) corresponding to the determined data “0” or “1” by the multiplier 51c is supplied from the latch circuit O3, which is the second signal determiner, via the multiplier 51c. The feedback signal S1_O (+, −) is fed back to the determination feedback input unit 92. The first feedback signal S1_O (+, −) is a differential signal having an amplitude of about 400 mV, for example. When this differential output signal is received, in the NMOS pair circuit (62 ₂ , 63 ₂ ), for example, if there is an input potential difference of about 400 mV, only one NMOS is turned on and the other NMOS is turned off. A current corresponding to the first feedback signal S1_O to be fed back flows into the data signal line (one of L1 and L2) connected to the NMOS that is turned on.

  Here, of the first feedback signal S1_O (+, −), the positive signal S1_O (+) is connected to the data signal line L2, and the negative signal S1_O (−) is connected to the data signal line L1. Has been. That is, the polarities of the differential voltage signal corresponding to the data signal applied to the data signal lines L1 and L2 and the differential output signal of the latch circuit O3 are reversed. Therefore, a current corresponding to the first feedback signal S1_O (+, −) flows through one of the data signal lines L1 and L2, and is subtracted from the current corresponding to the data signal. Thereby, the correction of the data signal using the output Tap1_O of the latch circuit O3 in the even cycle is realized.

Since the second adder E2 is thus configured, the NMOS for feeding back Tap2E and Tap3O from the plurality of latch circuits E4 and O5 is not arranged, and only the NMOSs 62 ₁ , 63 ₁ , 62 ₂ and 63 ₂ are provided. Therefore, the parasitic capacitance generated in the NMOS of the second adder E2 can be minimized, and the delay time of calculation by the second adder E2 can be shortened as much as possible.

  That is, in the conventional equalizer, a plurality of feedback signals are fed back to one adder, so it is necessary to provide the same number of circuits as the decision feedback input unit 92 as many as the number of feedback signals. The resulting parasitic capacitance increases. As a result, for example, when the input data is switched from “0” to “1”, it takes time until the output of the adder reaches a level corresponding to “1”, and the equalizer can be operated at high speed. There wasn't.

  On the other hand, in the equalization apparatus 1 of the present embodiment, as described above, since the parasitic capacitance generated in the second adder E2 is minimized, the input data is switched from “0” to “1”. In this case, since the time until the output of the adder reaches a level corresponding to “1” can be shortened, high-speed operation becomes possible.

  Further, as shown in FIG. 3B, the first adder E1 is a data having a structure similar to that of the data signal input unit 91 of the second adder E2 on the two data signal lines L3 and L4. The input unit 81 is connected to a first determination feedback input unit 82 and a second determination feedback input unit 83 that have the same structure as the determination feedback input unit 92 of the second adder E2.

The data input unit 81 includes a constant current source 71 _1, the NMOS 72 _1, 73 _1, resistors 74 _1, 75 ₁ are provided. In the data input unit 81, the differential voltage signals D + and D− of the data signal Sin input from the outside via the transmission path 2 are input to the gates of the NMOSs 72 ₁ and 73 ₁ , and are applied to the signal lines L3 and L4. , Currents corresponding to these differential voltage signals D + and D− flow in, respectively.

The first decision feedback input unit 82 includes a constant current source 71 _2, an NMOS pair circuit (72 _2, 73 ₂₎ comprises a second decision feedback input unit 83 includes a constant current source 71 ₃ And an NMOS pair circuit (72 ₃ , 73 ₃ ).

At each gate of the NMOS pair circuit (72 ₂ , 73 ₂ ) of the first determination feedback input unit 82, the second feedback signal S2_E (+) obtained by multiplying the output Tap2_E (+, −) of the latch circuit E4 by the multiplier 51b. ,-) Is fed back. Then, currents corresponding to the second feedback signal S2_E (+, −) flow into the signal lines L3 and L4, respectively.

At each gate of the NMOS pair circuit (72 ₃ , 73 ₃ ) of the second determination feedback input unit 83, a second feedback signal S3_O (+) obtained by multiplying the output Tap3_O (+, −) of the latch circuit O5 by the multiplier 51a. ,-) Is fed back. Then, currents corresponding to the second feedback signal S3_O (+, −) flow into the signal lines L3 and L4, respectively.

  As described above, the first adder E1 includes one data input unit 81 and two decision feedback input units 82 and 83, and the number of transistors increases as compared with the second adder E2. As shown in FIG. 2, the signals Tap2_E and Tap3_O, which are the sources of the signals S2_E and S3_O, are fed back sufficiently before the signal Tap1_O, and there is no problem in operating at high speed.

  In addition, in the equalizing apparatus 1, the output of the first adder E1 (O1) is amplified between the first adder E1 (O1) and the second adder E2 (O2), and the second adder E2 ( Since the amplifier E (O) to be input to O2) is provided, not only the calculation time by the second adder E2 (O2) can be further shortened, but also erroneous determination of the data signal by the signal determiner 3 can be prevented. Can do.

In the above description, the output Tap1_O (+, −) of the latch circuit O3 that is the second signal determiner is input to the determination feedback input unit 92 via the multiplier 51c. However, Tap1_O (+, −) is input. You may make it input into the direct determination feedback input part 92. FIG. In this case, the constant current source 61 ₂ to a variable current source, and the adjusted according to the current setting value (digital value). Similarly, the outputs Tap2_E (+, −) and Tap3_O (+, −) of the latch circuits E4 and O5 are input to the first and second determination feedback input units 82 and 83 via the multipliers 51b and 51a, respectively. However, Tap2_E (+, −) and Tap3_O (+, −) may be directly input to the first and second determination feedback input units 82 and 83, respectively. In this case, the constant current sources 71 ₂ and 71 ₃ are variable current sources and are adjusted according to the current set value (digital value).

  Here, as described above, a correction unit is configured by two adders and an amplifier provided between them, and an equalizing apparatus 1 that performs an interleave operation, and a conventional one that includes a correction unit by one adder and performs an interleave operation. Differences in signal waveforms from the conversion apparatus will be described with reference to FIGS. FIG. 4 is an explanatory diagram showing signal waveforms in a conventional equalizer, and FIG. 5 is an explanatory diagram showing signal waveforms in the equalizer 1 of the present embodiment. 4 and 5, the vertical axis represents the signal voltage V, and the horizontal axis represents the time axis t. The pulse waveform shown in the upper part of the figure is a waveform of a clock signal for operating the latch circuit.

  Also, here, as an example, the operation of the equalization apparatus when the data signal Sin is switched from “0” to “1” at time t0 and then the data signal “1” is continuously transmitted in the transmission side circuit. I will give a description. Note that the data signal Sin transmitted from the transmission side circuit is delayed in the transmission path, and the input of the equalizer starts to change between the times t0 and t1.

  As shown in FIG. 4, in the conventional equalization apparatus, when the voltage of the data signal Sin input between time t1 and time t2 changes, the output of the second adder E2 follows this data signal Sin. The SumE voltage changes.

  At this time, in the conventional equalizer, the voltage of SumE rises gently due to the parasitic capacitance of the adder. In addition, in this conventional equalization apparatus, since the signal components of all feedback signals are subtracted from the input data signal Sin, the amplitude of SumE input to the signal determination circuit is reduced.

  As a result, in the conventional equalization apparatus, the signal determiner may erroneously determine the value of the data signal Sin. That is, since the signal determiner latches SumE at the edge timing at which the clock signal switches to the high level and determines the value of the data signal, the change in SumE is gradual and the amplitude of SumE is small as described above. In this case, the output Tap1_E of the signal determiner does not transition at high speed, and at time t2, the voltage value of Tap1_E does not reach the threshold value Vth which is a reference for determining data as “1”, and is determined as “1”. In spite of this, there is a case where the data is erroneously determined to remain “0”.

  On the other hand, in the equalization apparatus 1 of this embodiment, since the parasitic capacitance of the adder is suppressed, the change in SumE can be made steep following the voltage increase of the data signal Sin, and Since the amplifier E is provided, the output of the first adder E1 can be amplified and the amplitude of the output SumE of the second adder E2 can be made larger than that of the conventional SumE as shown in FIG.

  For this reason, in this equalization apparatus 1, since the output Tap1_E of the latch circuit E3 that is the first signal determiner transitions at high speed, the voltage value of Tap1E is the reference for determining the data as “1” at time t2. It is possible to accurately determine that the threshold value Vth has been reached and the data has been switched from “0” to “1”.

  In this equalization apparatus 1, a nonlinear amplifier having nonlinear amplification characteristics is used as the amplifier E (O).

  When a linear amplifier is used as the amplifier E (O), it may be necessary to connect amplifiers in multiple stages because the amplification factor is low. However, this increases the delay time. Therefore, it is desirable to use a nonlinear amplifier having a high amplification factor as the amplifier E (O).

  When a nonlinear amplifier is used, distortion occurs, but this distortion is not a problem here. Hereinafter, the reason will be described with reference to FIG. Here, it is assumed that the amplifier E (O) is configured by a CML (Current Mode Logic) circuit, a differential signal output from the first adder E1 (O1) is amplified and output as a differential signal. .

  If equalization up to Tap2E (Tap2O) is correctly performed, the voltage of the signal input to the second adder E2 (O2) is only four. That is, when the n-th cycle data is set to Dn, when equalizing the n-th cycle, the set of the data Dn-1 of the (n-1) th cycle and Dn (Dn, Dn-1) = (1, 1 ), (1, 0), (0, 1), and (0, 0).

  For each combination, FIG. 6 schematically shows the state of subtraction in the second adder E2 (O2). The signal handled by the second adder E2 (O2) is a differential signal. In FIG. 6, DP is the voltage of the positive logic signal in the nth cycle output from the amplifier E (O), and DN is the amplifier E ( This is the voltage of the negative logic signal in the nth cycle output from O).

  When (Dn, Dn−1) = (1, 1), the highest potential is input to DP and the lowest potential is input to DN. The second adder E2 (O2) is a differential adder. In this case, the voltage of Vtap1 shown in FIG. 6 is subtracted from the voltage of DP. The output voltage is Vout shown in FIG. Hereinafter, the other three diagrams shown in FIG. 6 have the same meaning. In the case of a CML amplifier, even if it is non-linear, the amplification factor of the amplifier E (O) is the target in the vertical direction of the voltage. Therefore, the Tap1 voltage to be drawn is the same in any of the four cases. Therefore, the amplifier E (O) in FIG. 1 may be a nonlinear amplifier.

    As described above, according to the equalization circuit in the present embodiment, the correction unit that is provided between the transmission line and the signal determination unit and corrects the input signal based on the feedback signal, the input signal from the latest determination result. A first arithmetic unit that corrects based on a second feedback signal corresponding to each past determination result, and a first feedback signal that corresponds to the latest determination result by the signal determiner using the input signal corrected by the first arithmetic unit Therefore, the load capacity can be minimized by the arithmetic unit that feeds back the first feedback signal, thereby reducing the signal delay time in the feedback path. Thus, the speed of the equalizer can be increased. In addition, a node having succeeded in equalization can exist and a clock phase can be generated from the node.

  Also, an amplifier for amplifying the signal output from the first arithmetic unit and inputting it to the second arithmetic unit is provided between the first arithmetic unit and the second arithmetic unit, and the amplitude is reduced by the correction by the first arithmetic unit. By amplifying the input signal with an amplifier and inputting it to the second arithmetic unit, the operation of the signal decision unit can be speeded up, and the speed of the equalizer can be further increased.

  Moreover, since an amplifier having a high amplification factor and a nonlinear amplification characteristic can be used as the amplifier, it is easy to provide an amplifier between the first arithmetic unit and the second arithmetic unit.

  Further, by performing the interleaving operation, it is possible to further increase the speed of the equalizer.

1 is a diagram showing a schematic configuration of an equalization apparatus according to an embodiment of the present invention. It is a timing chart of the signal in the equalization apparatus of FIG. (A) is a figure which shows an example of the circuit structure of a 2nd adder, (b) is a figure which shows an example of the circuit structure of a 1st adder. It is explanatory drawing which shows the signal waveform in the conventional equalization apparatus. It is explanatory drawing which shows the signal waveform in the equalization apparatus of FIG. It is explanatory drawing about the amplifier of FIG. It is explanatory drawing which shows the circuit structure of the conventional equalization apparatus. It is explanatory drawing of the determination timing of the conventional equalization apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Equalizer 2 Transmission path 3 Signal determination device 5 Correction | amendment part 51 1st correction | amendment part 52 2nd correction | amendment part E, O Amplifier E3 1st signal determination device O3 2nd signal determination device E1, O1 1st adder (1st Arithmetic unit)
E2, O2 second adder (second computing unit)
S1_E, S1_O first feedback signal S2_E, S2_O, S3_E, S3_O second feedback signal

Claims (4)

An equalizer for waveform equalizing input signals sequentially input via a transmission line,
A signal determiner for sequentially determining whether the input signal is 0 or 1;
A feedback circuit that generates a signal corresponding to the latest determination result by the signal determiner as a first feedback signal, and generates a signal corresponding to each previous determination result as the second feedback signal from the latest determination result;
A first arithmetic unit that is provided between the transmission path and the signal determiner and corrects the input signal based on the second feedback signal; and the input signal corrected by the first arithmetic unit is the first arithmetic unit. And a correction unit including a second computing unit that performs correction based on the feedback signal.   The amplifier which amplifies the signal output from the said 1st computing unit and inputs it into the said 2nd computing unit between the said 1st computing unit and the 2nd computing unit is provided. Equalization device.   The equalization apparatus according to claim 2, wherein the amplifier has a non-linear amplification characteristic. The signal determiner is
A first signal determiner for determining an even-numbered input signal;
A second signal determiner for determining an odd-numbered input signal;
The correction unit is
A first correction unit provided between the transmission line and the first signal determination unit, the first correction unit including the first calculation unit and the second calculation unit;
A second correction unit that is provided between the transmission line and the second signal determination unit and includes the first arithmetic unit and the second arithmetic unit;
The feedback circuit is
When determining the even-numbered input signal by the first signal determiner, the first feedback signal corresponding to the latest determination result by the second signal determiner is input to the second calculator of the first correction unit, A second feedback signal corresponding to a past determination result from the latest determination result by the first signal determiner and the second signal determiner is input to the first calculator of the first correction unit;
When determining the odd-numbered input signal by the second signal determiner, the first feedback signal corresponding to the latest determination result by the first signal determiner is input to the second calculator of the second correction unit, A second feedback signal corresponding to a past determination result from the latest determination result by the first signal determination unit and the second signal determination unit is input to the first calculator of the second correction unit. The equalization apparatus of any one of 1-3.

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