JP2009020511A - Display control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To uniform the length of each wiring in a wiring area while suppressing the area increase of the wiring area. <P>SOLUTION: As an example of a display control circuit, an LCD driver for driving a liquid crystal panel comprises: a data register 1; a load register 2; a polarity switching circuit 3; level shifter circuits 4a, 4b; a positive electrode side gradation voltage generating circuit 5; a positive electrode gradation selecting circuit 6; a negative electrode side gradation voltage generating circuit 7; a negative electrode gradation selecting circuit 8; and an output circuit 9. The output circuit 9 is provided therein with not only an output buffer 12 but also the polarity switching circuit 3, and the output circuit 9 is arranged in proximity to an output pad 10 at the same pitch as the output pad 10. The first and second wiring areas 23, 24 are provided between the output circuit 9 and the positive (negative) gradation selecting circuits 6, 8. The wiring lengths of the respective wiring patterns in the first and second wiring areas 23, 24 are uniformed to make the wiring length as short as possible. The degradation of display quality due to dispersion in the propagation delay of signals is thereby prevented. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display control circuit capable of polarity switching and gradation control.

  An LCD (Liquid Crystal Display) driver that drives a liquid crystal panel tends to increase the number of wirings as the resolution and gradation of the liquid crystal panel increase. In particular, when the number of signal lines increases due to higher resolution, the number of output signal lines of the LCD driver also increases, the wiring area in the LCD driver increases, and the outer diameter of the LCD driver increases.

  Conventional LCD drivers have a circuit pitch from the data register to the output buffer narrower than the pitch of the output pad for high-density mounting, and the pitch is converted in the wiring area between the output buffer and the output pad. (See Patent Document 1).

  However, as the number of output signal lines increases, a large number of wiring patterns must be arranged in the wiring area between the output buffer and the output pad, which increases the wiring area and makes the length of each wiring uniform. This makes it difficult to cause variations in the amount of wiring delay, causing display unevenness.

Further, conventionally, another circuit (for example, a gradation voltage generation circuit) must be arranged in accordance with the pitch of the output buffer or output pad. The location of the output buffer and output pad is also limited, and the placement area in the chip cannot be used effectively.
JP 2004-212836 A

  The present invention provides a display control circuit capable of making the length of each wiring in the wiring region uniform while effectively using the arrangement region and suppressing an increase in the area of the wiring region.

According to one aspect of the present invention, (N + M) / 2 (N and M are positive even numbers) grayscale voltage generation circuits that convert input pixel data into grayscale voltages and output the grayscale voltages;
(N + M) / 2 is provided corresponding to each of the two gradation voltage generation circuits, and switches whether or not to output by switching the polarity of the gradation voltage output from the corresponding gradation voltage generation circuit (N + M). ) / 2 output circuits,
It is connected to each output terminal of the (N + M) / 2 output circuits, is arranged at a pitch substantially equal to the pitch of the (N + M) / 2 output circuits, and is arranged close to the corresponding output circuit (N + M). ) Output pads,
Between the (N + M) / 2 output circuits arranged along two opposing sides, the (N + M) / 2 grayscale voltage generation circuits are arranged in a line along the direction in which these output circuits are arranged. A semiconductor substrate,
Each of the (N + M) / 2 grayscale voltage generation circuits includes:
A positive-tone gradation selection circuit that generates a positive-polarity gradation voltage according to input pixel data;
A negative gradation selecting circuit that generates a negative gradation voltage corresponding to the input pixel data,
The (N + M) / 2 grayscale voltage generation circuits are arranged in the order of the first to N / 2th grayscale voltage generation circuits and the (N / 2 + 1) th to (N + M) / 2th levels. Arranged on the semiconductor substrate so that the arrangement order of the regulated voltage generating circuit is opposite to each other,
The semiconductor substrate is
First and second output region portions arranged along two opposing sides, wherein the (N + M) / 2 output circuits and the (N + M) output pads are arranged;
Provided between the first and second output region portions and the (N + M) / 2 gradation voltage generation circuits, respectively, and the first and second output region portions and the (N + M) / 2 pieces. There is provided a display control circuit characterized by comprising first and second wiring region portions in which wiring patterns for connecting the grayscale voltage generation circuit are arranged.

  According to the present invention, the length of each wiring in the wiring region can be made uniform, and the arrangement region can be used effectively, so that an increase in the area of the wiring region can also be suppressed.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Hereinafter, an LCD driver for driving a liquid crystal panel will be described as an example of a display control circuit according to the present invention.

  FIG. 1 is a block diagram showing a schematic configuration of an LCD driver according to an embodiment of the present invention.

  1 includes a data register 1, a load register 2, a polarity switching circuit 3, level shifter circuits 4a and 4b, a positive gradation voltage generation circuit 5, a positive gradation selection circuit 6, and a negative polarity side. A gradation voltage generation circuit 7, a negative gradation selection circuit 8, and an output circuit 9 are provided.

  The data register 1 latches pixel data on the data bus in order in synchronization with the clock signal. The load register 2 latches pixel data for a plurality of pixels in synchronization with the load signal. The polarity switching circuit 3 switches the polarity of the output signal of the load register 2.

  The positive-side gradation voltage generation circuit 5 generates a plurality of positive-side gradation voltages. For example, when 10-bit gradation display is performed, 1024 positive-side gradation voltages are generated. The positive gradation selection circuit 6 selects one of a plurality of positive gradation voltages based on the logic of the gradation selection signal. The negative side gradation voltage generation circuit 7 generates a plurality of negative side gradation voltages. The negative gradation selection circuit 8 selects one of a plurality of negative gradation voltages based on the logic of the gradation selection signal.

  The output circuit 9 includes a polarity switching circuit 11 and an output buffer 12, and two output buffers 12 are provided for each polarity switching circuit 11. The polarity switching circuit 11 switches the polarity of the voltage selected by the positive gradation selection circuit 6 and the polarity of the voltage selected by the negative gradation selection circuit 8 in conjunction with each other. The output buffer 12 adjusts the gain of the output voltage of the polarity switching circuit 11 and supplies it to the signal line in the liquid crystal panel.

  The polarity switching circuit 3 and the polarity switching circuit 11 in the output circuit 9 operate in conjunction with each other, and when one selects positive polarity, the other also selects positive polarity. By alternately switching the logic of the polarity signal, a positive gradation voltage is output from one of the two adjacent output buffers 12, and a negative gradation voltage is output from the other.

  The data register 1, the load register 2, the polarity switching circuit 3, the level shifter circuits 4a and 4b, the positive gradation selection circuit 6, and the negative gradation selection circuit 8 constitute a gradation voltage generation circuit 20. A plurality of output circuits 9 corresponding to the gradation voltage generation circuit 20 are arranged along the long side of the semiconductor substrate. For example, when the LCD driver has 720 output signal lines (for 240 pixels), 360 grayscale voltage generation circuits 20 are arranged in a row, and two long sides facing the semiconductor substrate are arranged on the outside thereof. 360 output circuits 9 are arranged along the line.

  Since each output circuit 9 is provided with two output buffers 12, the total number of output buffers 12 is 720. In the following, it is assumed that (N + M) / 2 (N and M are positive even numbers) gradation voltage generation circuits 20 are provided in the LCD driver.

  The (N + M) / 2 grayscale voltage generation circuits 20 are arranged in a line, but the arrangement order of the grayscale voltage generation circuits 20 from the first to the N / 2th, and (N / 2 + 1) The order of the gradation voltage generation circuits 20 from the 2nd to the (N + M) / 2nd is opposite to each other. This is one feature of the present embodiment.

  In addition to this, as shown in FIG. 1, pixel data IN1 to IN (N) input from the data bus are input sequentially from left to right, and pixel data IN (N + 1) to IN (N + M) are input from right to left. Are entered in order.

  FIG. 2A is a diagram showing the positional relationship among the output pad 10, the output circuit 9, and the gradation voltage generation circuit 20 on the semiconductor substrate. The output pad 10 is formed along two opposing long sides of the semiconductor substrate. First and second output regions 21 and 22 are provided in the vicinity of the output pad 10, and the first and second output regions 10 are provided inside the output pad 10. Wiring regions 23 and 24 are provided.

  The output circuit 9 and the output pad 10 are disposed in the first and second output areas 21 and 22. The gradation voltage generation circuit 20 is disposed between the first and second wiring regions 23 and 24. A wiring pattern that connects the positive (negative) gradation selection circuits 6 and 8 and the output circuit 9 in the gradation voltage generation circuit 20 is arranged in the first and second wiring regions 23 and 24.

  The pitch of the output buffers 12 arranged in the first and second output areas 21 and 22 is substantially equal to the pitch of the output pad 10, and the output buffer 12 is arranged close to the output pad 10. Yes.

  In FIG. 2A, the gradation voltage generation circuit 20 is disposed between the first and second wiring basins 23 and 24. However, the first and second wiring areas 23 and 24 have gradations. Since the voltage generation circuit 20 is formed in a different layer, the first and second wiring regions 23 and 24 and the grayscale voltage generation circuit 20 partially overlap each other as shown in FIG. Also good.

  As described above, this embodiment is characterized in that the output buffer 12 is disposed close to the output pad 10 and the wiring between the positive (negative) gradation selection circuits 6 and 8 and the output circuit 9 is routed.

  Further, the pitch of the gradation voltage generation circuit 20 is narrower than the pitch of the output buffer 12. As a result, the gradation voltage generation circuit 20 can be mounted at high density, and the display resolution can be improved without increasing the circuit scale.

  FIG. 3 is a schematic layout pattern diagram of the LCD driver according to the present embodiment, and FIG. 4 is an enlarged view of a part of FIG.

  As shown in FIG. 3, the LCD driver has two display control units 25 and 26 and one logic unit (logic circuit unit) 27. The two display control units 25 and 26 are arranged on both ends in the longitudinal direction of the semiconductor substrate, and the logic unit 27 is arranged between the display control units 25 and 26. The logic unit 27 generates various signals (for example, a polarity signal, a load signal, a clock signal, a data bus for supplying pixel data, an enable signal, etc.) used in the display control units 25 and 26.

  Each of the two display control units 25 and 26 has the same block configuration as that in FIG. 1, and each has, for example, 360 output signal lines. Eventually, the entire LCD driver has 720 output signal lines. The number of output signal lines is an example, and the number is not particularly limited.

  The output circuit 9 is disposed along two opposing long sides of the semiconductor substrate. An input pad 28 is disposed near the center of the long side close to the logic unit 27.

  FIG. 4 shows a layout pattern of the right half of the LCD driver. As shown in the figure, output circuits 9 and output pads 10 corresponding to 180 + 32 output signal lines are provided along one long side of the semiconductor substrate, and 148 lines are provided along the other long side. An output circuit 9 and an output pad 10 corresponding to the output signal lines are provided.

  In the output pad 10 arranged along one long side of the semiconductor substrate and the output pad 10 arranged along the other long side, the arrangement of the output signal lines is reversed. That is, on one long side, the output pad 10 and the output circuit 9 corresponding to the output signal lines OUT149 to OUT360 are sequentially arranged from right to left, whereas on the other long side, the left to right The output pad 10 and the output circuit 9 corresponding to the output signal lines OUT1 to OUT148 are sequentially arranged.

  The output circuit 9 corresponding to the output signal lines OUT149 to OUT360 is connected to the output terminal of the gradation voltage generation circuit 20 at a close position by a wiring pattern. This wiring pattern is disposed in the first wiring region 23 between the output circuit 9 and the gradation voltage generation circuit 20.

  Similarly, the output circuit 9 corresponding to the output signal lines OUT1 to OUT148 is connected to the grayscale voltage generation circuit 20 at a close position by a wiring pattern. This wiring pattern is disposed in the second wiring region 24 between the output circuit 9 and the gradation voltage generation circuit 20.

  An output pad 10 and an output circuit 9 corresponding to the output signal lines OUT149 to OUT180 are arranged on one long side of the semiconductor substrate. A wiring pattern between the output circuit 9 and the gradation voltage generation circuit 20 is as follows. , Extending to the other long side.

  FIG. 5 is a diagram illustrating an example of a wiring pattern that connects the output pad 10 and the output circuit 9 corresponding to the output signal lines OUT149 to OUT180. As illustrated, the wiring patterns are arranged so that the wiring patterns do not cross each other. With these wiring patterns, the first and second wiring regions 23 and 24 in FIG. 2 are connected along the short side of the semiconductor substrate.

  The wiring patterns in the first and second wiring regions 23 and 24 are arranged so that all the wiring lengths are uniform and the wiring length is as short as possible. More specifically, as shown in FIG. 5, each wiring pattern is zigzag-shaped, and the length of all wirings is made uniform by adjusting the number of times zigzag is performed.

  The circuit of the LCD driver of this embodiment is formed using a plurality of layers of a semiconductor substrate. For example, each circuit shown in FIG. 1 is laid out using the lower layer (which may be one layer or plural layers), and the uppermost layer is used as a wiring layer. In the uppermost layer, for example, the wiring patterns in the first and second wiring regions 23 and 24, the power supply pattern, and the ground pattern are formed.

  FIG. 6 is a layout pattern diagram showing an example of the uppermost layer. In FIG. 6, the wiring patterns 31 and 32 in the first and second wiring regions 23 and 24 are indicated by hatching, and the power supply pattern 33 and the ground pattern 34 are indicated by hatching. In FIG. 6, a wiring pattern group for connecting the output circuit 9 corresponding to the output signal lines OUT181 to OUT360 and the gradation voltage generation circuit 20 is arranged in the first wiring region 23, and the second wiring region 24 Includes a wiring pattern group connecting the output circuit 9 corresponding to the output signal lines OUT1 to OUT148 and the gradation voltage generation circuit 20, and the output circuit 9 and gradation voltage generation circuit 20 corresponding to the output signal lines OUT149 to OUT180. And a wiring pattern group for connecting the two.

  As shown in FIG. 6, the power supply pattern 33 and the ground pattern 34 are each formed in a wide pattern so as to surround the first and second wiring regions 23 and 24.

  Note that how to allocate the LCD driver circuits and wirings to a plurality of layers of the semiconductor substrate may be determined by comprehensively considering the circuit scale, the number of wirings, the wiring length, etc. FIG. 6 is merely an example. Absent.

  FIG. 6 illustrates an example in which the area of the display control unit 25 and the first and second wiring areas 23 and 24 partially overlap each other. However, as illustrated in FIG. May be.

  FIG. 7 is a schematic layout pattern diagram on the chip showing FIG. 4 in more detail. As shown in FIG. 7, in this embodiment, the pitch between the output circuit (AMP) 9 and the output pad 10 is made equal, and the distance between the output circuit 9 and the output pad 10 is shortened. Further, the pitch of the gradation voltage generation circuit 20 is made narrower than the pitch of the output circuit 9 and the output pad 10.

  A logic unit 27 is disposed at a substantially central portion of the chip, and a plurality of gradation voltage generation circuits 20 are disposed at narrow pitches on both sides in the long side direction with the logic unit 27 interposed therebetween. Between the 20 and the corresponding output circuit 9, first and second wiring regions 23 and 24 are provided.

  The pitch of the gradation voltage generation circuit 20 is converted into the pitch of the output circuit 9 by the first and second wiring regions 23 and 24. As described above, the pattern lengths of the wiring pattern groups in the first and second wiring regions 23 and 24 are adjusted to be equal length wiring.

  In the layout arrangement of FIG. 7, the input pad 28 is arranged along one side of the logic unit 27, and the output pad 10 is arranged along the opposite side. If the pitch between the gradation voltage generation circuit 20 and the output pad 10 is made equal, the output circuit 9 and the output pad 10 must be arranged in accordance with the arrangement location of the gradation voltage generation circuit 20. The output pad 10 cannot be disposed along the side of the logic unit 27, and the region where the output pad 10 is disposed is limited. However, according to the present embodiment, since the output pad 10 can be arranged along the side of the chip, the degree of freedom of arrangement of the output pad 10 is improved.

  Further, in this embodiment, since it is not necessary to arrange the gradation voltage generation circuit 20 in accordance with the pitch between the output circuit 9 and the output pad 10, the gradation voltage generation circuit 20 is mounted with high density as shown in FIG. In addition, since the degree of freedom of arrangement of the output circuit 9 and the output pad 10 is increased as described above, as a result, the number of output pads 10 that can be arranged on the long side output side of the chip can be increased. Can be reduced.

  In this embodiment, since the distance between the output circuit 9 and the output pad 10 is shortened, the display quality is not deteriorated due to the variation in the length of the output line of the output circuit 9.

  In the present embodiment, the first and second wiring regions 23 and 24 are provided between the grayscale voltage generation circuit 20 and the output circuit 9, but the first and second wiring regions 23 and 24 are provided. Since almost no current flows through the signal, signal propagation delay is unlikely to be a problem. In particular, since the delay in the output circuit 9 is larger than the signal propagation delay amount in the first and second wiring regions 23 and 24, the internal signal propagation delay in the first and second wiring regions 23 and 24 is reduced. The possibility of being visible from the outside as an output delay of IC characteristics is low. Therefore, even if the first and second wiring regions 23 and 24 are provided, the possibility of display quality deterioration is low.

  In FIG. 7, a plurality of dummy pads 13 are arranged along the short side direction of the chip. These dummy pads 13 are for adjusting the stress of the chip, do not transmit / receive signals, and are not essential components.

  Thus, in this embodiment, among the (N + M) / 2 number of gradation voltage generation circuits 20, the arrangement order of the gradation voltage generation circuits from the first to the N / 2th and the (N / 2 + 1) th number To (N + M) / 2, the order of arrangement of the gradation voltage generation circuits is reversed. Then, not only the output buffer 12 but also the polarity switching circuit 3 is provided in the output circuit 9, and the output circuit 9 is arranged close to the output pad 10 at the same pitch as the output pad 10, and the output circuit 9 and the gradation voltage generation circuit The first and second wiring regions 23 and 24 are provided between the first wiring region 20 and the second wiring region 23. Since little current originally flows between the gradation selection circuits 6 and 8 and the output circuit 9, no voltage drop occurs in the first and second wiring regions 23 and 24, and no signal deterioration occurs. . However, since the wiring capacity may increase, in this embodiment, the wiring length of each wiring pattern in the first and second wiring regions 23 and 24 is made uniform and the wiring length is made as short as possible. More specifically, the output circuit 9 is arranged along two long sides of the semiconductor substrate, and the arrangement order of the output signal lines is reversed with respect to the two long sides, whereby the first and second wiring regions are arranged. The wiring length in 23 and 24 is shortened. As a result, the display quality can be prevented from deteriorating due to variations in signal propagation delay, the areas of the first and second wiring regions 23 and 24 can be greatly reduced, and the short side direction of the semiconductor substrate can be shortened.

  In this embodiment, since the output circuit 9 is arranged only along the long side of the semiconductor substrate, it is not necessary to arrange the output circuit 9 along the short side, and all the transistors in the output circuit 9 are aligned. The electrical characteristics of the output circuit 9 can be made uniform.

  In the present embodiment, the wiring patterns in the first and second wiring regions 23 and 24 can be combined into one layer, and the layout layout of the circuit can be easily designed.

  In the above-described embodiment, the output circuit 9 is arranged along two opposing long sides of the semiconductor substrate. However, if there is a margin on the short side, the output circuit 9 is also arranged on the short side. May be. In this case, it is desirable to match the direction of the transistors in the output circuit 9 on the long side with the direction of the transistors in the output circuit 9 on the short side.

  In the embodiment described above, the number of output signal lines output from the LCD driver and the detailed circuit configuration in the LCD driver are not limited to those shown in FIG.

  In FIG. 6, different numbers of output circuits 9 are arranged along two opposing long sides of the semiconductor substrate, but the number of output circuits 9 arranged along each of the two long sides. May be the same or different. In FIG. 6, the first and second wiring regions 23 and 24 are formed in the same layer, but may be formed in a plurality of layers. Further, the wiring pattern and the power supply (grounding) pattern may be formed in separate layers.

  In FIG. 3, the two display control units 25 and 26 are arranged on both ends in the longitudinal direction of the semiconductor substrate. However, the number and location of the display control units 25 and 26 arranged on the same semiconductor substrate are not particularly limited.

1 is a block diagram showing a schematic configuration of an LCD driver according to an embodiment of the present invention. (A) And (b) is a figure which shows the positional relationship of the output pad 10, the output circuit 9, and the gradation voltage generation circuit 20 on a semiconductor substrate. 4 is a schematic layout pattern diagram of the LCD driver according to the present embodiment, and FIG. 4 is an enlarged view of a part of FIG. The figure which expanded a part of FIG. FIG. 4 is a diagram illustrating an example of a wiring pattern that connects an output pad 10 and an output circuit 9 corresponding to output signal lines OUT149 to OUT180. The layout pattern figure which shows an example of the uppermost layer. FIG. 5 is a schematic layout pattern diagram on a chip showing FIG. 4 in more detail.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data register 2 Load register 3 Polarity switching circuit 4a, 4b Level shifter circuit 6 Positive gradation selection circuit 8 Negative gradation selection circuit 9 Output circuit 10 Output pad 11 Polarity switching circuit 12 Output buffer 20 Gradation voltage generation circuit 21 1st Output region 22 Second output region 23 First wiring region 24 Second wiring region 25, 26 Display control unit 27 Logic unit 28 Input pad

Claims (5)

(N + M) / 2 (N and M are positive even numbers) grayscale voltage generation circuits that convert input pixel data into grayscale voltages and output them;
(N + M) / 2 is provided corresponding to each of the two gradation voltage generation circuits, and switches whether or not to output by switching the polarity of the gradation voltage output from the corresponding gradation voltage generation circuit (N + M). ) / 2 output circuits,
It is connected to each output terminal of the (N + M) / 2 output circuits, is arranged at a pitch substantially equal to the pitch of the (N + M) / 2 output circuits, and is arranged close to the corresponding output circuit (N + M). ) Output pads,
Between the (N + M) / 2 output circuits arranged along two opposing sides, the (N + M) / 2 grayscale voltage generation circuits are arranged in a line along the direction in which these output circuits are arranged. A semiconductor substrate,
Each of the (N + M) / 2 grayscale voltage generation circuits includes:
A positive-tone gradation selection circuit that generates a positive-polarity gradation voltage according to input pixel data;
A negative gradation selecting circuit that generates a negative gradation voltage corresponding to the input pixel data,
The (N + M) / 2 grayscale voltage generation circuits are arranged in order of the grayscale voltage generation circuits from the first to the N / 2th and from the (N / 2 + 1) th to the (N + M) / 2th. Arranged on the semiconductor substrate so that the arrangement order of the regulated voltage generating circuit is opposite to each other,
The semiconductor substrate is
First and second output region portions arranged along two opposing sides, wherein the (N + M) / 2 output circuits and the (N + M) output pads are arranged;
Provided between the first and second output region portions and the (N + M) / 2 gradation voltage generation circuits, respectively, and the first and second output region portions and the (N + M) / 2 pieces. A display control circuit comprising: first and second wiring region portions in which wiring patterns for connecting the grayscale voltage generation circuit are arranged. The semiconductor substrate has a plurality of layers,
The layer in which the first and second wiring region portions are formed is different from the layer in which the (N + M) / 2 gradation voltage generation circuits and the (N + M) / 2 output circuits are formed. The display control circuit according to claim 1. The first and second output region portions are formed along two opposing long sides of the semiconductor substrate,
The display control circuit according to claim 2, wherein a power pattern and a ground pattern are formed in a layer in which the first and second wiring region portions are formed. First and second display control units formed on both ends in the longitudinal direction of the semiconductor substrate;
A logic circuit unit formed between the first and second display control units,
Each of the first and second display control units includes the (N + M) / 2 gradation voltage generation circuits and the (N + M) / 2 output circuits,
4. The display control circuit according to claim 1, wherein the logic circuit section generates a control signal and a clock signal used in the first and second display control sections. An input pad formed along a central portion of the long side of the semiconductor substrate;
The display control circuit according to claim 1, wherein the output pad is disposed along a long side on both sides of the input pad.

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