JP2009016939A - Interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface circuit capable of constituting a logic control circuit by a simple circuit configuration while adopting a bipolar process. <P>SOLUTION: The interface circuit is provided with a flip flop circuit 9f and a logic control circuit 9s for switching an output logic and holding the switched output logic which are configured of bipolar processes. The logic control circuit 9s is configured by a differential pair wherein emitters of a first transistor in which a reference voltage is applied to a base and a second transistor in which a control voltage is applied to a base are connected to each other and, a constant current source CCS9 is connected to a connection node of the emitters through a switch Qs93 for switching or holding the output logic of the flip flop. The collector of the first transistor is connected to one input terminal of the flip flop circuit 9f, and the collector of the second transistor is connected to the other input of the flip flop circuit 9f. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a flip-flop circuit and an interface circuit that includes a logic control circuit that switches its output logic and holds the switched output logic, each of which is constituted by a bipolar process.

  As shown in FIG. 2, a flip-flop (the left side of the two-dot chain line in the figure) and a logic control circuit (the right side of the two-dot chain line in the figure) for changing the output state of the flip-flop and maintaining the state until the next update. When an interface circuit having a circuit) is configured by a bipolar process, a pair of wired OR circuits is generally formed in a single logic control circuit to generate a logic signal to be input to a flip-flop control terminal. .

  Such an interface circuit is used when a pull-up resistor or a pull-down resistor is connected to an external signal terminal input to a logic circuit such as a microcomputer for impedance matching or the like, and is flipped by a logic control circuit. A logic signal for controlling the output of the signal is generated. When the number of external signal systems increases, it is necessary to provide a plurality of flip-flops and a logic control circuit correspondingly.

On the other hand, in Patent Document 1, for the purpose of reducing idle current by switching switches, a differential pair that receives a signal voltage applied to an input pair differentially, an output pair of the differential pair, and a first A differential stage having a load element pair connected between the power sources of the first power source and a current source connected between the differential pair and a second power source and supplying a constant current to the differential pair, The pair and / or the load element pair is composed of a relatively low threshold transistor, and is inserted into the current path of the differential stage, and the low threshold is used as a switch function for controlling conduction / cutoff of the current path. There is described a differential amplifier circuit including at least one transistor having a threshold value higher than that of the first transistor and controlled to be turned on / off by a control signal input to a control terminal.
JP 2004-128487 A

  However, the above-described conventional interface circuit requires a plurality of logic circuits such as a pair of wired OR circuits in the logic control circuit. When designing with transistor logic, the circuit scale increases as the number of signal systems increases. There is a problem that not only the circuit area increases but also the cost increases because a large and very complicated logic circuit has to be constructed.

  An object of the present invention is to provide an interface circuit capable of constructing a logic control circuit with a simple circuit configuration while employing a bipolar process in view of the above-described conventional problems.

  In order to achieve the above-mentioned object, the characteristic configuration of the interface circuit according to the present invention includes a flip-flop circuit and a logic control circuit for switching the output logic and holding the switched output logic, each of which is configured by a bipolar process. An interface circuit, wherein the logic control circuit is connected to the emitters or collectors of a first transistor to which a reference voltage is applied to the base and a second transistor to which a control voltage is applied to the base, and the emitter or collector is connected. A differential pair in which a constant current source is connected to a node via a switch that switches or holds the output logic of the flip-flop, and the collector or emitter of the first transistor is connected to one input terminal of the flip-flop circuit And the second transistor collection Or the emitter in that connected to the other input terminal of the flip-flop circuit.

  According to the above configuration, the logic control circuit is configured by a differential pair, and a logic for controlling the output of the slip flop by applying a voltage higher or lower than the reference voltage to one terminal of the differential pair. Since the signal is generated, the logic control circuit can be constructed very simply, and the circuit area can be reduced and the cost can be reduced.

  According to the present invention, it is possible to provide an interface circuit capable of constructing a logic control circuit with a simple circuit configuration while employing a bipolar process.

  The interface circuit according to the present invention will be described below.

  As shown in FIG. 1, the interface circuit (hereinafter referred to as “IF circuit”) 9 has a signal level when an external input signal indicating the state of the switch SW9 or the like is input to the input port of the microcomputer 8. This is a circuit for matching, and is provided between the output terminal of the switch SW9 and the input port of the microcomputer 8.

  The microcomputer 8 is incorporated in an electronic control device (hereinafter referred to as “ECU”) mounted on the vehicle, and the signal level of the state signal input to the input port corresponding to the ON or OFF state of the switch SW9 is The switch SW9 is determined to be in the off state when it is equal to or higher than the preset high level threshold VHth, and the switch SW9 is determined to be in the on state when it is equal to or lower than the preset low level threshold VLth. Control brakes appropriately.

  Here, the switch SW9 is composed of various hardware switches such as a door switch mounted on the vehicle, a transistor incorporated in a signal processing circuit such as a sensor, and the like.

  One end of such a hardware switch is grounded to a vehicle chassis or the like, and the other end is connected to a power source such as a battery via a pull-up resistor Rpu9, or the output stage transistor of the signal processing circuit is pulled. If the terminal is open, the output terminal of the switch SW9 may be directly connected to the input port of the microcomputer 8, but if the terminal is open, the signal of the external input signal is connected to the input port side of the microcomputer. It is necessary to provide a pull-up resistor R9 as a pull-up resistor circuit for determining the level.

  However, whether the terminal is open or pulled up varies depending on the switch, and it is very complicated to design the hardware circuit of the electronic control unit individually.

  Therefore, an IF circuit 9 controlled by a microcomputer is provided. When the terminal of the switch SW9 is open, the switch SW9 is connected to an input port or a comparison circuit for comparison with a predetermined threshold voltage via a pull-up resistor R9. When the terminal of SW9 is pulled up, it is configured to be directly connected to the input port or the comparison circuit. When the terminal of the switch SW9 is connected to the comparison circuit CMP9, the output of the comparison circuit CMP9 is connected to the input port of the microcomputer.

  Such an IF circuit 9 includes a transistor Q9 for switching whether or not to apply a power supply voltage to the pull-up resistor R9, a comparison circuit including a Schmitt trigger type comparator CMP9 for determining the output signal level of the switch SW9, a microcircuit, The switching circuit 9 is configured to switch or hold the output logic of a signal applied to the base of the transistor Q9 in accordance with a control signal from the computer 8.

  The transistor Q9 has a collector connected to the power supply, an emitter connected to the pull-up resistor R9, and the pull-up resistor circuit is activated when the signal input to the base is at a high level and the pull-up when the signal is at a low level. Switch the resistance circuit to the inactive state.

  The comparator CMP9 compares the signal level input according to the on / off state of the switch SW9 with the reference voltage generated by the reference voltage generation circuit Vref, and absorbs noise caused by chattering of the switch SW9, and the like. The signal is converted into a logic signal of a predetermined level and input to the microcomputer 8.

  As shown in FIG. 3 (a), the switching circuit 9 includes a flip-flop circuit 9f (a circuit on the left side of the two-dot chain line in the drawing) and a logic control circuit 9s (from the two-dot chain line in the drawing) configured by a bipolar process. The logic control circuit 9s operates so as to switch the output logic of the flip-flop circuit 9f and to hold the switched output logic.

  The logic control circuit 9s includes a first transistor Qs91 to which the reference voltage generated by the reference voltage generation circuit Vs9 is applied to the base, and a control signal S / R (set / reset signal) output from the output terminal of the microcomputer 8. A second transistor Qs92 to which a voltage is applied to the base, and a differential pair in which the emitters of both transistors are connected to each other and a constant current source CCS9 is connected to the emitter connection node Z via a transistor Qs93. .

  The transistor Qs93 functions as a switch for switching or holding the output logic of the flip-flop circuit 9f. The control signal EN output from the output terminal of the microcomputer 8 is applied to the base of the transistor Qs93, and the control signal EN is at a high level. Sometimes a current is supplied from the constant current source CCS9 to the connection node Z, and the current is cut off when it is at a low level.

  The collector of the first transistor Qs91 is connected to one input terminal Pi91 of the flip-flop circuit 9f, and the collector of the second transistor Qs92 is connected to the other input terminal Pi92 of the flip-flop circuit 9f.

  Each of the transistors Qf99, Qf98, Qf97, Qf96, and Qf95 constituting the flip-flop circuit 9f is grounded on the emitter, and the transistors Qf98 and Qf97 and the transistors Qf96 and Qf95 are connected to each other at their respective collector nodes X, Y is connected to a power source via a resistor Rf99 and a resistor Rf98.

  The collector output signal OUT91 of the first transistor Qs91 of the logic control circuit 9s is input to the base of the transistor Qf98, and each collector output signal OUT92 of the second transistor Qs92 of the logic control circuit 9s is input to the base of the transistor Qf95. The base of the transistor Qf96 is connected to the power supply via the resistor Rf99, and the base of the transistor Qf97 is connected to the power supply via the resistors Rf98 and Rf95.

  The base of transistor Qf99 is connected to the power supply via resistors Rf98 and Rf96, and the emitter is connected to the power supply via resistor Rf97. The output terminal Po90 outputs the emitter input signal of the transistor Qf99, and the signal is input to the base of the transistor Q9.

  As shown in FIG. 3B, when the control signal EN is at a low level, the transistor Qs93 is turned off and power is not supplied to the differential pair. Therefore, regardless of the voltage level of the control signal S / R, the first transistor The collector output signals OUT1 and OUT2 of Qs91 and the second transistor Qs92 are both at a low level, and the output logic of the signal output from the flip-flop circuit 9f is held at the immediately preceding logic.

  When the control signal EN for the differential pair becomes high level and the transistor Qs93 is turned on, power is supplied to the differential pair, and if the control signal S / R becomes a voltage higher than the reference voltage generated by the reference voltage generation circuit Vs9, the first transistor The collector current flowing through Qs91 becomes larger than the collector current flowing through the second transistor Qs92, the collector output signal OUT91 becomes high level, the collector output signal OUT92 becomes low level, and the output logic of the signal output from the flip-flop circuit 9f is high level. It becomes.

  Further, if the control signal S / R becomes a voltage lower than the reference voltage generated by the reference voltage generation circuit Vs9, the collector current flowing through the first transistor Qs91 becomes smaller than the collector current flowing through the second transistor Qs92, and the collector output signal OUT91 is at a low level, the collector output signal OUT92 is at a high level, and the output logic of the signal output from the flip-flop circuit 9f is at a low level.

  That is, by providing the switching circuit 9s configured as shown in FIG. 3 in the IF circuit 9, the IF circuit 9 is shown in FIG. 2 with respect to the control signals EN and S / R input from the microcomputer 8. While exhibiting the same function as a conventional circuit, its components are greatly reduced.

  By the way, when there are a plurality of, for example, seven systems of external input signals such as the switch SW9, the IF circuit x (x = 0, 1,..., 7) has the switch SWx (x = 0, 1,..., 7). ) And need to be installed in pairs. Therefore, the logic control circuit xs (x = 0, 1,..., 7) of the IF circuit x (x = 0, 1,..., 7) is parallel to the power supply as shown in FIG. Although the logic control circuits xs (x = 0, 1,..., 7) have the same circuit configuration, as shown in FIG. 5, the constant current source CCSx is replaced with one constant current source CCS9. The circuit size can be further reduced and the cost can be reduced.

  In the circuit configuration shown in FIG. 5, it is necessary to individually input control signals EN and S / R from the microcomputer 8 to the logic control circuit xs (x = 0, 1,..., 7). Two output terminals of the microcomputer 8 having a limited number are exclusively used for each of the control circuits xs.

  Therefore, as shown in FIG. 6, the difference from the constant current source CCSx (x = 0, 1,..., 7) to the connection node Z of the logic control circuit xs (x = 0, 1,..., 7). By including a transistor Qsx3 (x = 0, 1,..., 7) as a selection switch for selectively passing or interrupting the current supplied to the moving pair, the logic control circuit xs (x = 0, 1,..., 7) can be shared by control signals EN and S / R.

  The current supplied or cut off from the constant current source CCSx (x = 0, 1,..., 7) to the differential pair is a control signal input from the microcomputer output terminal to the base of the transistor Qsx0. Since control is performed based on the output logic of SLx (x = 0, 1,..., 7), it is necessary to newly input one control signal SLx to the logic control circuit xs. The output terminal of the microcomputer 8 that outputs EN and S / R can be shared. The reduction effect increases as the number of switches SW increases.

  Further, the transistor Qsx3 (x = 0, 1,..., 7) and the reference voltage generation circuit Vsx (x = 0, 1,..., 7) are respectively connected to one transistor Qs93 as shown in FIG. And the reference voltage generation circuit Vs9, in addition to the effect of reducing the output terminals, the circuit size can be reduced and the cost can be reduced.

  When the logic control circuit xs (x = 0, 1,..., 7) is connected in parallel as shown in FIG. 7, the logic control circuit xs (x = 0, 1,..., 7) As shown in FIG. 8, a common control signal EN, S / R from the microcomputer 8 is inputted in parallel, and a control circuit SLx for switching a transistor Qsx0 as a plurality of selection switches is a decoding circuit composed of a 3-8 decoder. Are input separately. The state signal of the switch SWx is converted into a logic signal by the comparison circuit x and input to the microcomputer 8.

  The microcomputer 8 selects the pull-up resistor circuit to be switched between operation and non-operation, and in order to validate the control signals EN and S / R input to the logic control circuit for the pull-up resistor circuit, the 3-8 Three control signals SL are input to the decoder, and the 3-8 decoder outputs a low level control signal SL to the selected logic control circuit and a high level control signal SL to the other six logic control circuits. . Thereby, the operation or non-operation of the pull-up resistor circuit is switched.

  Further, when there are a plurality of pull-up resistor circuits to be switched between operation and non-operation, the microcomputer 8 sequentially switches the output logic of the control signal SLx and outputs the control signals EN and S / R correspondingly, All pull-up resistor circuits are configured to be switched on or off. Since the microcomputer 8 can output substantially eight control signals with three control signals through the 3-8 decoder, the output of the microcomputer 8 necessary for outputting the control signal SLx. The number of terminals used is reduced.

  More specifically, for example, since the microcomputer 8 operates the pull-up resistor circuit of the switch SW0 to which the pull-up resistor Rpu0 is not connected, all of the control signals EN, S / R at high level (1) Outputs three control signals SL of low level (000). The 3-8 decoder controls a low level (0) control signal SL0 for the logic control circuit 0 and a high level (1) control for the other logic control circuits 1-7 based on the three control signals SL. Signals SL1 to SL7 are output.

  Thereafter, the microcomputer 8 deactivates the pull-up resistor circuit of the switch SW1 connected to the pull-up resistor Rpu1, and three control signals SL of two low levels and one high level (001), A level (1) control signal EN and a low level (0) S / R are output. The 3-8 decoder has a logic control circuit 1 with a low level (0) control signal SL1 and other logic controls. High-level (1) control signals SL0 and 2 to 7 are output to the circuits 0 and 2 to 7, respectively.

  The microcomputer 8 and the 3-8 decoder sequentially repeat the above-described operation for all the switches SW, and when the operation of all the pull-up resistor circuits is switched, the microcomputer 8 sets the control signal EN to low. Output at level (0) to keep the switched pull-up resistor circuit active or inactive.

  Another embodiment will be described below.

  In the above-described embodiment, the configuration and operation of the interface circuit when there are eight external input signals have been described, but it goes without saying that the present invention can be applied to single or multiple external input signals.

  In the embodiment described above, the microcomputer 8 is composed of an ECU mounted on the vehicle, but the present invention is not limited to this. In other words, the switch SW9 may be configured so that the status signal of the switch SW9 is converted into a logic signal via the IF circuit 9 and input.

  In the above-described embodiment, the interface circuit 9 has been described as including the transistor Q9 as the level setting circuit, the comparison circuit including the comparator CMP9, and the switching circuit 9. However, the interface circuit 9 does not include the level setting circuit and the comparison circuit. The switch circuit 9 only, that is, the switch circuit 9 may be the interface circuit 9 itself. In this case, a circuit configuration similar to that of the IF circuit 9 in the above-described embodiment can be realized by externally connecting a level setting circuit and a comparison circuit to the interface circuit 9.

  In the above-described embodiment, the first transistor Qs91 and the second transistor Qs92 constituting the differential pair are configured by pnp transistors, but the pair of transistors configuring the differential pair is configured by npn transistors. It may be a thing. In this case, the logic control circuit connects the collectors of the first transistor to which the reference voltage is applied to the base and the second transistor to which the control voltage is applied to the base, and connects the flip-flop to the collector connection node. A differential pair connected to a constant current source via a switch for switching or holding the output logic of the first transistor, the emitter of the first transistor being connected to one input terminal of the flip-flop circuit, and the second transistor May be connected to the other input terminal of the flip-flop circuit.

  In the above-described embodiment, the pull-up resistor R9 constituting the pull-up resistor circuit is externally attached so that an appropriate resistor having different accuracy and value can be selected based on the detection accuracy of the external input signal. However, as shown in FIG. 9, it may be built in the interface circuit 9. In this case, the work of installing the pull-up resistor R9 externally, its cost, installation space, etc. can be omitted.

  In the embodiment described above, the level setting circuit switches the operation or non-operation of the pull-up resistor circuit. However, as shown in FIG. 9A, an external pull-down resistor R9 or FIG. As shown in FIG. 6, the operation of the pull-down resistor circuit including the pull-down resistor R9 built in the interface circuit 9 may be switched.

  In the above-described embodiment, the case where the interface circuit is connected to the battery has been described. However, it goes without saying that the interface circuit may be connected to a regulator that steps down the battery voltage.

  It should be noted that each of the above-described embodiments is merely an example of the present invention, and it is needless to say that the specific configuration and the like of each block can be changed and designed as appropriate within the scope of the effects of the present invention.

Illustration of interface circuit (A) is explanatory drawing of the interface circuit (switching circuit) by a prior art example, (b) is a characteristic view of the interface circuit (switching circuit) by a prior art example. (A) is explanatory drawing of a switching circuit, (b) is a characteristic figure of an interface circuit. Explanatory diagram when multiple logic control circuits are connected in parallel Explanatory diagram when multiple logic control circuits are connected in parallel Explanatory diagram when multiple logic control circuits are connected in parallel Explanatory diagram when multiple logic control circuits are connected in parallel Illustration of interface circuit when there are 7 switches Explanatory drawing of the interface circuit incorporating the pull-up resistor in another embodiment (A) is explanatory drawing of the interface circuit which attached the pull-down resistor in another Example, (b) is explanatory drawing of the interface circuit which incorporated the pull-down resistor in another Example.

Explanation of symbols

8: Microcomputer 9f: Flip-flop circuit 9s: Logic control circuit CCS9: Constant current source Pi91: Input terminal Pi92: Input terminal Qs91: First transistor Qs92: Second transistor Qs93: Switch SW: Switch

Claims (4)

A flip-flop circuit and a logic control circuit for switching the output logic and holding the switched output logic, each of which is an interface circuit configured by a bipolar process,
The logic control circuit connects the emitters or collectors of a first transistor to which a reference voltage is applied to the base and a second transistor to which the control voltage is applied to the base, and the flip-flop is connected to a connection node of the emitter or collector. A differential pair is connected to a constant current source via a switch for switching or holding the output logic, the collector or emitter of the first transistor is connected to one input terminal of the flip-flop circuit, and the second An interface circuit in which a collector or emitter of a transistor is connected to the other input terminal of the flip-flop circuit.   A level setting circuit for switching the operation or non-operation of a pull-up resistor circuit or a pull-down resistor circuit for determining the signal level of the external input signal based on the output of the flip-flop circuit, and converting the external input signal into a logic signal of a predetermined level The interface circuit according to claim 1, further comprising a comparison circuit that outputs the result.   A plurality of selection switches that connect a plurality of the second transistors in parallel to the connection node and selectively conduct or cut off a current supplied from the constant current source to each differential pair. 3. The interface circuit according to 1 or 2.   4. The interface circuit according to claim 3, wherein a control signal for switching the plurality of selection switches is input to each via a decoding circuit.

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