JP2009099872A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that has a gate metal and a source metal and is manufactured at low cost, and to provide a method of manufacturing the same. <P>SOLUTION: A structure includes: a configration in which a silicon substrate 2, a resistive layer 4, a channel layer 5, and a source layer 6 are laminated in the described order; a gate trench 8 that penetrates the source layer 6 and the channel layer 5 and reaches the resistive layer 4; a gate insulation film 11 that is formed on the inner surface of the gate trench 8; and a gate electrode 12 that is buried in a lower portion of the gate trench 8. In the structure, a source trench 9 that penetrates the source layer 6 and reaches the inside of the channel layer 5 is formed. Next, a metal film, in which a Ti layer 16, TiN layer 17, and W layer 18 are laminated in the described order, is formed over the entire surface of an element region. Then, the metal film is selectively removed so that it remains only on an upper portion of the inside of the gate trench 8 and in the inside of the source trench 9. This method forms a gate metal 13 and a source metal 15 at the same time by using the same type of metal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device provided with a trench gate and a manufacturing method thereof.

  Conventionally, in a vertical power semiconductor device such as a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in order to reduce the cell area and reduce the on-resistance, There is known a technique of forming a gate electrode by forming a trench that penetrates into the trench and burying polysilicon in the trench. In addition, in order to reduce the resistance of the gate electrode, a technique of embedding a metal member (gate metal) above the gate electrode is also known (see, for example, Patent Document 1).

  On the other hand, in such a semiconductor device, in order to improve the avalanche resistance, a trench reaching the channel layer is formed, and a metal member (source metal) connected to the source electrode is embedded in the trench. Technology is also being developed. Thereby, carriers generated in the semiconductor device can be efficiently discharged, and the avalanche resistance is improved.

  However, when the gate metal and the source metal are formed, there are problems that the number of processes increases and the cost of the semiconductor device increases.

JP 2007-35841 A

  An object of the present invention is to provide a semiconductor device including a gate metal and a source metal and having a low manufacturing cost, and a manufacturing method thereof.

  According to one aspect of the present invention, a first conductivity type drain layer, a second conductivity type channel layer provided on the drain layer, and a first conductivity type source layer provided on the channel layer. A gate trench penetrating the source layer and formed in at least the channel layer, a source trench penetrating the source layer and reaching the channel layer, and a gate insulating film formed on the inner surface of the gate trench A gate electrode embedded in a lower portion of the gate trench, a gate metal embedded in an upper portion of the gate trench, and a source metal embedded in the source trench, the gate metal and the A semiconductor device is provided in which the source metal is formed of the same kind of metal material.

  According to another aspect of the present invention, a channel layer of the second conductivity type is formed on the drain layer of the first conductivity type, a source layer of the first conductivity type is formed on the channel layer, and at least the channel A structure in which a gate trench penetrating the source layer is formed in a layer, a gate insulating film is formed on an inner surface of the gate trench, and a gate electrode is embedded in a lower portion of the gate trench; Forming a source trench penetrating into the channel layer, forming a metal film made of a metal material on the structure, selectively removing the metal film, and And a step of remaining in the source trench. A method of manufacturing a semiconductor device is provided.

  According to the present invention, a semiconductor device including a gate metal and a source metal and having a low manufacturing cost and a manufacturing method thereof can be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to this embodiment.

As shown in FIG. 1, in the semiconductor device 1 according to the present embodiment, a vertical trench gate type MOSFET (UMOS) is formed. That is, a silicon substrate 2 made of, for example, N ⁺ type single crystal silicon is provided, and an epitaxial layer 3 is provided on the silicon substrate 2 by epitaxial growth of the single crystal silicon. Epitaxial layer 3 is provided with resistance layer 4 of N ⁻ type conductivity type and connected to silicon substrate 2, and current mainly flows in the element region in the upper layer portion of resistance layer 4, that is, in semiconductor device 1. A channel layer 5 having a conductivity type of P type is formed in the region, and a source layer 6 having a conductivity type of N type is formed in a part of the upper layer portion of the channel layer 5. A drain layer is formed by the silicon substrate 2 and the resistance layer 4.

  In the element region of the semiconductor device 1, a plurality of gate trenches 8 that penetrate the source layer 6 and the channel layer 5 from the upper surface side of the epitaxial layer 3 and reach the resistance layer 4, and a source from the upper surface side of the epitaxial layer 3 A plurality of source trenches 9 penetrating the layer 6 and reaching the channel layer 5 are formed. When viewed from above, the gate trenches 8 and the source trenches 9 are both striped and are arranged in parallel and alternately with each other. Note that the gate trench 8 does not necessarily reach the resistance layer 4 but needs to be formed at least in the channel layer 5. Further, the lower end of the source trench 9 needs to be located in the channel layer 5.

  A gate insulating film 11 is formed on the inner surface of the gate trench 8. The gate insulating film 11 is, for example, an ONO film (Oxide Nitride Oxide film: oxide-nitride-oxide film). A gate electrode 12 made of, for example, polysilicon is buried in the lower part of the gate trench 8, and a gate metal 13 made of a metal material is buried in the upper part of the gate trench 8. The gate metal 13 is in contact with the gate electrode 12.

  Further, a protective insulating film 14 is interposed between the gate insulating film 11 and the gate metal 13. The protective insulating film 14 is made of, for example, a single layer of silicon nitride (SiN), and therefore has a film configuration different from that of the gate insulating film 11 made of an ONO film. The gate electrode 12 is insulated from the epitaxial layer 3 by the gate insulating film 11, and the gate metal 13 is insulated from the epitaxial layer 3 by the protective insulating film 14 and the gate insulating film 11. Therefore, the distance between the gate metal 13 and the epitaxial layer 3 is larger than the distance between the gate electrode 12 and the epitaxial layer 3.

  In the example shown in FIG. 1, the interface between the gate electrode 12 and the gate metal 13 is located at a position lower than the interface between the channel layer 5 and the source layer 6, and thus is located in the channel layer 5. However, the interface between the gate electrode 12 and the gate metal 13 may be higher than the interface between the channel layer 5 and the source layer 6. In this case, the interface between the gate electrode 12 and the gate metal 13 is located in the source layer 6.

  On the other hand, a source metal 15 made of a metal material is embedded in the source trench 9. The upper surface of the gate metal 13 and the upper surface of the source metal 15 are substantially coincident with the upper surface of the source layer 6. That is, the upper surface of the gate metal 13, the upper surface of the source metal 15, and the upper surface of the epitaxial layer 3 constitute substantially the same plane.

  The gate metal 13 and the source metal 15 are made of the same type of metal material. In this specification, the term “metal material” includes alloys and conductive metal compounds in addition to pure metals. For example, a Ti (titanium) layer 16 is formed on the upper surface of the gate electrode 12 and the side surface of the protective insulating film 14 in the gate trench 8, and a TiN (titanium nitride) layer 17 is formed on the Ti layer 16. W (tungsten layer) 18 is buried in the space surrounded by the TiN layer 17. A gate metal 13 is formed by the Ti layer 16, the TiN layer 17, and the W layer 18 provided in the gate trench 8. On the other hand, a Ti layer 16 is formed on the inner surface of the source trench 9, a TiN layer 17 is formed on the Ti layer 16, and a W layer 18 is embedded in a space surrounded by the TiN layer 17. Has been. A source metal 15 is formed by the Ti layer 16, the TiN layer 17 and the W layer 18 provided in the source trench 9.

Furthermore, an insulating interlayer film 21 is provided in a region including the region immediately above the gate trench 8 on the epitaxial layer 3 so as to cover the gate trench 8. The interlayer film 21 is not provided immediately above the source trench 9. The interlayer film 21 is formed by, for example, a CVD method (Chemical Vapor Deposition method: chemical vapor deposition method) using TEOS (Tetra-Ethyl-Ortho-Silicate: tetraethyl orthosilicate (Si (OC ₂ H ₅ ) ₄ )) as a raw material. This is a silicon oxide film formed by the above.

  Furthermore, a TiW layer 22 made of TiW is provided over the entire element region on the epitaxial layer 3 so as to cover the interlayer film 21. The thickness of the TiW layer 22 is 0.2 μm, for example. An Al layer 23 made of aluminum (Al) is formed on the TiW layer 22. The thickness of the Al layer 23 is, for example, 3.8 μm. A source electrode 24 having a thickness of, for example, 4.0 μm is formed by the TiW layer 22 and the Al layer 23. That is, the source electrode 24 is formed on the entire surface of the epitaxial layer 3 so as to cover the interlayer film 21, and is provided in a region including a region directly above the interlayer film 21 and a region directly above the source metal 15. The TiW layer 22 is a barrier metal that prevents Al forming the Al layer 23 from diffusing into the epitaxial layer 3. The source electrode 24 is connected to the source metal 15 and the source layer 6, and is insulated from the gate metal 13 by the interlayer film 21. On the other hand, a drain electrode 25 is provided on the lower surface of the silicon substrate 2.

Next, a method for manufacturing the semiconductor device 1 according to this embodiment configured as described above will be described.
2 to 8 are process cross-sectional views illustrating the method for manufacturing a semiconductor device according to this embodiment.
First, as shown in FIG. 2, an N ⁻ type epitaxial layer 3 is formed on an N ⁺ type silicon substrate 2. Next, etching is performed from the upper surface side of the epitaxial layer 3 to form a plurality of gate trenches 8 in the element region. Next, a gate insulating film 11 made of an ONO film is formed on the inner surface of the gate trench 8 and the upper surface of the epitaxial layer 3. Next, polysilicon is deposited on the entire surface of the element region. Thereafter, by etching back, polysilicon is left only in the lower part in the gate trench 8. Thereby, the gate electrode 12 is formed in the lower part in the gate trench 8.

  Next, a P-type impurity, for example, boron (B) is ion-implanted into the element region of the epitaxial layer 3 from above, and the channel layer 5 is formed in the upper layer portion of the epitaxial layer 3. At this time, the portion of the epitaxial layer 3 that did not become the channel layer 5 becomes the resistance layer 4. Thereafter, the gate insulating film 11 formed on the epitaxial layer 3 is removed.

  Next, as shown in FIG. 3, an N-type impurity such as arsenic (As) is ion-implanted from above into the element region to form a source layer 6 in at least a part of the upper layer portion of the channel layer 5. As a result, a P-type channel layer 5 is formed on the N-type drain layer (silicon substrate 2 and resistance layer 4), an N-type source layer 6 is formed on the channel layer 5, and at least in the channel layer 5 A gate trench 8 penetrating the source layer 6 is formed, a gate insulating film 11 is formed on the inner surface of the gate trench 8, and a structure 31 in which the gate electrode 12 is embedded in the lower portion of the gate trench 8 is manufactured.

  Next, as shown in FIG. 4, SiN is deposited on the entire surface of the element region of the structure 31 by plasma CVD to form a SiN film. Then, the SiN film is selectively removed by RIE (Reactive Ion Etching) or wet etching to remain in a region including the region directly above the gate trench 8. Thereby, the protective insulating film 14 made of a single layer SiN film is formed so as to cover the exposed portion of the gate insulating film 11. At this time, the protective insulating film 14 is not left in a region where the source trench 9 (see FIG. 1) is to be formed.

  Next, as shown in FIG. 5, a hard mask 32 made of silicon oxide, for example, silicon oxide using DTEOS (Densified Tetra Ethyl Ortho Silicate) as a raw material is formed on the entire surface of the source layer 6. The thickness of the hard mask 32 is, for example, 1.6 to 1.8 μm. Next, the hard mask 32 is patterned to form an opening 32a in a region where the source trench 9 (see FIG. 1) is to be formed. Etching is then performed using the hard mask 32 as a mask to selectively remove a portion of the epitaxial layer 3 corresponding to the region immediately below the opening 32a, thereby forming the source trench 9. The source trench 9 is formed, for example, in a region between the gate trenches 8.

  Next, as shown in FIG. 6, wet etching is performed to remove the hard mask 32 (not shown) made of silicon oxide. At this time, the gate insulating film 11 made of the ONO film also contains silicon oxide, but the gate insulating film 11 is protected by the protective insulating film 14 made of silicon nitride. The membrane 11 is not damaged. Next, RIE is performed on the entire surface, and the protective insulating film 14 formed on the upper surface of the source layer 6 and the upper surface of the gate electrode 12 is removed. At this time, the protective insulating film 14 remains on the inner side surface of the gate trench 8. Also, heat treatment is performed to activate the implanted impurities.

  Next, as shown in FIG. 7, a Ti / TiN blanket W step is performed. That is, the Ti layer 16 is formed on the entire surface, the TiN layer 17 is formed, and then the W layer 18 is formed. The Ti layer 16, the TiN layer 17, and the W layer 18 (hereinafter also collectively referred to as “metal film”) are deposited on the source layer 6, the gate electrode 12 and the source trench 9 in the gate trench 8. It is also embedded inside.

  Next, as shown in FIG. 8, the metal film is removed from the source layer 6 and left only in the gate trench 8 and the source trench 9. As a result, the metal film remaining in the gate trench 8, that is, the gate metal 13 is formed from the Ti layer 16, the TiN layer 17 and the W layer 18, and the source metal 15 is formed from the metal film remaining in the source trench 9. The

  Next, as shown in FIG. 1, a silicon oxide film is formed on the entire surface of the source layer 6 by a CVD method using TEOS as a raw material. Next, the silicon oxide film is selectively removed by RIE, and the interlayer film 21 is formed by remaining in a region including the region immediately above the gate trench 8. Next, a TiW layer 22 having a thickness of, for example, 0.2 μm is formed on the entire surface of the source layer 6 so as to cover the interlayer film 21. Next, an Al layer 23 having a thickness of, for example, 3.8 μm is formed on the entire surface of the TiW layer 22 by, eg, CVD. Thereby, the source electrode 24 composed of the TiW layer 22 and the Al layer 23 is formed. On the other hand, a drain electrode 25 made of a metal material is formed on the lower surface of the silicon substrate 2. In this way, the semiconductor device 1 is manufactured.

  In the semiconductor device 1 manufactured in this manner, an inversion layer is formed in a region of the channel layer 5 in contact with the gate trench 8 by applying a potential higher than the threshold voltage to the gate electrode 12 through the gate metal 13. Is done. As a result, the transistor is turned on, and current flows from the drain electrode 25 to the source electrode 24 through the silicon substrate 2, the resistance layer 4, the channel layer 5, and the source layer 6. On the other hand, when a potential lower than the threshold voltage is applied to the gate electrode 12, the inversion layer in the channel layer 5 disappears and is turned off. Also, the carriers generated in the on state are quickly discharged to the source electrode 24 through the source metal 15 when the off state is established.

Next, the effect of this embodiment is demonstrated.
In the present embodiment, after a metal film is formed on the entire surface in the step shown in FIG. 7, the metal film is removed from the source layer 6 in the step shown in FIG. The gate metal 13 and the source metal 15 are formed by being left inside. Thus, since the gate metal 13 and the source metal 15 are simultaneously formed by the same process, manufacturing cost can be suppressed.

  Therefore, according to this embodiment, since the gate metal is provided, the gate resistance is low, and since the source metal is provided, the avalanche resistance is high, miniaturization is easy, and the gate metal and the source metal are formed in the same process. Therefore, a semiconductor device with low manufacturing cost can be realized.

  In this embodiment, since the protective insulating film 14 remains between the gate metal 13 and the gate insulating film 11, the distance between the gate metal 13 and the epitaxial layer 3 is equal to that of the gate electrode 12 and the epitaxial layer 3. It is larger than the distance between the layers 3. Thereby, the breakdown voltage can be increased and the gate voltage can be effectively applied only to the channel region 5.

  Further, in the present embodiment, in the step shown in FIG. 2, the position of the interface between the gate electrode 12 and the gate metal 13 can be arbitrarily adjusted by adjusting the etch back amount of the polysilicon buried in the gate trench 8. Can be controlled. For example, this interface can be located in the source layer 6 or in the channel layer 5. Thereby, the threshold voltage and the withstand voltage of the semiconductor device 1 can be arbitrarily controlled.

  Furthermore, in the present embodiment, since the protective insulating film 14 made of silicon nitride is formed so as to cover the exposed portion of the gate insulating film 11 in the step shown in FIG. 4, in the step shown in FIG. When the hard mask 32 made of silicon oxide is removed, the gate insulating film 11 containing silicon oxide is not damaged.

  Furthermore, in this embodiment, the high-temperature process such as heat treatment for activating the impurities is completed by the step shown in FIG. 6, and the temperature exceeds 420 ° C., for example, after the step shown in FIG. Such a high temperature process is not performed. Thereby, tungsten (W) contained in the gate metal 13 and the source metal 15 is not shrunk due to high temperature, and aluminum (Al) contained in the Al layer 22 is not melted and moved.

The present invention has been described above with reference to the embodiment. However, the present invention is not limited to this embodiment. For example, as long as a person skilled in the art adds, deletes, or changes a design, or adds, deletes, or changes a process as appropriate to the above-described embodiment, the gist of the present invention is included. , Within the scope of the present invention. For example, in the above-described embodiment, an N ⁺ diffusion layer may be provided immediately below the gate trench. In the above-described embodiment, an example in which the semiconductor device is a MOSFET has been described. However, the present invention is not limited to this, and can be applied to any semiconductor device having a vertical trench gate structure, for example, an IGBT. It can also be applied to (Insulated Gate Bipolar Transistor).

1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the invention. 6 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the embodiment; FIG. 6 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the embodiment; FIG. 6 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the embodiment; FIG. 6 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the embodiment; FIG. 6 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the embodiment; FIG. 6 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the embodiment; FIG. 6 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the embodiment; FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Silicon substrate, 3 Epitaxial layer, 4 Resistance layer, 5 Channel layer, 6 Source layer, 8 Gate trench, 9 Source trench, 11 Gate insulating film, 12 Gate electrode, 13 Gate metal, 14 Protective insulating film, 15 source metal, 16 Ti layer, 17 TiN layer, 18 W layer, 21 interlayer film, 22 TiW layer, 23 Al layer, 24 source electrode, 25 drain electrode, 31 structure, 32 hard mask, 32a opening

Claims (5)

A drain layer of a first conductivity type;
A channel layer of a second conductivity type provided on the drain layer;
A source layer of a first conductivity type provided on the channel layer;
A gate trench penetrating the source layer and formed at least in the channel layer;
A source trench penetrating the source layer and reaching the channel layer;
A gate insulating film formed on the inner surface of the gate trench;
A gate electrode embedded in a lower portion of the gate trench;
A gate metal buried in the upper part of the gate trench;
A source metal embedded in the source trench;
With
The semiconductor device, wherein the gate metal and the source metal are formed of the same kind of metal material.   2. The semiconductor device according to claim 1, further comprising an insulating film interposed between the gate insulating film and the gate metal and having a configuration different from that of the gate insulating film. An insulating interlayer film provided in a region including the region directly above the gate metal;
A source electrode provided in a region including a region directly above the interlayer film and a region directly above the source metal;
The semiconductor device according to claim 1, further comprising: A second conductivity type channel layer is formed on the first conductivity type drain layer, a first conductivity type source layer is formed on the channel layer, and at least the gate layer penetrates the source layer in the channel layer. And a source that penetrates the source layer and reaches the channel layer in a structure in which a gate insulating film is formed on the inner surface of the gate trench and a gate electrode is buried in the lower portion of the gate trench. Forming a trench;
Forming a metal film made of a metal material on the structure;
Selectively removing the metal film, and leaving the upper part in the gate trench and the source trench;
A method for manufacturing a semiconductor device, comprising: Forming an insulating film having a configuration different from that of the gate insulating film so as to cover an exposed portion of the gate insulating film with respect to the structure;
Forming a hard mask formed on the source layer by a material different from the insulating film and having an opening in a region where the source trench is to be formed;
Removing the hard mask;
Removing a portion of the insulating film formed on the upper surface of the gate electrode;
Further comprising
5. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the source trench includes a step of etching the source layer and the channel layer using the hard mask as a mask.

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