JP2009098375A - Liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display capable of displaying excellent images of display quality by improving flexibility of a drive method without increasing the maximum signal amplitude. <P>SOLUTION: The liquid crystal display composed to hold a liquid crystal layer between a pair of substrates has scanning lines Y extending in the line direction of a matrix-like pixel and the signal lines X extending in a row direction of the pixels, and each of pixels PX between a pair of signal lines adjoining in a line direction includes a switching element W connected to one signal line on the same substrate, a first electrode E1 connected to one signal line, and a second electrode E2 facing the first electrode via an interlayer insulating film and connected to the other signal line. The switching elements of the pixel adjoining in the line direction are connected to each different scanning line. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a structure including a pair of electrodes facing each other through an interlayer insulating film on one substrate constituting a liquid crystal display panel.

  2. Description of the Related Art In recent years, flat display devices have been actively developed. In particular, liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thinness, and low power consumption. In particular, in an active matrix liquid crystal display device in which a switching element is incorporated in each pixel, a structure that mainly uses a lateral electric field (including a fringe electric field) such as an IPS (In-Plane Switching) mode or an FFS (Fringe Field Switching) mode. Is attracting attention. (For example, refer to Patent Document 1 and Patent Document 2).

  This IPS mode or FFS mode liquid crystal display device includes a pixel electrode and a common electrode formed on an array substrate, and switches liquid crystal molecules with a lateral electric field substantially parallel to the main surface of the array substrate. In addition, polarizing plates are arranged on the outer surfaces of the array substrate and the counter substrate so that the polarization axes are orthogonal to each other. With such a polarizing plate arrangement, for example, a black screen is displayed when no voltage is applied, and a white screen is displayed by gradually increasing the transmittance (modulation factor) by applying a voltage corresponding to the video signal to the pixel electrode. To do. In such a liquid crystal display device, since the liquid crystal molecules rotate in a plane substantially parallel to the main surface of the substrate, the polarization state does not greatly affect the incident direction of transmitted light, so the viewing angle dependency is small and a wide field of view. There is a feature of having angular characteristics.

  According to Patent Document 3, in the IPS system, the display is affected by the electric field generated by the change in the signal line potential after writing to the pixel and the electric field by the change in the potential of the adjacent signal line. On the other hand, there is disclosed a technique for securing a wide pixel area by sharing a signal line and a pixel electrode without arranging wiring for preventing the influence on the display.

According to Patent Document 4, a technique is disclosed in which a potential variation does not occur in the pixel voltage of each pixel when a voltage applied to each scanning signal line changes from a selected scanning voltage to a non-selected scanning voltage. Particularly, in the IPS liquid crystal display module, a technique for reducing the maximum amplitude level of the gradation voltage applied to the pixel electrode is disclosed.
JP 2005-107535 A JP 2006-139295 A Japanese Patent Laid-Open No. 2000-047250 JP 2001-174784 A

  In a liquid crystal mode mainly using a lateral electric field, it is desired to improve display quality by shielding an electric field that affects display from a signal line and suppressing unwanted parasitic capacitance. In addition, it is desired to improve the degree of freedom of the driving method without increasing the maximum signal amplitude.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to improve the degree of freedom of the driving method without increasing the maximum signal amplitude and to improve the display quality. An object of the present invention is to provide a liquid crystal display device capable of displaying an image.

A liquid crystal display device according to an aspect of the present invention includes:
A liquid crystal display device having a liquid crystal layer held between a pair of substrates,
A scanning line extending in the row direction of the matrix-shaped pixels;
A signal line extending in the column direction of the pixels,
Each of the pixels between a pair of signal lines adjacent in the row direction includes a switching element connected to one signal line, a first electrode connected to the switching element, and the first electrode on the same substrate. A second electrode facing the interlayer insulating film and connected to the other signal line,
Switching elements of pixels adjacent in the row direction are connected to different scanning lines.

  According to the present invention, it is possible to provide a liquid crystal display device capable of improving the degree of freedom of the driving method without increasing the maximum signal amplitude and displaying an image with a good display quality.

  A liquid crystal display device according to an embodiment of the present invention will be described below with reference to the drawings.

Here, an FFS mode liquid crystal is provided as a liquid crystal mode in which a pair of electrodes is provided on one substrate, and liquid crystal molecules are switched using mainly a lateral electric field (horizontal electric field substantially parallel to the substrate surface) formed between the electrodes. A display device will be described as an example.

  As shown in FIGS. 1 and 2, the liquid crystal display device is an active matrix type liquid crystal display device and includes a liquid crystal display panel LPN. The liquid crystal display panel LPN includes an array substrate AR, a counter substrate CT arranged to face the array substrate AR, a liquid crystal layer LQ held between the array substrate AR and the counter substrate CT, It is configured with. Such a liquid crystal display panel LPN includes an active area DSP for displaying an image. The active area DSP is composed of m × n pixels (m and n are natural numbers) arranged in a matrix.

  In this embodiment, a liquid crystal display device including a transmissive liquid crystal display panel LPN will be described. However, the present invention is not limited to a transmissive type, and may be applied to a reflective type. The transmissive liquid crystal display device includes a backlight unit BL disposed on the array substrate AR side with respect to the liquid crystal display panel LPN. A liquid crystal display device including such a transmissive liquid crystal display panel LPN is configured to display an image by selectively transmitting backlight light from the backlight unit BL.

  A more specific configuration of the liquid crystal display device will be described.

  The array substrate AR is formed using an insulating substrate 10 having optical transparency such as a glass plate or a quartz plate. That is, the array substrate AR includes, in the active area DSP, m × n first electrodes E1 arranged for each pixel PX, and at least (2 × n) pieces extending in the row direction H of each pixel PX. The scanning line Y (Y1 to Y (2n)), at least (m + 1) signal lines X (X1 to X (m + 1)) extending in the column direction V of each pixel PX, and the scanning line Y in each pixel PX There are provided m × n switching elements W arranged in a region including an intersection with the signal line X, m × n second electrodes E2 arranged for each pixel PX, and the like. The surface of the array substrate AR that contacts the liquid crystal layer LQ is covered with the alignment film 20.

  Each switching element W is, for example, an n-channel thin film transistor, and is connected to the scanning line Y and the signal line X, respectively. That is, the switching element W includes the semiconductor layer 12 disposed on the insulating substrate 10. The semiconductor layer 12 can be formed of, for example, polysilicon or amorphous silicon, and is formed of polysilicon here. The semiconductor layer 12 has a source region 12S and a drain region 12D on both sides of the channel region 12C. The semiconductor layer 12 is covered with a gate insulating film 14.

  The gate electrode WG of the switching element W is connected to the scanning line Y (or formed integrally with the scanning line Y). Both the gate electrode WG and the scanning line Y are disposed on the gate insulating film 14. These gate electrodes WG and scanning lines Y are covered with a first interlayer insulating film 16. The gate insulating film 14 and the first interlayer insulating film 16 can be formed of a thin film made of an inorganic material such as a silicon oxide film or a silicon nitride film.

  The source electrode WS and the drain electrode WD of the switching element W are disposed on both sides of the gate electrode WG on the first interlayer insulating film 16. The source electrode WS is connected to the signal line X (or formed integrally with the signal line X), and the source of the semiconductor layer 12 through a contact hole penetrating the gate insulating film 14 and the first interlayer insulating film 16. The region 12S is contacted. The drain electrode WD is connected to the first electrode E1 (or formed integrally with the first electrode E1), and the semiconductor layer 12 via a contact hole that penetrates the gate insulating film 14 and the first interlayer insulating film 16. In contact with the drain region 12D. The source electrode WS, the drain electrode WD, and the signal line X are covered with the second interlayer insulating film 18.

  When the polysilicon thin film transistor having the above-described configuration is applied, the second interlayer insulating film 18 can be formed of an organic material (resin material). When an amorphous silicon thin film transistor is applied, the second interlayer insulating film 18 can be formed by a thin film made of an inorganic material such as a nitride film.

  The (2 × n) scanning lines Y (Y1 to Y (2n)) are arranged in the column direction V, respectively. (M + 1) signal lines X (X1 to X (m + 1)) are arranged in the row direction H, respectively. That is, each of the m × n pixels PX is located between a pair of signal lines X adjacent in the row direction. A pair of scanning lines Y adjacent to each other in the column direction is assigned to the pixels for one row.

  In each pixel PX, the first electrode E1 and the second electrode E2 are opposed to each other through an interlayer insulating film. The first electrode E1 and the second electrode E2 have a function as a storage capacitor formed between adjacent signal lines.

  In the example shown in FIG. 2, the first electrode E1 and the second electrode E2 are opposed to each other with the second interlayer insulating film 18 interposed therebetween. That is, the first electrode E1 is arranged in an island shape on the second interlayer insulating film 18, and one signal line (hereinafter referred to as a first signal line) of a pair of signal lines arranged on both sides of the pixel PX. ) It is connected to XA. The second electrode E2 is disposed in an island shape under the second interlayer insulating film 18, that is, between the first interlayer insulating film 16 and the second interlayer insulating film 18, and a pair of signals disposed on both sides of the pixel PX. The other signal line (hereinafter referred to as a second signal line) XB among the lines is connected.

  Here, the first electrode E1 is electrically connected to the drain electrode WD via a contact hole penetrating the second interlayer insulating film 18, and the first signal line XA is connected via the switching element W of each pixel PX. It is connected to the. The second electrode E2 is connected to the second signal line XB adjacent in the row direction H to the first signal line XA to which the first electrode E1 is connected. That is, the edge of the second electrode E2 overlaps the second signal line XB, and the two are electrically connected. According to such a configuration, the first electrode E1 and the second electrode E2 form a liquid crystal capacitor Clc therebetween, and function as a storage capacitor element that forms an auxiliary capacitor Cs for holding the liquid crystal capacitor Clc. Have both.

  The first electrode E1 and the second electrode E2 are formed of a light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

  The array substrate AR further includes at least a part of the scan line driver YD connected to the (2 × n) scan lines Y in the drive circuit region DCT around the active area DSP, or (m + 1) At least a part of the signal line driver XD connected to the signal line X is included. The scanning line driver YD sequentially supplies scanning signals (driving signals) to the (2 × n) scanning lines Y based on control by the controller CNT. Further, the signal line driver XD supplies video signals (drive signals) to the (m + 1) signal lines X at a timing when the switching elements W in each row are turned on by the scanning signal based on the control by the controller CNT.

  The signal line driver XD has a function as a potential setting unit that sets a predetermined pixel potential for each pixel PX in each row. That is, when the signal line driver XD supplies a video signal to each signal line X, for each pixel PX, the potential of one signal line is set to a pixel potential based on the potential of the other signal line. Outputs signal voltage.

  On the other hand, the counter substrate CT is formed using an insulating substrate 30 having optical transparency such as a glass plate or a quartz plate. In particular, in the color display type liquid crystal display device, as shown in FIG. 2, the counter substrate CT has a black matrix 32 that partitions each pixel PX on the inner surface of the insulating substrate 30, that is, the surface facing the liquid crystal layer LQ. A color filter layer 34 and the like arranged individually for each pixel PX surrounded by the black matrix 32 are provided. The color filter layer 34 may be disposed on the array substrate AR side. Further, the counter substrate CT further includes a shield electrode for reducing the influence of the external electric field, an overcoat layer disposed with a relatively thick film thickness so as to flatten the unevenness of the surface of the color filter layer 34, and the like. It may be provided.

  The black matrix 32 is arranged on the insulating substrate 30 so as to face wiring portions such as the scanning lines Y, the signal lines X, and the switching elements W provided on the array substrate AR. The color filter layer 34 is disposed on the insulating substrate 30 and is formed of colored resins that are respectively colored in a plurality of different colors, for example, three primary colors such as red, blue, and green. The red colored resin, the blue colored resin, and the green colored resin are disposed corresponding to the red pixel, the blue pixel, and the green pixel, respectively. The surface of the counter substrate CT that contacts the liquid crystal layer LQ is covered with the alignment film 36.

  When the array substrate AR and the counter substrate CT configured as described above are arranged so that the alignment film 20 and the alignment film 36 face each other, a spacer (not shown) formed between them (for example, formed of a resin material) A predetermined gap is formed by the columnar spacer). The liquid crystal layer LQ is composed of a liquid crystal composition including liquid crystal molecules 40 enclosed in a gap formed between the alignment film 20 of the array substrate AR and the alignment film 36 of the counter substrate CT.

  The liquid crystal molecules 40 included in the liquid crystal layer LQ are aligned by the regulating force by the alignment film 20 and the alignment film 36. That is, no potential difference is formed between the potential of the first electrode E1 and the potential of the second electrode E2 (that is, no electric field is formed between the first electrode E1 and the second electrode E2). In some cases, the liquid crystal molecules 40 are aligned such that the major axis thereof is oriented in a direction parallel to the rubbing direction of the alignment film 20 and the alignment film 36.

  In addition, the liquid crystal display device includes an optical element OD1 provided on one outer surface of the liquid crystal display panel LPN (that is, the surface opposite to the surface in contact with the liquid crystal layer LQ of the array substrate AR), and the liquid crystal display panel An optical element OD2 provided on the other outer surface of the LPN (that is, the surface opposite to the surface in contact with the liquid crystal layer LQ of the counter substrate CT) is provided.

  These optical elements OD1 and OD2 include a polarizing plate, for example, to realize a normally black mode in which the transmittance of the liquid crystal display panel LPN is lowest (that is, a black screen is displayed) when there is no electric field. The optical elements OD1 and OD2 may be configured to realize a normally white mode in which the transmittance of the liquid crystal display panel LPN is maximized (that is, a white screen is displayed) when there is no electric field.

  In such a liquid crystal display device, the first electrode E1 and the second electrode E2 are formed in a shape that forms an electric field extending to the liquid crystal layer LQ. In the example shown in FIGS. 2 and 3, the first electrode E1 is overlapped with the second electrode E2 via the second interlayer insulating film 18 between the first signal line XA and the second signal line XB. It is arranged and has a notch in a part thereof to expose the second electrode E2. Here, the first electrode E1 has a plurality of slits SL facing the second electrode E2. The slit SL is formed such that its long axis intersects the rubbing direction S of the alignment film 20 and the alignment film 36. The shape of the second electrode E2 is a substantially rectangular shape without a slit or the like.

  According to such a configuration, when a potential difference is formed between the potential of the first electrode E1 and the potential of the second electrode E2 (that is, the potential (reference potential) of the second electrode E2 is applied to the first electrode E1). When a voltage having a potential different from the reference potential is applied as a reference), an electric field E is formed between the first electrode E1 and the second electrode E2 via the slit SL. This electric field E is formed in a direction substantially orthogonal to the edge of the slit SL. At this time, the liquid crystal molecules 40 are driven so that their long axes are aligned in a direction parallel to the electric field E from the rubbing direction S.

  Thus, when the orientation of the major axis of the liquid crystal molecules 40 changes from the rubbing direction S, the modulation factor for the light transmitted through the liquid crystal layer LQ changes. Therefore, the backlight light emitted from the backlight unit BL is incident on the liquid crystal display panel LPN via the first optical element OD1, and then a part of the backlight light is based on the modulation factor of the liquid crystal layer LQ. The white light screen is displayed through the element OD2. That is, the transmittance of the liquid crystal display panel LPN changes depending on the magnitude of the electric field E. In the liquid crystal mode using the horizontal electric field, the backlight is selectively transmitted in this way, and an image is displayed.

  As described above, according to this embodiment, each pixel includes a storage capacitor element formed between a pair of adjacent signal lines. That is, the signal line has a function as an auxiliary capacity line (common use of the signal line and the auxiliary capacity line). Therefore, it is possible to suppress the generation of an electric field that affects the display from the signal line, and a problem that may occur when the auxiliary capacitance line is arranged separately from the signal line, that is, the signal line and the auxiliary capacitance line. The problem with the capacity between is resolved. As a result, it is possible to display an image with good display quality. In addition, since the auxiliary capacitance line is not necessary, the pixel aperture ratio can be increased. Further, a power supply circuit for supplying a potential to the auxiliary capacitance element is not necessary, and the cost can be reduced.

  In the example illustrated in FIG. 3, each pixel PX has a shape in which the length along the row direction H is shorter than the length along the column direction V.

  That is, the first electrode E1 is disposed between a pair of signal lines, that is, the first signal line XA corresponding to the own pixel PX and the second signal line XB adjacent to the first signal line XA. It has a rectangular shape that is long in a direction V parallel to the extending direction. The first electrode E1 has four slits SL extending in the column direction V and arranged in the row direction H. The second electrode E2 is disposed so that it is separated from the first signal line XA and has an edge on one end thereof overlapping the second signal line XB, and has a substantially rectangular shape that is long in the column direction V. The first electrode E1 is connected to the first signal line XA, and the second electrode E2 is connected to the second signal line XB. In the pixel PX having such a configuration, the pixel aperture ratio is about 66%.

  On the other hand, in the example shown in FIG. 4, each pixel PX has a shape in which the length along the row direction H is longer than the length along the column direction V.

  That is, the first electrode E1 is disposed between the first signal line XA and the second signal line XB, and has a rectangular shape that is long in the row direction (that is, the direction parallel to the scanning line extending direction) H. Yes. The first electrode E1 has four slits SL extending in the row direction H and arranged in the column direction V. The second electrode E <b> 2 is spaced from the first signal line XA and is disposed so that the edge on one end thereof overlaps the second signal line XB, and has a rectangular shape that is generally long in the row direction H. The first electrode E1 is connected to the first signal line XA, and the second electrode E2 is connected to the second signal line XB. In the pixel PX having such a configuration, the space between the second electrode E2 and the first signal line XA can be reduced as compared with the example shown in FIG. 3, and the pixel aperture ratio is about 73%. . That is, in this embodiment, the pixel aperture ratio can be improved in the pixel shape longer in the row direction H than in the pixel shape longer in the column direction V.

  As described above, in this embodiment, (2 × n) scanning lines Y are arranged for n rows of pixels PX. A pair of scanning lines Y adjacent to each other in the column direction V is assigned to pixels for one row, that is, m pixels PX arranged in the row direction H. That is, the scanning lines Y1 and Y2 are assigned to the m pixels PX in the first row, the scanning lines Y3 and Y4 are assigned to the m pixels PX in the second row, and similarly, the nth row. The scanning lines Y (2n−1) and Y (2n) are assigned to the m pixels PX.

  The switching elements W of the pixels PX adjacent in the row direction H are connected to different scanning lines Y, respectively.

  Here, as shown in FIG. 5, a specific configuration will be described focusing on two pixels adjacent in the row direction H, that is, the first pixel PX1 and the second pixel PX2 in a certain row. For this row, a pair of scanning lines adjacent in the column direction V, that is, the first scanning line YA and the second scanning line YB are assigned.

  First, the first pixel PX1 will be described. That is, for the switching element W of the first pixel PX1, its gate electrode WG is connected to the first scanning line YA, its source electrode WS is connected to the signal line XA, and its drain electrode WD is connected to the first electrode E1. It is connected to the. The second electrode E2 of the first pixel PX1 is connected to the signal line XB adjacent in the row direction H of the signal line XA.

  Subsequently, the second pixel PX2 will be described. That is, for the switching element W of the second pixel PX2, its gate electrode WG is connected to the second scanning line YB, its source electrode WS is connected to the signal line XB, and its drain electrode WD is connected to the first electrode E1. It is connected to the. The second electrode E2 of the second pixel PX2 is connected to the signal line XC adjacent to the signal line XB in the row direction H.

  With such a configuration, adjacent pixels can be independently driven with respect to a plurality of pixels PX configuring the same row.

  That is, the timing at which the scanning line driver YD outputs a scanning signal for turning on the switching element W to the first scanning line YA and simultaneously outputs a scanning signal for turning off the switching element W to the second scanning line YB. Then, the signal line driver XD outputs a signal voltage that is set to a pixel potential based on the potential of the signal line XB with respect to the signal line XA. As a result, the pixel potential is written to the first pixel PX1.

  Following this timing, the scanning line driver YD outputs a scanning signal for turning on the switching element W to the second scanning line YB and simultaneously outputs a scanning signal for turning off the switching element W to the first scanning line YA. At the timing, the signal line driver XD outputs a signal voltage that is set to the pixel potential with respect to the signal line XB with reference to the potential of the signal line XC. Thereby, the pixel potential is written to the second pixel PX2.

  For this reason, even if V line inversion driving or dot inversion driving (HV inversion driving) is applied, an increase in the maximum signal amplitude is suppressed.

  The configuration as shown in FIG. 5 can be applied to m pixels for one row. That is, among the pixels for one row, the switching element W of the odd-numbered column (or odd-numbered) pixel is connected to one scanning line of a pair of scanning lines adjacent in the column direction V, for example, the first scanning line YA. The switching elements W of the pixels in the even-numbered columns (or even-numbered pixels) are connected to the other scanning line of the pair of scanning lines adjacent in the column direction V, for example, the second scanning line YB. That is, as in the configuration shown in FIG. 5, the gate electrode WG of the switching element W of the pixel in the odd-numbered column corresponding to the first pixel PX1 is connected to the first scanning line YA and the even number corresponding to the second pixel PX2. The gate electrode WG of the switching element W of the pixel in the column is connected to the second scanning line YB.

  In such a configuration, for example, when the first scanning line YA is on, in each pixel, one of the pair of adjacent signal lines is kept at the reference potential, and the other signal line is connected to the other signal line. Write pixel potential. Thereby, writing is performed on the pixels in the odd-numbered columns in one row (that is, (m / 2) pixels in m pixels for one row). Subsequently, when the second scanning line YB is on, in each pixel, one of the adjacent signal lines is kept at the reference potential, and the pixel potential is written to the other signal line. At this time, the signal line in which the pixel potential is written at the preceding stage timing is set to the reference potential of the adjacent pixel, and the reference potential signal line is set to the pixel potential of the adjacent pixel at the preceding stage timing. As a result, writing is performed on the pixels in the even-numbered columns in one row (that is, the remaining half of the m pixels in one row).

  This will be explained more specifically as follows.

Here, to simplify the explanation, as shown in FIG. 6A, focusing on the four pixels (PX1, PX2, PX3, PX4) in the first row in the active area DSP, a normally black mode (potential difference is 5 V drive). A driving example of black display at 0V and white display at a potential difference of 5V will be described.

  The pixel PX1 is disposed between the signal lines X1 and X2, and has a first electrode connected to the signal line X1 and a second electrode connected to the signal line X2. The pixel PX2 is disposed between the signal lines X2 and X3, and has a first electrode connected to the signal line X2 and a second electrode connected to the signal line X3. The pixel PX3 is disposed between the signal lines X3 and X4, and the first electrode is connected to the signal line X3 and the second electrode is connected to the signal line X4. The pixel PX4 is disposed between the signal lines X4 and X5, and has a first electrode connected to the signal line X4 and a second electrode connected to the signal line X5.

  Among these four pixels, the gate electrodes of the switching elements of the pixels PX1 and PX3 are respectively connected to the scanning line Y1, and when an ON signal is supplied to the scanning line Y1, the pixel potential is passed through each signal line. Can be written, and the written pixel potential is held within the period during which the OFF signal is supplied to the scanning line Y1. Further, the gate electrodes of the switching elements of the pixels PX2 and PX4 are connected to the scanning line Y2, respectively, and when the ON signal is supplied to the scanning line Y2, the pixel potential can be written through each signal line. In addition, the written pixel potential is held within the period during which the OFF signal is supplied to the scanning line Y2.

  In writing such a pixel potential, in any pixel, the potential of one signal line is set to a pixel potential based on the potential of the other signal line.

  For example, when all four pixels are displayed in white, as shown in FIG. 6B, the potential of the signal line X2 is set to the reference potential, for example, 0 V, for the pixel PX1 at the timing when the ON signal is supplied to the scanning line Y1. When the potential of the signal line X1 is set to 5V, white display is obtained. Similarly, regarding the pixel PX3, white display is performed by setting the potential of the signal line X4 to 0V and the potential of the signal line X3 to 5V.

  As shown in FIG. 6C, at the timing when the ON signal is supplied to the scanning line Y2, for the pixel PX2, the potential of the signal line X3 is set to 0V, and the potential of the signal line X2 is set to 5V. Display. Similarly, regarding the pixel PX4, white display is performed by setting the potential of the signal line X5 to 0V and the potential of the signal line X4 to 5V. By setting the potential of each signal line by such a driving method, a desired screen display can be performed.

  In this manner, all pixels in one row are written at different timings by the on / off control via the two scanning lines.

  As described above, according to this embodiment, even if normal V-line inversion driving or dot inversion driving is applied, the increase in the maximum signal amplitude is suppressed, so that the degree of freedom of the driving method is improved. Is possible. In addition, an increase in power consumption can be suppressed, and an image with a relatively low cost and good display quality can be displayed.

  In addition, this invention is not limited to the said embodiment itself, In the stage of implementation, it can change and implement a component within the range which does not deviate from the summary. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

FIG. 1 is a diagram schematically showing a configuration of a liquid crystal mode liquid crystal display device using a lateral electric field according to an embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing a structural example of one pixel of the liquid crystal display device shown in FIG. FIG. 3 is a plan view schematically showing a structural example of one pixel of the array substrate applicable to the liquid crystal display device shown in FIG. FIG. 4 is a plan view schematically showing another structure example of one pixel of the array substrate applicable to the liquid crystal display device shown in FIG. FIG. 5 is a diagram for explaining the configuration of two pixels adjacent in the row direction in the liquid crystal display device of this embodiment. FIG. 6A is a diagram for explaining an example of driving in the liquid crystal display device of this embodiment. FIG. 6B is a diagram illustrating a driving example in the case where the odd-numbered pixels perform white display in the 5V-driven normally black mode liquid crystal display device illustrated in FIG. 6A. FIG. 6C is a diagram illustrating a driving example in the case where the even-numbered pixels perform white display in the normally black mode liquid crystal display device of 5 V driving illustrated in FIG. 6A.

Explanation of symbols

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate LQ ... Liquid crystal layer DSP ... Active area Y ... Scanning line X ... Signal line PX ... Pixel W ... Switching element E1 ... First electrode (upper electrode)
E2 ... Second electrode (lower electrode)
SL ... Slit XD ... Signal line driver YD ... Scanning line driver CNT ... Controller Clc ... Liquid crystal capacitance Cs ... Auxiliary capacitance

Claims (5)

A liquid crystal display device having a liquid crystal layer held between a pair of substrates,
A scanning line extending in the row direction of the matrix-shaped pixels;
A signal line extending in the column direction of the pixels,
Each pixel between a pair of signal lines adjacent in the row direction includes a switching element connected to one signal line, a first electrode connected to the switching element, and the first electrode on the same substrate. A second electrode facing the interlayer insulating film and connected to the other signal line,
A liquid crystal display device, wherein switching elements of pixels adjacent in the row direction are connected to different scanning lines.   Among the pixels for one row, the switching element of the pixel in the odd column is connected to one scanning line of a pair of scanning lines adjacent in the column direction, and the switching element of the pixel in the even column is the other The liquid crystal display device according to claim 1, wherein the liquid crystal display device is connected to the scanning line.   At least (2 × n) scanning lines and at least (m + 1) signal lines are arranged for m × n pixels (m and n are natural numbers) arranged in a matrix. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device.   The liquid crystal display device according to claim 1, wherein the potential of one signal line is set to a pixel potential based on the potential of the other signal line.   The liquid crystal display device according to claim 1, wherein the pixel has a shape in which a length along a row direction is longer than a length along a column direction.

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