JP2009075279A - Display panel, drive method thereof, display device and video display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve vertical stripes in a selector-drive liquid crystal display device by reducing a difference of the effect of coupling resulting from a parasitic capacitance between signal lines. <P>SOLUTION: In an odd-numbered set, a switch circuit connected to a first signal line is connected to a first control signal supply line L1, a switch circuit connected to a second signal line is connected to a second control signal supply line L2, a switch circuit connected to a third signal line is connected to a third control signal supply line L3, and a switch circuit connected to a fourth signal line is connected to a fourth control signal supply line. In an even-numbered set, the switch circuit connected to the first signal line is connected to the fourth control signal supply line L4, the switch circuit connected to the second signal line is connected to the third control signal supply line L3, the switch circuit connected to the third signal line is connected to the second control signal supply line L2, and the switch circuit connected to the fourth signal line is connected to the first control signal supply line. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display panel, a driving method thereof, a display device, and a video display device. Specifically, the present invention relates to a display panel that performs time-division driving and a driving method thereof, and a display device and a video display device that use such a display panel.

  In a flat panel display device, for example, a liquid crystal display device using a liquid crystal cell as an electro-optic element of a pixel, each pixel in a matrix arrangement is arranged to drive a liquid crystal panel in which pixels including the liquid crystal cell are arranged in a matrix. For example, by supplying a video signal from a driver IC outside the liquid crystal panel through a signal line wired for each pixel column on the liquid crystal panel while performing selective scanning in units, for example, an image is displayed on each pixel in the selected row. A signal is being written.

  Here, the relationship between each of the signal lines wired for each pixel column on the liquid crystal panel and the output of the driver IC outside the panel that supplies a video signal to these signal lines is set with a one-to-one correspondence. Therefore, it is necessary to prepare driver ICs having the number of outputs corresponding to the number of signal lines, and wirings corresponding to the number are required to electrically connect the driver IC and the liquid crystal panel.

  From such a point of view, a plurality of signal lines are assigned as a unit (set) to one output of the driver IC, and the plurality of signal lines are sequentially selected in a time division manner, while the selected signal line is selected. A so-called selector drive method (time division drive method) is employed in which each signal line is driven by distributing and supplying video signals output in time series for each output of the driver IC (for example, patents). Reference 1 and Patent Reference 2).

  Here, in the selector driving method, the relationship between the output of the driver IC and the signal line is set with a correspondence of 1 to x (x is an integer of 2 or more), and x assigned to one output of the driver IC. This is a driving method of selecting and driving one signal line by x time division. By adopting this selector driving method, the number of outputs of the driver IC and the number of wirings between the driver IC and the liquid crystal panel can be obtained. It is possible to reduce the number of signal lines to 1 / x.

  When the selector driving method is adopted, a liquid crystal panel has a switch circuit for distributing one video signal (time series signal) output from the driver IC to x signal lines in a time division manner. The switch circuit is controlled to be switched by a drive signal input from the outside of the panel.

Hereinafter, a conventional liquid crystal display device adopting a selector driving method will be described with reference to the drawings.
FIG. 13 is a schematic diagram for explaining a conventional liquid crystal display device, and a liquid crystal display device 201 shown here includes a liquid crystal panel 207 and a driver IC 208.

  The liquid crystal panel includes a pixel array unit 202 and peripheral circuits that drive each pixel, for example, a vertical drive circuit 203, a switch circuit group 204, a buffer group 205, and a precharge circuit 206. The liquid crystal panel 207 includes N systems from the driver IC 208. Video signals SIG # 1 to SIG # N are input.

  Here, in the pixel array unit 202, pixels 209 including liquid crystal cells that are electro-optical elements are two-dimensionally arranged in a matrix on a first glass substrate that is a transparent insulating substrate. Each of the m scanning lines G1, G2, G3,... Gm is wired, and n signal lines D1, D2, D3,. A second glass substrate is disposed opposite to the first glass substrate with a predetermined gap therebetween, and a liquid crystal material is sealed in the gap between the two glass substrates, whereby a liquid crystal panel Is configured.

  The vertical drive circuit 203 includes a shift register, a buffer circuit, and the like. The vertical drive circuit 203 sequentially outputs vertical scanning pulses, and the vertical scanning pulses are supplied to the scanning lines G of the pixel array unit 202, so that the pixels 209 are row-wise. Will be selected.

  Further, since the selector driving method (time-division driving method) is adopted as the driving method of the signal lines D in the liquid crystal panel, the four signal lines D adjacent to each other in the pixel array unit 202 are set (unit). It is said.

  In addition, N (= n / 4) video signals SIG # 1 to SIG # N are input to the signal line D from the driver IC 208 provided outside the liquid crystal panel. The N video signals SIG # 1 to SIG # N are input in a state in which signals for four signal lines forming a set are arranged in time series every 1H (H: horizontal scanning period). To the N switch circuits SW1, SW2, SW3... SWN.

  Further, the N switch circuits SW are connected to the buffers 205-1, 205-2, 205-3, and 205- of the buffer group 205 based on drive pulses HSEL1, HSEL2, HSEL3, and HSEL4 input from the outside of the liquid crystal panel. 4 are sequentially selected in a time division manner in synchronism with the drive pulses Hdrive1, Hdrive2, Hdrive3, and Hdrive4 output from each of the four, and the video signal SIG # is selected for the selected signal lines. Each of 1 to SIG # N is distributed in time division and supplied.

As shown in FIG. 14, in the conventional liquid crystal panel, a common drive pulse is applied to the switch circuits connected to the k-th (k = 1, 2, 3, 4) signal lines of each set. It is configured as follows.
Specifically, the switch pulse connected to the first signal line of each set, that is, the switch circuit connected to the (4i-3) th (i: natural number) signal line is supplied with the drive pulse Hdrive1. The switch circuit connected to the first control signal supply line L1 and connected to the second signal line of each set, that is, the switch circuit connected to the (4i-2) th signal line is a drive. Connected to the second control signal supply line L2 to which the pulse Hdrive2 is supplied and connected to the third signal line of each set, that is, connected to the (4i-1) th signal line The switch circuit is connected to the third control signal supply line L3 to which the drive pulse Hdrive3 is supplied, and is connected to the fourth signal line of each set, that is, connected to the (4i) th signal line. Made Circuit is connected to a fourth control signal supply line L4 drive pulse Hdrive4 is supplied.

  Hereinafter, a driving method of the liquid crystal display device configured as described above will be described. Hereinafter, the switch circuit connected to the jth signal line is referred to as a “jth switch circuit”.

  In the case of driving the liquid crystal display device configured as described above, in order to reduce the burden on the driver IC, first, in the horizontal blanking period, the precharge control pulse PCG is set to logical positive, The precharge signal Psig is written into the signal line. Note that the precharge circuit is configured as shown in FIG. 17, and by setting the precharge control pulse PCG to a logic positive, a switch circuit that connects each signal line with a wiring that supplies a precharge signal Psig is provided. The conduction state is established all at once, and the precharge signal Psig is written to each signal line.

  Next, in a state where the vertical drive circuit outputs an H level signal to the gate line G1 in the first row and the gate line G1 is selected, Hdrive1 is set to the high level (hereinafter referred to as the H level) at the timing indicated by the symbol t1 in FIG. The first (4i-3) th switch circuit connected to the first control signal supply line L1 is turned on to supply a video signal to the (4i-3) th signal line. When the timing Hdrive1 indicated by the symbol t2 in FIG. 15 is set to the low level (hereinafter referred to as L level), the (4i-3) th switch circuit is turned off and the (4i-3) th signal line is turned off. Floating state. That is, a video signal is supplied to the signal line D (4i-3) during a period indicated by a symbol T1 in FIG. 15, and the video signal is supplied to the pixels connected to the gate line G1 and the signal line D (4i-3) during this period. Write.

  Further, by setting Hdrive2 to the H level at the timing indicated by the symbol t2 in FIG. 15, the (4i-2) th switch circuit connected to the second control signal supply line L2 is brought into the conductive state (4i-2). ) The video signal is supplied to the first signal line, and Hdrive2 is set to the L level at the timing indicated by the symbol t3 in FIG. 15, thereby setting the (4i-2) th switch circuit to the non-conductive state (4i-2). The main signal line is set in a floating state. That is, a video signal is supplied to the signal line D (4i-2) during a period indicated by a symbol T2 in FIG. 15, and the video signal is supplied to the pixels connected to the gate line G1 and the signal line D (4i-2) during this period. Write.

  Further, by setting Hdrive3 to the H level at the timing indicated by the symbol t3 in FIG. 15, the (4i-1) th switch circuit connected to the third control signal supply line L3 is set in the conductive state (4i-1). ) The video signal is supplied to the first signal line, and Hdrive3 is set to the L level at the timing indicated by reference numeral t4 in FIG. 15, thereby setting the (4i-1) th switch circuit to the non-conductive state (4i-1). The main signal line is set in a floating state. That is, a video signal is supplied to the signal line D (4i-1) during a period indicated by a symbol T3 in FIG. 15, and the video signal is supplied to the pixels connected to the gate line G1 and the signal line D (4i-1) during this period. Write.

  Further, by setting Hdrive4 to the H level at the timing indicated by the symbol t4 in FIG. 15, the (4N) th switch circuit connected to the fourth control signal supply line L4 is brought into a conductive state. The video signal is supplied to the line, and Hdrive4 is set to the L level at the timing indicated by t5 in FIG. 15, so that the (4N) -th switch circuit is turned off and the (4N) -th signal line is set to the floating state. To do. That is, a video signal is supplied to the signal line D (4N) in a period indicated by a symbol T4 in FIG. 15, and the video signal is written to the pixels connected to the gate line G1 and the signal line D (4N) in this period.

  As described above, the writing of the video signal to the pixels in the first row is completed. Note that the video signal is written by repeating the same operation for the pixels in the second and subsequent rows.

JP 11-338438 A JP 2001-134245 A

  However, the above-described conventional liquid crystal panel is configured such that a common drive pulse is applied to the switch circuits connected to the k-th signal line of each set, so that a display image is deteriorated. Has occurred. Hereinafter, this point will be described in detail by taking as an example the case where the video signal SIG # 2 is supplied to the signal lines D5 to D8 belonging to the second group.

  Note that the parasitic capacitance generated between the signal lines does not necessarily occur between adjacent signal lines but also between signal lines that are separated from each other, but it has the greatest influence on the potential of the signal line. Since this is a parasitic capacitance between adjacent signal lines, the following description will be made assuming that parasitic capacitance is generated only between adjacent signal lines.

  That is, considering the case where the video signal SIG # 2 is supplied to the signal lines D5 to D8 belonging to the second group and the video signal is written to the pixels, as described above, the period indicated by the symbol T1 in FIG. The video signal is supplied to the signal line D5 at the same time, but the video signal is supplied to the signal line D6 adjacent to the signal line D5 by setting Hdrive2 to the H level at the timing indicated by the symbol t2 in FIG. Will be. When a video signal is supplied to the signal line D6, the parasitic capacitance existing between the signal line D5 and the signal line D6 causes a potential fluctuation of the signal line D5 (reference a in FIG. 16). reference.).

  Further, the video signal is supplied to the signal line D6 in the period indicated by the symbol T2 in FIG. 15. However, by setting the Hdrive3 to the H level at the timing indicated by the symbol t3 in FIG. 15, the signal line D6 is supplied. A video signal is supplied to the adjacent signal line D7. When a video signal is supplied to the signal line D7, the parasitic capacitance existing between the signal line D6 and the signal line D7 causes a potential fluctuation of the signal line D6 (reference b in FIG. 16). reference.).

  Further, the video signal is supplied to the signal line D7 in the period indicated by the symbol T3 in FIG. 15, but by setting the Hdrive4 to the H level at the timing indicated by the symbol t4 in FIG. 15, the signal line D7 is supplied. A video signal is supplied to the adjacent signal line D8. When a video signal is supplied to the signal line D8, the parasitic capacitance existing between the signal line D7 and the signal line D8 causes a potential fluctuation of the signal line D7 (reference c in FIG. 16). reference.). Note that, when a video signal is supplied to the signal line D8 adjacent to the signal line D9, a parasitic capacitance existing between the signal line D8 and the signal line D9 may cause a potential fluctuation of the signal line D9. (See symbol d in FIG. 16).

  Further, by setting Hdrive4 to the H level at the timing indicated by the symbol t4 in FIG. 15, the video signal is supplied to the signal line D4 belonging to the first group. When a video signal is supplied to the signal line D4 adjacent to the signal line D5, the parasitic capacitance existing between the signal line D4 and the signal line D5 causes a potential fluctuation of the signal line D5. (See symbol e in FIG. 16).

  As for the signal line D8, the video signal is supplied during the period indicated by the symbol T4 in FIG. 15. After the video signal is supplied, the video signal is supplied to the signal line adjacent to the signal line D8. Therefore, the parasitic capacitance does not cause potential fluctuation.

  In this manner, the signal line D5 undergoes potential fluctuation due to parasitic capacitance when the video signal is supplied to the signal line D4 and the signal line D6, and the signal line D6 has a parasitic capacitance when the video signal is supplied to the signal line D7. As a result, the potential fluctuation occurs, and the potential fluctuation occurs in the signal line D7 due to the parasitic capacitance when the video signal is supplied to the signal line D8. In other words, the signal line D5 is twice affected by the coupling due to the parasitic capacitance, the signal line D6 and the signal line D7 are once affected by the coupling due to the parasitic capacitance, and the signal line D8 is affected by the coupling due to the parasitic capacitance. It will not receive.

  Therefore, a potential difference becomes significant between a signal line that is affected by the coupling twice and a signal line that is not affected by the coupling, and vertical stripes are generated between pixels connected to the signal line. As a result, the display image deteriorates as described above.

  In Japanese Patent Laid-Open No. 2006-154804, the order in which video signals are written to signal lines within a horizontal period is changed by changing the order in which drive pulses are applied within the horizontal period for each horizontal period or vertical period. There has been proposed a technique for making it difficult to visually recognize vertical stripes by making the potential variation of a signal line generated at the time of writing a video signal uniform over time by making it different for each horizontal period or vertical period. However, such a technique requires control for making the drive pulses input from the drive ICs different for each horizontal period or each vertical period, which makes it very difficult to control the display panel.

  The present invention has been devised in view of the above points, and a display panel that can improve image quality by mitigating the amount of potential fluctuation between signal lines, a driving method thereof, and such a display. It is an object of the present invention to provide a display device and a video display device using a panel.

  In order to achieve the above object, in the display panel according to the present invention, x lines (x: an integer of 2 or more) are grouped together and a video signal for supplying a video signal to the signal line Connected to an arbitrary signal line in a display panel comprising a supply line, a switch circuit that connects the signal line and the video signal supply line, and a control signal supply line that supplies a control signal to turn on the switch circuit The switch circuit is connected to the control signal supply line different from the control signal supply line connected to the switch circuit connected to the other signal line belonging to the same set as the arbitrary signal line. The switch circuit is connected to at least one of the switch circuit connected to the first signal line of each set or the switch circuit connected to the x-th signal line. Are connected to the same said control signal supply line and the switch circuit signal line connected to the signal line adjacent to.

  Here, at least one of the switch circuit connected to the first signal line of each set or the switch circuit connected to the x-th signal line is connected to the signal line to which the switch circuit is connected. Are connected to the same control signal supply line as the switch circuit connected to the signal line adjacent to each other, so that at least one of the first signal line of each set or the xth signal line of each set Is less susceptible to coupling due to parasitic capacitance.

  A switch circuit connected to an arbitrary signal line is connected to a control signal supply line different from a control signal supply line connected to a switch circuit connected to another signal line belonging to the same set as the arbitrary signal line. Since it is connected, it is connected to the same control signal supply line “a switch circuit connected to the first signal line of each set or a switch circuit connected to the x-th signal line” The “signal line to which at least one switch circuit is connected” and “the signal line adjacent to the signal line” are signal lines belonging to different sets.

  In addition, the signal lines are grouped into y groups, and the switch circuit connected to the (y−1) th group of xth signal lines is connected to the yth group of first signal lines. By connecting to the same control signal supply line as the switched switch circuit, all signal lines adjacent to different sets of signal lines are not easily affected by coupling due to parasitic capacitance.

  In order to achieve the above object, in the display panel driving method according to the present invention, x signal lines (x: an integer of 2 or more) are grouped, and video signals are transmitted to the signal lines. And a switch circuit for connecting the signal line and the video signal supply line, the switch circuit connected to the first signal line of each set, The switch circuit connected to a signal line adjacent to the signal line to which the switch circuit is connected and belonging to a different set, at least one of the switch circuits connected to the x-th signal line; The conductive state is made substantially simultaneously.

  Here, at least one of the switch circuit connected to the first signal line of each set or the switch circuit connected to the x-th signal line is connected to the signal line to which the switch circuit is connected. And at least one of the first signal line of each set and the x-th signal line of each set by bringing the switch circuits connected to the signal lines that are adjacent to each other and that belong to a different set substantially simultaneously. Is less susceptible to coupling due to parasitic capacitance.

  In addition, the signal lines are grouped into y groups, and the switch circuit connected to the x-th signal line of the (y−1) -th group is connected to the first signal line of the y-th group. By making the conductive state substantially simultaneously with the switch circuit formed, all the signal lines adjacent to different sets of signal lines are hardly affected by the coupling due to the parasitic capacitance.

  In order to achieve the above object, in the display device according to the present invention, x lines (x: an integer of 2 or more) are grouped together, and video signals are supplied to the signal lines. In a display device including a driver IC, a switch circuit that connects the signal line and the driver IC, and a control signal supply line that supplies a control signal for turning on the switch circuit, the display device is connected to an arbitrary signal line. The switch circuit is connected to the control signal supply line different from the control signal supply line connected to the switch circuit connected to the other signal line belonging to the same set as the arbitrary signal line, and The switch circuit is connected to at least one of the switch circuit connected to the first signal line of the set or the switch circuit connected to the x-th signal line. The signal lines are connected to the same said control signal supply line and connected to the switching circuit to the signal line adjacent.

  In order to achieve the above object, in the video display device according to the present invention, x lines (x: an integer of 2 or more) are grouped together, and video signals are supplied to the signal lines. A display device comprising: a driver IC that performs switching; a switch circuit that connects the signal line and the driver IC; and a control signal supply line that supplies a control signal for bringing the switch circuit into a conductive state, and is modulated by the display device In the video display device that performs video display using the light, the switch circuit connected to an arbitrary signal line includes the switch circuit connected to another signal line belonging to the same set as the arbitrary signal line. The control signal supply line is connected to the control signal supply line different from the connected control signal supply line, and is connected to the switch circuit connected to the first signal line of each set or the xth signal line. At least one of the switching circuits of the switch circuit is connected to the switch circuit identical said control signal supply line and that the switching circuit is connected to the signal line adjacent to the signal line connected to.

  Here, at least one of the switch circuit connected to the first signal line of each set or the switch circuit connected to the x-th signal line is connected to the signal line to which the switch circuit is connected. Are connected to the same control signal supply line as the switch circuit connected to the signal line adjacent to each other, so that at least one of the first signal line of each set or the xth signal line of each set Is less susceptible to coupling due to parasitic capacitance.

  In the display panel and the driving method thereof, the display device, and the video display device of the present invention described above, adjacent signal lines are not easily affected by coupling due to parasitic capacitance, and the potential fluctuation amount between the signal lines is reduced. It is possible to improve image quality.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic diagram for explaining a liquid crystal display device which is an example of a display device to which the present invention is applied. The liquid crystal display device 1 shown here includes a liquid crystal panel 7 and a driver IC 8.

  Like the conventional liquid crystal panel described above, the liquid crystal panel includes a pixel array unit 2 and peripheral circuits for driving each pixel, such as a vertical drive circuit 3, a switch circuit group 4, a buffer group 5, and a precharge circuit 6. The liquid crystal panel 7 is configured such that N system video signals SIG # 1 to SIG # N are input from the driver IC8.

  Here, in the pixel array unit 2, as in the above-described conventional liquid crystal panel, pixels 9 including liquid crystal cells that are electro-optical elements are two-dimensionally arranged in a matrix on a first glass substrate that is a transparent insulating substrate. In this pixel arrangement, m scanning lines G1, G2, G3... Gm are wired for each pixel row, and n signal lines D1, D2, D3. It has been configured. A second glass substrate is disposed opposite to the first glass substrate with a predetermined gap therebetween, and a liquid crystal material is sealed in the gap between the two glass substrates, whereby a liquid crystal panel Is configured.

  As shown in FIG. 2, each pixel 9 includes a pixel transistor, for example, a TFT (Thin Film Transistor) 10, a liquid crystal cell 11 having a pixel electrode connected to the drain of the TFT 10, and a drain connected to the TFT 10. And a storage capacitor 12 to which the electrodes are connected.

  Further, the TFT 10 has a gate connected to the gate line G and a source connected to the signal line D, and the counter electrode of the liquid crystal cell 11 and the other electrode of the storage capacitor 12 are connected to the common line 13 in common for each pixel. ing. A common voltage (counter electrode voltage) VCOM is applied to the common electrode of the liquid crystal cell 11 via the common line 13.

  In addition, the vertical drive circuit 3 is disposed, for example, on the right side of the pixel array unit 2. Here, the case where the vertical drive circuit 3 is arranged on the right side of the pixel array unit 2 is described as an example, but it is described on the left side of the pixel array unit 2 or on the left and right sides of the pixel array unit 2. A vertical drive circuit 3 may be arranged. Here, the vertical drive circuit 3 is configured by a shift register, a buffer circuit, and the like, and outputs vertical scanning pulses in order, and applies the vertical scanning pulses to the scanning lines G of the pixel array unit 2 to thereby make the pixels 9 row by row. Will be selected.

  Further, since the selector driving method (time division driving method) is adopted as the driving method of the signal lines D in the liquid crystal panel, the four signal lines D adjacent to each other in the pixel array unit 2 are set (unit). It is said.

  Further, N (= n / 4) video signals SIG # 1 to SIG # N are input to the signal line D from the driver IC 8 provided outside the liquid crystal panel. The N video signals SIG # 1 to SIG # N are input in a state where signals of four signal lines forming a set are arranged in time series every 1H (H: horizontal scanning period). Are supplied to the N switch circuits SW1, SW2, SW3,... SWN, respectively. Specifically, the driver IC 8 is provided with an output terminal (not shown) corresponding to each set, N system video signals are output from each output terminal, and the output video signals are output terminals and switch circuits. Are supplied to the switch circuit via a video signal supply line connecting the two.

  Further, the N switch circuits SW are connected to the buffers 5-1, 5-2, 5-3, 5- of the buffer group 5 based on drive pulses HSWL1, HSEL2, HSEL3, HSEL4 inputted from the outside of the liquid crystal panel. 4 are sequentially selected in a time division manner in synchronism with the drive pulses Hdrive1, Hdrive2, Hdrive3, and Hdrive4 output from each of the four, and the video signal SIG # is selected for the selected signal lines. Each of 1 to SIG # N is distributed in time division and supplied.

  Here, as shown in FIG. 3, in the (2N-1) th (N: natural number) group in the liquid crystal panel to which the present invention is applied, a switch circuit connected to the first signal line of each group, That is, the switch circuit connected to the (8i-7) th (i: natural number) signal line is connected to the first control signal supply line L1 to which the drive pulse Hdrive1 is supplied, and the second circuit of each set is connected. The switch circuit connected to the signal line, that is, the switch circuit connected to the (8i-6) th signal line is connected to the second control signal supply line L2 to which the drive pulse Hdrive2 is supplied. The switch circuit connected to the third signal line, that is, the switch circuit connected to the (8i-5) th signal line is connected to the third control signal supply line L3 to which the drive pulse Hdrive3 is supplied. Each pair The switch circuit connected to the fourth signal line, that is, the switch circuit connected to the (8i-4) th signal line is connected to the fourth control signal supply line L4 to which the drive pulse Hdrive4 is supplied. Yes.

  On the other hand, in the (2N) th (N: natural number) group, the switch circuit connected to the first signal line of each group, that is, the switch circuit connected to the (8i-3) th signal line. Is connected to the fourth control signal supply line L4 to which the drive pulse Hdrive4 is supplied, and connected to the second signal line of each set, that is, connected to the (8i-2) th signal line. The switch circuit connected to the third control signal supply line L3 to which the drive pulse Hdrive3 is supplied is connected to the third signal line of each set, that is, the (8i-1) th switch circuit. The switch circuit connected to the signal line is connected to the second control signal supply line L2 to which the drive pulse Hdrive2 is supplied, and is connected to the fourth signal line of each set, that is, the (8i) th switch circuit. Main signal line Connected switch circuit is connected to the control signal supply line L1 the drive pulse Hdrive1 is supplied.

Here, in the liquid crystal panel in the liquid crystal display device to which the present invention is applied, all signal lines adjacent to different sets of signal lines are connected to the same control signal supply line as the adjacent different sets of signal lines. However, all signal lines adjacent to a different set of signal lines are always connected to the same control signal supply line as the adjacent different set of signal lines. There is no need, and one of the switch circuits connected to the first signal line of each set or the switch circuit connected to the fourth signal line is connected to the signal line to which this switch circuit is connected. May be connected to the same control signal supply line as the switch circuit connected to the signal line adjacent to the switch circuit.
However, for all signal lines adjacent to a different set of signal lines, if the same control signal supply line is connected to the adjacent different set of signal lines, the quality can be further improved. Can do.

  Hereinafter, a driving method of the liquid crystal display device configured as described above will be described. That is, an example of a display panel driving method to which the present invention is applied will be described. Hereinafter, the switch circuit connected to the jth signal line is referred to as a “jth switch circuit”.

  In the case of driving the liquid crystal display device configured as described above, in order to reduce the burden on the driver IC, first, in the horizontal blanking period, the precharge control pulse PCG is set to logical positive, The precharge signal Psig is written into the signal line.

  Next, with the vertical drive circuit outputting the H level signal to the gate line G1 in the first row and selecting the gate line G1, the first level is obtained by setting Hdrive1 to the H level at the timing indicated by the symbol t1 in FIG. The (8i-7) th switch circuit and the (8i) th switch circuit connected to the control signal supply line L1 are turned on, and the (8i-7) th signal line and the (8i) th switch circuit are turned on. The video signal is supplied to the signal line, and Hdrive1 is set to the L level at the timing indicated by reference numeral t2 in FIG. 4, thereby setting the (8i-7) -th switch circuit and the (8i) -th switch circuit in the non-conductive state. The (8i-7) th signal line and the (8i) th signal line are set in a floating state. That is, a video signal is supplied to the signal line D (8i-7) and the signal line D (8i) in a period indicated by a symbol T1 in FIG. 4, and in this period, the gate line G1, the signal line D (8i-7), and the gate A video signal is written to the pixels connected to the line G1 and the signal line D (8i).

  In addition, by setting Hdrive2 to the H level at the timing indicated by the symbol t2 in FIG. 4, the (8i-6) th switch circuit connected to the second control signal supply line L2 and the (8i-1) th switch circuit are connected. The switch circuit is turned on to supply a video signal to the (8i-6) th signal line and the (8i-1) th signal line, and Hdrive2 is set to L level at the timing indicated by symbol t3 in FIG. Then, the (8i-6) th switch circuit and the (8i-1) th switch circuit are made non-conductive, and the (8i-6) th signal line and the (8i-1) th signal line are floated. State. That is, a video signal is supplied to the signal line D (8i-6) and the signal line D (8i-1) in a period indicated by a symbol T2 in FIG. 4, and the gate line G1 and the signal line D (8i-6) are supplied in this period. Then, the video signal is written to the pixel connected to the gate line G1 and the signal line D (8i-1).

  Further, by setting Hdrive3 to the H level at the timing indicated by the symbol t3 in FIG. 4, the (8i-5) th switch circuit connected to the third control signal supply line L3 and the (8i-2) th switch circuit are connected. The switch circuit is turned on to supply a video signal to the (8i-5) th signal line and the (8i-2) th signal line, and Hdrive3 is set to the L level at the timing indicated by t4 in FIG. Then, the (8i-5) th switch circuit and the (8i-2) th switch circuit are turned off, and the (8i-5) th signal line and the (8i-2) th signal line are floated. State. That is, the video signal is supplied to the signal line D (8i-5) and the signal line D (8i-2) in the period indicated by the symbol T3 in FIG. 4, and the gate line G1 and the signal line D (8i-5) are supplied in this period. Then, the video signal is written to the pixel connected to the gate line G1 and the signal line D (8i-3).

  In addition, by setting Hdrive4 to H level at the timing indicated by the symbol t4 in FIG. 4, the (8i-4) th switch circuit and the (8i-3) th switch connected to the fourth control signal supply line L4. By turning the circuit into a conductive state, supplying the video signal to the (8i-4) th signal line and the (8i-3) th signal line, and setting Hdrive4 to the L level at the timing indicated by t5 in FIG. The (8i-4) th switch circuit and the (8i-3) th switch circuit are turned off, and the (8i-4) th signal line and the (8i-3) th signal line are in a floating state. And That is, a video signal is supplied to the signal line D (8i-4) and the signal line D (8i-3) in a period indicated by a symbol T4 in FIG. 4, and the gate line G1 and the signal line D (8i-4) are supplied in this period. Then, the video signal is written to the pixel connected to the gate line G1 and the signal line D (8i-3).

  As described above, the writing of the video signal to the pixels in the first row is completed. Note that the video signal is written by repeating the same operation for the pixels in the second and subsequent rows.

In the liquid crystal display device described above, the occurrence of vertical stripes can be reduced as compared with the conventional liquid crystal display device, and the image quality is improved.
Hereinafter, regarding this point, the video signal SIG # 1 is supplied to the signal lines D1 to D4 belonging to the first group, and the video signal SIG # 2 to the signal lines D5 to D8 belonging to the second group. This will be described in detail by taking as an example the case of supplying.

  Note that the parasitic capacitance generated between the signal lines does not necessarily occur between adjacent signal lines but also between signal lines that are separated from each other, but it has the greatest influence on the potential of the signal line. Since this is a parasitic capacitance between adjacent signal lines, the following description will be made assuming that parasitic capacitance is generated only between adjacent signal lines.

  That is, the video signal SIG # 1 is supplied to the signal lines D1 to D4 belonging to the first group, and the video signal SIG # 2 is supplied to the signal lines D5 to D8 belonging to the second group. Considering the case of writing a video signal to the pixel, as described above, the video signal is supplied to the signal line D1 and the signal line D8 in the period indicated by the symbol T1 in FIG. By setting Hdrive2 to the H level at the timing indicated by t2, the video signal is supplied to the signal line D2 and the signal line D7 adjacent to the signal line D1 and the signal line D8. When a video signal is supplied to the signal line D2, the potential fluctuation of the signal line D1 is caused by the parasitic capacitance existing between the signal line D1 and the signal line D2 (reference a in FIG. 5). reference.). Similarly, when a video signal is supplied to the signal line D7, the parasitic capacitance existing between the signal line D7 and the signal line D8 causes the potential fluctuation of the signal line D8 (see the sign in FIG. 5). b)).

  Further, the video signal is supplied to the signal line D2 and the signal line D7 in the period indicated by the symbol T2 in FIG. 4, but by setting the Hdrive3 to the H level at the timing indicated by the symbol t3 in FIG. A video signal is supplied to the signal line D3 and the signal line D6 adjacent to the signal line D2 and the signal line D7. When the video signal is supplied to the signal line D3, the parasitic capacitance existing between the signal line D2 and the signal line D3 causes the potential fluctuation of the signal line D2 (reference c in FIG. 5). reference.). Similarly, when a video signal is supplied to the signal line D6, a potential fluctuation of the signal line D7 is caused by a parasitic capacitance existing between the signal line D6 and the signal line D7 (indicated by reference numerals in FIG. 5). see d).

  Further, the video signal is supplied to the signal line D3 and the signal line D6 in the period indicated by the symbol T3 in FIG. 4, but by setting the Hdrive4 to the H level at the timing indicated by the symbol t4 in FIG. A video signal is supplied to the signal line D4 and the signal line D5 adjacent to the signal line D3 and the signal line D6. When a video signal is supplied to the signal line D4, the parasitic capacitance existing between the signal line D3 and the signal line D4 causes a potential fluctuation of the signal line D3 (reference e in FIG. 5). reference.). Similarly, when a video signal is supplied to the signal line D5, a potential fluctuation of the signal line D6 is caused by a parasitic capacitance existing between the signal line D5 and the signal line D6 (reference numeral in FIG. 5). see f).

  As for the signal line D4 and the signal line D5, the video signal is supplied during the period indicated by the symbol T4 in FIG. 4, but the video signal is supplied to the adjacent signal line after the video signal is supplied. Therefore, the parasitic capacitance does not cause potential fluctuation.

  In this way, the signal line D1 undergoes potential fluctuation due to parasitic capacitance when the video signal is supplied to the signal line D2, and the signal line D2 undergoes potential fluctuation due to parasitic capacitance when the video signal is supplied to the signal line D3. The signal line D3 undergoes potential fluctuation due to parasitic capacitance when the video signal is supplied to the signal line D4, and the signal line D6 undergoes potential fluctuation due to parasitic capacitance when the video signal is supplied to the signal line D5. When the video signal is supplied to the signal line D6, the signal line D7 changes in potential due to the parasitic capacitance, and when the video signal is supplied to the signal line D7, the signal line D8 changes in potential due to the parasitic capacitance. . In other words, the signal line D1, the signal line D2, the signal line D3, the signal line D6, the signal line D7, and the signal line D8 are once affected by the coupling due to the parasitic capacitance, and the signal line D4 and the signal line D5 are caused by the parasitic capacitance. It means that it is not affected by the coupling.

  Therefore, in the conventional liquid crystal display device, the signal line affected by the coupling twice and the signal line not affected by the coupling are generated, whereas in the liquid crystal display device to which the present invention is applied, the signal line is once. Only the signal lines that are affected by the coupling and the signal lines that are not affected by the coupling are generated. As described above, the occurrence of vertical stripes can be reduced as compared with the conventional liquid crystal display device. Improvement of quality will be realized.

  FIG. 6 is a schematic diagram showing a connection state between the control signal supply line and the switch circuit in the modification (1) of the liquid crystal panel to which the present invention is applied. The liquid crystal panel in the modification (1) to which the present invention is applied is shown in FIG. In the (2N-1) th (N: natural number) group, the switch circuit connected to the first signal line of each group, that is, the (8i-7) th (i: natural number) signal line is connected. The switch circuit connected to the first control signal supply line L1 is connected to the second signal line of each set, that is, the switch connected to the (8i-6) th signal line. The circuit is connected to the third control signal supply line L3, and the switch circuit connected to the third signal line of each set, that is, the switch circuit connected to the (8i-5) th signal line is the first. 2 control signal supply lines L2 and the fourth signal line of each set Connected switch circuit, i.e., the (8i-4) a switching circuit connected to the first signal line is connected to a fourth control signal supply line L4.

  On the other hand, in the (2N) th (N: natural number) group, the switch circuit connected to the first signal line of each group, that is, the switch circuit connected to the (8i-3) th signal line. Is connected to the fourth control signal supply line L4, and the switch circuit connected to the second signal line of each set, that is, the switch circuit connected to the (8i-2) th signal line is the second. The switch circuit connected to the control signal supply line L2 and connected to the third signal line of each set, that is, the switch circuit connected to the (8i-1) th signal line is the third control signal. The switch circuit connected to the fourth signal line of each set connected to the supply line L3, that is, the switch circuit connected to the (8i) th signal line is connected to the first control signal supply line L1. Has been.

  Hereinafter, a method for driving a liquid crystal display device having the liquid crystal display panel configured as described above will be described. That is, another example of a display panel driving method to which the present invention is applied will be described.

  In the case of driving the liquid crystal display device configured as described above, in order to reduce the burden on the driver IC, first, in the horizontal blanking period, the precharge control pulse PCG is set to logical positive, The precharge signal Psig is written into the signal line.

  Next, with the vertical drive circuit outputting an H level signal to the gate line G1 in the first row and selecting the gate line G1, the first level is obtained by setting Hdrive1 to the H level at the timing indicated by the symbol t1 in FIG. The (8i-7) th switch circuit and the (8i) th switch circuit connected to the control signal supply line L1 are turned on, and the (8i-7) th signal line and the (8i) th switch circuit are turned on. The video signal is supplied to the signal line, and the Hdrie1 is set to the L level at the timing indicated by the symbol t2 in FIG. 7, so that the (8i-7) -th switch circuit and the (8i) -th switch circuit are turned off. The (8i-7) th signal line and the (8i) th signal line are set in a floating state. That is, a video signal is supplied to the signal line D (8i-7) and the signal line D (8i) in a period indicated by a symbol T1 in FIG. 7, and the gate line G1, the signal line D (8i-7), and the gate are supplied in this period. A video signal is written to the pixel connected to the line G1 and the gate line D (8i).

  In addition, by setting Hdrive2 to the H level at the timing indicated by the symbol t2 in FIG. 7, the (8i-5) th switch circuit connected to the second control signal supply line L2 and the (8i-2) th switch circuit are connected. The switch circuit is turned on to supply the video signal to the (8i-5) th signal line and the (8i-2) th signal line, and Hdrive2 is set to the L level at the timing indicated by reference numeral t3 in FIG. Then, the (8i-5) th switch circuit and the (8i-2) th switch circuit are turned off, and the (8i-5) th signal line and the (8i-2) th signal line are floated. State. That is, a video signal is supplied to the signal line D (8i-5) and the signal line D (8i-2) in a period indicated by a symbol T2 in FIG. 7, and the gate line G1 and the signal line D (8i-5) are supplied in this period. Then, the video signal is written to the pixel connected to the gate line G1 and the signal line D (8i-2).

  In addition, by setting Hdrive3 to the H level at the timing indicated by the symbol t3 in FIG. 7, the (8i-6) th switch circuit connected to the third control signal supply line L3 and the (8i-1) th switch circuit are connected. The switch circuit is turned on to supply a video signal to the (8i-6) th signal line and the (8i-1) th signal line, and Hdrive3 is set to L level at the timing indicated by t4 in FIG. Then, the (8i-6) th switch circuit and the (8i-1) th switch circuit are made non-conductive, and the (8i-6) th signal line and the (8i-1) th signal line are floated. State. That is, a video signal is supplied to the signal line D (8i-6) and the signal line D (8i-1) in a period indicated by a symbol T3 in FIG. 7, and the gate line G1 and the signal line D (8i-6) are supplied in this period. Then, the video signal is written to the pixel connected to the gate line G1 and the signal line D (8i-1).

  In addition, by setting Hdrive4 to the H level at the timing indicated by the symbol t4 in FIG. 7, the (8i-4) th switch circuit and the (8i-3) th switch circuit connected to the fourth control signal supply line L4. The switch circuit is turned on to supply a video signal to the (8i-4) th signal line and the (8i-3) th signal line, and Hdrive4 is set to L level at the timing indicated by t5 in FIG. Then, the (8i-4) th switch circuit and the (8i-3) th switch circuit are turned off, and the (8i-4) th signal line and the (8i-3) th signal line are floated. State. That is, a video signal is supplied to the signal line D (8i-4) and the signal line D (8i-3) in a period indicated by a symbol T4 in FIG. 7, and the gate line G1 and the signal line D (8i-4) are supplied in this period. Then, the video signal is written to the pixel connected to the gate line G1 and the signal line D (8i-3).

  As described above, the writing of the video signal to the pixels in the first row is completed. Note that the video signal is written by repeating the same operation for the pixels in the second and subsequent rows.

In the liquid crystal display device described above, the occurrence of vertical stripes can be reduced as compared with the conventional liquid crystal display device, and the image quality is improved.
Hereinafter, regarding this point, the video signal SIG # 1 is supplied to the signal lines D1 to D4 belonging to the first group, and the video signal SIG # 2 to the signal lines D5 to D8 belonging to the second group. This will be described in detail by taking as an example the case of supplying.

  That is, the video signal SIG # 1 is supplied to the signal lines D1 to D4 belonging to the first group, and the video signal SIG # 2 is supplied to the signal lines D5 to D8 belonging to the second group. Considering the case where the video signal is written to the pixel, as described above, the video signal is supplied to the signal line D1 and the signal line D8 in the period indicated by the symbol T1 in FIG. By setting Hdrive3 to the H level at the timing indicated by t3, the video signal is supplied to the signal line D2 and the signal line D7 adjacent to the signal line D1 and the signal line D8. When a video signal is supplied to the signal line D2, the potential fluctuation of the signal line D1 is caused by the parasitic capacitance existing between the signal line D1 and the signal line D2 (reference a in FIG. 8). reference.). Similarly, when a video signal is supplied to the signal line D7, the parasitic capacitance existing between the signal line D7 and the signal line D8 causes a potential fluctuation of the signal line D8 (reference numeral in FIG. 8). b)).

  In addition, the video signal is supplied to the signal line D3 and the signal line D6 in the period indicated by the symbol T2 in FIG. 7, but by setting the Hdrive4 to the H level at the timing indicated by the symbol t4 in FIG. A video signal is supplied to the signal line D4 and the signal line D5. When a video signal is supplied to the signal line D4, the parasitic capacitance existing between the signal line D3 and the signal line D4 causes a potential fluctuation of the signal line D3 (reference c in FIG. 5). reference.). Similarly, when a video signal is supplied to the signal line D5, a potential fluctuation of the signal line D6 is caused by a parasitic capacitance existing between the signal line D5 and the signal line D6 (reference numeral in FIG. 5). see d).

  Note that a video signal is supplied to the signal line D2 and the signal line D7 in a period indicated by a symbol T3 in FIG. 7, and a video signal is supplied to the signal line D4 and the signal line D5 in a period indicated by a symbol T4 in FIG. However, since the video signal is not supplied to the adjacent signal line after the video signal is supplied, the potential fluctuation is not caused by the parasitic capacitance.

  Thus, the signal line D1 undergoes potential fluctuations due to parasitic capacitance when the video signal is supplied to the signal line D2, and the signal line D3 undergoes potential fluctuations due to parasitic capacitance when the video signal is supplied to the signal line D4. As a result, the potential fluctuation of the signal line D6 occurs due to the parasitic capacitance when the video signal is supplied to the signal line D5, and the potential fluctuation occurs due to the parasitic capacitance when the video signal is supplied to the signal line D7. It becomes. In other words, the signal line D1, the signal line D3, the signal line D6, and the signal line D8 are once affected by the coupling due to the parasitic capacitance, and the signal line D2, the signal line D4, the signal line D5, and the signal line D7 are caused by the parasitic capacitance. It means that it is not affected by the coupling.

  Accordingly, in the conventional liquid crystal display device, the signal line that is affected by the coupling twice and the signal line that is not affected by the coupling are generated, whereas a modification of the liquid crystal display device to which the present invention is applied. In (1), only signal lines that are affected by the coupling and signal lines that are not affected by the coupling are generated. As described above, the occurrence of vertical stripes is reduced as compared with the conventional liquid crystal display device. It is possible to improve the image quality.

  FIG. 9 is a schematic diagram showing a connection state between the control signal supply line and the switch circuit in the modification (2) of the liquid crystal panel to which the present invention is applied. In the modification (2) of the liquid crystal panel to which the present invention is applied, A switch circuit connected to the first signal line of each group in the (2N-1) th (N: natural number) group, with six signal lines D adjacent to each other as a group (unit). That is, the switch circuit connected to the (12i-11) th (i: natural number) signal line is connected to the first control signal supply line L1 and connected to the second signal line of each set. The switch circuit, that is, the switch circuit connected to the (12i-10) th signal line is connected to the second control signal supply line L2, and is connected to the third signal line of each set, That is, the switch connected to the (12i-9) th signal line. The circuit is connected to the third control signal supply line L3, and the switch circuit connected to the fourth signal line of each set, that is, the switch circuit connected to the (12i-8) th signal line is the first. The switch circuit connected to the fourth control signal supply line L4 and connected to the fifth signal line of each set, that is, the switch circuit connected to the (12i-7) th signal line is the fifth control line. The switch circuit connected to the signal supply line L5 and connected to the sixth signal line of each set, that is, the switch circuit connected to the (12i-6) th signal line is the sixth control signal supply line. L6 is connected.

  On the other hand, in the (2N) th (N: natural number) group, the switch circuit connected to the first signal line of each group, that is, the switch circuit connected to the (12i-5) th signal line. Is connected to the sixth control signal supply line L6, and the switch circuit connected to the second signal line of each set, that is, the switch circuit connected to the (12i-4) th signal line is the fifth. The switch circuit connected to the control signal supply line L5 and connected to the third signal line of each set, that is, the switch circuit connected to the (12i-3) th signal line is the fourth control signal. The switch circuit connected to the supply line L4 and connected to the fourth signal line of each set, that is, the switch circuit connected to the (12i-2) th signal line is the third control signal supply line L3. And a switch circuit connected to the fifth signal line of each set That is, the switch circuit connected to the (12i-1) th signal line is connected to the second control signal supply line L2, and the switch circuit connected to the sixth signal line of each set, (12i) The switch circuit connected to the first signal line is connected to the first control signal supply line L1.

  Hereinafter, a method for driving a liquid crystal display device having the liquid crystal display panel configured as described above will be described. That is, another example of the display panel driving method to which the present invention is applied will be described.

  In the case of driving the liquid crystal display device configured as described above, in order to reduce the burden on the driver IC, first, in the horizontal blanking period, the precharge control pulse PCG is set to logical positive, The precharge signal Psig is written into the signal line.

  Next, with the vertical drive circuit outputting an H level signal to the gate line G1 in the first row and selecting the gate line G1, Hdrive1 is set to the H level at the timing indicated by the symbol t1 in FIG. The (12i-11) th switch circuit and the (12i) th switch circuit connected to the control signal supply line L1 are turned on, and the (12i-11) th signal line and the (12i) th switch circuit are turned on. The video signal is supplied to the signal line, and Hdrive1 is set to the L level at the timing indicated by the symbol t2 in FIG. 10 to turn off the (12i-11) th switch circuit and the (12i) th switch circuit. The (12i-11) th signal line and the (12i) th signal line are set in a floating state. That is, a video signal is supplied to the signal line D (12i-11) and the signal line D (12i) in a period indicated by a symbol T1 in FIG. 10, and the gate line G1, the signal line D (12i-11), and the gate are supplied in this period. A video signal is written to the pixels connected to the line G1 and the signal line D (12i).

  Further, by setting Hdrive2 to the H level at the timing indicated by the symbol t2 in FIG. 10, the (12i-10) th switch circuit connected to the second control signal supply line L2 and the (12i-1) th switch circuit are connected. The switch circuit is turned on to supply a video signal to the (12i-10) th signal line and the (12i-1) th signal line, and Hdrive2 is set to the L level at the timing indicated by symbol t3 in FIG. Thus, the (12i-10) th switch circuit and the (12i-1) th switch circuit are turned off, and the (12i-10) th signal line and the (12i-1) th signal line are floated. State. That is, a video signal is supplied to the signal line D (12i-10) and the signal line D (12i-1) in a period indicated by a symbol T2 in FIG. 10, and the gate line G1 and the signal line D (12i-10) are supplied in this period. Then, the video signal is written to the pixel connected to the gate line G1 and the signal line D (12i-1).

  In addition, by setting Hdrive3 to the H level at the timing indicated by the symbol t3 in FIG. 10, the (12i-9) th switch circuit and the (12i-2) th switch circuit connected to the third control signal supply line L3. The switch circuit is turned on to supply the video signal to the (12i-9) th signal line and the (12i-2) th signal line, and Hdrive3 is set to the L level at the timing indicated by t4 in FIG. Then, the (12i-9) th switch circuit and the (12i-2) th switch circuit are turned off, and the (12i-9) th signal line and the (12i-2) th signal line are floated. State. That is, a video signal is supplied to the signal line D (12i-9) and the signal line D (12i-2) in a period indicated by a symbol T3 in FIG. 10, and the gate line G1 and the signal line D (12i-9) are supplied in this period. The video signal is written to the pixel connected to the gate line G1 and the signal line D (12i-2).

  In addition, by setting Hdrive4 to the H level at the timing indicated by the symbol t4 in FIG. 10, the (12i-8) th switch circuit and the (12i-3) th switch circuit connected to the fourth control signal supply line L4. The switch circuit is turned on to supply a video signal to the (12i-8) th signal line and the (12i-3) th signal line, and Hdrive4 is set to L level at the timing indicated by t5 in FIG. Then, the (12i-8) th switch circuit and the (12i-3) th switch circuit are made non-conductive, and the (12i-8) th signal line and the (12i-3) th signal line are floated. State. That is, a video signal is supplied to the signal line D (12i-8) and the signal line D (12i-3) in a period indicated by a symbol T4 in FIG. 10, and the gate line G1 and the signal line D (12i-8) are supplied in this period. The video signal is written to the pixel connected to the gate line G1 and the signal line D (12i-3).

  In addition, by setting Hdrive5 to the H level at the timing indicated by the symbol t5 in FIG. 10, the (12i-7) th switch circuit connected to the fifth control signal supply line L5 and the (12i-4) th switch circuit are connected. The switch circuit is turned on to supply the video signal to the (12i-7) th signal line and the (12i-4) th signal line, and Hdrive5 is set to the L level at the timing indicated by symbol t6 in FIG. Thus, the (12i-7) th switch circuit and the (12i-4) th switch circuit are made non-conductive, and the (12i-7) th signal line and the (12i-4) th signal line are floated. State. That is, a video signal is supplied to the signal line D (12i-7) and the signal line D (12i-4) in a period indicated by a symbol T5 in FIG. 10, and the gate line G1 and the signal line D (12i-7) are supplied in this period. Then, the video signal is written to the pixel connected to the gate line G1 and the signal line D (12i-4).

  In addition, by setting Hdrive6 to the H level at the timing indicated by the symbol t6 in FIG. 10, the (12i-6) th switch circuit and the (12i-5) th switch circuit connected to the fifth control signal supply line L6. The switch circuit is turned on to supply the video signal to the (12i-6) th signal line and the (12i-5) th signal line, and Hdrive6 is set to the L level at the timing indicated by t7 in FIG. Then, the (12i-6) th switch circuit and the (12i-5) th switch circuit are made non-conductive, and the (12i-6) th signal line and the (12i-5) th signal line are floated. State. That is, the video signal is supplied to the signal line D (12i-6) and the signal line D (12i-5) in the period indicated by the symbol T6 in FIG. 10, and the gate line G1 and the signal line D (12i-6) are supplied in this period. The video signal is written to the pixel connected to the gate line G1 and the signal line D (12i-5).

  As described above, the writing of the video signal to the pixels in the first row is completed. Note that the video signal is written by repeating the same operation for the pixels in the second and subsequent rows.

In the liquid crystal display device described above, the occurrence of vertical stripes can be reduced as compared with the conventional liquid crystal display device, and the image quality is improved.
Hereinafter, regarding this point, the video signal SIG # 1 is supplied to the signal lines D1 to D6 belonging to the first group, and the video signal SIG # 2 is supplied to the signal lines D7 to D12 belonging to the second group. This will be described in detail by taking as an example the case of supplying.

  That is, the video signal SIG # 1 is supplied to the signal lines D1 to D6 belonging to the first group, and the video signal SIG # 2 is supplied to the signal lines D7 to D12 belonging to the second group. Considering the case of writing a video signal to the pixel, as described above, the video signal is supplied to the signal line D1 and the signal line D12 in the period indicated by the symbol T1 in FIG. By setting Hdrive2 to the H level at the timing indicated by t2, the video signal is supplied to the signal line D2 and the signal line D11 adjacent to the signal line D1 and the signal line D12. When a video signal is supplied to the signal line D2, the potential fluctuation of the signal line D1 is caused by the parasitic capacitance existing between the signal line D1 and the signal line D2 (reference a in FIG. 11). reference.). Similarly, when a video signal is supplied to the signal line D11, the potential fluctuation of the signal line D12 is caused by the parasitic capacitance existing between the signal line D11 and the signal line D12 (see reference symbol b in FIG. 11). ).

  In addition, the video signal is supplied to the signal line D2 and the signal line D11 in the period indicated by the symbol T2 in FIG. 10, but by setting Hdrive3 to the H level at the timing indicated by the symbol t3 in FIG. A video signal is supplied to the signal line D3 and the signal line D10 adjacent to the signal line D2 and the signal line D11. Then, when a video signal is supplied to the signal line D3, a potential fluctuation of the signal line D2 is caused by a parasitic capacitance existing between the signal line D2 and the signal line D3 (reference c in FIG. 11). reference.). Similarly, when a video signal is supplied to the signal line D10, a potential fluctuation of the signal line D11 is caused by a parasitic capacitance existing between the signal line D10 and the signal line D11 (see reference numeral d in FIG. 11). ).

  Further, the video signal is supplied to the signal line D3 and the signal line D10 in the period indicated by the symbol T3 in FIG. 10, but by setting the Hdrive4 to the H level at the timing indicated by the symbol t4 in FIG. A video signal is supplied to the signal line D4 and the signal line D9 adjacent to the signal line D3 and the signal line D10. When a video signal is supplied to the signal line D4, the parasitic capacitance existing between the signal line D3 and the signal line D4 causes a change in the potential of the signal line D3 (symbol e in FIG. 11). reference.). Similarly, when a video signal is supplied to the signal line D9, the potential fluctuation of the signal line D10 is caused by the parasitic capacitance existing between the signal line D9 and the signal line D10 (see reference f in FIG. 11). ).

  In addition, the video signal is supplied to the signal line D4 and the signal line D9 in the period indicated by the symbol T4 in FIG. 10, but by setting the Hdrive5 to the H level at the timing indicated by the symbol t5 in FIG. A video signal is supplied to the signal line D5 and the signal line D8 adjacent to the signal line D4 and the signal line D9. When the video signal is supplied to the signal line D5, the parasitic capacitance existing between the signal line D4 and the signal line D5 causes the potential variation of the signal line D4 (see symbol g in FIG. 11). reference.). Similarly, when a video signal is supplied to the signal line D8, the potential fluctuation of the signal line D9 is caused by the parasitic capacitance existing between the signal line D8 and the signal line D9 (see symbol h in FIG. 11). ).

  Further, the video signal is supplied to the signal line D5 and the signal line D8 in the period indicated by the symbol T5 in FIG. 10, but by setting Hdrive6 to the H level at the timing indicated by the symbol t6 in FIG. A video signal is supplied to the signal line D6 and the signal line D7 adjacent to the signal line D5 and the signal line D8. When a video signal is supplied to the signal line D6, the parasitic capacitance existing between the signal line D5 and the signal line D6 causes the potential fluctuation of the signal line D5 (see symbol i in FIG. 11). reference.). Similarly, when a video signal is supplied to the signal line D7, a potential fluctuation of the signal line D8 is caused by a parasitic capacitance existing between the signal line D7 and the signal line D8 (refer to a symbol j in FIG. 11). ).

  Note that the video signal is supplied to the signal line D6 and the signal line D7 in the period indicated by the symbol T6 in FIG. 10, but after the video signal is supplied, the video signal is supplied to the adjacent signal line. Therefore, the parasitic capacitance does not cause potential fluctuation.

  In this way, the signal line D1 undergoes potential fluctuation due to parasitic capacitance when the video signal is supplied to the signal line D2, and the signal line D2 undergoes potential fluctuation due to parasitic capacitance when the video signal is supplied to the signal line D3. When the video signal is supplied to the signal line D4, the potential fluctuation occurs due to the parasitic capacitance, and the signal line D4 causes the potential fluctuation due to the parasitic capacitance when the video signal is supplied to the signal line D5. When the video signal is supplied to the signal line D6, the signal line D5 undergoes potential fluctuation due to the parasitic capacitance, and when the video signal is supplied to the signal line D7, the signal line D8 undergoes potential fluctuation due to the parasitic capacitance. D9 has a potential fluctuation caused by parasitic capacitance when a video signal is supplied to the signal line D8, and the signal line D10 has a potential fluctuation caused by parasitic capacitance when a video signal is supplied to the signal line D9. Route D10 occurs potential fluctuation due to the parasitic capacitance when the video signal is supplied to the signal line D12 becomes the potential fluctuation is caused by parasitic capacitance in the video signal to the signal line D11 is supplied. In other words, the signal line D1, the signal line D2, the signal line D3, the signal line D4, the signal line D5, the signal line D8, the signal line D9, the signal line D10, the signal line D11, and the signal line D12 are affected by coupling due to parasitic capacitance. Therefore, the signal line D6 and the signal line D7 are not affected by the coupling due to the parasitic capacitance.

  Accordingly, in the conventional liquid crystal display device, the signal line that is affected by the coupling twice and the signal line that is not affected by the coupling are generated. In (2), only a signal line that is affected by one coupling and a signal line that is not affected by the coupling are generated. It is possible to improve the image quality.

  Here, in the display panel to which the present invention is applied, a liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel is described as an example, but the display panel is limited to the liquid crystal display panel. For example, an EL display panel using an EL element may be used as the electro-optical element of the pixel. The pixel including the electro-optical element is two-dimensionally arranged in a matrix, and a selector driving method (time-division driving). Any display panel may be used as long as it adopts a method.

  In the display device to which the present invention is applied, the case where four signal lines are combined and the case where six signal lines are combined is described as an example. Of course, the number is not limited to these.

In the display device to which the present invention is applied, the switch circuit connected to the first signal line in each set is connected to the xth signal line (x: the number of signal lines in one set). Take as an example a case where the switch circuit is sequentially turned on, or the switch circuit connected to the x-th signal line in each set is sequentially turned on from the switch circuit connected to the first signal line. Although described, the switch circuit connected to the x-th signal line from the switch circuit connected to the first signal line or the switch circuit connected to the x-th signal line is not necessarily used. It is not necessary to sequentially turn on the switch circuit connected to the first signal line.
However, in each set, the switch circuit connected to the first signal line to the switch circuit connected to the x-th signal line (x: the number of signal lines in one set) is sequentially turned on, or It is considered that the video signal control in the driver IC can be facilitated by sequentially conducting the switch circuit connected to the x-th signal line to the switch circuit connected to the first signal line in the set. .

  FIG. 12 is a schematic diagram for explaining a transmissive liquid crystal projector which is an example of an image display device to which the present invention is applied. The transmissive liquid crystal projector 100 shown here is a so-called three-plate system that uses red, green, and blue. This is a projection-type image display device that uses a liquid crystal display device to which the present invention is applied to three light valves corresponding to three primary colors and displays a color image enlarged and projected on a screen (not shown).

  Specifically, the transmissive liquid crystal projector includes a lamp 101 that is a light source that emits illumination light, an R dichroic mirror 103R that reflects only red light (R) among illumination light from the lamp, and illumination light from the lamp. Among them, a G dichroic mirror 103G that reflects only green light (G), and an R light valve 104R that is a light modulation means that modulates and transmits red light (R), green light (G), and blue light (B). , G light valve 104G and B light valve 104B, dichroic prism 105 which is a combining optical means for combining modulated red light (R), green light (G), and blue light (B), and combined illumination light And a projection lens 106 which is a projection means for projecting the image onto the screen.

  Here, the lamp emits white light including red light (R), green light (G), and blue light (B), and includes, for example, a halogen lamp, a metal halogen lamp, a xenon lamp, or the like.

  Further, in the optical path between the lamp and the R dichroic mirror, a filter 109 that cuts infrared rays and ultraviolet rays, a fly-eye lens 107 that equalizes the illuminance distribution of the illumination light emitted from the lamp, and the P of the illumination light , A polarization conversion element 108 for converting the S polarization component into one polarization component (for example, S polarization component) is disposed.

  Further, a total reflection mirror 110 that reflects red light (R) toward the R light valve is arranged between the R dichroic mirror and the R light valve, and between the G dichroic mirror and the B light valve, A total reflection mirror 110 that reflects blue light (B) toward the B light valve is disposed, and a relay lens 111 is disposed.

  The projection lens has a function of enlarging and projecting light from the dichroic prism toward the screen.

  In the transmissive liquid crystal projector configured as described above, the white light emitted from the lamp is separated into red light (R), green light (G), and blue light (B) by the R dichroic mirror and the G dichroic mirror. . The separated red light (R), green light (G), and blue light (B) are incident on each light valve via the condenser lens 112. Red light (R), green light (G), and blue light (B) incident on each light valve are subjected to polarization modulation in accordance with a driving voltage applied to each pixel of each light valve, and then are dichroic prism. The synthesized light is enlarged and projected on the screen by the projection lens.

  As described above, in this transmissive liquid crystal projector, a color image is displayed by enlarging and projecting an image corresponding to the light modulated by the light valve on the screen.

  By the way, since the liquid crystal display device constituting each light valve can reduce the occurrence of vertical stripes as described above, the transmission type projector shown here can also reduce the occurrence of vertical stripes. Improvement of quality will be realized.

  In the present embodiment, a projection type video display device that projects onto a screen like a transmission type projector has been described as an example. However, the present invention is a direct view type video display device that directly looks at a liquid crystal display device. Also widely applicable.

It is a schematic diagram for demonstrating the liquid crystal display device which is an example of the display apparatus to which this invention is applied. It is a circuit diagram which shows an example of the circuit structure of a pixel. It is a circuit diagram which shows the connection state of a control signal supply line and a switch circuit. It is a timing chart which shows the circuit operation of a liquid crystal display. It is a figure for demonstrating the electric potential fluctuation | variation of the signal line at the time of circuit operation | movement of a liquid crystal display device. It is a schematic diagram which shows the connection state of the control signal supply line and switch circuit in the modification (1) of the liquid crystal panel to which this invention is applied. It is a timing chart which shows the circuit operation | movement of the modification (1) of a liquid crystal display device. It is a figure for demonstrating the electric potential fluctuation | variation of the signal line at the time of circuit operation | movement of the modification (1) of a liquid crystal display device. It is a schematic diagram which shows the connection state of the control signal supply line and switch circuit in the modification (2) of the liquid crystal panel to which this invention is applied. It is a timing chart which shows the circuit operation | movement of the modification (2) of a liquid crystal display device. It is a figure for demonstrating the electric potential fluctuation | variation of the signal line at the time of circuit operation | movement of the modification (2) of a liquid crystal display device. It is a schematic diagram for demonstrating the transmissive liquid crystal projector which is an example of the video display apparatus to which this invention is applied. It is a schematic diagram for demonstrating the conventional liquid crystal display device. It is a circuit diagram which shows the connection state of the control signal supply line and switch circuit in the conventional liquid crystal display device. It is a timing chart which shows the circuit operation | movement of the conventional liquid crystal display device. It is a figure for demonstrating the electric potential fluctuation | variation of the signal line at the time of circuit operation | movement of the conventional liquid crystal display device. It is a circuit diagram which shows an example of a structure of a precharge circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Pixel array part 3 Vertical drive circuit 4 Switch circuit group 5 Buffer group 6 Precharge circuit 7 Liquid crystal panel 8 Driver IC
9 pixels 10 TFT
DESCRIPTION OF SYMBOLS 11 Liquid crystal cell 12 Holding capacity 13 Common line 100 Transmission-type liquid crystal projector 101 Lamp 103R R dichroic mirror 103G G dichroic mirror 104R R light valve 104G G light valve 104B B light valve 105 Dichroic prism 106 Projection lens 107 Fly eye lens 108 Polarization conversion element 109 Filter 110 Total reflection mirror 111 Relay lens 112 Condenser lens

Claims (7)

a signal line grouped in groups of x (x: an integer of 2 or more);
A video signal supply line for supplying a video signal to the signal line;
A switch circuit for connecting the signal line and the video signal supply line;
In a display panel comprising a control signal supply line for supplying a control signal for turning on the switch circuit,
The switch circuit connected to an arbitrary signal line is different from the control signal supply line connected to the switch circuit connected to another signal line belonging to the same set as the arbitrary signal line. Connected to the wire,
At least one of the switch circuit connected to the first signal line of each set or the switch circuit connected to the xth signal line is connected to the signal line to which the switch circuit is connected. A display panel connected to the same control signal supply line as the switch circuit connected to an adjacent signal line. The signal lines are grouped into y groups (y: an integer of 2 or more),
The switch circuit connected to the x-th signal line of the (y-1) th group is the same control signal as the switch circuit connected to the first signal line of the y-th group The display panel according to claim 1, wherein the display panel is connected to a supply line. a signal line grouped in groups of x (x: an integer of 2 or more);
A video signal supply line for supplying a video signal to the signal line;
In a driving method of a display panel comprising the switch circuit for connecting the signal line and the video signal supply line,
At least one of the switch circuit connected to the first signal line of each set or the switch circuit connected to the xth signal line is connected to the signal line to which the switch circuit is connected. A display panel driving method, wherein the switch circuits connected to signal lines that are adjacent to each other and that belong to a different set are brought into a conductive state substantially simultaneously. The signal lines are grouped into y groups (y: an integer of 2 or more),
The switch circuit connected to the x-th signal line of the (y-1) th set is in a conductive state substantially simultaneously with the switch circuit connected to the first signal line of the y-th set. The method of driving a display panel according to claim 3. The switch circuit connected to the signal line belonging to the (2N-1) th (N: natural number) group is connected to the x-th signal line from the switch circuit connected to the first signal line. In order, the switch circuit is turned on,
The switch circuits connected to the signal lines belonging to the 2Nth set are in a conductive state in order from the switch circuit connected to the xth signal line to the switch circuit connected to the first signal line. And
Or
For the switch circuit connected to the signal line belonging to the (2N-1) th group, the switch circuit connected to the first signal line from the switch circuit connected to the x-th signal line In order,
The switch circuits connected to the signal lines belonging to the 2Nth group are in a conductive state in order from the switch circuit connected to the first signal line to the switch circuit connected to the xth signal line. The display panel driving method according to claim 3, wherein: a signal line grouped in groups of x (x: an integer of 2 or more);
A driver IC for supplying a video signal to the signal line;
A switch circuit connecting the signal line and the driver IC;
In a display device comprising a control signal supply line for supplying a control signal for turning on the switch circuit,
The switch circuit connected to an arbitrary signal line is different from the control signal supply line connected to the switch circuit connected to another signal line belonging to the same set as the arbitrary signal line. Connected to the wire,
At least one of the switch circuit connected to the first signal line of each set or the switch circuit connected to the xth signal line is connected to the signal line to which the switch circuit is connected. The display device, wherein the display device is connected to the same control signal supply line as the switch circuit connected to an adjacent signal line. a signal line grouped in groups of x (x: an integer of 2 or more);
A driver IC for supplying a video signal to the signal line;
A switch circuit connecting the signal line and the driver IC;
A display device having a control signal supply line for supplying a control signal for turning on the switch circuit;
In a video display device that performs video display using light modulated by the display device,
The switch circuit connected to an arbitrary signal line is different from the control signal supply line connected to the switch circuit connected to another signal line belonging to the same set as the arbitrary signal line. Connected to the wire,
At least one of the switch circuit connected to the first signal line of each set or the switch circuit connected to the xth signal line is connected to the signal line to which the switch circuit is connected. An image display device, wherein the video signal display device is connected to the same control signal supply line as the switch circuit connected to an adjacent signal line.

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