JP2009071354A - Solid-state imaging apparatus and imaging system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that image quality is degraded caused by power source noise due to the reset of a non-read pixel when performing a thinning read operation in a solid-state imaging apparatus. <P>SOLUTION: The pixels of a non-read row are subjected to a resetting operation only in a period from the end of the operation of reading signals from read pixels in a certain frame to the start of the operation of reading signals from read pixels in the next frame. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device used for imaging equipment such as a digital still camera and a video camera.

  In recent years, there has been an increasing demand for high-functionality and multi-functionality for solid-state imaging devices. In addition to high-definition reading of signals from all effective pixels for forming an image, so-called all-pixel reading, a high frame There is also a need for a readout method that outputs a moving image at a rate. For the output at a high frame rate, a reading method called so-called thinning-out reading, in which only the signals of some of the effective pixels are read out, is known.

  When performing thinning-out readout, the photoelectric conversion and accumulation of the photoelectric conversion element of the pixel that does not read the signal (non-readout pixel) overflows, and a false signal is generated in the adjacent pixel that reads the signal (readout pixel) There is concern about making it happen. As a technique for suppressing leakage of electric charge from a non-read pixel to a read pixel, there is Patent Document 1. Patent Document 1 describes that a reset operation is performed on a non-read pixel simultaneously with a reset operation of the read pixel, and that the non-read pixel is always in a reset state.

Patent Document 2 discloses a technique for reducing the number of vertical selection switches MOS in order to reduce the number of transistors per pixel and realize a solid-state imaging device with a narrow pixel pitch. This is to select a pixel from which a signal is read out by changing the operating point of a floating diffusion (hereinafter referred to as FD) portion which is an input terminal (gate terminal) of a source follower MOS which is a signal amplifying portion. More specifically, the potential of the FD portion of the pixel from which a signal is to be read is set to a potential at which the source follower MOS is in an operating state, and the FD portion of the other pixels is set to a potential at which the source follower MOS does not operate. By setting, a signal is selectively read out to the vertical signal line.
JP 2000-350103 A JP-A-11-112018

  FIG. 7 is a schematic diagram of a photoelectric conversion device, and FIG. 8 is another example of the pixel configuration of the photoelectric conversion device illustrated in FIG. 7. FIG. 9 shows the operation timing of this photoelectric conversion device. 7 to 9 are extracted from Patent Document 1. FIG. Hereinafter, a case where the photoelectric conversion device includes the pixel illustrated in FIG. 8 will be described. Here, the pixels in the first and third rows are readout pixels, and the pixels in the second and fourth rows are non-readout pixels.

  In FIG. 9, during a period in which the signal SEL1 or SEL3 is at a high level, signals are read from the pixels in the row corresponding to each signal to the vertical signal line 6. That is, in the solid-state imaging device having the pixel of FIG. 8, the charge transfer switch 901 and the vertical selection switch MOS3 are in conduction during these periods.

  At time t0, the read row, that is, the RES1 input to the pixel of the first row that is the read row and the RES1 that is input to the pixel that is not read, that is, the second row of the non-read row, simultaneously. Transition to high level. In the pixel in the readout row, the accumulated charge is once transferred from the photoelectric conversion element 1 to the gate terminal of the amplifying source follower input MOS 2 via the charge transfer switch 901 during the period when SEL1 is at the high level. The charge (accumulated charge) accumulated in the photoelectric conversion element 1 when reset is small. On the other hand, in the non-reading row, since the accumulated charge is not transferred from the photoelectric conversion element 1 during the period when SEL1 is at the high level, the accumulated charge at time t0 is reset from the previous frame until time t0. The amount of charge accumulated during the period is larger than that in the readout row. Under a condition where the amount of irradiation light is large so that the accumulated charge of the non-reading row leaks to the adjacent reading row, the accumulated charge amount of the non-reading row is further increased. Therefore, when resetting at time t0, a large instantaneous current flows through the power supply terminal 5 which is a terminal from which the accumulated charge is discharged. Since the power supply terminal 5 and the power supply line 4 for supplying power have a finite impedance, the potential varies when a large instantaneous current flows.

  When SEL3 becomes high level in a period subsequent to time t0, a signal is read out from the pixel in the third row which is the next readout row. However, at this time, the potentials of the power supply terminal 5 and the power supply line 4 that have fluctuated due to the large instantaneous current described above are not stable, and noise is superimposed on the signal from the readout row. When noise is superimposed on the signal read from the read pixel, the image quality of the image formed based on the read signal is deteriorated.

  FIG. 9 is an example in which the readout rows and the non-readout rows are alternately arranged one by one. However, in recent years, the number of pixels of the solid-state imaging device tends to increase. There is an increasing demand for higher decimation rates and higher frame rates. In such an application in which many non-reading rows are used, the number of pixels that are simultaneously reset increases, so that the instantaneous current is further increased, and the above-described problem due to power supply noise becomes more remarkable.

  Patent Document 1 also discloses an example in which pixels in non-read rows are always kept in a reset state. In this case, the instantaneous current flowing in the power supply terminal 5 and the power supply line 4 is smaller than that in the case of performing the above-described operation. However, the electric potential that is photoelectrically converted by the pixels in the non-reading row is always discharged to the power supply line. Always fluctuates. For this reason, random noise is superimposed on the signals read from the pixels in the readout row, causing a problem that the image quality of the obtained image is deteriorated.

  Even in the configuration of a pixel that does not have a vertical selection switch MOS as disclosed in Patent Document 2, the above-described noise due to resetting of a non-reading row occurs, and the same problem occurs.

  An object of the present invention is to provide a solid-state imaging device, an imaging system, and a driving method of the solid-state imaging device that can reduce deterioration in image quality due to power noise caused by resetting non-readout pixels.

  In order to achieve the above object, a solid-state imaging device according to the first aspect of the present invention includes a pixel unit including a plurality of pixels arranged in a matrix and an operation of resetting the plurality of pixels arranged in the matrix. A solid-state imaging device having a control unit that controls the operation of reading out signals from the plurality of pixels arranged in rows and columns, and controls the operations in row units, When only a part of the pixels performs an operation of reading out a signal, the operation of accumulating charges in the pixels of the first pixel group in which the operation of reading out the signal is performed ends the operation of resetting by the control unit And the control unit finishes the operation of reading out signals from the pixels in the first pixel group in the first frame period. From In the second frame period following the first frame period, the second pixel in which the signal reading operation is not performed in the second frame period only during the period until the operation of resetting the pixels of the first pixel group is started. An operation of resetting the pixels of the group is performed.

  In order to achieve the above object, an imaging system according to a second aspect of the present invention outputs the above-described solid-state imaging device, an optical system that forms an image on a pixel portion of the solid-state imaging device, and the solid-state imaging device. And a signal processing unit for processing the signal to generate image data.

  In order to achieve the above object, a driving method of a solid-state imaging device according to a third aspect of the present invention is a driving method of a solid-state imaging device having a pixel unit including a plurality of pixels arranged in a matrix, and the matrix When the signal reading operation is performed on only a part of the plurality of pixels arranged in the shape, the operation of accumulating the charge of the pixels of the first pixel group that reads the signal is started by ending the operation of resetting the pixels. Furthermore, the operation of reading out signals from the pixels of the second pixel group that is terminated by performing the operation of reading out signals and that does not read out signals is the operation of reading out signals from the pixels of the first pixel group in the first frame period. It is characterized in that it is performed only during a period from the end to the start of the operation of resetting the pixels of the first pixel group in the second frame period following the first frame period.

  The present invention can reduce image quality deterioration due to power supply noise caused by resetting non-readout pixels.

(First embodiment)
A first embodiment according to the present invention will be described with reference to FIGS.

  FIG. 1 is a schematic diagram of a solid-state imaging device according to the present embodiment. A plurality of pixels 100 are arranged in a matrix in the pixel portion 101. The pixel 100 includes a reset control line 15 to which a signal for selecting a reset row, that is, a signal for selecting a reset row, and a selection control line 8 to which a signal for selecting a readout row is input. It is connected. Note that a transfer control line connected to the gate electrode of the charge transfer switch is omitted for simplicity. Further, a vertical signal line 6 to which a signal read from the selected pixel is transmitted and a reset power supply line 4 are connected to the pixel 100. The reset power supply line 4 is connected to a power supply terminal 5. Here, the power supply terminal 5 is used as a reset power supply for the pixel 100 and a power supply for a source follower circuit described later. A switch 10 is connected to the vertical signal line 6 in addition to a source follower MOS 2 of the pixel 100 and a load 7 which is a constant current source constituting a source follower circuit. The horizontal output line 11 is connected to the vertical signal line 6 via the switch 10. Connected. The switch 10 is turned on or off based on a signal input from the horizontal scanning circuit 13, and the signal on the vertical signal line 6 is transmitted to the horizontal output line 11 when the switch 10 is turned on. The signal output to the horizontal output line 11 is output from the output terminal OUT to the outside of the solid-state imaging device via the output amplifier 12. The switch 10, the horizontal output line 11, the output amplifier 12, and the output terminal OUT constitute an output unit 21.

  Here, the scanning circuit 20 serving as a control unit includes a first vertical scanning circuit 9 serving as a first scanning unit for sequentially selecting readout rows in units of rows and a row of pixels to be reset (reset rows) in units of rows. And a second vertical scanning circuit 16 which is a second scanning means for selecting sequentially. The first vertical scanning circuit 9 outputs signals SEL <b> 1 to SEL <b> 9 to the selection control line 8 to select the pixel 100 connected to the corresponding selection control line 8, and to each transfer control line 402 (not shown). Signals TX1 to TX9 are output to control transfer of accumulated charges from the photoelectric conversion element 1 included in the pixel 100. Although the transfer control line 402 is omitted in FIG. 1 for simplification of the drawing, it is commonly connected to the pixels 100 in the same row. The second vertical scanning circuit outputs RES1 to RES9 to the reset control line 15, and controls the reset operation of the pixel 100 connected to the corresponding reset control line. The non-reading row batch reset signal input terminal 17 inputs a non-reading row batch reset signal that defines the reset timing of the non-reading row when there is a non-reading row.

  What is input to the HSTART terminal 18 of the horizontal scanning circuit 13 is a scanning signal of the horizontal scanning circuit, and what is input from the HSCAN terminal 19 is a pulse indicating a period during which the scanning drive clock is input.

  FIG. 2 is a circuit diagram illustrating an example of a specific configuration of the pixel 100. The pixel 100 includes a photoelectric conversion element 1 that accumulates charges corresponding to the amount of incident light. The charge accumulated in the photoelectric conversion element 1 is supplied to a source follower MOS (amplifier unit) via a charge transfer switch (transfer unit) 901 that switches between conduction and non-conduction based on a signal input via the transfer control line 402. ) Is transferred to the gate terminal 9. Since the charge accumulated in the photoelectric conversion element 1 is completely transferred, the photoelectric conversion element 1 is reset by this transfer operation. The gate terminal of the source follower MOS 2 is further connected to the power supply line 4 via a reset switch (reset unit) 14. The reset switch 14 is switched to a conductive state based on a signal input from the scanning circuit 20 via the reset control line 15. One end of the source follower MOS 2 is connected to the power supply line 4, and the other end is connected to a vertical selection switch MOS 3 which is a selection unit. The vertical selection switch MOS3 is activated based on a signal input from the scanning circuit 20 via the selection control line 8, becomes conductive when activated, and is a source follower composed of the source follower MOS2 and the load 7. The circuit becomes operational.

  Subsequently, the operation of the solid-state imaging device according to the present embodiment will be described. In the solid-state imaging device of FIG. 1, assuming that all pixels are effective pixels that can be used to form an image, the pixels in the first, fourth, and seventh rows from the top are readout rows, FIG. 3 shows a timing chart when the pixels in the third, fifth, sixth, eighth, and ninth rows are non-read rows. In this embodiment, the pixels in the first, fourth, and seventh rows from the top are the pixels of the first pixel group, and the pixels in the second, third, fifth, sixth, eighth, and ninth rows from the top are the second pixel group. is there. The names of the pulses in FIG. 3 correspond to the names in FIG. Here, when the solid-state imaging device is repeatedly driven with the same drive pattern as in moving image shooting, the operation of an arbitrary frame (here, the nth frame) and the preceding and succeeding frames (here, n−1). And a part of the operation of the (n + 1) th frame). The shaded area indicates a period during which a signal based on the pixel 100 is output from the output terminal OUT to the outside of the solid-state imaging device.

  Although not shown for simplification, the photoelectric conversion element 1 and the gate portion of the source follower MOS 2 are reset by setting TXn to high level when RESn is high level. That is, the pixel is reset.

  The dotted lines in FIG. 3 are arranged at equal intervals from each other, and indicate a period of a certain interval. Further, the times r1, r2, r3 and the times t1, t2, t3 are equally spaced from each other in each series.

  When the scanning circuit 20 selects the pixel in the seventh row, which is the last readout row in the (n−1) th frame which is the first frame period, a signal is read out onto the vertical signal line 6. The signal read out to the vertical signal line 6 is sequentially output from the output terminal OUT to the outside in accordance with HSTART and HSCAN input to the horizontal scanning circuit 13.

  In the nth frame, which is the second frame period starting after the period T7, first, the RESALL signal transitions from the high level to the low level at time r0. At this time, reset signals RES2, RES3, RES5, RES6, RES8, RES9 and TX2, TX3, TX5, TX6, TX8, TX9 corresponding to the second, third, fifth, sixth, eighth, and ninth rows which are non-reading rows. Transition from conductive to non-conductive state. Thereby, the reset operation of the pixels in the second, third, fifth, sixth, eighth and ninth rows is completed at once.

  In the subsequent period, RES1 and TX1 become high level, and at time r1, RES1 transitions from high level to low level, thereby resetting the photoelectric conversion elements 1 and the source follower MOS2 of the pixels in the first row, that is, Pixel reset is complete. As a result, the operation of accumulating the charge in the pixels in the first row starts from time r1.

  The same operation is performed for the pixels in the fourth row and the seventh row, and the operation for accumulating the charge from the pixel in the fourth row starts from time r2, and the pixel from the seventh row starts from time r3.

  Next, the signal of the pixel in the first row is read out to the vertical signal line. When HSCAN becomes high level at time t1 and HSSTART changes from high level to leo level, signals corresponding to signals read from the pixels in the first row are sequentially output terminals while HSCAN is at high level. Output from OUT.

  In the period starting from time t2 and t3, the same control as in the first row is performed on the pixels in the fourth row and the seventh row, respectively, and signals corresponding to the signals read from the pixels in the respective rows are sequentially transmitted. Output from the output terminal OUT. After the signal based on the pixels in the seventh row has been output from the output terminal OUT, the operation of the nth frame is finished and the operation of the (n + 1) th frame is started. The same operation as described above is repeated after the (n + 1) th frame.

Here, the operation of the read row will be described in more detail. Focusing on the pixels in the first row, first, RES1 and TX1 are at a high level prior to time r1, and the accumulated charge up to that time is supplied to the power supply terminal via the charge transfer switch 901, the reset switch 14, and the power supply line 4. It is discharged to 5. Next, since the charge accumulated in the photoelectric conversion element 1 in the period starting from the time t1 is transferred to the gate part of the source follower MOS via the charge transfer switch 901, the accumulation time of the signal read from the pixels in the first row △ TS1 is
ΔTS1 = t1-r1 (1)
It becomes. The same applies to the pixels in the fourth and seventh rows.
ΔTS4 = t2-r2 (2)
ΔTS7 = t3-r3 (3)
It becomes. As described above, the times r1, r2, and r3 and the times t1, t2, and t3 are equally spaced from each other.
ΔTS1 = ΔTS4 = ΔTS7 (4)
Thus, it can be seen that the accumulation time of all rows is constant.

  Next, the non-reading row will be described in more detail. In the driving shown in FIG. 3, the pixels in the non-reading row are collectively reset in synchronization with the non-reading row collective reset signal RESALL at time r0. The amount of charge discharged to the power supply line 4 and the power supply terminal 5 at this timing is a reset power supply having a finite impedance because the accumulated charge accumulated during one frame period is 9 columns × 6 rows = 54 pixels. Potential fluctuations of the line 4 and the power supply terminal 5 occur. However, an operation of reading a signal from the pixel is not performed during a period in which the potential variation occurs. In other words, when at least two frame periods are consecutive, the pixel in the non-reading row has the operation of resetting the signal from the reading pixel in the next frame after the operation of reading the signal of the reading pixel in a certain frame is completed. Only the period until the start is performed. Thereby, the influence which the power supply fluctuation accompanying reset has on a signal can be reduced.

  In the present embodiment, since the non-reading rows are collectively reset, the waiting time is reduced as compared with the case where the reading row and the non-reading row are reset simultaneously in Patent Document 1.

  When the readout row reset and the non-readout row reset are simultaneously performed as in Patent Document 1, an operation of reading a signal from the next readout row is attempted in order to reduce the influence of the power supply noise generated by the reset. It is necessary to provide a waiting time before performing. Assuming that a standby time until the power supply fluctuation returns to the steady state is taken, the technology disclosed in Patent Document 1 requires a standby time of (standby time) × (number of read lines). However, in applications where a high frame rate is required, there is a possibility that a sufficient frame rate may not be obtained if a standby time is provided, and if the standby time is reduced, the image quality may be deteriorated due to power supply noise accompanying reset. On the other hand, according to the present embodiment, the non-reading rows are reset in a lump, and therefore, even when operation at a high frame rate is required, the power supply fluctuation that occurs due to the resetting of the non-reading rows. It is possible to reduce the deterioration of the image quality due to the influence of.

  In this embodiment, the non-read line is reset at the beginning of each frame, but this is not essential, and the reset may be performed at the end of each frame. That is, in the present invention, the pixel in the non-reading row is important only in the period from the end of the operation of reading out the signal from the readout pixel in a certain frame to the start of the operation of reading out the signal from the readout pixel in the next frame. The resetting operation is performed.

  Further, it is not always necessary to reset all the non-reading rows at once. For example, there is no problem if the timing for resetting some non-reading rows is different from the timing for resetting other non-reading rows. However, as described above, the standby time until the power supply fluctuation returns to the steady state is determined according to the time constant determined by the power supply and the power supply line. This is particularly effective for operation at a high frame rate.

  In this embodiment, the output to the outside is started after all the resetting of the readout row is completed. However, a part of the output operation may be temporally overlapped with the resetting operation of the readout row. . For example, the times t1, t2, and t3 in FIG. 3 may be r0, r1, t1, r2, t2, r3, and t3. In this case, the accumulation time of the pixels in the readout row is shortened, but the frame rate can be increased.

  In this embodiment, the pixels in the non-reading row are reset only in a period from the end of the operation of reading out signals from the readout pixels in a certain frame to the start of operation of reading out signals from the readout pixels in the next frame. Operation is taking place. That is, in FIG. 3, the operation of resetting pixels in the non-reading row performed at time r <b> 0 may be performed in the period indicated by the oblique line in which the signal is output from the output terminal OUT in the period T <b> 7. However, if an operation for outputting a signal to the outside is performed during a period when the power supply fluctuation occurs, noise may be superimposed on the output signal. It is desirable to be performed only during the period from the end of the operation of outputting a signal according to the signal from the readout pixel to the outside of the solid-state imaging device until the start of the operation of reading the signal from the readout pixel in the next frame. .

(Second embodiment)
FIG. 4 is a circuit diagram of a pixel according to the second embodiment of the present invention. 2 is different from the circuit diagram of the pixel shown in FIG. 2 in that the vertical selection switch MOS3 is not provided, and the source terminal of the source follower MOS is directly connected to the vertical signal line 6.

  When the pixel shown in FIG. 4 is provided, the pixel from which the signal is read is selected by changing the operating point of the FD unit that is the input terminal of the source follower MOS 2 that is the signal amplification unit. That is, by setting the potential of the FD portion of the pixel from which the signal is to be read to a potential at which the source follower MOS 2 is in an operating state, and setting the FD portion of the other pixels to a potential at which the source follower MOS 2 does not operate. A signal is selectively read out to the vertical signal line.

  In the case where the pixel shown in FIG. 2 is provided, the instantaneous current can be reduced by always resetting the pixel in the non-reading row. On the other hand, in the circuit of FIG. 4, since the source follower MOS 2 included in the pixels in the non-reading row becomes an operation state by performing the reset operation, it cannot be always set to the reset state. Noise may be superimposed on the read signal. Therefore, there is a problem that if the non-reading row is always reset, the signal cannot be selectively read from the reading pixel.

  In the present embodiment, as in the first embodiment, when at least two frame periods are continuous, the pixels in the non-reading row perform the following operation after the operation of reading out signals from the reading pixels in a certain frame is completed. Reset is performed only during a period until an operation of outputting a signal from the readout pixel in the frame is started. In this case, since the source follower MOS 2 included in the pixel in the non-reading row is in the non-operating state during the period in which the signal reading operation is performed from the pixel in the reading row, the signal is selectively read from the pixel in the reading row. Can be realized. According to the solid-state imaging device according to the present embodiment, even when the pixel configuration does not include the vertical selection switch MOS, it is possible to reduce image quality degradation due to power supply noise accompanying resetting of non-readout pixels.

(Third embodiment)
As a third embodiment, among effective pixels that can be used to form an image, a so-called thinning-out reading operation in which a non-reading row exists and a so-called all-pixel reading operation in which all signals from the effective pixels are read out are performed. A scanning circuit for performing switching control will be described. Here, a case will be described as an example where the pixels in the first row, the fourth row, and the seventh row become readout pixels during the thinning readout operation.

  FIG. 5 is an example of a circuit diagram of the second vertical scanning circuit 16 used for selecting a reset row for realizing the operation according to the present embodiment. Reference numeral 501 denotes a shift pulse generation circuit which is a basic configuration of the shift register, and is a circuit for receiving a previous stage input to generate a shift pulse signal and shifting the signal to the next stage. This can be realized by a generally known configuration such as a clocked inverter or a flip-flop. Reference numerals 502 and 503 denote first and second transfer switches, which are opened and closed by a signal on the read mode switching selection line 505. Here, the first and second transfer switches 502 and 503 use transmission gates. In general, the transmission gate is supplied with a normal rotation signal and its inverted signal to control the conduction state, but one input is omitted in FIG. 5 for the sake of simplicity. Reference numeral 504 denotes an OR circuit that outputs a logical sum of the shift pulse of each row and a non-reading row collective reset signal or the ground, that is, a low level, to the reset line 15.

  In the case of the second readout mode in which the all-pixel readout operation is performed, the signal input to the readout mode switching selection line 505 is at a low level, and the first transfer switch 502 is turned on and the second transfer switch 503 is turned off. It becomes. As a result, RES1 to RES9 are sequentially output from the second vertical scanning circuit, and TX1 to TX9 are sequentially output from the first vertical scanning circuit, thereby resetting the pixels of the first and second pixel groups. It is done sequentially. The operation of reading signals from the pixels in the first row to the ninth row is also sequentially performed.

  On the other hand, in the first read mode in which the thinning-out read operation is performed, the signal input to the read mode switching selection line 505 is at a high level, the first transfer switch 502 is non-conductive, and the second transfer switch 503 is turned on. It becomes conduction. As a result, RES1, RES4, and RES7 are sequentially output from the second vertical scanning circuit, and signals are sequentially read from the pixels in the first row, the fourth row, and the seventh row. Further, when a high-level non-reading row collective reset signal is input, RES2, RES3, RES5, RES6, RES8, and RES8, which reset the second, third, fifth, sixth, eighth, and ninth rows that are non-reading rows, and RES9 goes high, and non-read rows are reset at once.

  Here, an example of the second vertical scanning circuit 16 for selecting the reset row is shown, but the first vertical scanning circuit 9 for selecting the readout row can also be realized with a configuration similar to that of FIG. That is, TX1 to TX9 are sequentially output according to the signal input to the read mode switching selection line, or TX2, 3, 5, 6, 8, and 9 are skipped and TX1, 4, and 7 are sequentially output. What is necessary is just to make the structure which switches. When the signal input to the read mode switching selection line is at a high level, the high level TX2, 3, 5, 6, 8, and 9 are output at a time when the high level batch reset signal is input.

  According to this embodiment, the scanning circuit can be shared between the all-pixel reading operation and the thinning-out reading operation, and the switching between the all-pixel reading operation and the thinning-out reading operation is performed by the signal input to the reading mode switching selection line. It can be realized simply by switching. When performing a thinning-out readout operation, even when a high-frame operation is performed like a moving image, the power supply noise generated by resetting the non-reading row is reset because the pixels in the non-reading row are reset at the above timing. It is possible to reduce the deterioration of the image quality due to.

(Fourth embodiment)
A schematic configuration and a schematic operation of the imaging system 200 according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a configuration diagram of an imaging system 200 according to the fourth embodiment of the present invention.

  The imaging system 200 includes an optical system 110, an imaging device 120, and a signal processing unit 180. The signal processing unit 180 includes a signal processing circuit unit 130, a recording / communication unit 140, a timing control circuit unit 150, a system control circuit unit 160, and a playback / display unit 170.

  The optical system 110 forms an image of a subject on a pixel array that is an imaging surface of the imaging device 120.

  The imaging device 120 is, for example, a solid-state imaging device according to the first embodiment. The imaging device 120 converts the image of the subject formed in the pixel array into an image signal. The imaging device 120 reads the image signal from the pixel array and outputs it to the signal processing circuit unit 130.

  The signal processing circuit unit 130 processes the image signal supplied from the imaging device 120 according to a predetermined method. For example, the image signal that is an analog signal is A / D converted to generate image data that is a digital signal, or the image data is compressed. The signal processing circuit unit 130 supplies the image data subjected to signal processing to the recording / communication unit 140 and the reproduction / display unit 170.

  The recording / communication unit 140 records the image data supplied from the signal processing circuit unit 130 on a recording medium (not shown) or transmits it to an external device (not shown). Alternatively, the recording / communication unit 140 reads out image data from the recording medium and supplies it to the reproduction / display unit 170, or receives a predetermined instruction from an input unit (not shown) and supplies it to the system control circuit unit 160.

  The reproduction / display unit 170 displays the image data supplied from the signal processing circuit unit 130 or the recording / communication unit 140 on a display device.

  The timing control circuit unit 150 supplies a signal for controlling the timing of driving the imaging device 120, and has a role as a mode switching unit. For example, a non-reading row batch reset signal and a reading mode switching signal are supplied to the control circuit 20 which is a control means, or a pulse indicating a period during which a scanning signal or a scanning drive clock is input is supplied to the horizontal scanning circuit. .

  The system control circuit unit 160 receives predetermined instruction information from the recording / communication unit 140. The system control circuit unit 160 controls the optical system 110, the recording / communication unit 140, the reproduction / display unit 170, and the timing control circuit unit 150 in accordance with a predetermined instruction. For example, the optical system 110, the recording / communication unit 140, the reproduction / display unit 170, and the timing control circuit unit 150 are controlled in accordance with the respective modes in the all-pixel readout mode and the thinning readout mode.

  The imaging system according to the present embodiment uses the solid-state imaging device as described in any one of the first to third embodiments. That is, the pixel in the non-reading row is reset only during the period from the end of the operation of reading out the signal from the reading pixel in a certain frame to the start of the operation of reading out the signal from the reading pixel in the next frame. . As a result, it is possible to reduce the deterioration of the image quality due to the influence of the power supply fluctuation caused by the reset of the non-reading row.

  In any of the above-described embodiments, the signal read out from the pixel is output to the horizontal output line via only the switch 10, but an amplifier or CDS (Correlated Double Sampling; correlation) is provided on the vertical signal line. The present invention can be applied even to a configuration provided with a double sampling circuit. That is, the pixel in the non-reading row is reset only during the period from the end of the operation of reading out the signal from the reading pixel in a certain frame to the start of the operation of reading out the signal from the reading pixel in the next frame. This is very important.

The schematic diagram which concerns on the Example of this invention Timing chart of operation according to the first embodiment of the present invention 1 is a circuit diagram of a pixel according to a first embodiment of the present invention. Circuit diagram of a pixel according to the second embodiment of the present invention. The circuit diagram of the scanning circuit which concerns on 3rd Example of this invention. The figure of the imaging system concerning the 4th example of the present invention. Schematic diagram of photoelectric conversion device in the prior art Schematic diagram of pixels in the prior art Operation timing chart of photoelectric conversion device in the prior art

Explanation of symbols

1 Photoelectric conversion element 2 Source follower MOS
3 Vertical selection switch MOS
4 Power Line 5 Power Terminal 6 Vertical Signal Line 7 Load 8 Selection Control Line 9 First Vertical Scan Circuit 10 Switch 11 Horizontal Output Line 12 Output Amplifier 13 Horizontal Scan Circuit 14 Reset Switch 15 Reset Switch Control Line 16 Second Vertical Scan Circuit 17 Non-read row collective reset signal input terminal 18 Horizontal scanning circuit start signal 19 Search drive clock input period signal 20 Scanning circuit 21 Output unit 100 Pixel 101 Pixel unit 110 Optical system 120 Imaging device 130 Signal processing circuit unit 140 Recording / communication unit 150 Timing Control Circuit Unit 160 System Control Circuit Unit 170 Playback / Display Unit 180 Signal Processing Unit 200 Imaging System 402 Transfer Switch Control Line 501 Scan Pulse Generator 502 First Transfer Switch 503 Second Transfer Switch 504 OR Circuit 5 5 read mode switching terminal 901 a charge transfer switch 902 transfer gate line

Claims (13)

A pixel portion including a plurality of pixels arranged in a matrix;
Control means for controlling the operation of resetting a plurality of pixels arranged in a matrix in units of rows, and a control means for controlling an operation of reading out signals from the plurality of pixels arranged in a matrix in units of rows,
A solid-state imaging device comprising:
When only a part of the plurality of pixels arranged in the matrix is subjected to an operation of reading a signal,
The operation of accumulating the charge in the pixels of the first pixel group in which the operation of reading out the signal is started is started by ending the operation of resetting by the control unit, and further the operation of reading out the signal by the control unit is performed. End with
The control means includes a second frame period following the first frame period after the operation of reading out signals from the pixels of the first pixel group is completed in the first frame period. A solid-state imaging device that performs an operation of resetting pixels of a second pixel group in which an operation of reading out signals in the second frame period is not performed only during a period until an operation of resetting pixels starts. The control means includes
First scanning means for controlling an operation of resetting a plurality of pixels arranged in a matrix;
Second scanning means for controlling an operation of reading signals from the plurality of pixels arranged in a matrix;
The solid-state imaging device according to claim 1, comprising:   The solid-state imaging device according to claim 1, wherein the control unit collectively controls an operation of resetting pixels of the second pixel group. The solid-state imaging device according to any one of claims 1 to 3,
The solid-state imaging device
A first readout mode in which only a part of the plurality of pixels arranged in a matrix performs an operation of reading out a signal;
A second readout mode for performing an operation of reading out signals from all of the plurality of pixels arranged in a matrix;
With
The solid-state imaging device, wherein the control unit causes an operation of sequentially resetting pixels for which a signal is read in the second reading mode, in units of rows. The solid-state imaging device according to claim 4,
A solid-state imaging device comprising mode switching means for supplying a mode switching signal for switching between the first readout mode and the second readout mode to the control means.   The solid-state imaging device according to claim 4, wherein a moving image is captured in the first readout mode. The solid-state imaging device according to claim 1,
An output unit for outputting a signal read from the pixel to the outside;
The control means performs the first frame period in a second frame period following the first frame period after the operation of outputting signals from the pixels of the first pixel group to the outside in the first frame period ends. A solid state characterized in that an operation of resetting the pixels of the second pixel group, in which an operation of reading a signal in the second frame period is not performed only during a period until an operation of resetting the pixels of the pixel group is started, is performed. Imaging device. Each of the plurality of pixels arranged in a matrix is
A photoelectric conversion element;
An amplifier that outputs a signal corresponding to the charge accumulated in the photoelectric conversion element;
A transfer unit that controls transfer of charges accumulated in the photoelectric conversion element to the amplification unit;
The solid-state imaging device according to claim 1, further comprising: a reset unit that controls discharge of electric charge accumulated in the amplification unit and / or the photoelectric conversion element. Each of the plurality of pixels arranged in a matrix is
The solid-state imaging device according to claim 8, further comprising a selection unit that selects a pixel to be read by being activated by the control unit. A solid-state imaging device according to any one of claims 1 to 9,
An optical system for forming an image on a pixel portion of the solid-state imaging device;
A signal processing unit that processes signals output from the solid-state imaging device to generate image data;
An imaging system comprising: A method for driving a solid-state imaging device having a pixel portion including a plurality of pixels arranged in a matrix,
When performing an operation of reading out only a part of the plurality of pixels arranged in the matrix,
The operation in which the pixels of the first pixel group that reads out the signal accumulates the charge starts by ending the operation of resetting the pixel, and further ends by performing the operation of reading out the signal.
The operation of resetting the pixels of the second pixel group from which signals are not read out is performed after the operation of reading out signals from the pixels of the first pixel group is completed in the first frame period. A method for driving a solid-state imaging device, which is performed only during a period until an operation for resetting pixels of the first pixel group is started in two frame periods.   The solid-state imaging device driving method according to claim 11, wherein the pixels of the second pixel group are collectively reset. It is a drive method of the solid-state imaging device according to claim 11 or 12,
The solid-state imaging device further includes an output unit that outputs a signal read from the pixel of the pixel unit to the outside,
The operation of resetting the pixels of the second pixel group is performed following the first frame period after the operation of outputting the signals from the pixels of the first pixel group to the outside in the first frame period is completed. The solid-state imaging device driving method according to claim 11, wherein the driving is performed only during a period until an operation of resetting pixels of the first pixel group is started in two frame periods.

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