JP2009070980A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure reducing power consumption in a semiconductor integrated circuit. <P>SOLUTION: A clock generating part performing clock signal generation processing and a data processing part inputting a clock generated by the clock generating part and performing data processing are separated. Supply power to the clock generating part is made at a low voltage (0.8 V, for example) which is relatively lower than that of the data processing part. Power consumption of the whole circuit is reduced with such structure. Since high voltage (1.2 V, for example) is supplied to the data processing part, the data processing part can perform data processing at a high operation frequency. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit. More specifically, the present invention relates to a semiconductor integrated circuit that realizes reduction of power consumption.

  The increase in power consumption in a CMOS semiconductor integrated circuit accompanying the increase in operating frequency with the miniaturization of processes in recent years has become a problem. The increase in power consumption is a major factor that hinders the goal of longer portable battery life, for example. Power consumption in semiconductor integrated circuits is mainly classified into leakage power and dynamic power. The dynamic current has a relative value of several orders of magnitude compared to the leakage current and has a large impact on power.

  As a technique for suppressing the dynamic power, a technique for lowering the operating frequency can be considered first. Patent Document 1 (Japanese Patent Laid-Open No. 3-68007) describes a technique for realizing low power consumption by switching the frequency of an operation clock signal of a microcomputer according to an operation frequency required for each functional block. Yes.

  Further, a method for reducing power by voltage control has been proposed. For example, Patent Document 2 (Japanese Patent Laid-Open No. 5-108193) changes the power supply voltage and clock signal frequency supplied from the outside according to the set value of the built-in register. However, a microcomputer for reducing power consumption is described. Further, Patent Document 3 (Registered Patent No. 3,870,052) discloses a semiconductor integrated circuit by switching and supplying a plurality of power supply voltages having different values to a plurality of circuit blocks and switching and supplying a plurality of clocks having different frequencies. A configuration is disclosed that maximizes performance while minimizing dynamic current.

However, when the voltage of the entire chip or a part of the functional blocks is lowered as described above, the voltage of both the data line and the clock line is lowered. on the other hand,
High-performance system LSIs in recent years require a high operating frequency, and it is difficult to meet the setup time timing constraints associated with increased data line delay time with low-voltage drive, causing processing errors. May end up.
JP-A-3-68007 Japanese Patent Laid-Open No. 5-108193 Registered Patent No. 3857052

  The present invention has been made in view of the above problems, and provides a semiconductor integrated circuit that suppresses delay in a data processing circuit and realizes reduction in power consumption.

  The present invention, for example, drives a clock generation block in a semiconductor integrated circuit at a lower voltage than a data processing circuit block that receives data and executes data processing, and boosts the clock when the clock is input to the data processing circuit block. Provided is a semiconductor integrated circuit capable of reducing power in a clock generation block and preventing a delay in a data processing circuit having a high operating frequency by performing supply.

  Further, according to the present invention, in a semiconductor integrated circuit, a clock signal is driven at a voltage lower than that of a data signal, and is supplied with a voltage boosted by a level shifter immediately before being input to a flip-flop (hereinafter abbreviated as F / F). Provided is a semiconductor integrated circuit capable of reducing power consumption of an entire clock network including a buffer inserted in a clock tree and efficiently saving power of an LSI.

The first aspect of the present invention is:
A clock generation unit for executing a clock signal generation process;
A data processing unit that inputs a clock generated by the clock generation unit and executes data processing;
A power supply unit that performs power supply to the clock generation unit and the data processing unit;
The clock generation unit may be configured to operate by inputting power having a relatively low voltage compared to the data processing unit from the power supply unit.

  Furthermore, in one embodiment of the semiconductor integrated circuit according to the present invention, the clock generator includes a global clock generator that generates clock signals for a plurality of functional blocks set in the semiconductor integrated circuit, and the semiconductor integrated circuit Including a local clock generation unit that generates a clock signal for each of a plurality of functional blocks including a data processing unit set to the data processing unit, and both the global clock generation unit and the local clock generation unit are included in the data processing unit. In comparison, the power supply unit operates by inputting relatively low-voltage power from the power supply unit.

  Furthermore, in an embodiment of the semiconductor integrated circuit of the present invention, the data processing unit is configured to boost the clock signal via a boosting unit set as an input unit of a clock signal from the clock generation unit to the data processing unit. It is the structure which receives supply of this.

  Furthermore, in one embodiment of the semiconductor integrated circuit of the present invention, the semiconductor integrated circuit further includes a clock tree unit configured in each of a plurality of functional blocks including a data processing unit set in the semiconductor integrated circuit. In addition, the clock tree unit also has a configuration that operates with low voltage power that is relatively lower than that of the data processing unit.

  Furthermore, in one embodiment of the semiconductor integrated circuit according to the present invention, the data processing unit is configured to boost the clock signal via a boosting unit set from the clock tree unit to a clock signal input unit to the data processing unit. It is the structure which receives supply of this.

  Furthermore, in one embodiment of the semiconductor integrated circuit of the present invention, the clock tree unit is a circuit that performs clock skew adjustment by a plurality of CTS buffers, and considers clock skew in a path from a clock signal supply source to the boosting unit. It has a CTS buffer setting configuration.

  Furthermore, in one embodiment of the semiconductor integrated circuit of the present invention, the data processing unit includes a plurality of flip-flops that input a clock signal through one boosting unit, and the plurality of flip-flops is the one boosting unit. It has the structure arrange | positioned adjacent to a part.

  Other objects, features, and advantages of the present invention will become apparent from a more detailed description based on embodiments of the present invention described later and the accompanying drawings. In this specification, the system is a logical set configuration of a plurality of devices, and is not limited to one in which the devices of each configuration are in the same casing.

  According to the configuration of one embodiment of the present invention, a clock generation unit that executes clock signal generation processing and a data processing unit that executes data processing by inputting a clock generated by the clock generation unit are divided into clock generation units. Since the power supplied to the unit is set to a relatively low voltage (for example, 0.8 V) compared to the data processing unit, the power consumption of the entire circuit is reduced. In addition, since the data processing unit is configured to supply a high voltage (for example, 1.2 V), the data processing unit can perform data processing at a high operating frequency.

Hereinafter, details of the semiconductor integrated circuit of the present invention will be described with reference to the drawings.
As described above, an increase in power consumption in a CMOS semiconductor integrated circuit due to a recent process miniaturization and an increase in operating frequency has been a problem. Power consumption in CMOS semiconductor integrated circuits is mainly classified into leakage power and dynamic power. Dynamic power is the power consumed in device operation mainly due to signal toggle and capacitive load charging / discharging. The dynamic current has a large relative value compared to the leakage current at several order levels, and the impact on power is very high. large.

The dynamic power [P _D ] of a CMOS semiconductor integrated circuit is generally expressed by the following formula (Formula 1).
P _D = αfCV ² (Equation 1)
In the above formula,
α is the activation rate,
f is the operating frequency,
C is capacity
V is the operating voltage.

  Usually, a semiconductor integrated circuit is composed of a plurality of functional blocks. That is, there are a plurality of functional blocks such as a clock generation block that generates a clock signal and a data processing block that inputs a clock signal generated by the clock generation block and executes various data processing.

Each of these blocks generally has an activation rate [α], an operating frequency [f], and a capacitance [C], and each functional block is used to calculate the power consumption of the entire semiconductor integrated circuit. It is necessary to calculate in consideration of the activation rate [α], the operating frequency [f], and the capacitance [C]. For example, as a different voltage configuration with different supply voltages for each block, it is simplified if each block operates at a constant activation rate and frequency, and one clock generation block and a plurality (n) of data processing Dynamic power [P _D ] in a semiconductor integrated circuit constituted by blocks can be obtained by the following calculation formula (Formula 2).
P _D = α _ck f _ck C _ck V _ck ² + α ₁ f ₁ C ₁ V ₁ ² + α ₂ f ₂ C ₂ V ₂ ² +... + Α _n f _n C _n V _n ² (Equation 2)

In the above formula (formula 2), [α _ck f _ck C _ck V _ck ² ] of one item is dynamic power consumed in the clock generation block, and the following [α ₁ f ₁ C ₁ V ₁ ² ] to [Α _n f _n C _n V _n ² ] is the dynamic power consumed in each of the data processing blocks 1 to n.

In the above formula (formula 2), one clock-related signal in particular has a great impact on dynamic power. this is,
P _D = αfCV ²
In the above formula,
Activation rate [α],
Operating frequency [f],
This is because these values are larger in the clock signal used in the clock generation block than in the data signal used in each of the other data processing blocks 1 to n.

For dynamic power indicated by the data processing block terms [α ₁ f ₁ C ₁ V ₁ ² ] to [α _n f _n C _n V _n ² ] after the second item in the above equation (Equation 2), the setup of the data line Due to timing constraints, it is difficult to reduce the voltage significantly. That is, when the supply voltage is lowered, for example, a data transfer timing delay between flip-flops (FF) in the data processing circuit may occur, which may cause a processing error.

On the other hand, regarding the dynamic power consumed in the clock generation block indicated by one item of clock term [α _ck f _ck C _ck V _ck ² ], the voltage can be greatly reduced independently of other functional blocks.

  In view of such circumstances, the present invention efficiently reduces power consumption by reducing only the voltage of the transistor handling the clock signal without reducing the drive voltage of the transistor of the data processing block handling the data signal. Realize power.

That is, the configuration of an embodiment of the present invention includes a plurality of functional blocks constituting a CMOS semiconductor integrated circuit.
The voltage of the clock generation block for generating the clock signal is lowered.
Do not lower the voltage of data processing blocks other than the clock generation block.
In this way, the supply voltage is different for each functional block.

With reference to FIG. 1, a configuration example of a semiconductor integrated circuit 100 in which a clock generation block according to an embodiment of the present invention is selectively reduced in voltage will be described. FIG.
One clock generation block 110;
Functional blocks 120, 140, 160 including a local clock generation block and a data processing block;
This is a semiconductor integrated circuit 100 having these functional blocks.

  Details of the circuit configuration shown in FIG. 1 will be described. The clock is generated by the crystal unit 101 and multiplied by a PLL (Phase Locked Loop) 102. A clock source signal [HIF] that is an output clock signal of the PLL 102 is input to the global clock generation block 110.

  The clock source signal [HIF] output from the PLL 102 is input to the functional blocks 120, 140, and 160 via the frequency dividing / CG units 111 to 113 configured in the global clock generation block 110. The frequency division / CG units 111 to 113 perform frequency division processing according to the processing function of each functional block 120, 140, 160 (for example, functional block A is divided by a, functional block B is divided by b, and functional block C is c Frequency division) and clock gating (CG) processing. In this way, a clock signal suitable for each functional block 120, 140, 160 is generated and input to each functional block 120, 140, 160.

Each of the three functional blocks 120, 140, and 160 shown in FIG. 1 is a circuit example having local clock generation blocks 130, 150, and 170 in the functional blocks 120, 140, and 160. That is, as shown in FIG.
The functional blocks A and 120 have a local clock generation block A130.
The functional blocks B and 140 have a local clock generation block B150.
The functional blocks A and 160 have a local clock generation block C170.
In addition to the functional block, a power control block 190 for controlling the power supply voltage is set.

In this example,
Global clock generation block 110,
Local clock generation block A130,
Local clock generation block B150,
Local clock generation block C170,
Set the supply voltage for these clock generation blocks to low voltage (for example, 0.8V),
Data processing block that receives data from these clock generation blocks and executes data processing, that is,
Data processing blocks A-1, 121,
Data processing blocks A-2, 122,
Data processing blocks B-1, 141,
Data processing blocks B-2, 142,
Data processing blocks C-1, 161,
Data processing blocks C-2, 162,
The supply voltage for these data processing blocks is set to a high voltage (eg, 1.2 V).

  In the configuration shown in FIG. 1, 1.2V is constantly output from the power control block 190, and the supply voltage to each functional block can be freely changed by a voltage control signal. That is, the output 1.2V voltage of the power control block 190 is reduced to, for example, 0.8V by the control by the voltage control signal, so that each functional block, that is, the global clock generation block 110, each functional block 120, 140, 160.

  The supply voltage to the data processing blocks 121, 122, 141, 142, 161, 162 is boosted by a level shifter or the like set in the local clock generation blocks 130, 150, 170 of the function blocks 120, 140, 160 (for example, 0). .8V → 1.2V), a high voltage (1.2V) is supplied to the data processing blocks 121, 122, 141, 142, 161, 162.

  As shown in the figure, the data processing blocks 121, 122, 141, 142, 161, 162 are boosting units (level shifters) set as input portions of clock signals from the local clock generation blocks 130, 150, 170 to the data processing blocks. In this configuration, the boosted clock signal is supplied via the.

  That is, in the configuration of this embodiment, the voltage of the block having only the clock signal is lowered, and the clock signal is boosted by a level shifter or the like when the clock is input to another block. Thus, in this embodiment, the “global clock generation block 110”, “local clock generation block A130”, “local clock generation block B150”, and “local clock generation block C170” are set to a low voltage of, for example, 0.8 V, and the others This portion is set to a high voltage of 1.2V.

  The high voltage of 1.2 V is set in a data processing circuit constituted by, for example, a flip-flop that receives data from the local clock generation block and executes data processing in each functional block 120, 140, 160 Are data processing blocks 121, 122, 141, 142, 161, 162.

In the configuration shown in FIG.
Functional blocks A-1, 121, A-2, 122, which receive data from the local clock generation block A130 in the functional blocks A, 120 and execute data processing;
Functional blocks B-1, 141, B-2, 142 that receive data from the local clock generation block B150 in the functional blocks B, 140 and execute data processing;
Functional blocks C-1, 161, C-2, 162 that receive data from the local clock generation block C170 in the functional blocks C, 160 and execute data processing;
These data processing circuits are supplied with a high voltage (eg, 1.2 V).

  With this setting, all of the global clock generation block and the local clock generation block are driven by a low voltage (0.8 V), and data processing as a data processing circuit that executes data processing upon receiving a clock supply from the clock generation block A high voltage (1.2 V) is supplied to the block.

  In the data processing blocks 121, 122, 141, 142, 161, 162, data processing at a high operating frequency may be required, and if the voltage is lowered, a processing error due to processing delay may occur. In the configuration of this embodiment, the data processing blocks 121, 122, 141, 142, 161, 162 are driven at a high voltage, and a high processing capability with a high operating frequency can be exhibited. A specific example of the processing sequence will be described later.

  In this embodiment, by selectively changing the supply voltage for each functional block, that is, by setting only the clock signal generation block to a low voltage, the power consumption of the entire semiconductor integrated circuit is reduced, and a high operating frequency is achieved. The configuration that can execute the data processing by is realized.

The dynamic power [P _D ] of the semiconductor integrated circuit according to the present embodiment is included in the dynamic power [α _ck f _ck C _ck V _ck ² ] consumed in the clock generation block of one item in the above-described formula (Formula 2). Operating voltage: V _ck is decreased (for example, 1.2 V → 0.8 V), and dynamic power [α ₁ f ₁ C ₁ V consumed in each of the functional blocks 1 to n in the above formula (Formula 2) ₁ ² ] to [α _n f _n C _n V _n ² ] in the clock generation block having a large value,
Activation rate [α _ck ],
Operating frequency [f _ck ],
As a result, the power consumption of the entire semiconductor integrated circuit can be reduced.

  As described above, in the configuration shown in FIG. 1, the power control block 190 constantly outputs 1.2V, and the voltage of the clock generation block 110 can be freely changed by the voltage control signal. . For example, when restrictions such as clock skew and clock jitter are severe, the voltage of the clock generation block 110 to which 0.8V is supplied can be set to 1.2V by the voltage control signal, or the clock system voltage can be further reduced. The clock voltage can be set to 0.6V. Note that the voltage control signal may be omitted, and 0.8 V may be always supplied to the clock generation block.

  This embodiment is expected to reduce power consumption even more when applied to designs with a small number of data toggles but a high clock activation rate and a high operating frequency or designs with a large clock generation block size for functional blocks. be able to.

  Next, the configuration of the semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIG. The second embodiment is a configuration that realizes lower power consumption than the configuration described with reference to FIG.

  First, the background of the second embodiment will be described. In recent semiconductor integrated circuits, a technique called clock tree synthesis (CTS) is widely used. This is because the CTS buffer is appropriately inserted into a clock line set as a path for supplying a clock signal to each data processing circuit set in the semiconductor integrated circuit, so that it can be placed at various positions in the chip. By adjusting the delay time of the clock supplied to the flip-flop (FF) in the arranged data processing circuit to ensure the setup and hold time, the data exchange between the flip-flops (FF) can be performed at an appropriate timing. It is something that can be done. Due to the recent increase in the gate scale, the number of CTS buffers has become very large, and it is important to suppress the power of this buffer group.

  The second example is an embodiment in view of such circumstances. A second embodiment will be described with reference to FIG. FIG. 2 shows the configuration of one functional block shown in FIG. 1, for example, the configuration corresponding to the functional block 120. The entire functional block 200 shown in FIG. 2 corresponds to one functional block 120 shown in FIG.

  In the frequency division / CG unit 111 of the global clock generation block 110 in the semiconductor integrated circuit shown in FIG. 1, the clock signal after frequency division and clock gating (CG) is executed is the function block 200 shown in FIG. After the local frequency division and clock gating (CG) are executed by the frequency division / CG units 211 and 212, the data processing block A-1 configured in the functional block 200 is input to the local clock generation block 210. 220, and functional blocks A-2 and 230.

  Also in the second embodiment, as in the first embodiment described above with reference to FIG. 1, the global clock generation block that executes the clock generation processing and the local clock generation block have a low voltage (for example, 0.8 V). It is. In this embodiment, in addition to these clock generation blocks, some circuits in the data processing block are also operated at a low voltage (for example, 0.8 V).

  FIG. 2 shows two data processing blocks A- 1 and 220 and data processing blocks A- 2 and 230 configured in the functional block 200. These correspond to the data processing blocks A-1 and 121 and the data processing blocks A-2 and 122 shown in FIG.

  FIG. 2 shows a detailed circuit in which only the data processing blocks A-1 and 220 are enlarged. Note that the data processing blocks A-2 and 230 also have substantially the same configuration as this enlarged detailed view.

  In this embodiment, the data processing block is divided into a plurality of areas, and a different voltage is supplied for each divided area. As shown in FIG. 2, each of the data processing blocks A-1 and 220 includes a clock tree unit 221 having a CTS buffer, and a flip-flop (FF) that receives a clock from the clock tree unit 221 and performs data processing. The data processing circuit unit 222 is divided.

  In this embodiment, the clock tree unit 221 including the CTS buffer is reduced in voltage (for example, 0.8 V), and the data processing circuit unit 222 including the flip-flop (FF) supplies a normal voltage (1.2 V). It is configured.

  As described above, the clock tree unit 221 provided with the CTS buffer adjusts the delay time of the clock supplied to the flip-flops (FF) arranged at various positions in the chip to ensure the setup and hold time. Thus, data is exchanged between flip-flops (FF) at an appropriate timing, and a plurality of CTS buffers 251 are provided on a path to be input to each flip-flop constituting unit. The clock input timing for the flip-flop (FF) in the data processing circuit unit 222 is adjusted according to the number of CTS buffers 251.

  The outputs of the final stage CTS buffers 261 to 263 that are input to the data processing circuit unit 222 including the flip-flop (FF) are input to the level shifters 241 to 243, and the clock line is boosted immediately before the input to the flip-flop (FF). The That is, for example, the voltage is boosted from 0.8V to 1.2V and input to the flip-flop (FF).

  In this embodiment, as shown in FIG. 2, one level shifter is set corresponding to a plurality of flip-flops (FF), for example, 8 FFs, and an input voltage to the plurality of flip-flops (FF) is set to one. The voltage is boosted by a level shifter.

  A configuration may be adopted in which one level shifter is set for each flip-flop (FF) to perform boosting processing. However, since this is not efficient from the viewpoint of power and area, a plurality of flip-flops (FF) ) (For example, 8 FFs), one level shifter boosts the voltage. Therefore, specify the minimum bit width within the range in which the level shifter can drive the flip-flop (FF) in the same way as when “clock gating multiple clock bits together” To optimize the number of level shifter cells.

  In this embodiment, all the CTS buffer groups in the clock tree unit 221 are also driven at a low voltage (0.8 V). As a result, the huge number of CTS buffers including the end of the clock tree are all toggled at a low voltage, so the voltage reduction effect is very large.

  Further, in the optimization of the clock skew by the normal CTS processing, the clock wiring delay from the clock supply source to the terminal buffer cell (final stage buffer cell) that supplies the clock directly to the flip-flop (FF) is attempted to be uniform. In the present invention, the clock skew from the clock supply source to the level shifter cell is optimized.

  That is, the clock tree unit is set as a circuit that performs clock skew adjustment by a plurality of CTS buffers. In the configuration of the present invention, a CTS buffer that takes into account the clock skew in the path from the clock signal supply source to the booster unit (level shifter). It has a setting configuration. For this reason, it is desirable that the flip-flop (FF) to which the clock is supplied be arranged near the level shifter cell.

  An example of a physical layout in which a flip-flop (FF) to which a clock is supplied is arranged near the level shifter cell will be described with reference to FIG. FIG. 3 shows a physical layout of the eight flip-flops (FF) in the data processing circuit 222 shown in FIG. 2 and the level shifter 243 connected to the data processing circuit 222. FIG. 3 is a plan view of a part of the semiconductor integrated circuit.

  The level shifter 243 is supplied with a clock from the CTS buffer 263 at the final stage of the clock tree unit 221, supplies clock information to the eight flip-flops (FF) in the data processing circuit 222, and transfers data between the flip-flops (FF). The timing is controlled. With this configuration, the wiring delay from the level shifter cell to the eight flip-flops (FF) is made uniform, and in addition to the optimization of the clock skew from the clock supply source to the level shifter cell, the flip-flop to which the clock is supplied In (FF), the clock supply timing is made uniform.

  In this embodiment, CTS buffers driven at a low voltage of 0.8V and level shifters boosted from 0.8V to 1.2V are arranged scattered in the functional block. A cell library having two power supplies of 2V is prepared, and two power supply rails are set to run in the entire logic area. These are the 0.8V power rail 311 and the 1.25 power rail 312 shown in FIG.

  The clock signal output from the final stage CTS buffer 263 shown on the left side of FIG. 3 is boosted by the level shifter 243 and sent to eight flip-flops (FF_1 to FF_8) arranged adjacent to each other. The wiring delay from the level shifter to the flip-flop (FF) is not subjected to CTS processing and thus affects the clock skew. As shown in FIG. 3, eight flip-flops (FF) are arranged adjacent to the level shifter 243. By doing so, the wiring delay from the level shifter 243 to the eight flip-flops (FF) can be equalized and minimized.

The configuration of the embodiments of the present invention has been described above with reference to FIGS. In both the first embodiment and the second embodiment, a high voltage (for example, 1.2 V) is supplied to the data processing circuit that executes data processing.
Example 1
Reduce the voltage of the global clock generation block and local clock generation block,
Example 2
In this configuration, the global clock generation block and the local clock generation block are reduced in voltage, and the voltage of the entire clock network is reduced by reducing the voltage of the clock tree portion configured in the data processing block.

  In any of the embodiments, the voltage of the data processing circuit that receives the clock signal and executes the data processing is not reduced. With such a configuration, a configuration is realized in which power consumption can be reduced and data processing can be performed at a high operating frequency in the data processing circuit.

The fact that data processing at a high operating frequency is possible in the configuration of the present invention will be described in comparison with the conventional technology, that is, the configuration in which the entire functional block is reduced in voltage.
Hereinafter, referring to FIGS.
Configuration of the present invention, that is, configuration of the present invention configured to selectively lower the voltage of the clock generation block or the clock network including the clock generation block and the clock tree and maintain the data processing block or data processing unit at a high voltage When,
Conventional low power consumption configuration, that is, a conventional configuration in which the entire circuit including the data processing circuit is reduced in voltage,
The processing in these configurations will be described in comparison.

  FIG. 4 shows a circuit configuration for transferring signals between two flip-flops (FF1) 401 and flip-flop (FF2) 402 as a circuit example of the data processing circuit.

  The two flip-flops (FF1) 401 and the flip-flop (FF2) 402 perform data input / output by controlling the timing according to the input clock signal [CLK].

  First, data (DATA) taken into the flip-flop (FF1) 401 is output from the flip-flop (FF1) 401 as DATA_D_1 at the rising edge of the clock signal [CLK].

  Since the data line between the flip-flops (FF) normally includes a combinational circuit, the output data [DATA_D_1] from the flip-flop (FF1) 401 is data [DATA_D_2] having a delay time corresponding to the path length. ] Is taken into the next flip-flop (FF2) 402. The signal taken into the flip-flop (FF2) 402 is output from the flip-flop (FF2) 402 as [DATA_2D] at the rising edge of the clock signal [CLK].

FIG. 5 shows a timing chart of the above circuit in the case where a conventional technique, that is, a technique for reducing the voltage of the entire functional block is applied. In FIG.
(1) Timing chart when clock generation block and data processing block are set to high voltage,
(2) Timing chart when the clock generation block and the data processing block are set to low voltage,
These two timing charts are shown.

5 (1) and (2) from above,
(A) Clock signal: (a1) Clock pulse source signal and (a2) Input clock signal for data processing block (b) Data [DATA] input timing to previous stage flip-flop (FF) 401 (c) Previous stage flip-flop (FF ) Data [DATA_D_1] output timing from 401 (d) Data [DATA_D_2] input timing to the subsequent flip-flop (FF) 402 (e) Data [DATA_2D] output timing from the subsequent flip-flop (FF) 402 Show.

  5 (1) and 5 (2), the movement timing of the data [D] is indicated by dotted arrows.

First, a timing chart in the case where the high voltage shown in FIG. Before the time [T1], the data [D] is held in the previous flip-flop (FF) 401,
(B) The data [DATA] input timing to the preceding flip-flop (FF) 401 is output from the preceding flip-flop (FF) 401 in response to the rising edge of the clock signal at time [T2] as shown in FIG.
This output timing is time [T2].
Times [T1] to [T2] are delay times [td_clk_hiv_old] required for the clock signal to reach a predetermined voltage level. This delay time changes according to the drive voltage of the clock generation block.

(C) At the time [T2] shown in the data [DATA_D_1] output from the previous stage flip-flop (FF) 401, the output data [D]
(D) As shown in data [DATA_D_2] input timing to the subsequent flip-flop (FF) 402, the data is input to the subsequent flip-flop (FF) 402 at time [T3].
Times [T2] to [T3] are delay times [td_data_hiv_old] corresponding to the path length between the front-stage flip-flop (FF) 401 and the rear-stage flip-flop (FF) 402. This delay time changes according to the drive voltage in the data processing block.

The data [D] input to the subsequent flip-flop (FF) 402 is
(E) As shown in data [DATA_2D] output timing from the subsequent stage flip-flop (FF) 402, it is output from the subsequent stage flip-flop (FF) 402 at time [T5].

here,
(D) Data [DATA_D_2] input timing [T3] to the subsequent flip-flop (FF) 402;
(E) Data [DATA_2D] output timing [T5] from the subsequent flip-flop (FF) 402,
The period from [T3] to [T5] is the setup time [ts_hiv_old].

  As shown in FIG. 5A, in a setting in which a high voltage is supplied to both the clock generation block and the data processing block, a relatively long setup time [ts_hiv_old] can be secured.

  Next, the sequence shown in FIG. 5 (2), that is, a timing chart when the clock generation block and the data processing block are set to a low voltage will be described.

Before the time [t1], the data [D] is held in the previous flip-flop (FF) 401,
(B) The data [DATA] input timing to the previous flip-flop (FF) 401 is output from the previous flip-flop (FF) 401 in response to the rising edge of the clock signal at time [t2].
This output timing is time [t2].
Times [t1] to [t2] are delay times [td_clk_lov_old] necessary for the clock signal to reach a predetermined voltage level. As described above, this delay time changes according to the driving voltage of the clock generation block.

  Compared with the time [T1] to [T2] in FIG. 5 (1) in which the high voltage is set, the time [t1] to [t2] in FIG. 5 (2) in which the low voltage is set is longer. This is a phenomenon associated with a decrease in supply voltage to the clock generation block.

next,
(C) At the time [t2] shown in the data [DATA_D_1] output from the previous stage flip-flop (FF) 401, the output data [D]
(D) As shown in data [DATA_D_2] input timing to the subsequent flip-flop (FF) 402, the data is input to the subsequent flip-flop (FF) 402 at time [t3].
Times [t2] to [t3] are delay times [td_data_lov_old] corresponding to the path length between the front-stage flip-flop (FF) 401 and the rear-stage flip-flop (FF) 402. As described above, this delay time changes according to the drive voltage in the data processing block.

  Compared with the time [T2] to [T3] in FIG. 5 (1) in which the high voltage is set, the time [t2] to [t3] in FIG. 5 (2) in which the low voltage is set is longer. This is a phenomenon associated with a decrease in the supply voltage to the data processing block.

The data [D] input to the subsequent flip-flop (FF) 402 is
(E) As shown in data [DATA_2D] output timing from the subsequent stage flip-flop (FF) 402, it is output from the subsequent stage flip-flop (FF) 402 at time [t5].

here,
(D) Data [DATA_D_2] input timing [t3] to the subsequent flip-flop (FF) 402;
(E) Data [DATA_2D] output timing [t5] from the subsequent flip-flop (FF) 402,
The period from [t3] to [t5] is the setup time [ts_lov_old].

  Compared with the time [T3] to [T5] in FIG. 5 (1) in which the high voltage is set, the time [t3] to [t5] in FIG. 5 (2) in which the low voltage is set is shorter. In other words, the setup time has been shortened. This is a phenomenon associated with a decrease in the supply voltage to the data processing block.

  Thus, if the supply voltage of the data processing block is lowered, sufficient setup time cannot be secured. As a result, the operating frequency of the data processing circuit cannot be increased.

  Next, referring to FIG. 6, the configuration of the present invention, that is, the clock generation block or the clock network including the clock generation block and the clock tree is selectively reduced in voltage, and the data processing block or data processor is increased in voltage. A timing chart in this case will be described.

6 shows the operation timing of the flip-flops 401 and 402 shown in FIG.
(1) Timing chart when clock generation block and data processing block are set to high voltage,
(2) Timing chart when the voltage of the clock generation block is lowered and the data processing block is set to a high voltage,
These two timing charts are shown.

6 (1) and 6 (2) from above,
(A) Clock signal: (a1) Clock pulse source signal and (a2) Input clock signal for data processing block (b) Data [DATA] input timing to previous stage flip-flop (FF) 401 (c) Previous stage flip-flop (FF ) Data [DATA_D_1] output timing from 401 (d) Data [DATA_D_2] input timing to the subsequent flip-flop (FF) 402 (e) Data [DATA_2D] output timing from the subsequent flip-flop (FF) 402 Show.

  6 (1) and 6 (2), the movement timing of the data [D] is indicated by dotted arrows.

  The timing chart when the high voltage shown in FIG. 6A is set is exactly the same as the setting shown in FIG. The sequence shown in FIG. 6 (2), that is, a timing chart when the clock generation block or the clock network including the clock generation block and the clock tree is selectively lowered in voltage and the data processing block or data processor is increased in voltage. Will be described.

Prior to time [t1], data [D] is held in the previous flip-flop (FF) 401,
(B) The data [DATA] input timing to the previous flip-flop (FF) 401 is output from the previous flip-flop (FF) 401 in response to the rising edge of the clock signal at time [t2].
This output timing is time [t2].
Times [t1] to [t2] are delay times [td_clk_lov_new] necessary for the clock signal to reach a predetermined voltage level. As described above, this delay time changes according to the driving voltage of the clock generation block.

  Compared with the time [T1] to [T2] in FIG. 6 (1) in which the entire functional block is set to a high voltage, the time [t1] to [[2] in FIG. t2] is longer. This is a phenomenon that accompanies a decrease in the supply voltage to the clock generation block, and this part is the same as the relationship of FIGS. 5 (1) and (2).

next,
(C) At the time [t2] shown in the data [DATA_D_1] output from the previous stage flip-flop (FF) 401, the output data [D]
(D) As shown in data [DATA_D_2] input timing to the subsequent flip-flop (FF) 402, the data is input to the subsequent flip-flop (FF) 402 at time [t3].
Times [t2] to [t3] are delay times [td_data_lov_new] corresponding to the path length between the front-stage flip-flop (FF) 401 and the rear-stage flip-flop (FF) 402. As described above, this delay time changes according to the drive voltage in the data processing block.

FIG. 6A shows the time [T2] to [T3] ([td_data_hiov_new]) of FIG. 6 (1) in which all functional blocks are set to high voltage, the clock generation block and the like are set to low voltage, and the data processing unit is set to high voltage The delay time is the same as the time [t2] to [t3] of 6 (2). That is,
[Td_data_lov_new] = [td_data_hiv_new]
It has become.
This is because the same high voltage (for example, 1.2 V) is present in the data processing unit in FIGS. 6A and 6B, and the delay is the same time.

Next, the data [D] input to the subsequent flip-flop (FF) 402 is
(E) As shown in data [DATA_2D] output timing from the subsequent stage flip-flop (FF) 402, it is output from the subsequent stage flip-flop (FF) 402 at time [t5].

here,
(D) Data [DATA_D_2] input timing [t3] to the subsequent flip-flop (FF) 402;
(E) Data [DATA_2D] output timing [t5] from the subsequent flip-flop (FF) 402,
The period from [t3] to [t5] is the setup time [ts_lov_new].

Compared to the times [T3] to [T5] in FIG. 6A in which all the functional blocks are set to high voltage, the clock generation block and the like are set to low voltage, and the data processing unit is set to high voltage. The times [t3] to [t5] of 2) are substantially the same time, and unlike FIG.
Setup time is not shortened. This is because the supply voltage to the data processing block is not lowered.

  In this way, a sufficient setup time can be ensured by adopting a configuration in which the supply voltage of the data processing block is maintained at a high voltage without decreasing. As a result, the operating frequency of the data processing circuit can be increased.

  Thus, in the configuration of the present invention, the clock generation block or the clock network including the clock generation block and the clock tree is selectively lowered in voltage, and the data processing block or the data processing unit is increased in voltage. Thus, low power consumption is realized, and it is possible to increase the operating frequency in the data processing unit by securing a sufficient setup time.

  Finally, let us consider the power consumption reduction effect when using this method using specific numerical values. For example, in a recent image processing LSI, the clock power consumption accounts for nearly 40% of the power consumption of the entire logic. Furthermore, if we focus only on the functional blocks of the controller system, there are cases where over 80% of the total power is actually from the clock system.

  Therefore, the power reduction effect is estimated when the clock logic voltage can be reduced from 1.2 V to 0.8 V in the case where the clock system power accounts for 40% and 80% of the total, respectively. Reduced rate = power consumption when high voltage (1.2V) is supplied to all functional blocks as [1], power consumption [X] when clock system power occupies 40% and 80% respectively Calculate as [1]-[X].

If the clock power is 40%,
Reduction rate = [1]-[X]
= 1-{(0.4 × 0.8 ² + 0.6 × 1.2 ² ) /1.2 ² }
= 0.22 → 22% reduction When the clock system power is 80%.
Reduction rate = [1]-[X]
= 1-{(0.8 × 0.8 ² + 0.2 × 1.2 ² ) /1.2 ² }
= 0.45 → 45% reduction

  As described above, the power generation can be significantly reduced by selectively reducing the voltage of the clock generation block or by selectively reducing the voltage of the clock network including the clock generation block and the clock tree. Furthermore, by applying the present invention, the power consumption can be almost halved without affecting the setup time, that is, the maximum operating frequency of the LSI.

  The present invention has been described in detail above with reference to specific embodiments. However, it is obvious that those skilled in the art can make modifications and substitutions of the embodiments without departing from the gist of the present invention. In other words, the present invention has been disclosed in the form of exemplification, and should not be interpreted in a limited manner. In order to determine the gist of the present invention, the claims should be taken into consideration.

  As described above, in the configuration of an embodiment of the present invention, the clock generation unit that executes the clock signal generation process, and the data processing unit that executes the data processing by inputting the clock generated by the clock generation unit are provided. Since the power supplied to the clock generation unit is set to a relatively low voltage (for example, 0.8 V) compared to the data processing unit, the power consumption of the entire circuit is reduced. In addition, since the data processing unit is configured to supply a high voltage (for example, 1.2 V), the data processing unit can perform data processing at a high operating frequency.

It is a figure explaining the structural example of the semiconductor integrated circuit of one Example of this invention. It is a figure explaining the structural example of the semiconductor integrated circuit of one Example of this invention. It is a figure explaining the example of physical arrangement | positioning of the level shifter and flip-flop (FF) in the semiconductor integrated circuit structure of one Example of this invention. It is a figure explaining the flip-flop (FF) which comprises the data processing circuit in the semiconductor integrated circuit of one Example of this invention. It is a figure explaining the timing chart of the data processing in the conventional type semiconductor integrated circuit. It is a figure explaining the timing chart of the data processing in the semiconductor integrated circuit of one Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor integrated circuit 101 Crystal oscillator 102 PLL (Phase Locked Loop)
110 Clock generation block 111 to 113 Frequency division / CG unit 120, 140, 160 Function block 121, 122, 141, 142, 161, 162 Data processing block 130, 150, 170 Local clock generation block 190 Power control block 200 Function block 210 Local clock generation block 211, 212 Frequency division / CG unit 220 Data processing block 221 Clock tree unit 222 Data processing unit 230 Data processing block 241-243 Level shifters 251, 261-263 CTS buffer 311 0.8V power supply rail 312 1.2V power supply Rail 401 flip-flop (FF1)
402 Flip-flop (FF2)

Claims (7)

A clock generation unit for executing a clock signal generation process;
A data processing unit that inputs a clock generated by the clock generation unit and executes data processing;
A power supply unit that performs power supply to the clock generation unit and the data processing unit;
The semiconductor integrated circuit according to claim 1, wherein the clock generation unit is configured to operate by inputting low-voltage power that is relatively lower than that of the data processing unit from the power supply unit. The clock generator is
A global clock generator for generating clock signals for a plurality of functional blocks set in the semiconductor integrated circuit;
A local clock generation unit that generates a clock signal for each of a plurality of functional blocks including a data processing unit set in the semiconductor integrated circuit;
Both the global clock generation unit and the local clock generation unit are configured to operate by inputting relatively low power from the power supply unit as compared with the data processing unit. The semiconductor integrated circuit according to claim 1. The data processing unit
2. The semiconductor integrated circuit according to claim 1, wherein the boosted clock signal is supplied from the clock generation unit via a boosting unit set in a clock signal input unit to the data processing unit. circuit. The semiconductor integrated circuit further includes:
A clock tree unit configured in each of a plurality of functional blocks including a data processing unit set in the semiconductor integrated circuit, the clock tree unit also having a relatively low voltage compared to the data processing unit The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit has a configuration that operates by electric power. The data processing unit
5. The semiconductor integrated circuit according to claim 4, wherein the boosted clock signal is supplied from the clock tree unit through a boosting unit set as a clock signal input unit to the data processing unit. circuit.   6. The clock tree unit is a circuit that performs clock skew adjustment by a plurality of CTS buffers, and has a CTS buffer setting configuration in consideration of clock skew in a path from a clock signal supply source to the boosting unit. A semiconductor integrated circuit according to 1. The data processing unit includes a plurality of flip-flops that input a clock signal through one boosting unit,
6. The semiconductor integrated circuit according to claim 5, wherein the plurality of flip-flops have a configuration arranged adjacent to the one boosting unit.

Images