JP2009064891A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which includes an inspection process where a supply current from a power source incorporated in a tester can be suppressed when a plurality of semiconductor chips are inspected together at a time. <P>SOLUTION: The method of manufacturing the semiconductor device is provided with a step of inputting a clock signal and an input signal to respective self-diagnostic circuits with different delay times. Consequently, when many semiconductor chips are inspected together at a time, the plurality of semiconductor chips do not have current peaks at the same timing. Especially, the method includes a step of providing a delay circuit which inputs one clock signal and input signal to the respective self-diagnostic circuits at different delay time based upon the clock signal and input signal. A circuit module includes the delay circuit, and wirings connecting the circuit module and the respective self-diagnostic circuits are formed on a scribe line of a semiconductor substrate. Consequently, a pad of a semiconductor chip need not be probed, thereby maintaining the quality of the product pad. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including an inspection process for measuring a plurality of semiconductor integrated circuits simultaneously.

  A series of manufacturing processes for a semiconductor integrated circuit includes a diffusion process for processing a fine pattern of a circuit and an inspection process for inspecting the function of each semiconductor chip formed on the wafer in the wafer state after the completion of the diffusion process. Yes.

  Conventionally, as a technique for inspecting a plurality of semiconductor chips formed on a semiconductor wafer all at once, there is a method of providing a power supply wiring and a signal wiring which are wirings shared by a plurality of semiconductor chips on a scribe line. Then, the common power supply wiring and signal wiring are connected to the bonding pads provided on each of the plurality of semiconductor chips, and inspection is performed using a self-diagnosis circuit provided in each semiconductor chip by batch electrical control. A method has been proposed.

  The inspection by the self-diagnosis circuit is an inspection method performed by providing an inspection circuit capable of executing inspection and self-determination of the inspection result in the inspection target circuit in the semiconductor chip and controlling the inspection circuit from the outside.

  There are various methods for realizing this self-diagnosis circuit. For example, as shown in FIG. 4, first, the basic operation of the internal circuit of the semiconductor chip 312 is designed, and a fixed clock signal is supplied from the clock supply line 322. , And an inspection signal is input from the signal line 321. On the other hand, an expected value of a normal response to the inspection signal is stored in a ROM (Read Only Memory) or the like. Then, the quality of the semiconductor chip 312 is determined based on whether or not the actually obtained response matches the expected value.

  This pass / fail result is stored in the shift register 331 in the self-diagnosis circuit 325. For example, if the value of the shift register 331 is 1, it is determined that it is a non-defective product, and if it is 0, it is a defective product. In the example of FIG. 4, the semiconductor chip 312 is a non-defective product. For each of the plurality of semiconductor chips 312 on the wafer, the value of the shift register 331 can be taken out from the output line 323 and referenced to check which semiconductor chip is a good product or a defective product.

  With this method, for example, in system LSI products, logic circuits, memory circuits such as SRAM (Static Random Access Memory) and ROM, analog circuits such as PLL (Phase Locked Loop) circuits and AD / DA converters should be inspected. Can do. The inspection time can be shortened by simultaneously controlling and inspecting the self-diagnosis circuits of a plurality of semiconductor chips on the wafer as described above. In the inspection by the self-diagnosis circuit, it is not necessary to directly contact the probe needle attached to the probe card (inspection card) with the bonding pad provided on the semiconductor chip. For this reason, damage to the bonding pad can be reduced, and the deterioration of the quality of the semiconductor chip can be prevented.

As described above, for example, Patent Document 1 below discloses a method in which a power supply wiring and a signal wiring are provided on a scribe line and a plurality of semiconductor chips are simultaneously inspected by such a self-diagnosis circuit.
Japanese Patent Laid-Open No. 11-204597 (page 8, FIG. 1)

  The inspection method disclosed in Patent Document 1 has the following problems when a logic circuit such as a large-scale, high-function system LSI is inspected by this method.

  First, in order to perform this inspection, it is necessary to operate a plurality of semiconductor chips through one (possibly several) internal power supply pads on the wafer. For this reason, it is presumed that there arises a problem that the operating current during the inspection increases in proportion to the number of semiconductor chips on the wafer to be inspected at the same time.

  In addition, as the logic circuit becomes larger due to the recent miniaturization of semiconductor element patterns, the number of inspection terminals and inspection patterns has increased, and as one of the solutions, inspection by self-diagnosis circuits has increased. It is coming. However, when testing a large-scale logic circuit with a self-diagnostic circuit, the logic elements are activated all at once in the test operation, and the operation signal changes, so that even when considering the operation of one semiconductor chip, a large current is consumed. There is a case.

  Furthermore, when simultaneously inspecting a large number of semiconductor chips, if the current peak timing is overlapped by a plurality of semiconductor chips, the single power supply built in the tester cannot supply the current, so the inspection cannot be performed normally. There is a problem that problems arise.

  The present invention has been made in view of such problems, and in the case where a plurality of semiconductor chips are inspected at the same time, a semiconductor device including an inspection process capable of suppressing the amount of current supplied from a power source built in the tester It aims to provide a method.

  In order to achieve the above object, the present invention employs the following means.

  First, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of semiconductor devices mounted with a self-diagnosis circuit on a semiconductor substrate, and a step of providing a supply circuit for supplying a voltage to the self-diagnosis circuit from the outside. It has. In addition, the self-diagnosis circuit includes a step of providing an input circuit for inputting a clock signal and an input signal, and a step of inspecting the quality of the semiconductor device based on a response to the input.

  In such a semiconductor device manufacturing method, a step of inputting the clock signal and the input signal to each of the self-diagnosis circuits with different delay times is provided. Thus, as described above, when a large number of semiconductor chips are inspected at the same time, the current peak timing does not overlap among a plurality of semiconductor chips.

  In particular, there is provided a step of providing a delay circuit for inputting the clock signal and the input signal to each of the self-diagnosis circuits with different delay times based on one clock signal and the input signal. Then, a circuit module (an assembly of circuits) including the delay circuit and wiring for connecting the circuit module and each of the self-diagnosis circuits are formed on the scribe line of the semiconductor substrate. This eliminates the need for probing the pads of the semiconductor chip, so that the quality of the product pads can be maintained.

  Further, each semiconductor device, the circuit module, and the wiring are formed in one exposure shot region in a photolithography process of the semiconductor device. Thereby, the circuit module and the wiring can be easily manufactured simultaneously with the internal circuit constituting the semiconductor chip.

  Further, a plurality of the circuit modules are provided, the circuit modules are connected to the respective self-diagnostic circuits by the wiring, and the circuit modules are arranged at the four corners in the one exposure shot area. Thus, even when the exposure shot area is missing in the wafer peripheral area and some of the circuit modules are missing, the inspection can be performed with any of the four circuit modules.

  As described above, according to the present invention, when a plurality of semiconductor chips are operated by a single power source and inspected, the current peak is dispersed by shifting the circuit operation timing of each semiconductor chip using an input delay circuit. Since the amount of supplied current can be suppressed, it is possible to perform the inspection normally. If semiconductor chips can be inspected all at once, the inspection time can be shortened. Further, if each semiconductor chip can be inspected with the pads and signal lines provided on the scribe line, it is not necessary to perform probing on the pads of the semiconductor chip, so that the quality of the product pads can be maintained. In addition, since the number of probe card needles is minimized, the cost of the jig can be reduced.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram schematically showing a circuit for explaining an inspection process used in a method for manufacturing a semiconductor device according to the present invention.

  In FIG. 1, three semiconductor chips 101 are illustrated, but in actuality, a larger number of semiconductor chips exist on the wafer. A self-diagnosis circuit 102 is formed inside each semiconductor chip 101. Each semiconductor chip 101 is supplied with power from a power supply pad 104 through a power supply line 103 and grounded by a ground pad 106 through a ground line 105. The power supply pad 104 and the power supply line 103 are called a supply circuit.

  In addition, a clock signal is input to each semiconductor chip 101 from the clock signal pad 108 through the clock signal line 107, and an inspection signal is input from the input signal pad 110 through the input signal line 109. The clock signal pad 108, the clock signal line 107, the input signal pad 110, and the input signal line 109 are referred to as an input circuit. The pass / fail result in response to this test signal of the self-diagnosis circuit 102 in each semiconductor chip 101 is taken out from the output signal line 112, temporarily stored in the output storage circuit 113, and output from the output signal pad 114 to the outside of the wafer. . Note that the arrows in FIG. 1 indicate the connection and the direction of the signal flowing through the connection.

  The power line 103, the ground line 105, the clock signal line 107, the input signal line 109, the output signal line 112, and the like, the circuit including the output storage circuit 113 and the delay circuit 111 described later, and the power pad 104 and the ground pad 106 The clock signal pad 108, the input signal pad 110, and the output signal pad 114 are formed on the scribe line 115. Here, the scribe line 115 refers to a region between the semiconductor chips 101 including a cutting region for separating each semiconductor chip 101 formed on the wafer.

  These circuits and each pad arranged on the scribe line 115 are treated as a circuit module (collection of circuits) in a lump. Specifically, the circuit module is arranged at four apex portions of one exposure shot in a photolithography process for forming a semiconductor chip pattern on a wafer, for example. This is to cope with the lack of one exposure shot located at the periphery of the wafer and the formation of some circuit module patterns, which will be separately described in a second embodiment to be described later.

  The layout of the circuit and each pad in this circuit module is basically arbitrary, but it is necessary to apply a probe card needle to each pad such as the ground pad 106 formed on the scribe line 115 in order to supply a signal. There is. For this reason, in order to perform pad arrangement at intervals where needles can be held and to perform inspection with one probe card (inspection card), the arrangement of pads for each of the plurality of circuit modules is always required to be the same. . The shortest wiring is made from the circuit module to each pad provided on each semiconductor chip 101. This wiring is formed on the scribe line 115 as described above. The circuit module on the scribe line 115 has a layout determined for each exposure shot, and can be easily manufactured simultaneously with the internal circuits constituting the semiconductor chip 101.

  Next, an inspection method for suppressing the peak current of the semiconductor integrated circuit in the present embodiment will be described with reference to FIG.

  The semiconductor chip 101 determines whether the internal circuit of the semiconductor chip 101 itself is acceptable or not using the self-diagnosis circuit 102 provided inside. That is, the self-diagnosis circuit 102 operates by the power supply, clock signal, and input signal supplied from the LSI tester device. As described above, power is supplied from the power supply pad 104 to the plurality of semiconductor chips 101 through the power supply line 103. The plurality of semiconductor chips 101 are grounded by the ground pads 106 through the respective ground lines 105. The clock signal is supplied from the clock signal pad 108 to the plurality of semiconductor chips 101 through the clock signal line 107. The input signal is supplied from the input signal pad 110 to the plurality of semiconductor chips 101 through the input signal line 109.

  The pass / fail result of the self-diagnosis circuit 102 is temporarily taken into the output storage circuit 113 from the output signal line 112 of each of the plurality of semiconductor chips 101, and taken out from the output signal pad 114 to the LSI tester device. When fetching the pass / fail result into the output storage circuit 113, it fetches in synchronization with the clock signal from the clock signal line 107.

  For example, when a sufficient amount of time has elapsed until all the test result data of the plurality of semiconductor chips 101 are output from the output signal line 112 having a parallel output configuration, the output is output to the serial register row in the output storage circuit 113. If the data is to be stored, then the clock signal 107 is used to capture into this register string (capture operation). In addition, when the output signal stored in the register row of the output storage circuit 113 is taken out from the output signal pad 114 in series, it is taken out using the clock signal 107 (shift operation).

  In this case, a signal line for switching between the capture operation and the shift operation of the register row is not shown in FIG. 1, but is formed on the scribe line 115 separately. The result extracted from the output signal pad 114 is determined by the LSI tester device. All the pads and circuits described above are formed on the scribe line 115 as described above. With these configurations, a plurality of semiconductor chips 101 can be inspected simultaneously.

  However, when a plurality of semiconductor chips 101 are actually inspected simultaneously, the operating current increases in proportion to the number of semiconductor chips to be inspected. For example, when a large-scale logic circuit is inspected by the self-diagnosis circuit 102, logic elements on a plurality of semiconductor chips 101 may operate at the same time to consume a large current. Then, if the current peak timing overlaps between the plurality of semiconductor chips 101, the single power source built in the LSI tester device cannot supply current, and thus the inspection cannot be performed normally.

  Therefore, in this embodiment, the input delay circuit 111 is provided on the clock signal line 107 and the input signal line 109. This input delay circuit 111 is also formed on the scribe line 115.

  The clock signal and the input signal are supplied to the plurality of semiconductor chips 101 by giving different delay amounts to the input delay circuit 111. The signal delay amount is obtained by power consumption simulation and timing simulation at the time of designing a semiconductor integrated circuit. As a result, the amount of delay of the signal is determined by taking into account the wiring distance between the semiconductor chip 101 and the pads on the scribe line 115, and the delay time in which the current peak is dispersed for each semiconductor chip involved in the simultaneous inspection. It is the value that was given. The obtained delay amount is stored in the delay adjustment buffer cell in the input delay circuit 111, and is uniquely given every time a test is performed.

  In this way, the input delay circuit 111 disperses the timing of the circuit operation of each semiconductor chip 101 so that the current peaks are dispersed, and the inspection current value is reduced even when the power supply of the LSI tester device is one. The test can be carried out normally.

  As described above, by using the inspection process according to the first embodiment of the present invention, the input delay circuit 111 gives different delay amounts to the clock signal and the input signal of each semiconductor chip 101. A timing difference occurs in the circuit operation of the semiconductor chip 101, and current peaks are dispersed without overlapping. Therefore, a shortage of power supply current of the LSI tester device is avoided, so that the inspection can be carried out normally. As a result, simultaneous inspection of the semiconductor chips 101 can be performed, and the entire inspection time can be shortened. In addition, since the probe needle is not brought into contact with the bonding pad formed on each semiconductor chip 101, it is possible to contribute to maintaining product quality. Further, since the probe needles need only be brought into contact with each pad on the scribe line 115, the number of probe needles is reduced, and the cost of the probe card can be reduced.

(Second Embodiment)
FIG. 2 is a diagram for explaining an inspection process used in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

  As shown in FIG. 2 (a), a plurality of semiconductor chips 215 are arranged on the wafer. Similar to the first embodiment, a circuit composed of an output storage circuit 211 and a delay circuit 209, a power pad 202, a ground pad 204, a clock signal pad 206, an input signal pad 208, and an output are provided around the scribe line 214. Each pad of the signal pad 212 forms a circuit module 217 (FIG. 2 (b)).

  Further, a self-diagnosis circuit 216 is formed inside each semiconductor chip 215, and each semiconductor chip 215 is supplied with power from the power supply pad 202 through the power supply line 201 and grounded by the ground pad 204 through the ground line 203. Yes. Similar to the first embodiment, the power supply pad 202 and the power supply line 201 are referred to as a supply circuit.

  In addition, a clock signal is input to each semiconductor chip 215 from the clock signal pad 206 through the clock signal line 205, and an inspection signal is input from the input signal pad 208 through the input signal line 207. As in the first embodiment, the clock signal pad 206, the clock signal line 205, the input signal pad 208, and the input signal line 207 are referred to as an input circuit. The pass / fail result of each semiconductor chip 215 in response to the inspection signal is taken out from the output signal line 210, temporarily stored in the output storage circuit 211, and output from the output signal pad 212 to the outside of the wafer.

  In the present embodiment, the circuit module 217 is arranged at the four corners of the shot region 213 where four semiconductor chips 215 are taken as one exposure shot. Here, the four corners are four partial areas including the apexes in the shot area 213 as shown in FIG. 2 (a). Note that the circuit modules 217 are similarly arranged at the four corners of the shot area adjacent to the shot area 213. Therefore, the circuit module 217 in both the shot area 213 and the adjacent shot area is included on one scribe line 214. Further, for the semiconductor chip 215 in the shot region 213 surrounded by the four circuit modules 217, the power line 201, the ground line 203, the clock signal line 205, the input signal line 207, and the output signal line from the four circuit modules 217. Each wiring of 210 is wired so as to be shared by four semiconductor chips.

  With the above configuration, the four semiconductor chips 215 in the shot region 213 can be collectively inspected by any one of the four circuit modules 217. In this configuration, one shot region 213 includes the semiconductor chip 215, the circuit module 217 for inspection, and the wiring. Therefore, there is an advantage that manufacturing can be easily performed with one type of reticle, that is, a photomask, having four semiconductor chips, four circuit modules, and wiring patterns.

  Further, as shown by a dotted line in FIG. 3, even if the shot area 213 is missing in the peripheral area of the wafer 300 and some of the circuit modules 217 are missing, a semiconductor chip can be used if any one of the four circuit modules 217 can be used. 215 can be tested.

  Note that each of the wirings described above is formed in the shortest distance from all the four circuit modules 217 to all the semiconductor chips 215 in the shot region 213, and is formed on the scribe line 214. Even when chipping occurs in the shot area 213, the circuit module 217 and the wiring that are opposite to the chipping position or in the diagonal direction are considered to function without disconnection because they are not routed to the chipping chip area.

  If it is considered to eliminate the problem of disconnection more completely, as shown in FIG. 2 (c), by providing the same power supply / signal pad on each of the four sides of the semiconductor chip 215, shorter wiring is made. It can be considered that the influence of the disconnection due to the chipping of the shot can be completely eliminated.

  As described above, by using the inspection process according to the second embodiment of the present invention, the circuit module 217 can be easily formed in manufacturing. Also, from the viewpoint of current consumption, a plurality of simultaneous inspections of the semiconductor chip 215 can be easily realized. As a result, the inspection time of the semiconductor chip 215 can be shortened. Furthermore, since it is not necessary to bring the probe needle into contact with the bonding pad on the semiconductor chip, it contributes to the maintenance of product quality, and the probe card only needs to have the minimum probe needle required on the scribe line. Cost reduction of tools can be realized. The inspection method according to the present invention is effective for simultaneous inspection of large-scale, high-density, and multifunctional system LSIs using process technologies such as 90 nm, 65 nm, and 45 nm below the 100 nm node process. This is because such an LSI itself consumes a large amount of power, and the current during standby is large due to the thin gate insulating film of the MOS transistor.

  The method of manufacturing a semiconductor device according to the present invention, when operating and testing a plurality of semiconductor chips with a single power source, shifts the timing of the circuit operation of each semiconductor chip using an input delay circuit, thereby increasing the current peak. It is possible to carry out inspections normally by dispersing them. If semiconductor chips can be inspected all at once, the inspection time can be shortened. Further, if each semiconductor chip can be inspected with the pads and signal lines provided on the scribe line, it is not necessary to perform probing on the pads of the semiconductor chip, so that the quality of the product pads can be maintained. In addition, since the number of probe card needles is minimized, the cost of the jig can be reduced. Therefore, it is particularly useful as a method for manufacturing a large-scale integrated circuit.

Explanatory drawing of the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing of the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. Explanatory drawing of a missing shot area. Explanatory drawing of a self-diagnosis circuit.

Explanation of symbols

101 Semiconductor chip 102 Self-diagnosis circuit 103 Power line 104 Power pad 105 Ground line 106 Ground pad 107 Clock signal line 108 Clock signal pad 109 Input signal line 110 Input signal pad 111 Input delay circuit 112 Output signal line 113 Output storage circuit 114 Output signal Pad 115 scribe line 201 power supply line 202 power supply pad 203 ground line 204 ground pad 205 clock signal line 206 clock signal pad 207 input signal line 208 input signal pad 209 input delay circuit 210 output signal line 211 output storage circuit 212 output signal pad 213 shot Region 214 Scribe line 215 Semiconductor chip 216 Self-diagnosis circuit 217 Circuit module

Claims (6)

Forming a plurality of semiconductor devices on which a self-diagnosis circuit is mounted on a semiconductor substrate; providing a supply circuit for supplying a voltage to the self-diagnosis circuit from outside; a clock signal and an input signal in the self-diagnosis circuit; In a method for manufacturing a semiconductor device, comprising: a step of providing an input circuit for performing the input of the step; and a step of inspecting the quality of the semiconductor device based on a response to the input.
A method of manufacturing a semiconductor device, comprising: inputting the clock signal and the input signal to the self-diagnosis circuits with different delay times.   The semiconductor according to claim 1, further comprising a step of providing a delay circuit that inputs the clock signal and the input signal to each of the self-diagnosis circuits with different delay times based on one clock signal and the input signal. Device manufacturing method.   3. The method of manufacturing a semiconductor device according to claim 2, wherein a circuit module including the delay circuit and wiring for connecting the circuit module and each of the self-diagnosis circuits are formed on a scribe line of the semiconductor substrate.   4. The method of manufacturing a semiconductor device according to claim 3, wherein each of the semiconductor devices, the circuit module, and the wiring are formed in one exposure shot region in a photolithography process of the semiconductor device.   5. The method of manufacturing a semiconductor device according to claim 3, wherein a plurality of the circuit modules are provided, and each of the circuit modules is connected to each of the self-diagnosis circuits by the wiring.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the circuit module is arranged at four corners in the one exposure shot area.

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