JP2009044139A - Carbon nanotube field-effect transistor, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method capable of manufacturing a carbon nanotube field-effect transistor which stably exhibits excellent electrical conductivity, with satisfactory reproducibility. <P>SOLUTION: The method includes a first step of placing a carbon nanotube serving as a channel on a substrate and then protecting the carbon nanotube with a passivation film; a second step of cutting the both ends of the carbon nanotube to expose faces which will be jointed to a source electrode and a drain electrode, respectively; and a last step of jointing cut faces located on the both ends of the carbon nanotube to the source electrode and the drain electrode, respectively. The field-effect transistor manufactured by this method has electrical characteristics independent of a sign of voltage applied to the source electrode and the drain electrode. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a carbon nanotube field effect transistor and a manufacturing method thereof.

  Carbon nanotubes (hereinafter referred to as “CNT”) exhibit semiconducting or metallic properties due to chirality. In addition, since CNT has a diameter of several nanometers and its current density is high, it enables formation of very thin wiring with one-dimensional conduction, and is expected to be applied to a quantum device operating at high speed. Further, semiconducting CNTs have been applied as channels of field effect transistors (hereinafter referred to as “FETs”) and are actively researched.

  A carbon nanotube field effect transistor (hereinafter referred to as “CNT-FET”) using CNT as a channel is a method in which a source electrode and a drain electrode are formed at both ends of a CNT after the CNT is dissolved in a solvent and dispersed on a substrate (dispersion method) Alternatively, it is manufactured by a method (direct growth method) in which a source electrode and a drain electrode are formed on both ends of a CNT after the CNT is grown from a catalyst arranged in advance on a substrate.

  However, in the above-described conventional manufacturing method, since the CNTs serving as channels are exposed to cleaning chemicals or resists for patterning during the electrode formation process, defects are formed by the chemicals or resist residues. (See Non-Patent Document 1 and Non-Patent Document 2). The defects formed in this way cause scattering in the electrical conduction of the FET. In addition, since CNTs with many defects are likely to adsorb oxygen, water molecules, etc. in the atmosphere, the formed defects together with contaminants that cannot be removed during the manufacturing process cause the hysteresis characteristics with respect to the gate bias of the FET. Efforts have been made to improve the hysteresis characteristics by removing contaminants by cleaning and forming a passivation film made of an insulator in the subsequent process, but defects once formed are not improved. In addition, contaminants remaining on the CNT can cause a deterioration in bonding characteristics between the CNT and the electrode, which will be described later.

  FIG. 10 is a diagram showing a configuration of a CNT-FET manufactured by a conventional method (direct growth method). In FIG. 10, a CNT-FET 10 includes a substrate 11, a source electrode 12, a drain electrode 13, a CNT 14 serving as a channel, and a catalyst 15. As shown in FIG. 10 (particularly, see the drain electrode 13 side), the CNT-FET manufactured by the conventional method is a so-called “side contact CNT-FET in which the source electrode and the drain electrode are joined to the side surfaces of the CNT. (Side-Contact CNT-FET) structure ”. At this time, since the CNTs serving as channels are arranged so as to lie on the substrate, the source electrode and the drain electrode cannot be bonded to the lower (substrate side) side surface of the CNTs. In addition, in the CNT-FET manufactured by the conventional method, since the length of the channel CNT is not controlled, the junction area between the source electrode and the CNT may be different from the junction area between the drain electrode and the CNT. (See FIG. 10). When a difference occurs in the junction area as described above, a difference occurs in the contact resistance between these junction surfaces, and there is a high possibility that the current characteristics become asymmetric. Furthermore, when the CNT-FET is manufactured by the conventional method using the direct growth method, the catalyst remains in the source electrode and the drain electrode (see FIG. 10). Such a catalyst in the electrode may affect the electrical characteristics of the CNT-FET. These problems cause variations in the performance and electric conduction characteristics of the CNT-FET.

When metal is bonded to CNT, the work function of the metal and the work function of CNT are reflected in the bonding characteristics, and an energy barrier is formed due to the difference in work function (see Non-Patent Document 3 and Non-Patent Document 4). Therefore, it is considered that different bonding characteristics are exhibited when the metal material is changed, but the same result is not necessarily obtained. This is presumably because defects and contaminants of CNTs differ depending on the difference in technical level and environmental level in the manufacturing process, and it is difficult to obtain the same quality of bonding characteristics.
T. Mizutani et al., "Effects of Fabrication Process on Current-Voltage Characteristics of Carbon Nanotube Field Effect Transistors", Jpn. J. Appl. Phys., (2005), Vol. 44, pp. 1599-1602. H. Shimauchi et al., “Suppression of Hysteresis in Carbon Nanotube Field-Effect Transistors: Effect of Contamination Induced by Device Fabrication Process”, Jpn. J. Appl. Phys., (2006), Vol. 45, pp. 5501- 5503. Z. Chen et al., "The Role of Metal-Nanotube Contact in the Performance of Carbon Nanotube Field-Effect Transistors", Nano Lett., Vol. 5, (2005), pp. 1497-1502. R. Martel et al., “Ambipolar Electrical Transport in Semiconducting Single-Wall Carbon Nanotubes”, Phys. Rev. Lett. Vol. 87, (2001), pp 256805.

  As described above, the CNT-FET manufactured by the conventional method has the following drawbacks and problems. (1) Since the channel CNT is exposed to the atmosphere, oxygen and water molecules in the atmosphere are easily adsorbed to the CNT, and the characteristics of the CNT-FET are greatly influenced by environmental changes such as humidity. (2) The CNT-FET is unstable due to the adsorbed water molecules because it exhibits a hysteresis characteristic with respect to the gate bias. (3) In the CNT-FET manufacturing process, CNTs are exposed to cleaning chemicals, resists for patterning, and the like, so that CNTs are contaminated and defects are formed. (4) The contaminants in (3) above deteriorate the bonding characteristics between the CNT and the electrode. (5) The formation of the defect in (3) causes deterioration of the characteristics of the CNT-FET due to scattering or the like, and the one-dimensional conduction that the original CNT has does not hold. (6) Since the length of the CNT is not controlled and the junction area of the source electrode-CNT and the junction area of the drain electrode-CNT are different, a difference in contact resistance between the source electrode and the drain electrode occurs, and current characteristics Is easily asymmetric and it is difficult to produce a CNT-FET having excellent reproducibility.

  This invention is made | formed in view of this point, and it aims at providing the method which can manufacture CNT-FET which shows the outstanding electrical conductivity stably with sufficient reproducibility.

  The FET manufacturing method of the present invention is a method for manufacturing an FET having a source electrode and a drain electrode formed on a substrate, and a channel made of CNTs connecting the source electrode and the drain electrode. And forming a passivation film on the CNT before forming the source electrode and the drain electrode, and cutting the CNT to expose the first end face and the second end face of the CNT. And forming a source electrode joined to the first end face and a drain electrode joined to the second end face.

  The FET of the present invention is a FET having a source electrode and a drain electrode formed on a substrate, and a channel made of CNT connecting the source electrode and the drain electrode, and the CNT is covered with a passivation film. The source electrode is joined to the first end face of the CNT, the drain electrode is joined to the second end face of the CNT, and the junction area of the source electrode and the CNT is the drain electrode and the CNT It is substantially the same as the bonding area of CNT.

  According to the present invention, a CNT-FET that stably exhibits excellent electrical conduction characteristics can be produced with good reproducibility.

1. CNT-FET of the present invention
A CNT-FET manufactured by the manufacturing method of the present invention (hereinafter also referred to as “CNT-FET of the present invention”) is a substrate, a source electrode and a drain electrode formed on the substrate, and a connection between the source electrode and the drain electrode. A channel made of CNTs and a gate electrode.

  FIG. 1 is a diagram showing an example of a connection relationship between CNTs serving as a source electrode, a drain electrode, and a channel in the CNT-FET of the present invention. In FIG. 1, a CNT-FET 100 includes a substrate 110, a source electrode 120, a drain electrode 130, a CNT 140 serving as a channel, and a passivation film 150. In this example, the substrate 110 includes a silicon substrate 112 and a silicon oxide film 114. In the CNT-FET 100, a current flowing between the source electrode 120 and the drain electrode 130 is controlled by a voltage applied to a gate electrode (not shown).

  As will be described later, the CNT-FET manufacturing method of the present invention is characterized in that the CNTs that become the channels are cut and the source electrode and the drain electrode are joined to the cut surfaces (end faces) located at both ends of the CNTs. And Therefore, the CNT-FET of the present invention has a so-called “end-contact CNT-FET (End-Contact CNT-FET) structure in which the source electrode and the drain electrode are respectively joined to cut surfaces (end surfaces) located at both ends of one CNT. (Refer to FIG. 1 and FIG. 10 for comparison).

[Substrate]
The substrate included in the CNT-FET of the present invention is preferably an insulating substrate. The insulating substrate is, for example, a substrate made of an insulator, or a substrate in which at least a surface on which a source electrode and a drain electrode are arranged is covered with an insulating film of a support substrate made of a semiconductor or metal.

  In a substrate made of an insulator, the insulator is, for example, an inorganic compound such as silicon oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or titanium oxide, or an organic compound such as acrylic resin or polyimide. What is necessary is just to set the thickness of the board | substrate which consists of an insulator suitably according to the objective.

  On the other hand, in a substrate in which an insulating film is formed on a support substrate, the material of the support substrate is preferably a semiconductor or metal. Examples of the semiconductor include group 14 elements such as silicon and germanium, III-V compounds such as gallium arsenide (GaAs) and indium phosphide (InP), and II-VI compounds such as zinc telluride (ZnTe). The metal is, for example, aluminum or nickel. The material of the insulating film is, for example, an inorganic compound such as silicon oxide, silicon nitride, aluminum oxide, or titanium oxide, or an organic compound such as acrylic resin or polyimide. The thicknesses of the support substrate and the insulating film may be set as appropriate according to the purpose. The insulating film may cover only one surface of the support substrate (the surface on which the source electrode and the drain electrode are disposed) or may cover both surfaces.

[About source and drain electrodes]
A source electrode and a drain electrode are arranged on the substrate of the CNT-FET of the present invention. The material of the source electrode and the drain electrode is, for example, a metal such as gold, platinum, chromium, titanium, aluminum, palladium, molybdenum, or a semiconductor such as polysilicon. The source electrode and the drain electrode may have a multilayer structure of two or more kinds of metals. For example, the source electrode and the drain electrode may be formed by stacking a gold layer on a titanium layer. The source electrode and the drain electrode are formed by evaporating these metals on a substrate, for example.

  The distance between the source electrode and the drain electrode is not particularly limited, but is usually about 0.5 to 10 μm. This interval may be further reduced to facilitate the connection between the electrodes by CNTs. The shape of the source electrode and the drain electrode is not particularly limited, and may be set as appropriate according to the purpose.

  As described above, the source electrode and the drain electrode are respectively joined to the end faces located at both ends of one CNT. That is, the source electrode is joined to the first end face of the CNT that becomes the channel, and the drain electrode is joined to the second end face of the CNT. At this time, the source electrode and the drain electrode may be bonded not only to the end face of the CNT but also to the side face in the vicinity of the end face (see FIG. 1). By manufacturing by a method using wet etching, which will be described later, a CNT-FET combining such an end contact structure and a side contact structure can be manufactured.

  As will be described later, the production method of the present invention can control the length of CNTs by cutting CNTs serving as channels. Therefore, the junction area of the source electrode-CNT can be made substantially the same as the junction area of the drain electrode-CNT (see FIG. 1).

[About channels]
In the CNT-FET of the present invention, the channel connecting the source electrode and the drain electrode is composed of CNTs. The CNT constituting the channel may be either single-wall CNT or multi-wall CNT, but single-wall CNT is preferable.

  In the CNT-FET of the present invention, the source electrode and the drain electrode may be connected by one CNT or may be connected by a plurality of CNTs. For example, the source electrode and the drain electrode may be connected by a bundle of CNTs, or a plurality of CNTs may be folded and connected between the source electrode and the drain electrode.

[Passivation film]
In the CNT-FET of the present invention, the CNT serving as a channel is protected by a passivation film. The passivation film is not particularly limited as long as it is an insulating film. For example, silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), oxide It is an insulating film made of titanium (TiO ₂ ) or silicon nitride (Si ₃ N ₄ ). The thickness of the passivation film is not particularly limited and may be appropriately set according to the purpose, but is preferably 10 nm or more.

[About gate electrode]
As described above, the CNT-FET of the present invention has a gate electrode. The material of the gate electrode is, for example, a metal such as gold, platinum, chromium, titanium, brass, and aluminum. The gate electrode is formed by evaporating these metals at an arbitrary position, for example. Alternatively, a separately prepared electrode (for example, a gold thin film) may be arranged at an arbitrary position to serve as a gate electrode. The position where the gate electrode is arranged is not particularly limited as long as the current between the source electrode and the drain electrode (source-drain current) arranged on the substrate can be controlled by the voltage, and may be arranged appropriately according to the purpose. For example, the CNT-FET of the present invention can adopt a top gate type, a side gate type, and a back gate type depending on the position of the gate electrode.

  As described above, the CNT-FET of the present invention has an end contact structure, and the junction area of the source electrode-CNT and the junction area of the drain electrode-CNT are substantially the same. Compared to, it exhibits excellent electrical characteristics. That is, the CNT-FET of the present invention exhibits electrical characteristics that do not depend on the sign of the voltage applied to the source electrode and the drain electrode. In the CNT-FET of the present invention, an ohmic junction is realized when ON (see Example 2). By realizing the ohmic junction, efficient carrier injection becomes possible. As a result, since the source-drain current under the same measurement conditions increases, that is, the conductance increases, for example, when the CNT-FET of the present invention is applied to a sensor, the sensitivity of the sensor can be improved. Conceivable.

  In the CNT-FET of the present invention in which the source electrode and the drain electrode are also bonded to the side surface near the end surface of the CNT, the source electrode and the drain electrode are bonded so as to wrap around the entire side surface including the substrate side (lower) side surface of the CNT. can do. Therefore, since the CNT-FET of the present invention of the above aspect can improve the carrier injection efficiency from the source electrode and the drain electrode to the CNT, the electric conduction characteristic inherent in the CNT can be maximized.

  Moreover, since the CNT-FET of the present invention protects CNTs from adsorption of water molecules and the like by the passivation film, the hysteresis characteristics can be reduced.

2. Manufacturing method of CNT-FET of the present invention The manufacturing method of the CNT-FET of the present invention is as follows. (1) After the CNTs are arranged on the substrate and before the source electrode and the drain electrode are formed on the substrate, they become channels. Forming a passivation film for protecting the CNT; and (2) cutting the CNT to be a channel and bonding a source electrode and a drain electrode to cut surfaces (end faces) positioned at both ends of the CNT, respectively. The steps such as “arrangement of CNT”, “formation of source and drain electrodes”, and “formation of gate electrode” can be performed by appropriately applying conventional techniques.

[Preparation of substrate]
First, a substrate is prepared. The substrate is preferably the aforementioned insulating substrate. What is necessary is just to set the thickness of a board | substrate suitably according to the objective. When the substrate is etched as described later, the thickness of the substrate made of an insulator (in the case of a substrate made of an insulator) or the thickness of the insulating film (in the case of a substrate covered with an insulating film) It is preferable to set so that the leakage current can be suppressed. In general, when the silicon oxide film has a thickness of 10 nm or more, leakage current can be suppressed. Therefore, when the silicon oxide film covering the silicon substrate is etched by 10 nm, the thickness of the silicon oxide film is preferably 20 nm or more (see the example).

[CNT arrangement]
CNTs serving as channels are arranged on the prepared substrate. As a method of arranging CNTs on a substrate, a conventionally known method such as the above-described dispersion method or direct growth method may be appropriately used. For example, by modifying an arbitrary region on the substrate surface with a substance having affinity for CNT and dispersing CNT separately prepared on this substrate, the CNT can be arranged in the modified region on the substrate surface (dispersion) Law). In addition, by placing a catalyst for growing CNTs at an arbitrary position on the surface of the substrate and growing the CNTs from the catalyst placed by the vapor phase growth method, the CNTs can be placed in the peripheral region of the catalyst on the substrate surface. Yes (direct growth method). FIG. 2A is a schematic diagram showing a state in which after the catalyst 160 is disposed on the substrate 110, the CNT 140 is grown from the catalyst 160 (direct growth method), and the CNT 140 is disposed on the substrate 110.

[Passivation]
After the CNTs are arranged on the substrate, the CNTs on the substrate are protected with a passivation film. The method for forming the passivation film is not particularly limited, but from the viewpoint of reducing the hysteresis characteristics of the FET, a method capable of removing water molecules adsorbed on the CNT is preferable. An example of such a method is an ALD (Atomic Layer Deposition) method. In the ALD method, water molecules adsorbed on the CNT are removed in the process of forming a passivation film. In the ALD method, since the passivation films are laminated by monoatomic layers, the film uniformity and step coverage are high, and the passivation film can be formed so as to go not only to the upper side surface but also to the lower side surface of the CNT. In addition, since the reaction temperature of the ALD method is lower than that of other methods, a passivation film can be formed without significantly affecting the CNT itself. Even if the passivation film is formed by EB evaporation method, resistance heating evaporation method, thermal CVD method, sputter film formation method, etc. after removing water molecules by heat treatment in vacuum in advance, the history of FET is the same as in ALD method. Characteristics can be reduced.

The passivation film to be formed is not particularly limited as long as it is an insulating film. For example, using an ALD method, silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), titanium oxide (TiO ₂ ), or silicon nitride (Si ₃₎ A film made of N ₄ ) may be formed. The thickness of the passivation film to be formed is not particularly limited and may be appropriately set according to the purpose, but is preferably 10 nm or more. FIG. 2B is a schematic diagram showing a state in which a passivation film 150 is formed on the substrate 110 on which the CNTs 140 are arranged.

  As described above, the manufacturing method of the present invention is characterized in that the channel CNTs are protected by the passivation film before the process for forming the source electrode and the drain electrode is started. Therefore, the CNT that becomes the channel is physically and chemically protected in the subsequent manufacturing process. This passivation film can also function as a protective film for the final FET device.

[CNT cutting]
The production method of the present invention is also characterized in that the CNTs disposed on the substrate are cut before the source electrode and the drain electrode are formed to expose the cut surfaces of the CNTs. The method for cutting the CNT is not particularly limited, and dry etching such as ECR (Electron Cyclotron Resonance) method may be used. When cutting CNTs using dry etching, for example, after masking regions other than the source electrode and drain electrode formation planned sites on a substrate protected by a passivation film with a resist film, the substrate masked with the resist film is applied to the substrate. On the other hand, dry etching may be performed. As a result, the passivation film and the CNT located at the site where the source electrode and the drain electrode are to be formed are removed, and the source electrode and the drain electrode formed after this are formed on the cut surfaces (end faces) located at both ends of the CNT serving as the channel. It becomes possible to join. FIG. 2C is a schematic diagram showing a state in which a region other than the regions where the source electrode and the drain electrode are to be formed is masked with a resist film 170. FIG. 2D is a schematic diagram showing a state in which the CNT 140 is cut by performing dry etching on the substrate 110 in FIG. As shown in FIG. 2D, in this process, it is preferable to partially etch the substrate 110 from the viewpoint of further improving the bonding state between the source and drain electrodes and the CNT.

  After cutting the CNTs, wet etching is performed on the passivation film around the CNTs and part of the substrate, whereby the junction region between the source electrode and the drain electrode and the CNTs can be controlled. That is, if the source electrode and the drain electrode are formed without performing wet etching, the source electrode and the drain electrode are bonded only to the cut surfaces (end surfaces) located at both ends of the CNT that becomes the channel (end contact structure). ). On the other hand, if the source electrode and the drain electrode are formed after wet etching, the source electrode and the drain electrode are bonded not only to both ends of the CNT to be a channel but also to the side surface of the CNT exposed by the wet etching. (Combination of end contact structure and side contact structure). In this case, since the side surface on the substrate side of the CNT is also exposed by wet etching, it is possible to realize a complete side contact structure that wraps around the entire circumference of the CNT, which has been impossible in the past. A method for performing wet etching may be appropriately selected depending on the type of the passivation film and the substrate, and for example, etching may be performed using hydrofluoric acid. In addition, the processing time may be appropriately set according to the target joining state. FIG. 2E is a schematic diagram showing a state where the passivation film 150 around the CNT 140 and a part of the substrate 110 are wet-etched after the CNT 140 is cut.

[Formation of source and drain electrodes]
After cutting the CNT, a source electrode and a drain electrode are formed. The method for forming the source electrode and the drain electrode at the electrode formation scheduled site is not particularly limited. For example, using a lithography method, a region other than the electrode formation scheduled portion of the substrate on which the CNT is fixed is masked with a resist film, and a metal such as gold, platinum, titanium, chromium, aluminum, palladium, molybdenum, or polysilicon is used. A semiconductor may be deposited and the resist film may be removed (lifted off). This resist film can be used when a region other than the regions where the source electrode and drain electrode are to be formed is masked with a resist film when the CNT is cut. Alternatively, after depositing titanium, gold may be further deposited and stacked to form an electrode having a two-layer structure. FIG. 2F is a schematic diagram illustrating a state where the resist film 170 is removed (lifted off) after the source electrode 120 and the drain electrode 130 are formed by vapor deposition of metal or the like.

  In the case where CNTs serving as channels are grown from a catalyst using a direct growth method (vapor phase growth method) (see FIG. 2A), it is preferable to form a source electrode and a drain electrode after removing the catalyst ( 2D and FIG. 2F). This is because the influence of the catalyst on the electrical characteristics of the CNT-FET can be eliminated. The catalyst removal may be performed simultaneously with the cutting of the CNT as shown in FIG. 2D, or may be performed in a separate step.

[Arrangement of gate electrode]
The method for arranging the gate electrode is not particularly limited. For example, similarly to the source electrode and the drain electrode, a metal or the like may be deposited using a lithography method. In addition, when a separately prepared electrode is used as a gate electrode, the electrode may be disposed at a desired position.

  As described above, in the manufacturing method of the present invention, the passivation film for protecting the CNTs is formed before the source electrode and the drain electrode are formed on the substrate. Thereby, the formation of CNT defects in the manufacturing process and the contamination of the CNTs with the resist can be suppressed. The clean CNT channel realized in this way makes the best use of the one-dimensional electrical conduction of CNTs and exhibits FET characteristics superior to those of conventional CNT-FETs.

  In addition, the manufacturing method of the present invention cuts CNTs serving as channels, and joins a source electrode and a drain electrode to cut surfaces (end surfaces) located at both ends of the CNTs, respectively, so that a CNT-FET having an end contact structure is formed. Can be manufactured. As described above, the CNT-FET having the end contact structure exhibits electrical characteristics superior in symmetry as compared with the conventional CNT-FET. In the CNT-FET of the present invention, an ohmic junction is realized when ON (see Example 2). By realizing the ohmic junction, efficient carrier injection becomes possible. As a result, since the source-drain current under the same measurement conditions increases, that is, the conductance increases, for example, when the CNT-FET of the present invention is applied to a sensor, the sensitivity of the sensor can be improved. Conceivable.

  Moreover, the manufacturing method of this invention can manufacture CNT-FET of the aspect which combined the end contact structure and the side contact structure by performing wet etching. As described above, the CNT-FET in which the end contact structure and the side contact structure are combined can improve the carrier injection efficiency from the source electrode and the drain electrode to the CNT. Can be maximized.

  Examples of the present invention will be described below, but the present invention is not limited to these examples.

[Example 1]
1. Production of CNT-FET of the Present Invention CNTs serving as channels were placed on a substrate using a conventionally known direct growth method. First, a pattern is developed by photolithography on one side of a silicon substrate (size: 20 mm × 20 mm, thickness: 0.55 mm) covered with silicon oxide (SiO ₂ ) having a thickness of 300 nm, and a portion other than a portion where a catalyst is to be formed is developed. The substrate surface was protected with a resist film (OFPR800, Tokyo Ohka Kogyo Co., Ltd.). Silicon (Si) is vapor-deposited with a thickness of 20 nm on the substrate on which the resist film is formed, aluminum (Al) is vapor-deposited with a thickness of 5 nm thereon, and iron (Fe) is vapor-deposited thereon with a thickness of 2 nm. Vapor deposition was performed, and molybdenum (Mo) was deposited thereon with a thickness of 0.3 nm. Next, the catalyst was lifted off, and a catalyst having a size of 3 μm × 10 μm was placed on the substrate. The distance between the catalysts was 10 μm. The substrate on which this catalyst was placed was heated to 900 ° C. in a mixed gas atmosphere of methane and hydrogen (thermal CVD method), and CNTs were grown from the catalyst placed on the substrate (see FIG. 2A).

After the CNTs were grown, a passivation film (thickness 20 nm) made of hafnium oxide (HfO ₂ ) or zirconium oxide (ZrO ₂ ) was formed on the substrate containing CNTs using the ALD method (FIG. 2B). reference). Next, a pattern was developed on the passivation film by photolithography, and the substrate surface other than the portions where the source and drain electrodes were to be formed was protected with the resist film (see FIG. 2C). The substrate on which the resist film was formed was dry-etched using the ECR method to etch the passivation film, the catalyst, and the silicon oxide film (10 nm or more) and cut the CNT (see FIG. 2D). The interval between the cut portions was 4 μm. The dry-etched substrate was treated with dilute hydrofluoric acid solution (2% HF) for 10 seconds to perform cleaning and wet etching (see FIG. 2E).

  After finishing the wet etching, titanium (Ti) is vapor-deposited on the substrate to form a titanium thin film with a thickness of 30 nm, and gold (Au) is vapor-deposited thereon to form a gold thin film with a thickness of 30 nm. A lift-off process was performed to form a source electrode and a drain electrode (see FIG. 2F). Further, after the silicon oxide film on the back surface of the substrate was removed by wet etching, aluminum (Al) was deposited to form an aluminum film having a thickness of 100 nm, and a gate electrode (back gate) was formed.

2. Preparation of CNT-FET of Comparative Example Similar to the above “1. Preparation of CNT-FET of the present invention”, after placing CNT on a silicon substrate covered with silicon oxide, a source electrode, a drain electrode and a gate electrode were Formed. The distance between the electrodes was 4 μm. The formation of the passivation film, dry etching, and wet etching were not performed.

3. Comparison Results of Electrical Characteristics FIG. 3A is a graph showing electrical characteristics of the CNT-FET of Example 1 (having a passivation film is a hafnium oxide film; see FIG. 1) manufactured by the method of the present invention. FIG. 3B is a graph showing the electrical characteristics of the CNT-FET of Comparative Example 1 (see FIG. 10) produced by a conventional method. Each graph shows the change of the back gate voltage (-20 V to +20 V) and the current flowing between the source electrode and the drain electrode (source-drain current) when a voltage of 1 V is applied between the source electrode and the drain electrode. The relationship (I _sd -V _g ) is shown.

  CNT-FETs are roughly classified into three types, p-type FETs, n-type FETs, and bipolar (p-type and n-type: Ambipolar) FETs, according to their characteristics. CNT-FETs using titanium (Ti) as an electrode often exhibit p-type characteristics. However, this is thought to be due to the poor bonding state between the titanium electrode and the CNT. The CNT-FET in which TiC, which is an ideal bonding state by high-temperature annealing at about 800 ° C., is realized as a bipolar FET. It is known to exhibit properties. Thus, the bipolar FET characteristics show that the work function of Ti (4.3 eV) is almost the same as the work function of CNT (4.0 eV to 4.5 eV), and energy for hole and electron injection from the electrode. It is considered that the barrier is small and comparable (see Non-Patent Document 4).

From the graph of FIG. 3B, it can be seen that the CNT-FET of Comparative Example 1 shows the properties of a p-type FET. Although the characteristics of the bipolar FET are also seen, the On current at V _g > 0 is smaller by two orders of magnitude or more than the On current at V _g <0. It can also be seen that the CNT-FET of Comparative Example 1 has a large ΔV _{th and a} large hysteresis characteristic.

On the other hand, from the graph of FIG. 3A, the CNT-FET of Example 1 has the same On current at V _g <0 and On current at V _g > 0, indicating the characteristics of a bipolar FET. Recognize. From this, it can be seen that in the CNT-FET of Example 1, the bonding state between the electrode and the CNT is excellent enough to be comparable to that of TiC even though the annealing treatment is not performed. It can also be seen that the CNT-FET of Example 1 has a very small ΔV _th and a low hysteresis characteristic.

[Example 2]
1. Production of CNT-FET of the Present Invention Using a silicon substrate covered with silicon oxide (SiO ₂ ) having a thickness of 300 nm or 900 nm, the CNT-FET of the present invention (having a passivation film of hafnium oxide) according to the same procedure as in Example 1. A membrane; see FIG. 1) was prepared. The CNT-FET of Example 2 is the same as the CNT-FET of Example 1 except that a silicon substrate having a different silicon oxide film thickness was also used.

2. Preparation of CNT-FET of Comparative Example Similarly to the above-mentioned “1. Preparation of CNT-FET of the present invention”, after CNTs are arranged on a silicon substrate, a source electrode, a drain electrode and a gate electrode are formed, and a passivation film is formed. The CNT-FET of Comparative Example 2 (the passivation film is a hafnium oxide film) was formed. As the substrate, a silicon substrate covered with silicon oxide having a thickness of 300 nm was used. The passivation film was formed after the electrodes were formed, but neither dry etching nor wet etching was performed.

3. FIG. 4 is a graph showing the electrical characteristics of the CNT-FET of Example 2 produced by the method of the present invention. The thickness of the silicon oxide film was 900 nm. This graph shows the relationship between the change in the back gate voltage (-20 V to +20 V) and the current flowing between the source electrode and the drain electrode (source-drain current) when a voltage of 1 V is applied between the source electrode and the drain electrode. (I _sd −V _g ) is shown.

As shown in FIG. 4, in the CNT-FET of Example 2, a path that is followed when the gate voltage is increased from −20 V to +20 V, and a path that is followed when the gate voltage is decreased from +20 V to −20 V Almost completely overlapped, and the ΔV _th was as small as about 0.2V.

  FIG. 5A is a graph showing the hysteresis characteristics of the CNT-FET of Example 2 and the hysteresis characteristics of the CNT-FET of Comparative Example 2. The thickness of each silicon oxide film was 300 nm. In this experiment, 49 CNT-FETs of Example 2 manufactured in one batch and 49 CNT-FETs of Comparative Example 2 manufactured in 1 batch were used.

As shown in FIG. 5A, in the CNT-FET of Comparative Example 2, ΔV _th averaged about 5 to 6 V, and some exceeded 10 V. The reason why the ΔV _th (average of about 5 to 6 V) of the CNT-FET of Comparative Example 2 is smaller than the ΔV _th (12 V or more) of the CNT-FET of Comparative Example 1 is that a protective film is formed. Conceivable. On the other hand, in the CNT-FET of Example 2, ΔV _th was almost 2 V or less. FIG. 5B is a graph showing ΔV _th of the CNT-FET of Example 2 in more detail. As shown in FIG. 5B, the average value of ΔV _th of the CNT-FET of Example 2 was about 1V.

  From these facts, it is understood that the hysteresis characteristics of the CNT-FET of the present invention are excellent not only due to the effect of the protective film but also due to its device structure and manufacturing method.

4). FIG. 6 is a graph showing electrical characteristics of the CNT-FET of Example 2 (indicated by “a” in the figure) and the CNT-FET of Comparative Example 2 (indicated by “b” in the figure). . Each of the silicon oxide films had a thickness of 900 nm. Here, a result of measuring the source-drain current 10 times continuously when a voltage of 1 V is applied between the source electrode and the drain electrode and the back gate voltage is swung back and forth between −20 V to +20 V is shown. In this measurement, a device having ΔV _th of about 1 V was used for the CNT-FET of Example 2, and a device having ΔV _th of about 6 V was used for the CNT-FET of Comparative Example 2. As shown in FIG. 6, in the CNT-FET of Comparative Example 2, the _Vth shift width (width between two arrows in the figure) in 10-times repeated measurement was about 2V. The shift width of _Vth corresponds to a noise component. On the other hand, in the CNT-FET of Example 2, the shift width of _Vth in the 10-times repeated measurement is about 0.2 V (overlapping and hardly visible), which is 1/10 compared to the CNT-FET of Comparative Example 2. It was reduced to.

  FIG. 7A shows the time change of the source-drain current of the CNT-FET of Example 2 (indicated by “a” in the figure) and the CNT-FET of Comparative Example 2 (indicated by “b” in the figure). It is a graph. Here, a result of measuring the source-drain current continuously for 3 hours (10800 seconds) when a voltage of 1 V is applied between the source electrode and the drain electrode and the back gate voltage is set to 0 V is shown. As shown in FIG. 7A, the time until the time change of the source-drain current is alleviated for both the CNT-FET of Example 2 and the CNT-FET of Comparative Example 2 is about 1 hour (3600 seconds). However, it can be seen that the variation width and variation of the CNT-FET of Comparative Example 2 are much larger.

  FIG. 7B is a graph in which the time change of the source-drain current from 5000 seconds to 9000 seconds is enlarged after the time change of the source-drain current is relaxed. In this graph, the value of the source-drain current is normalized in order to make it easy to compare changes with time. As shown in FIG. 7B, in the CNT-FET of Comparative Example 2 (indicated by “b” in the figure), the source-drain current variation or noise component was about 30%. In the CNT-FET (indicated by “a” in the figure), the source-drain current variation or the noise component was about 5%.

  From these facts, it can be seen that the history width and noise component of the CNT-FET of the present invention are greatly improved as compared with the conventional CNT-FET.

5). Comparison Result of Symmetry of Electrical Characteristics FIG. 8A is a graph showing electrical characteristics of the CNT-FET of Example 2. FIG. 8B is a graph showing the electrical characteristics of the CNT-FET of Comparative Example 2. The results of measuring the source-drain current when a voltage of +1 V or -1 V is applied between the source electrode and the drain electrode and the back gate voltage is swept from -20 V to +20 V are shown.

  As shown in FIG. 8B, in the CNT-FET of Comparative Example 2, the curve obtained when a voltage of +1 V is applied between the source electrode and the drain electrode is symmetrical with the curve obtained when a voltage of -1 V is applied. The property was as low as about 50%. On the other hand, as shown in FIG. 8A, in the CNT-FET of Example 2, a curve when a voltage of +1 V is applied between the source electrode and the drain electrode and a curve when a voltage of -1 V is applied The symmetry was as high as about 85%. The excellent symmetry of the electrical characteristics means that the junction characteristics between the CNT-source electrodes and the junction characteristics between the CNT-drain electrodes are substantially equal. It means that the property is excellent.

In addition, the S value (S = (d log ₁₀ Isd / dV _g ) ⁻¹ ) indicating the subthreshold characteristic was 2 to 5 V / dec in the CNT-FET of Comparative Example 2, but it was Example 2. In the CNT-FET, the voltage was improved to 1 V / dec. In the CNT-FET of Example 2 shown in FIG. 4, although the silicon oxide film of the substrate was sufficiently thick as 900 nm, the S value was 0.3 V / dec.

  These improvements are thought to be due to the fact that CNT is not contaminated by chemicals, resists, and the like, and that the junction symmetry between the CNT-electrodes is excellent, thereby realizing low junction resistance. Actually, the junction resistance of the CNT-FET of Comparative Example 2 was about 1 to 10 MΩ, whereas the junction resistance of the CNT-FET of Example 2 was a low value of about 100 to several hundred kΩ.

6). FIG. 9 shows the conductance of the CNT-FET of Example 2 (indicated by “a” in the figure) and the CNT-FET of Comparative Example 2 (indicated by “b” in the figure). It is a graph which shows the measurement result of a temperature characteristic. Here, normalized conductance characteristics of the source-drain current when a voltage of 200 mV is applied between the source electrode and the drain electrode and the back gate voltage is set to 20 V (when ON) are shown. Normalization takes into account ballistic conduction of CNTs.

  The conductance characteristic (indicated by “b” in the figure) in the CNT-FET of the comparative example is reduced by lowering the temperature from about room temperature (280 K) to a lower temperature (20 K). This means that the resistance at the junction between the CNT and the electrode is high, and there is a Schottky barrier. On the other hand, in the CNT-FET of the example (indicated by “a” in the figure), the conductance increases with a decrease in temperature, that is, exhibits a metallic characteristic, so that the junction between the CNT-electrode is an ohmic junction. It is suggested that there is.

  The present invention can produce a CNT-FET that stably exhibits excellent electrical conduction characteristics with good reproducibility, and is useful for the production of integrated devices and sensors that use the CNT-FET.

It is a schematic diagram which shows an example of a structure of CNT-FET of this invention. It is a schematic diagram which shows an example of the manufacturing method of CNT-FET of this invention. It is a graph showing the _I sd -V _g characteristics of the CNT-FET of CNT-FET and Comparative Examples Example 1. It is a graph which shows the I _sd -V _g characteristic of CNT-FET of Example 2. It is a graph which shows the history width of CNT-FET of Example 2 and CNT-FET of a comparative example. It is a graph showing the _I sd -V _g characteristics of the CNT-FET of CNT-FET and Comparative Examples of Example 2. It is a graph which shows the time change of the source-drain current of CNT-FET of Example 2, and CNT-FET of a comparative example. It is a graph showing the _I sd -V _g characteristics of the CNT-FET of CNT-FET and Comparative Examples of Example 2. It is a graph which shows the conductance characteristic of the temperature dependence of CNT-FET of Example 2 and CNT-FET of a comparative example. It is a schematic diagram which shows the structure of the conventional field effect transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,100 Field effect transistor 11,110 Substrate 12,120 Source electrode 13,130 Drain electrode 14,140 Carbon nanotube 15,160 Catalyst 112 Silicon substrate 114 Silicon oxide film 150 Passivation film 170 Resist film

Claims (9)

A method of manufacturing a field effect transistor having a source electrode and a drain electrode formed on a substrate, and a channel made of carbon nanotubes connecting the source electrode and the drain electrode,
Placing carbon nanotubes on a substrate;
Forming a passivation film on the carbon nanotubes before forming the source and drain electrodes;
Cutting the carbon nanotube to expose a first end face and a second end face of the carbon nanotube;
Forming a source electrode joined to the first end face and a drain electrode joined to the second end face;
A method of manufacturing a field effect transistor.   2. The method of manufacturing a field effect transistor according to claim 1, wherein the passivation film includes silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, or silicon nitride.   The field effect transistor manufacturing method according to claim 2, wherein the passivation film is formed by an ALD method.   The field effect transistor manufacturing method according to claim 1, wherein the carbon nanotube is cut by dry etching.   2. The field effect transistor according to claim 1, further comprising a step of performing wet etching after cutting the carbon nanotube to expose a side surface near the first end surface and a side surface near the second end surface of the carbon nanotube. Manufacturing method.   The field effect transistor manufacturing method according to claim 1, wherein the arrangement of the carbon nanotubes is performed by a vapor phase growth method.   The method of manufacturing a field effect transistor according to claim 6, further comprising a step of removing a catalyst used in the vapor deposition method before forming the source electrode and the drain electrode. A field effect transistor having a source electrode and a drain electrode formed on a substrate, and a channel made of carbon nanotubes connecting the source electrode and the drain electrode,
The carbon nanotube is covered with a passivation film,
The source electrode is bonded to the first end face of the carbon nanotube,
The drain electrode is bonded to the second end face of the carbon nanotube;
The junction area between the source electrode and the carbon nanotube is substantially the same as the junction area between the drain electrode and the carbon nanotube.
Field effect transistor. The source electrode is bonded to the first end face of the carbon nanotube and a side face in the vicinity of the first end face,
The drain electrode is bonded to the second end face of the carbon nanotube and a side face in the vicinity of the second end face;
The field effect transistor according to claim 8.

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