JP2008524754A - Memory system having in-stream data encryption / decryption and error correction functions - Google Patents

Abstract

When encrypting error correction of data in a data stream with minimal involvement with all controllers, the processing capacity of the memory system is improved. In order to perform error correction when reading data from the memory cell, the bit error of the data in the data stream passing between the cell and the encryption circuit is corrected before any encryption processing performed by the circuit. Preferably, when latency is reduced by using multiple buffers, error correction occurs in one or more buffers used to buffer data between the encryption circuit and the memory.
[Selection] Figure 2

Description

  The present invention generally relates to a memory system, and more particularly to a memory system having functions of encryption / decryption and error correction of in-stream data.

  The mobile device market is evolving to include content storage functions to increase average revenue by generating more data exchanges. This means that the content must be protected when stored on the mobile device.

  Traditionally, portable storage devices are used commercially. It transmits data from one computer device to another or stores backup data. Modern portable storage devices such as portable hard disk drives and portable flash memory disks and flash memory cards include a microprocessor for storage management control.

  In order to protect content stored on a portable storage device, the stored data is typically encrypted and only authorized users are allowed to decrypt the data.

  Since data stored in portable storage devices can have bit errors, it is desirable to use error correction. Current error correction mechanisms may not be compatible with portable storage devices with encryption capabilities. Accordingly, it would be desirable to provide an improved local storage device that alleviates such difficulties.

  Data stored in memory cells can contain errors for many reasons. Therefore, error correction is usually performed when reading data from the memory cell. Error correction may also detect the location of the error in the data stream. The encryption process performed by the circuit may change the position of the bits in the data stream, so if such processing is done, the bit error in the data stream has not been corrected, After the process, the position information of the bit error is no longer accurate, and after the encryption process is performed, error correction may no longer be possible. Accordingly, it is recognized that one aspect of the present invention preferably corrects bit errors in data in a data stream passing between the cell and the encryption circuit prior to any encryption processing performed by the circuit. It is based on. Preferably, at least one buffer is used to store the data in the data stream passing between the cell and the circuit, and all of the data stored in the buffer and starting from the cell is encrypted before the data is encrypted by the circuit. The error is to be fixed.

  One example of a memory system in which various aspects of the present invention may be implemented is shown in the block diagram of FIG. As shown in FIG. 1, the memory system 10 includes a central processing unit (CPU) 12, a buffer management unit (BMU) 14, a host interface module (HIM) 16 and a flash interface module (FIM) 18, a flash memory 20, and A peripheral access module (PAM) 22 is included. Memory system 10 communicates with host device 24 through host interface bus 26 and port 26a. The flash memory 20, which may be a NAND type, provides a data storage device for the host device 24. Also, software code (code) for the CPU 12 may be stored in the flash memory 20. The FIM 18 is connected to the flash memory 20 through the flash interface bus 28 and the port 28a. The HIM 16 is suitable for connection to a host system such as, for example, a digital camera, a personal computer, a PDA (Personal Digital Assistant), a digital media player, an MP-3 player, and a mobile phone or other digital device. Peripheral access module 22 selects an appropriate controller module, such as FIM, HIM, and BMU, for communication with CPU 12. In one embodiment, all components of the system 10 within the frame enclosed by the dotted line may be enclosed in a single unit, such as a memory card or stick 10 ', and preferably enclosed in a card or stick.

  The buffer management unit 14 includes a host direct memory access (HDMA) 32, a flash direct memory access (FDMA) controller 34, an arbiter 36, a buffer random access memory (BRAM) 38, and an encryption engine (Crypto-Engine) 40. Since arbiter 36 is a shared bus arbiter, only one master or initiator (which can be HDMA 32 or FDMA 34 or CPU 12) can be active at any time, and the slave or target is BRAM 38. The arbiter is responsible for transmitting the appropriate initiator request to the BRAM 38. The HDMA 32 and FDMA 34 play a role in data carried between the HIM 16 and FIM 18 and the BRAM 38 or between the CPU random access memory (CPU RAM) 12a. The operation of HDMA 32 and FDMA 34 is conventional and need not be detailed here. The BRAM 38 is used to buffer data passed between the host device 24, the flash memory 20, and the CPU RAM 12a. The HDMA 32 and the FDMA 34 transfer data between the HIM 16 / FIM 18 and the BRAM 38 or the CPU RAM 12a, and play a role of instructing the completion of sector transfer. As will be described below, the FIM 18 further has a capability of detecting an error in data read from the flash memory 20 and notifying the CPU 12 when an error is found.

  When data from the flash memory 20 is read by the host device 24, the encrypted data in the memory 20 is first retrieved through the bus 28, FIM 18, FDMA 34, and the crypto engine 40 that decrypts the encrypted data. The encrypted data is decrypted and stored in the BRAM 38. The decrypted data is then sent from the BRAM 38 to the host device 24 through the HDMA 32, the HIM 16, and the bus 26. The data stored in the memory 20 is fetched from the BRAM 38 so that the data sent to the host device 24 is encrypted again with a different key and / or algorithm compared to the decrypted key and / or algorithm. The data can be encrypted again by the crypto engine 40 before being sent to the HDMA 32. Preferably, and in an alternative embodiment, the data from memory 20 is stored in BRAM 38 rather than storing the data decrypted in the above process in BRAM 38 and the data can be attacked by unauthorized access. Before being transmitted, it may be decrypted by the encryption engine 40 and re-encrypted. The encrypted data in the BRAM 38 is then transmitted to the host device 24 as described above. This is an explanation of the data stream being read.

  When data is written to the memory 20 by the host device 24, the direction of the data stream is reversed. For example, if unencrypted data is sent by the host device via the bus 26, HIM 16 and HDMA 32 to the encryption engine 40, these data may be encrypted by the engine 40 before being stored in the BRAM 38. . Instead, unencrypted data may be stored in the BRAM 38. This data is then encrypted on the way to memory 20 before being sent to FDMA 34. When the written data passes through a multi-stage encryption process, the engine 40 preferably completes the process before storing the processed data in the BRAM 38.

  Although flash memory is included in the memory system 10 of FIG. 1, this system is instead replaced by other types, such as magnetic disks, optical discs CD, and all other types of rewritable non-volatile memory systems. The above-mentioned various advantages can be applied to this other embodiment as well. In this alternative embodiment, the memory is also preferably sealed in the same housing (such as a memory card or memory stick) along with the remaining components of the memory system.

<Error correction>
Data stored in non-volatile (eg, flash) memory can be corrupted or contain errors. Thus, the FIM 18 can have an error correction (ECC) circuit 102 that detects which bits of the data stream from the memory 20 have errors, including the location of errors in the bitstream. This is shown in FIG. 2, which is a block diagram of a memory system 100 for illustrating another aspect of the present invention. If an error is detected in the bitstream, the FIM 18 sends an interrupt signal to the CPU 12 and the circuit 102 sends information about the position of the bit in error to the CPU 12. In a conventional memory system that does not have an encryption function, the error is corrected in the BRAM 38 by the CPU. However, if the data from the data stream was previously encrypted prior to its correction, the encryption process may change the position and / or value of the data bits in the processed data stream, so The position and / or value of the bit error after the encryption process may be different from that sent by the circuit 102 to the CPU 12. This may make it impossible to correct the error when the encrypted data arrives at the BRAM 38. One aspect of the present invention originates from the recognition of correcting detected errors prior to data encryption processing to prevent this problem.

  An error buffer unit (EBU) 104 passes between BMU 14 and FIM 18 so that when CPU 12 receives an interrupt from FIM 18 indicating that there is an error in the data stream, CPU corrects the error with EBU 104 instead of BRAM 38. Used to store data from the data stream. To correct the digital data, the bit of the error is simply “flipped” (ie, “1” to “0” and “0” to “0” at the location of the error detected by the circuit 102). 1 ”).

  Two or more buffers may be used in the EBU 104 as shown in FIG. 3 to reduce the number of interrupts in the data stream when an error is detected. As shown in FIG. 3, two buffers 104a and 104b are used, one of the two buffers receives data from the memory 20 through the FIM 18, and the other sends the data to the encryption engine 40 through the FDMA 34 in the BMU 14. . In FIG. 3, two switches 106a and 106b are used. As shown in FIG. 3, when the two switches are in the solid line position, the buffer 104 a supplies data to the BMU 14, but the buffer 104 b receives data from the FIM 18. As shown in FIG. 3, when the two switches are in the dotted line position, the buffer 104 b is supplying data to the BMU 14, but the buffer 104 a is receiving data from the FIM 18. Before sending the data stored in the buffer to the BMU, each buffer can first be filled with data. When data is sent from or received by buffers 104a and 104b, the CPU corrects errors in buffers 104a and 104b. In this way, the only latency is the time required to fill one of the two buffers at the beginning of the data stream. Thereafter, if the time taken by the CPU for error correction is short compared to the time required to fill each buffer, there is no interruption in the data stream even when an error is detected by the circuit 102.

  If the data correction takes longer than filling the buffer, the data stream is interrupted only when an error is detected, but when no error is detected, the data stream flows without interruption. A buffer empty signal (not shown) connecting between EBU 104 and FDMA 34 informs the latter FDMA 34 that the data stream has been interrupted and no more data is available. Thereafter, both the FDMA 34 and the encryption engine 40 are suspended and wait for the data stream to resume.

  When the host device 24 writes data to the memory 20, it is considered that there is no need for error correction, so it is desirable to bypass the EBU. This can be accomplished with switch 108. When switch 108 is closed, data from HIM 16 (not fully shown in FIG. 2) simply bypasses the two buffers 104a and 104b. The switch 108 may also be closed in bypass mode if no encryption process is required when data is read from or written to the memory 20. According to this mode, the HDMA and FDMA are connected directly to the arbiter 36, as if the encryption engine 40 was removed from the system 10, and the data stream bypasses both the EBU 104 and the encryption engine 40. This can also be achieved using a switch. Thus, in bypass mode, under the control of the CPU 12, the logic circuitry (not shown) of the system 100 causes the data stream to bypass the block 40 and close the switch 108.

  The error correction process is shown in the flowchart of FIG. The CPU 12 starts a read operation after receiving a read command from the host device 24 (ellipse 150). Thereafter, the encryption engine 40 is set using appropriate security setting information to set parameters such as allocation of memory space in the BMU 14 for read operations and, for example, the BRAM 38 for operations (blocks 152, 154). The CPU 12 further sets the FIM 18, such as by identifying the location in the memory 20 from which data will be read (block 156). Thereafter, the HDMA and FDMA engines 32 and 34 are started. See block 158. If the CPU receives an interrupt, it checks whether it is a FIM interrupt (diamond 160). When an FIM interrupt is received, the CPU checks to see if the interrupt is an interrupt indicating that there is one or more errors in the data stream (162) (162). If an error is indicated, the CPU proceeds to correct errors in buffers 104a and / or 104b (block 164) and returns to setting FIM 18 to change the location in memory 20 where the data will be read next. (Block 156). If the FIM interrupt does not indicate an error in the data stream, it means that the FIM has completed its operation and the CPU also returns to block 156 to reconfigure and restart the FIM. If the interrupt detected by the CPU is not an FIM interrupt, the CPU checks to see if it is the end of the data interrupt (diamond 166). If so, the read operation ends (ellipse 168). Otherwise, this interrupt is unrelated to the data encryption process (ie, clock interrupt) and the CPU checks it (not shown) and returns to diamond 160 to check for interrupts. .

  In the case of a write operation, only a slight modification of FIG. 4 is necessary. Since the data written in the memory 20 has no ECC error processing, the CPU 12 can omit the processes in the diamond 162 and the block 164 by the write operation. If a FIM interrupt is received by the CPU 12 during a write operation, this means that the FIM has completed the operation and the CPU also returns to block 156 to reset the FIM. Other than this difference, the write operation is substantially similar to the read operation.

  While the invention has been described above with reference to various embodiments, it will be understood that changes and modifications can be made without departing from the scope of the invention as defined by the appended claims and their equivalents. All references cited here are for reference only.

FIG. 1 is a block diagram of a memory system that communicates with a host device for explaining the present invention. FIG. 2 is a block diagram of one of several blocks of the memory system in FIG. FIG. 3 is a circuit diagram illustrating in more detail a preferred setting of the error correction buffer unit of FIG. FIG. 4 is a flowchart illustrating the operation of the system of FIG. 2 to illustrate a preferred embodiment of one aspect of the present invention. For convenience of description, the same components are given the same numbers in this application.

Claims (10)

A method for correcting data in a memory system for storing encrypted data, comprising a non-volatile memory cell and an encryption circuit, the method comprising data in a data stream from or to the cell Using the circuit to perform an encryption process on
Providing at least one buffer for storing data in the data stream passing between the cell and the circuit;
Correcting all errors in the data stored in the buffer and starting from the cell before performing an encryption process on the data in the circuit.   In response to a signal indicating the presence of one or more errors in the data stream in the data stream from the cell to the circuit, the correction is performed before the data reaches the circuit. The method of claim 1, wherein the method is adapted to correct an error.   The system includes two buffers for storing data in the data stream passing between the cell and the circuit, the method alternately storing data and transmitting data from the cell to the circuit; 3. The method of claim 2, further comprising using the two buffers.   4. The method of claim 3, wherein the use stores data in a first buffer of the two buffers when sending data stored in a second buffer of the two buffers to the circuit. A memory system for storing encrypted data,
A non-volatile memory cell;
A circuit that performs an encryption process on data in the data stream from or to the cell;
At least one buffer for storing data in the data stream passing between the cell and the circuit;
The cell, at least one buffer, and the circuit are controlled to correct all errors in the data stored in the buffer, and the circuit performs the encryption process on such data. A memory system comprising a controller starting from said cell before execution.   Before the data reaches the circuit in response to a signal indicating that there is one or more errors in the data in the data stream destined for the circuit from the cell. 6. The system of claim 5, wherein the one or more errors are corrected.   7. The system of claim 6, further comprising an error correction circuit that detects an error in the data stream and causes the signal to be sent to the controller when it is detected that there is at least one error in the data stream. .   The system includes the two buffers that store data in the data stream passing between the cell and the circuit, the two buffers alternately storing data and sending data from the cell to the circuit 6. The system according to claim 5, wherein the system is used as follows.   9. The system of claim 8, wherein when the data stored in the second buffer of the two buffers is sent to the circuit, the data is stored in the first buffer of the two buffers.   The system of claim 5, wherein the controller causes data in the data stream to bypass the buffer and the circuit in an alternate bypass path in a bypass mode.

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