JP2008508848A - Boost-type switch driver with charge transfer - Google Patents

Abstract

The switch driver circuit utilizes charge transfer in and / or between the boost circuit and / or snubber circuit for the boost type switch driver. The boost circuit includes a divider for limiting the boosted signal for driving the switch. The snubber circuit can transfer charge to the boost circuit.
[Selection] Figure 2

Description

  This application includes US Provisional Application No. 60/598666, filed August 2, 2004, called Gate Drive and Subscriber for Switching Power Supply, and Boosted Switch Drive Treat, filed October 26, 2004. And claims the priority of US patent application Ser. No. 10 / 976,196, which is incorporated by reference.

  FIG. 1 shows a prior art gate drive circuit for a switching power supply. The circuit of FIG. 1 includes two transistors Q1 and Q2 connected to the switch node SW and configured to alternately switch the inductor between two different power supply terminals PS and GND. This type of switch configuration is commonly used in switching power supplies such as synchronous buck converters. Transistors Q1 and Q2 are controlled by input signals IN1 and IN2 that drive the gates of Q1 and Q2 via drive circuits 10 and 12, respectively.

  Since the source of Q2 refers to the power supply ground terminal GND, the drive circuit 12 can receive power from the positive power supply terminal PS. However, if the gate of Q1 has to be driven with a voltage much higher than PS, the source of Q1 refers to a switch terminal SW that is approximately the same voltage as PS. Accordingly, the circuit of FIG. 1 includes a boost circuit 14 for generating a boosted power supply BST that is used to operate the drive circuit 10 for Q1. Boost circuit 14 includes a diode DB and a capacitor CB connected in a charge pump configuration.

  The circuit of FIG. 1 also includes an RC snubber circuit 16 that suppresses voltage spikes in the switch SW caused by the transistor's parasitic inductance, a PC board on which the transistor can be mounted, and a main inductor for the switching power supply.

  Referring to the circuit of FIG. 1, as an example of operation, the power supply PS is assumed to be a positive voltage Vps, and the power supply terminal GND is assumed to be a ground potential. When the low side transistor Q2 is turned on, ie, when the switch node SW is grounded through Q2 (except for some resistive drop due to Q2), the boost circuit capacitor CB is up to VPS-VD. Charged. When the input IN1 is activated, this capacitor voltage is driven via the drive circuit 10 to the gate of the high voltage side transistor Q1. The capacitor voltage applied to the voltage at the switch node SW when Q1 is on generates the boost voltage VBST at the boost terminal BST. This adds approximately maximum supply voltage VCC (minus the diode drop) between Q1's gate-source inputs and CB is sufficient to charge Q1's gate capacitance to approximately maximum supply voltage. It is necessary to accumulate charges. This can cause high switching losses due to the large amount of charge involved.

  One possible technique for reducing switching losses is to supply a lower supply voltage to the boost circuit 14, i.e. not connect it directly to the PS. The reduced supply voltage is high enough to generate a boost voltage VBST that fully turns on the high-side transistor Q1 to minimize the conduction loss due to Q1, but low enough to minimize switching loss Will be necessary. In general, there is an optimally reduced supply voltage, which will result in an optimal boost voltage, but the reduced supply voltage must usually be generated by special circuitry, increasing the cost and complexity of the system .

  Another potential problem with the circuit of FIG. 1 is the power loss of the snubber circuit 16. In many situations, the snubber circuit is essential to prevent voltage spikes from damaging transistors Q1 and Q2. However, a significant amount of charge is diverted through the snubber to ground, thus consuming power and reducing efficiency.

  Some of the inventive principles of this patent disclosure relate to transferring charge within and / or between boost and / or snubber circuits. FIG. 2 illustrates an embodiment of a circuit for transferring charge in accordance with some of the inventive principles of this patent disclosure. The circuit of FIG. 2 includes a first switch 18 that is arranged between the power supply terminal PS and the switch node SW and is controlled by the drive signal of the drive node DRV1. The second switch 20 is disposed between the SW and the second power supply terminal GND, and is controlled by the second drive signal of the second drive node DRV2. Drive signals DRV1 and DRV2 are generated by drive circuits 22 and 24 in response to switching input signals IN1 and IN2, respectively.

  Boost circuit 26 generates a signal VBST that is boosted to boost node BST to operate drive circuit 22. The boost circuit includes a divider circuit 28, which in this embodiment is conceptually shown as a capacitive divider that moves charge between components to limit the boosted signal.

  FIG. 3 illustrates another embodiment of a circuit for transferring charge in accordance with some of the inventive principles of this patent disclosure. The circuit of FIG. 3 includes switches 18 and 20 and drive circuits 22 and 24 configured similarly to the circuit of FIG. However, the circuit of FIG. 3 includes a snubber circuit 30 configured to transfer charge to a boost circuit 32 that generates a boosted signal VBST for providing power to drive switch 18.

  FIG. 4 shows a circuit embodiment showing some example implementation details according to some of the inventive principles of this patent disclosure. Switches 18 and 20 are implemented as metal oxide semiconductor field effect transistors (MOSFETs), but other types of suitable switches can be used. The drive circuits 22 and 24 can be any suitable gate driver. Bootstrap diode D1 is connected between power supply node PS and boost node BST. Capacitor C1 is connected between switch node SW and boost node BST, preferably through resistor R1. The second capacitor C2 is connected between the BST and the power supply GND. Capacitors C1 and C2 form a capacitive voltage divider that reduces boost voltage VBST at boost node BST. The configuration of the components shown in FIG. 4 also includes snubbing at the switch node SW, and charge can be transferred from the switch node SW to the boost circuit.

  Depending on the implementation details, the circuit of FIG. 4 can reduce switching loss because the voltage level of the boost signal VBST is reduced due to the voltage division effect by C1 and C2. For feedback from switch node SW to boost node BST via R1 / C1 and C2, optimized slew rate control can be performed when switch 18 is turned on. That is, if the voltage of the gate of the transistor 18 is rapidly increased to turn on the transistor rapidly, the voltage spike at the switch node SW can be reduced by the final slew rate control. SW node snubbing due to the interaction of the C1 / C2 combination and R1 in series can achieve a better snubbing response than prior art methods because the snubbing is in the driver feedback. The configuration of FIG. 4 can reduce stress on some or all of the components, such as voltage stress on the switch and bootstrap diode. As a result, the overall efficiency that can be obtained from the circuit of FIG. 4 allows the use of fewer and / or lower cost switches and other components to be used. However, another potential benefit of the circuit of FIG. 4 is that resistor R1 can reduce stress by limiting the current surge through the bootstrap diode. Since boosting and snubbing functions are integrated into the same component, the potential benefits can be realized without additional components and associated costs. A further potential benefit is that efficiency can be improved since the charge consumed by shunting to ground is conserved by moving it to the boost node.

Although not necessary to understand the inventive principles of this patent disclosure, some useful formulas for the component values of FIG. 4 are given as follows.
The capacitor value is

および

から決定することができ、ここで、ＱＧＡＴＥは所望のゲート電圧ＶＧＡＴＥに対してスイッチ１８のゲートで必要とされる全電荷であり、ＶＣＣは電力供給電圧であり、ＶＤはＤ１の両端の電圧降下である。ブートストラップ・ダイオードのピーク・サージ電流ＩＰ（ＰＥＡＫ）定格は、

から決定することができる。

and

Where QGATE is the total charge required at the gate of switch 18 for the desired gate voltage VGATE, VCC is the power supply voltage, and VD is the voltage drop across D1. It is. The peak surge current IP (PEAK) rating of the bootstrap diode is

Can be determined from

  Although the inventive principles of this patent disclosure have been described above with reference to certain specific exemplary embodiments, these embodiments can be modified in arrangement and detail without departing from the inventive concept. For example, although the switch has been shown in some embodiments as MOSFETS, other suitable switches can be used in accordance with the inventive principles of this patent disclosure. As a further example, the power supply signal and the boosted signal are not limited to any particular polarity, voltage, or switching power supply topology. As yet another example, resistor R1 can be rearranged or omitted from the circuit of FIG. 4 while still retaining useful results. Moreover, as yet another example, the placement of C2 can be between BST and other nodes other than GND. Accordingly, such modifications and changes are considered to be within the scope of the appended claims.

It is a figure which shows the gate drive circuit of the prior art for switching power supplies. FIG. 4 illustrates an embodiment of a circuit according to some of the inventive principles of this patent disclosure. FIG. 4 illustrates another embodiment of a circuit according to some of the inventive principles of this patent disclosure. FIG. 7 illustrates an embodiment of a circuit showing some additional implementation details according to some of the inventive principles of this patent disclosure.

Claims (20)

A switch node;
A driving node;
A power node;
A boost circuit coupled to said switch node and said power supply node to generate a boosted signal for driving a switch coupled to said switch node and said drive node, wherein said boosted signal And a boost circuit including a divider for limiting the output.   The circuit of claim 1, wherein the divider comprises a capacitor coupled between a boost node and a power supply node.   The circuit of claim 1, wherein the divider comprises a capacitor coupled between a boost node and the switch node.   The divider comprises a first capacitor coupled between a boost node and a power supply node, and a second capacitor coupled between the boost node and the switch node. The circuit according to 1.   The circuit of claim 4, wherein the divider further comprises a resistor coupled in series with one of the capacitors.   The circuit of claim 1, wherein the divider is integrated with a snubber circuit. A snubber circuit coupled to the switch node;
A circuit comprising: a boost circuit coupled to the switch node to generate a boosted signal for driving the switch node and a switch coupled to the drive node;
A circuit configured to cause the snubber circuit to transfer charge from the switch node to the boost circuit.   The circuit of claim 7, wherein the snubber circuit comprises a capacitor and a resistor coupled between the switch node and the boost circuit.   The circuit of claim 8, wherein the capacitor and the resistor are coupled to a boost node of the boost circuit.   The circuit of claim 9, wherein the capacitor and the resistor are coupled in series.   The circuit of claim 9, wherein the boost circuit includes a second capacitor coupled between the boost node and a power supply terminal. Generating a boosted signal for driving a switch coupled to the switch node and the drive node;
Moving the charge to reduce the voltage of the boosted signal.   The method of claim 12, wherein moving the charge comprises moving the charge between two capacitors.   The method of claim 12, wherein moving the charge comprises dividing the voltage.   The method of claim 12, further comprising transferring charge from the switch node to the drive node.   The method of claim 15, wherein moving charge from the switch node to the drive node comprises moving charge through a capacitor.   The method of claim 16, wherein moving charge from the switch node to the drive node further comprises moving charge through a resistor. A switch node;
A driving node;
A power node;
Means for generating a boosted signal for driving a switch coupled to the switch node and the drive node;
Means for limiting the boosted signal.   The circuit of claim 18 further comprising means for snubbing the switch node.   20. The circuit of claim 19, wherein the means for snubbing the switch node is integrated with the means for limiting the boosted signal.

Images