JP2008503028A - Erasing algorithm for multilevel bit flash memory - Google Patents

Abstract

  A method (400) is provided for erasing a sector of a multi-level flash memory cell (MLB) having more than two data states (100, 200) into a single data state (1000). The present invention uses a bidirectional sector erase algorithm (400) to erase sectors (410, 440), verify (416), soft programming (420, 450), programming (430) in two or more erase phases. ) Is repeated to realize a high-density data state distribution (300, 1000). In one example, algorithm (400) essentially erases all MLB cells in the sector using a bi-directional erase pulse, soft programming pulse, and programming pulse in the first phase, and intermediate state (410, 600) and corresponding threshold voltage values. Next, in the second phase (440, 450), the algorithm further includes additional bi-directional erase pulses (440) until a final data state corresponding to the desired final threshold voltage value (1000) of the cell is obtained. And soft programming pulse (450) is used to erase all ML13 cells in the sector. Optionally, to prepare for a subsequent programming operation, the algorithm (400) may include one or more in similar operations that continuously bring the memory cells of the sector to a densified common erase state (1000). Additional phases may be included. In one aspect of the method, the actual thresholds and / or data states selected for these phases may be predetermined by the user and entered into the memory device.

Description

  The present invention relates generally to memory devices and the like, and more particularly to a method for erasing a sector of cells having multi-level data states in a flash memory device.

  There are many different types and forms of memory for storing data for computers and similar systems. For example, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), programmable read only memory (PROM), electrically programmable read only memory (EPROM) ), Electrically erasable programmable read only memory (EEPROM) and flash memory are all currently available for data storage.

  Each type of memory has its own advantages and disadvantages. For example, in DRAMs and SRAMs, individual bits of data can be erased one at a time, but such memories lose their data when powered off. Instead, the EEPROM can be easily deleted without adding an external device, but the data storage density is reduced, the speed is reduced, and the cost is increased. In contrast, EPROM is cheaper and denser, but lacks ease of erasure.

  Flash memory has become a popular memory type because it combines the advantages of high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory is non-volatile because it can be rewritten and can store its contents without a power source. This memory is used in many portable electronic products such as mobile phones, portable computers and voice recorders, as well as in many large electronic systems such as automobiles, aircraft and industrial control systems.

  Flash memory is typically composed of a large number of memory cells, where generally a single bit of data is stored in and read from each memory cell. The cell is typically programmed by hot electron injection and erased by Fowler-Nordheim tunneling or other mechanisms. As is the case in many aspects of the semiconductor industry, there is a continuing desire and commitment to obtain higher device recording densities and to increase the number of memory cells on a semiconductor wafer. Similarly, there is a need for improved device speed and performance so that more data can be stored in smaller memory devices.

  Individual flash memory cells are organized into individually addressable units or groups that are accessed through an address decoding circuit to perform read, program, or erase operations. Individual memory cells are typically constructed from semiconductor structures adapted to store bits of data, include appropriate decoding and group selection circuitry, and circuitry for applying a voltage to the operating cell including.

The erase operation, programming operation and read operation are usually performed by applying an appropriate voltage to a specific terminal of the memory cell. In an erase or write operation, an appropriate voltage is applied to remove charge from the memory cell or to be stored in the memory cell. In a read operation, an appropriate voltage is applied to cause a current to flow through the cell, and the amount of the current represents the value of the data stored in the cell. The memory device includes appropriate circuitry that senses the resulting cell current to determine the data stored in the memory device, the data being provided to the data bus terminal of the device, It can be accessed from other devices in your system.

  The programming circuit signals the word line that operates as the control gate and controls the bit of the cell by changing the bit line connection so that the bit is preserved by the source and drain connections. When a cell is programmed using a suitable mechanism, such as hot electron injection, the threshold voltage of the cell usually increases. Erasing is performed as a batch operation, allowing an array or sector of cells to be erased simultaneously, typically reducing the threshold voltage in the cell.

  In batch erase of flash memory, cells in an array or sector are typically erased simultaneously and can be performed by applying a short erase pulse one or more times. After each erase pulse, erase verify or read is performed so that each cell in the array is currently “erased” (blank), or not yet “erased”, or “insufficiently erased”. Can be determined (eg, whether the cell has a threshold voltage above a predetermined limit). If an undererased cell is detected, an erase pulse can be added to the entire array until all cells are fully erased. However, in such an erase procedure, some cells may be “overerased” before other cells are sufficiently erased. For example, a memory cell having a threshold voltage that is erased below a predetermined limit may generally be considered over-erased. For several reasons, it is undesirable for a memory cell to remain in an over-erased state.

  Regardless of the flash architecture used, accurately erasing and programming a multi-level flash cell is a complex that maintains a narrow Vt distribution to accurately read and determine the data state from the corresponding Vt level. Depending on the situation, it may be particularly careful. Furthermore, even if such narrow distributions in various multi-levels are realized, if the sector of the memory cell cannot be erased quickly, efficiently and reliably and brought within acceptable limits, it will compete. There may be little power gain.

  In view of the above, there is a need for an improved method for erasing a sector or array of multilevel flash memory cells.

SUMMARY OF THE INVENTION The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. This is not intended to identify basic or critical components of the invention, nor is it intended to indicate the scope of the invention. Rather, the primary purpose of this summary is merely to present one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

The present invention applies to a multi-level bit flash memory cell (MLB) by applying a bidirectional sector erase algorithm that performs sector erase, verify, soft programming and programming in two or more erase phases (or layers). The sector or array is erased to reach a single bit state (data state) to obtain a higher density Vt distribution. This algorithm provides an improved Vt distribution with a sigma over that obtained with some conventional single-phase methods. In one example, in the first phase, a bi-directional erase pulse, soft programming pulse and programming pulse are used to erase all MLB cells in the sector to an intermediate state corresponding to the intermediate threshold voltage value. In the first phase, the memory cells reach the same logic state and approach the same threshold voltage. Next, in the second phase, this algorithm is used to further densify the distribution of threshold voltage levels near the final data state. In the second phase of the invention, the algorithm uses additional bi-directional erase and soft programming pulses to obtain all of the sectors until the desired final threshold voltage value of the cell corresponding to the final data state is obtained. This MLB cell is erased again.

  The multi-level bit MLB flash memory cell of the present invention may contain a single physical bit, which can be programmed to more than two levels corresponding to more than two data states. Alternatively, the MLB cell may include a double bit cell or a mirror bit cell having two physically separate bits, each of which can be programmed to multiple levels, eg, four. Well, in that case, 16 states are available. This method can be suitably implemented in various flash memory architectures including single bit and double bit EEPROMs, and other single bit or multi-bit memory architectures that are electrically erasable, such cells or Such variations are considered to be within the scope of the invention.

  Yet another aspect of the algorithm of the present invention includes additional phases of similar erase and soft programming operations that can be used to further increase the threshold voltage distribution of the memory cells. In this additional phase, a second intermediate logic state is selected between the intermediate state and the final state. After the cells are erased, programmed and soft programmed to the intermediate state, these cells are erased and soft programmed in a similar manner to the second intermediate state, and finally to the final data state. . Any number of such intermediate phases can be applied to this method, including the total number of data states used by the sector or array of MLB memory cells.

  In this manner, the memory cell is erased until reaching a common erase state in which the Vt distribution is narrow, and is prepared for the subsequent programming and reading operations. In one aspect of this method, the user may pre-determine and enter the actual threshold voltage and data state selected for these phases into the memory device.

  In one method and implementation of the present invention, a memory cell in a sector has, for example, four data states L1, L2, L3 and L4 corresponding to four threshold voltage values, respectively. In this method, in the first phase operation, the memory cell is erased until reaching an intermediate threshold voltage value corresponding to the L2 data state, and then in the second phase operation, the memory cell is corresponded to the L1 data state. Erase until the final threshold voltage value is reached.

  In accordance with another aspect of the sector erase algorithm of the present invention, the memory cell is initially programmed to various states. Another aspect of the invention provides a method for erasing a plurality of sectors of an array including the entire array. The present invention is a method for erasing a sector of an array of MLB memory cells that produces a well-controlled low sigma Vt distribution using minimal erase time while maintaining device durability and reliability. Is to provide.

To the accomplishment of the foregoing and related ends, the following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are just a few of the various ways in which one or more aspects of the present invention may be used.
Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION One or more aspects of the present invention will be described with reference to the drawings. Throughout, the same reference numbers generally refer to the same components, and the various structures are not necessarily in proportion to the actual size. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the present invention. However, it will be apparent to one skilled in the art that one or more aspects of the present invention may be practiced with lower levels of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more aspects of the present invention.

  Increasing the density of memory devices leads to an increase in memory capacity. In memory device manufacturing costs and marketability, density and capacity are important considerations and are directly related to the amount of space used to store bits of information on a semiconductor chip. For example, if the density is increased by reducing the shape size and a larger number of memory cell transistors are accommodated in a chip of a predetermined size, a higher density can be realized. Another approach for increasing density and reducing manufacturing costs uses multi-level cell technology.

  Multi-level cells increase cell density by increasing the number of possible logic or data states associated with a cell, so that a single memory cell can store information corresponding to multiple data bits. It can be saved. One way to do this was to use multiple (three or more cell level and state related threshold) threshold voltage (Vt) levels corresponding to multiple data states per cell. This contrasts with the two states and levels used in conventional flash memory cells. Thus, in one example, a single mirror bit cell can store two physical bits of data with four Vt levels each corresponding to four logical states. However, in an attempt to maintain a well-controlled or tight distribution of Vt levels, especially as more data bit amounts are considered, cells with multiple levels are subject to a number of new problems. Presenting points.

  As a result of these trends, there is an increasing demand for accurate erasure of such multi-level cells and determination of their levels, especially as greater bit capacity is expected for a single cell. Yes. Accordingly, multi-level memory cells need to be quickly and efficiently erased to save erase operation time and power consumption. Furthermore, it is necessary to erase cells to a well-controlled narrow erase distribution (tight bit density) to ensure that the programming Vt distribution is narrow even in subsequent programming operations. As device geometries continue to shrink and the density of memory cells increases, the requirements and challenges of such devices are likely to increase.

  Memory device manufacturers often guarantee specific numbers for speed, durability, reliability, and power consumed during various modes of operation. These device specifications or operating parameters are beneficial for the user to ensure device performance as intended. Accordingly, it is an object of the present invention to provide a method for erasing a suitable MLB flash memory cell sector or array, which achieves the above requirements while at the same time speed, durability, reliability and application. Provide a specific number for the power consumed during possible modes of operation.

A sector erase algorithm may be used to erase a specified sector or sectors of the array of multi-level flash memory cells MLB to a single data state. The erasure algorithm of the present invention may be applied in, for example, two or more erasure phases (or layers). This algorithm can realize a well-controlled high-density Vt distribution as compared with some conventional single-phase methods. The method can be suitably implemented in a variety of flash memory architectures, including single and double bit EEPROMs, and other single or multi-bit memory architectures that are electrically erasable, such cells or variations thereof. Are considered to be within the scope of this invention.

  In the first phase, the algorithm of the present invention erases all MLB cells in a sector or cell group to an intermediate state corresponding to an intermediate threshold voltage value, then a bidirectional erase pulse, soft Add programming pulses and programming pulses. By the first phase, the memory cells reach the same logic state and approach the same threshold voltage. Next, in the second phase, this algorithm is used to further densify the distribution of threshold voltage levels near the final data state. In the second phase of the invention, the algorithm uses additional bi-directional erase and soft programming pulses until the cell achieves the desired final threshold voltage value corresponding to the final data state. Erase all MLB cells again.

  Referring initially to FIG. 1, an unsigned Vt distribution 100 for a 4-level MLB cell is shown in accordance with certain aspects of the present invention. Vt distribution 100 shows a collection of memory cell threshold voltages centered around four distinct target threshold voltages. Each target threshold voltage occupies a range of Vt values specified by levels L1, L2, L3 and L4, respectively. Ideally, each level is centered on the upper and lower Vt limits, eg, between Vt0, Vt1, Vt2, Vt3 and Vt4. Various levels have corresponding binary states (eg, L1 = 11, L2 = 10, L3 = 01 and L4 = 00 or L1 = 00, L2 = 01, L3 = 10 and L4 = 11) may be arbitrarily assigned. A four-level MLB cell associated with distribution 100 may include a single physical bit that can be programmed into four levels, or alternatively, a dual-bit cell having two physically distinct bits. Or it may include mirror bit cells, and each of these two bits may be programmed to multiple levels, such as four, in which case 16 states are available.

  The method of the present invention is preferably implemented in an MLB memory device having any combination of positive and negative Vt distributions. For example, in FIG. 1, the method of the present invention is equally applicable regardless of whether Vt0, Vt4, or another such Vt limit is used as the zero potential of the memory cell or another reference potential. Considering the example of the four-level single-bit memory cell of FIG. 1, in the first phase of operation, the method of the present invention is used to erase all memory cells originally programmed to the L3 and L4 data states. , An intermediate threshold voltage value corresponding to the L2 data state can be reached. Next, in a second phase of operation, the memory cell is erased using this method, as discussed in more detail below, to reach the final threshold voltage value corresponding to the L1 data state. In this example, it appears to imply that the L1 level corresponds to the erased state, but L1, L4 or any other level may represent the erased state.

FIG. 2 illustrates another illustrative unsigned Vt distribution 200 of a single bit 8-level cell in accordance with an aspect of the present invention. The Vt distribution 200 of FIG. 2 represents a collection of memory cell threshold voltages centered on eight individual target threshold voltages. Each target threshold voltage occupies a certain range of Vt values specified by level L1 to level L8. Ideally, each level is centered on the upper and lower Vt limits, eg, between Vt0 and Vt8. Various levels include corresponding binary states (eg, L1 = 111, L2 = 110, L3 = 101 to L8 = 000, or L1 = 000, L2 = 001, L3 = 0100 depending on the user's request. L8 = 111) may be arbitrarily assigned. Again, since the method of the present invention is preferably implemented in an MLB memory device having any combination of positive and negative Vt distributions, the Vt distribution 200 is not given polarity. If a dual bit cell is used (having two physically separate bit positions), an 8-level cell corresponds to 64 valid data states.

FIG. 3 shows a Vt distribution 300 of a population of Vt values at one exemplary level of a multi-level cell as shown in FIGS. 1 and 2 according to the present invention. The exemplary level LX of the Vt distribution 300 is ideally centered on a target Vt (target) having upper and lower collective boundary levels L _U and L _L , respectively. The population of Vt values is more ideally centered between the upper and lower Vt limits VtX-1 and VtX, but it may be different. One purpose of the method of the invention is to narrow the collective boundary levels L _U and L _L , ie “densify”, closer to each other. Sigma is often used to symbolize the standard deviation of such populations, which is a measure of population variability. Thus, a smaller sigma represents a narrower Gaussian distribution of the population, indicating that more cell threshold voltages are gathered closer to the target Vt (target).

  As the inventors of the present invention recognize, one solution for obtaining a predictable and well-controlled programmed Vt distribution from an MLB cell is to first make all cells in a group common To the erased state, which has a Vt distribution that is well controlled and erased in a predictable manner. The inventor of the present invention further observed and recognized that each time an operation is performed on a particular group of memory cells, the group progressively densifies or filters itself to the same It tends to be closer to the Vt potential. Accordingly, the inventor has devised a bi-directional method of repeatedly erasing, programming and soft programming a cell in two or more phases between two or more distinct Vt level values. These repetitive operations tend to narrow the cell distribution and tend to increase the cell density to a common data state.

For example, in one aspect of the invention, an erase operation is used to ensure that the slowest erase bit is adapted to the Vt ≦ L _U level, while programming and soft programming operations are used most The slow Vt bit is reliably matched to Vt ≧ L _L level. In other words, in one aspect of the invention, an erase operation can be used to reduce the Vt population of cells from the L _U boundary toward the target Vt (target), while another In the method aspect, programming and soft programming can be used to increase the Vt population of cells from the _LL boundary toward the target Vt (target) value. As a result, the inventor's observation is that each successive alternating operation that attempts to move Vt in the opposite direction, such as an erase operation followed by a soft programming operation and then an erase operation, The sigma of the Vt population is advantageously reduced and the bits are densified. The method of the present invention is similar to the successive approximation method in that the Vt distribution population of the cells is gradually fine-tuned toward the target Vt (target) value by each successive operation. . As a result, this method can be faster and more energy efficient than some other conventional single-phase methods.

A sector erase algorithm or group erase algorithm performed in one or more sectors or groups of an array of suitable flash MLB flash memory cells facilitates the method of the present invention. The algorithm of the present invention may be applied in, for example, two or more erase phases (or layers), and erase selected sectors to a single data state, improving subsequent programming operations. . This algorithm results in a well-controlled high-density Vt distribution for multilevel memory cells, which can increase erase speed and efficiency, effectively increasing device density and memory capacity. The erasure algorithm and method of the present invention are applied bi-directionally and evenly distributed across each sector of the array in two phases.

  Although this method is illustrated and described below as a series of operations or events, it will be understood that the invention is not limited by the illustrated order of such operations or events. For example, some operations may be performed in a different order and / or with other operations or events than those illustrated and / or described herein. Moreover, not all illustrated procedures may be required to implement a method in accordance with one or more aspects of the present invention. Note that one or more of these operations may be performed in one or more individual operations or phases.

  FIG. 4A shows a flow diagram of an exemplary method 400 for erasing a sector or array of MLB flash memory cells according to the present invention. Although the term “sector” is used throughout, this term is not to be construed as limited to one particular group of cells, but rather is applicable to any group of MLB cells. Should be understood. 4B to 4F further show a detailed flow diagram of various operations in the MLB sector erase method 400 of FIG. 4A. For the following method description and for the illustration of FIGS. 4B-4F, the four level flash memory cell is similar to that of FIG. 1, L1 represents blank or erased state, and L4 is the highest level. . In this example, L1 represents an erased state, but method 400 is valid for any level assignment and Vt distribution polarity of the MLB memory cell, and the difference is considered to be within the scope of the present invention. I want you to understand.

  For example, the method 400 of FIG. 4A includes a two-phase algorithm for bidirectionally erasing memory cells according to the present invention. The first phase of method 400 includes, for example, steps 402, 410, 420, and 430, while the second phase includes steps 440, 450, and 460. In the first phase of the method 400, the cells basically reach an intermediate threshold voltage value (IV) (eg, L2 of the four levels of FIG. 1), while in the second phase, the cells Further, it is erased to reach a final threshold voltage (FV) (for example, L1 is used as an erased state, L1 among the four levels in FIG. 4).

  For example, the first phase of MLB sector erase method 400 begins at 402, and different portions of the sector or array may initially be programmed to different levels (eg, some of L1, L2, L3 in FIG. 1 or L4 level). At 410, all memory cells in the selected sector or sectors of the array are erased to an intermediate value IV. Operation 410 of FIG. 4B is performed by repeatedly applying an erase pulse to the sector at 414 until all memory cells in the sector have been erased at least to an intermediate threshold voltage value IV at 416 (eg, Vt ≦ IV One implementation is shown in which all memory cells in a sector are erased and tested in both directions until it is determined that all cells have been erased to L2 in FIG. It is executed by iterating.

  At 420, the overerased cells in the erase operation of 410 are soft programmed until the final value FV (eg, the overerased cells are soft programmed until L1 in FIG. 1). Operation 420 of FIG. 4C illustrates an example of soft programming an over-erased cell to a final value, which indicates whether the cell selected at 424 has been over-erased (Vt <FV). , Then applying a soft programming pulse to the still over-erased cell at 426 and re-verifying the cell at 424 is repeated. This soft programming and verification process is performed for each overerased cell until it is determined at 428 that all overerased cells have returned to the final value FV (eg, L1 in FIG. 1). Continue iteratively.

  At 430, all remaining cells at final value FV (eg, at L1) are programmed to an intermediate value (eg, L2 in FIG. 1) to bring all cells in the sector to a single state. Operation 430 of FIG. 4D verifies whether the cell selected at 434 remains FV (Vt = FV), and then programming at 436 if the cell remains FV (eg, L1). An example is shown in which all final value FV cells are programmed to an intermediate value IV by iteratively applying pulses and revalidating the cell at 434. This programming and verification process continues iteratively for each FV level cell until it is determined at 438 that all FV level cells are programmed to an intermediate value IV (eg, L2 in FIG. 1). At this point and at the end of the first phase, all cells have reached the same intermediate state and have a moderate Vt distribution sigma. The term final value cell in this example refers to the cell that is initially programmed in a state where the entire sector will eventually be erased. In this example, it corresponds to the cell already programmed to L1 at the beginning of the erase method 400.

  In the second phase of the MLB sector erasing method 400, the sigma of the Vt distribution is further improved. At 440 in FIG. 4A, all memory cells in the selected sector or sectors in the array are erased again, but here reaches the final value FV (eg, L1 in FIG. 1). Operation 440 of FIG. 4E illustrates an example of iteratively erasing and testing all the memory cells in the sector, which is erased at 446 until all the memory cells in the sector reach at least the final value FV (eg, Vt.ltoreq.FV, and it is determined that all cells have been erased until reaching L1 in FIG.

  At 450 again, the over-erased cell (eg, Vt <FV) in the erase operation of 440 is soft-programmed to return to the final value FV (eg, the over-erased cell is soft-programmed to L1 in FIG. 1). To do). Operation 450 of FIG. 4F illustrates an example of soft programming an over-erased cell to a final value, which verifies whether the cell selected at 454 is over-erased (Vt <FV), and then In addition, a soft programming pulse is applied to the cell that is still over-erased at 456 and the cell is re-verified at 454 again. This soft programming and verification process is repeated for each overerased cell until it is determined that all cells overerased at 458 have returned to the final value FV (eg, L1 in FIG. 1). Continue. Thereafter, the method 400 ends at 460 and all MLB flash memory cells in one or more sectors of the array have reached the same data state and centered on the final value FV within a narrow Vt set distribution. Has reached an erased state.

  In accordance with another aspect of the present invention, various voltages used in the erase, programming and soft programming operations of method 400 can be adjusted to further optimize and speed up the bit algorithm and densification.

  FIG. 5 illustrates the Vt of some exemplary memory cells of a sector or array of MLB flash memory cells programmed to various initial logic states and corresponding Vt levels suitable for sector erase according to the method of the present invention. A level graph is shown. Subsequently, FIGS. 6-10 result from the various processing steps of the MLB sector erase method of the present invention, eg, the Vt level of the illustrative memory cell of FIG. 5 using the two-phase algorithm and method 400 of FIG. 4A. The graph of is shown.

For example, FIG. 5 shows random selection and programming 500 of six memory cells, cell 1, cell 2, cell 3, cell 4, cell 5 and cell 6, from different portions of a sector or array of memory cells. Cell 1 through cell 6 initially have different Vt levels (eg,
L1, L2, L3 and L4) of FIG. 1 and their levels correspond to, for example, one of four logic states of a single bit 4-level MLB memory cell. In the example of FIG. 5, cell 1 is programmed to L4, cell 2 is programmed to L4, cell 3 is programmed to L3, cell 4 is programmed to L2, cell 5 is programmed to L1, as shown. Cell 6 is programmed to L1.

  FIG. 6 shows the result 600 of the erase operation 410 of the first phase of the method 400, where all cells in one or more sectors are erased to an intermediate threshold voltage value IV (eg, L2 level). ). In our observation, cells are usually erased to some extent proportional to the level at which the cell started. For example, cells originating from “higher” L4 levels typically vary more greatly with erase pulses and the potential applied to the cells than cells resulting from “lower” levels such as L3, L2 and L1 levels. Thus, following one or more erase pulses, FIG. 6 shows that the cells have moved “down” and that the cells originating from L3 and L4 have moved at a greater rate than those originating from the L1 and L2 levels. Indicates.

  Always one or more cells (eg cell 2) have a slightly larger post-erase threshold and eventually more erase pulses (or larger erases) to reach the data state corresponding to the L2 level Potential) may be required. However, since erase operation 410 is a collective operation, cell 5 and cell 6 generated from L1 are overerased as shown in FIG. 6 before cell 2 is sufficiently erased and reaches L2 level. (For example, Vt <FV). Such cells require some level of programming and / or soft programming to correct the over-erased situation, as discussed in the next 420.

  FIG. 7 shows the result 700 of the soft programming operation 420 of FIG. 4A in the first phase of the method 400. For example, over-erased cell cells 5 and 6 are soft programmed (see, eg, FIG. 4C) to return to the final value FV (eg, L1 in FIG. 1).

  FIG. 8 shows the result 800 of the first phase programming operation 430 of the method 400 of FIG. 4A. At 430, all remaining cells in the final value FV cell, eg, cell 3, cell 4, cell 5, cell 6, in L1 or close to L1, are programmed to the intermediate value and all of its sectors Cells reach a single state (eg, L2). As described above, this can be accomplished by repeating the verification of the cell and applying a programming pulse to the cell until the cell obtains an intermediate value IV (eg, L2 in FIG. 1). At this point and at the end of the first phase, all cells have reached the same intermediate state and have a moderate Vt distribution sigma as shown in FIG.

  FIG. 9 shows the result 900 of the second erase operation 440 in the second phase of the method 400 of FIG. 4A. In the second phase, the sigma of the Vt distribution is further improved (decreased). At 440, all memory cells (cell 1 to cell 6) in the selected sector or sectors of the array are erased again, but here reaches the final value FV (eg, L1). Until it is determined that all memory cells have been erased to at least the final value FV (eg, L1 in FIG. 1), all memory cells in the sector are subjected to repeated application of erase pulses (eg, FIG. 4E). reference). However, once again, if a cell is more sensitive to the applied erase voltage compared to other cells in the sector, this will cause the cell to over-erase, as shown by cell 5. May remain.

FIG. 10 illustrates a second soft programming operation 45 in the second phase of the method 400.
A result of 1000 is shown. At 450, the cells over-erased in the 440 erase operation (eg, Vt <FV) are soft-programmed again to return to the final value FV (eg, L1). For example, cell 5 may be verified repeatedly until it is determined that the cell has returned to the final value FV (eg, L1 in FIG. 1), soft programmed with a soft programming pulse, and verified again.

  Thereafter, the method 400 causes all illustrative MLB flash memory cells (cell 1 to cell 6) of one or more sectors of the array to reach the same data state and the final value FV (eg, L1). The process ends with an erased state within a narrow Vt set distribution centered at.

  Note that additional phases are available at additional intermediate level values selected between intermediate value IV and final value FV. For example, if an 8-level MLB memory cell is used, the first IV is established at L6, the second IV is established at L4, the third IV is established at L2, and the final value FV is established at L1. be able to. In another example, if an 8-level MLB memory cell is used, the first IV may be established at L3, the second IV may be established at L5, and the final value FV may be established at L6 as an erased state. it can.

  While the invention has been illustrated and described with respect to one or more implementations, those skilled in the art will recognize equivalent modifications and variations upon reading and understanding this specification and the accompanying drawings. Will float. The present invention includes all such variations and modifications and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the components described above (assemblies, devices, circuits, etc.), the terms used to describe such components (including references to “means”) are separately Unless specified, it is intended to correspond to any component that performs a particular function of the above-described component (ie, is functionally equivalent), which is illustrative of the invention presented herein This is true even if the implementation is not structurally equivalent to the disclosed structure that performs that function. Furthermore, although certain features of the invention may have been disclosed for only one of several implementations, such features are desired in any given or particular application, and May be combined with one or more other features of other implementations that may be advantageous. Further, the words “includes”, “having”, “has”, “with” or variations thereof are used in the detailed description or in the claims. In scope, these terms are meant to be inclusive, as are the words “comprising”.

  These systems and methods can be used in the field of semiconductor manufacturing to provide a method for erasing a sector of a flash memory device cell having a multi-level data state.

FIG. 6 is a diagram of Vt distribution of a 4-level multilevel cell according to an aspect of the present invention. FIG. 7 is a Vt distribution diagram of an 8-level multi-level cell according to an aspect of the present invention. 1 is an exemplary level Vt distribution of a cell, according to one aspect of the present invention, and centered on a target Vt and having upper and lower collective boundary levels as shown in FIGS. 1 and 2 FIG. FIG. 6 is a flow diagram illustrating an exemplary method for erasing a sector or array of MLB memory cells, including a two-phase algorithm for bidirectionally erasing memory cells according to an aspect of the invention. 4B is a flow diagram illustrating further details of various portions in an exemplary method of erasing a sector or array of MLB memory cells in accordance with the MLB sector erase method of FIG. 4A. FIG. 4B is a flow diagram illustrating further details of various portions in an exemplary method of erasing a sector or array of MLB memory cells in accordance with the MLB sector erase method of FIG. 4A. FIG. 4B is a flow diagram illustrating further details of various portions in an exemplary method of erasing a sector or array of MLB memory cells in accordance with the MLB sector erase method of FIG. 4A. FIG. 4B is a flow diagram illustrating further details of various portions in an exemplary method of erasing a sector or array of MLB memory cells in accordance with the MLB sector erase method of FIG. 4A. FIG. 4B is a flow diagram illustrating further details of various portions in an exemplary method of erasing a sector or array of MLB memory cells in accordance with the MLB sector erase method of FIG. 4A. FIG. FIG. 4 is a graph of Vt levels of some exemplary memory cells of a sector or array of MLB memory cells programmed to various initial logic states and corresponding Vt levels suitable for sector erase according to the method of the present invention. . 6B is a graph of the Vt level of the exemplary memory cell of FIG. 5 resulting from the processing steps of the MLB sector erase method of the present invention using the two-phase algorithm of FIG. 4A. 6B is a graph of the Vt level of the exemplary memory cell of FIG. 5 resulting from the processing steps of the MLB sector erase method of the present invention using the two-phase algorithm of FIG. 4A. 6B is a graph of the Vt level of the exemplary memory cell of FIG. 5 resulting from the processing steps of the MLB sector erase method of the present invention using the two-phase algorithm of FIG. 4A. 6B is a graph of the Vt level of the exemplary memory cell of FIG. 5 resulting from the processing steps of the MLB sector erase method of the present invention using the two-phase algorithm of FIG. 4A. 6B is a graph of the Vt level of the exemplary memory cell of FIG. 5 resulting from the processing steps of the MLB sector erase method of the present invention using the two-phase algorithm of FIG. 4A.

Claims (10)

A method (400) of erasing a sector of a memory cell to a single data state (1000), wherein the memory cell has three or more corresponding to three or more threshold voltage values (100, 200) Data state (100, 200)
Performing a block erase operation on the sector of memory cells until all cells of the sector are erased to reach a threshold voltage generally corresponding to an intermediate value (410);
Performing a soft programming operation on the over-erased memory cells of the sector until the threshold voltage of the over-erased memory cells substantially corresponds to a final value (420);
Programming a memory cell in a sector determined to be at or near the threshold voltage corresponding to the final value until the threshold voltage of the memory cell generally corresponds to the intermediate value ( 430),
Re-executing the block erase operation for the sector until all cells of the sector are erased and the threshold voltage approximately corresponding to the final value is reached (440);
Re-executing (450) a soft programming operation for the over-erased memory cells of the sector until the threshold voltage corresponding to the final value is obtained (400). For the sector of memory cells, performing a block erase operation (410) until all cells of the sector are erased until a threshold voltage approximately corresponding to the intermediate value is reached (410).
Verifying the block erase operation of the memory cell by identifying whether the threshold voltage of the memory cell generally corresponds to the intermediate value (416);
Re-executing (414) the block erase operation for the sector of memory cells until it is determined that all cells of the sector have a threshold voltage generally corresponding to the intermediate value; The method (400) of claim 1.   Verifying the block erase operation (416) measures a threshold voltage value generally corresponding to a bit of each memory cell of the sector and compares the measured value to a minimum erase threshold voltage value. The method (400) of claim 2, comprising identifying an erased memory cell. Performing a soft programming operation on the over-erased memory cells of the sector until the threshold voltage of the over-erased memory cells substantially corresponds to the intermediate value (420);
Identifying (424) over-erased memory cells in the sector;
Performing a soft programming operation on the over-erased memory cells (426);
Verifying (424) the soft programming operation of the over-erased memory cell by identifying whether the threshold voltage of the over-erased memory cell corresponds to a final value;
For the over-erased memory cell, re-execute the soft programming operation until it is determined (428) that the over-erased memory cell of the sector has a threshold voltage corresponding to the final value. The method (400) of claim 1, comprising: Programming memory cells in the sector that are determined to be at or near the threshold voltage corresponding to the final value until the threshold voltage of the memory cell generally corresponds to the intermediate value. (430)
Identifying (434) a group of remaining memory cells in the sector having a threshold voltage corresponding to the final value;
Programming all remaining memory cells of the sector that have been determined to be at or near a threshold voltage generally corresponding to the final value (436);
Verifying (434) the programming operation of the memory cell by identifying (434) whether the threshold voltage of the memory cell generally corresponds to the intermediate value;
Re-programming the remaining memory cells of the sector determined to be at the threshold voltage corresponding to the final value until the memory cell is determined to have a threshold voltage generally corresponding to the intermediate value (438). The method (400) of claim 1, comprising: (436). For the sector, re-performing the block erase operation (440) until all cells of the sector are erased and the threshold voltage approximately corresponding to the final value is reached.
Verifying the block erase operation of the memory cell by identifying whether the threshold voltage of the memory cell generally corresponds to a final value (446);
Re-executing (444) the block erase operation for the sector of memory cells until it is determined that all cells of the sector have a threshold voltage generally corresponding to the final value. Item 400 (400). Re-running a soft programming operation (450) for the over-erased memory cells of the sector until the threshold voltage approximately corresponding to the final value is obtained.
Verifying the soft programming operation of the over-erased memory cell by identifying whether the threshold voltage of the over-erased memory cell generally corresponds to the final value (454);
For the over-erased memory cell, the soft programming operation until the over-erased memory cell of the sector is determined to have a threshold voltage that generally corresponds to the final value (458). The method (400) of claim 1, comprising re-executing (456).   The intermediate threshold voltage value and the final threshold voltage value individually correspond to one of three or more data states that generally correspond to three or more threshold voltage values (100, 200). The method (400) described.   To bring the threshold voltage of the memory cell to one or more additional threshold voltage values (100, 200) between the intermediate threshold voltage and the final threshold voltage to further densify the bit The method (400) of claim 1, further comprising an additional erase operation (410) and a soft programming operation (420) for the memory cell.   The method (400) of claim 1, wherein the intermediate threshold voltage value and the final threshold voltage value are predetermined by a user of a memory cell device.

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