JP2008300469A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive nonvolatile semiconductor storage device with large capacity which is free from problems arising when chips are stacked by using wire bonding, and can reduce the cost of the chips to be stacked. <P>SOLUTION: The nonvolatile semiconductor storage device is constituted by stacking: a memory array chip 10 having one or a plurality of memory arrays 11, a row selecting circuit 12, and column selecting circuits 13 and 14; and a control chip 20 which has at least control circuits 25 to 28, a voltage supply circuit 29, input interfaces 21 to 23, and an output interface circuit 24, and performs control over the memory array chip 10. First through electrodes T1 on the memory array chip and second through electrodes T2 on the control chip which correspond to each other are disposed at identical positions, and the corresponding first through electrodes on the memory array chip and second through electrodes on the control chip are stacked one over the other in a stacking direction to electrically be connected to each other, thereby electrically connecting the memory array chip and control chip to each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a plurality of chips of one or a plurality of memory array chips and a control chip.

  In recent years, due to an increase in the amount of data in digital home appliances and mobile phones typified by audio players, the mounted memory capacity of non-volatile semiconductor memory devices such as flash memory, in which data is not lost even when the power is turned off, in particular, is rapidly increasing. is doing. Although the miniaturization has progressed and the storage capacity of one chip (hereinafter abbreviated as “capacity” as appropriate) has increased, a large-capacity memory has been realized by mounting a plurality of flash memories according to the required product specifications. There are many. However, the trend toward smaller and lighter application products is accelerating, and the mounting area on the system board is narrowing. In addition, in the game industry and the like, the display image has become higher definition and the flash memory capacity for storing image data is increasing year by year, but the area where the memory is installed in game machines is also limited, It is difficult to place chips on a plane.

  As a workaround, as shown in FIG. 9, a chip stacked package in which a plurality of bare chips 6 are three-dimensionally stacked in one package using a wire bonding technique is realized. For example, by stacking four flash memories having a capacity of 256 Mbit, it is possible to realize a capacity of 1 Gbit with one package.

  In the above-described stacked packaging, a wire bond system in which external input / output pads of stacked flash memories are connected by wire bonding is generally used, and various variations of memory capacities depending on the capacity of the combined flash memory, that is, the chip size. Is feasible. However, as the number of stacked chips increases, an increase in the number of wires is unavoidable, and in order to stack the same chip size, it is necessary to add a spacer between chips on the chip-on-wire technology (COW) or chips. The challenges will be greater and the latter half manufacturing costs will increase.

  As described above, in a stacked package in which a plurality of chips are stacked, there is a silicon penetration technique as disclosed in the following Patent Document 1 as an alternative to the conventional inter-chip connection technique using wire bonding. In this prior art, a through hole is formed in a silicon substrate, an insulating film is formed on the inner wall of the through hole, and then an electrode protruding to the back surface of the silicon substrate is embedded. The electrode protruding on the back side is used as an electrode for electrical connection with a chip adjacent to the back side. As a result, even if the number of stacked chips increases, input / output signals can be exchanged between the chips via the silicon through hole, which frees you from the problem of stacking chips using wire bonds, and allows more stages. Lamination is possible.

  As described above, as a nonvolatile semiconductor memory device that achieves a large capacity by stacking using silicon penetration technology or the like, a flash memory whose capacity is being increased by a single chip is generally widely used. Next, the circuit configuration of the flash memory will be briefly described.

  FIG. 10 shows a schematic block configuration of a general flash memory. FIG. 11 shows a schematic layout arrangement on one chip of each functional block shown in FIG.

  As shown in FIGS. 10 and 11, a general flash memory has a memory array 11 in which a plurality of nonvolatile flash memory cells are arranged in the row and column directions, and a predetermined memory operation (write operation) from within the memory array 11. , Erase operation, read operation, etc.) one or more memory cells to be selected are individually selected along the row direction and the column direction, and a voltage necessary for a predetermined memory operation is applied to the selected memory cell. A row selection circuit 12 to be connected, a column selection circuit 13, 14 and a column selection gate 14 constituting a part of the column selection circuit, and a read circuit 15 for reading out storage information of the selected memory cell; Internal control circuits 16, 25 that select based on the input and control the circuit operation in the flash memory according to a predetermined operation procedure according to the selected memory operation 8. A high voltage necessary for a predetermined memory operation with respect to the memory array 11 is generated by control from a write state machine (WSM) 27 in the internal control circuit, and a row selection circuit 12 and a column selection circuit are generated. A high voltage supply circuit 29 for supplying power to 13, 14, etc., an address input buffer 21 for receiving an address input from the outside and generating an internal address signal, a data input buffer 23 for receiving an input data from the outside and generating an internal input data signal, A control input buffer 22 that receives an external control input and generates an internal control input signal, and a data output buffer 24 that outputs data read from the memory array 11 or an internal state signal output from the control circuit as an external output It is prepared for.

  In the block configuration of FIG. 10, the column selection circuits 13 and 14 include a column address decoder 13 and a column selection gate 14 that is activated by a decode signal of the column address decoder 13. The column selection gate 14 is connected to each bit line (not shown) of the memory array 11, and the output of the row address decoder constituting the row selection circuit 12 is connected to each word line (not shown) of the memory array 11. is doing. Further, in the block configuration of FIG. 10, the internal control circuits 16, 25 to 28 are based on the internal control input signal in addition to the WSM 27 for controlling the memory operation such as the write operation and the erase operation for the memory array 11 in accordance with a series of operation procedures. Input / output control logic 25 for controlling activation / deactivation of input / output interfaces such as address input buffer 21, control input buffer 22, data input buffer 23, data output buffer 24, etc., and data input based on internal control input signals A command user interface (CUI) 12 that recognizes an external command input to the buffer 23 and issues a necessary control signal to the WSM 27, and data that temporarily stores write data input to the data input buffer 23 Register 28, reading The data comparator 16 is configured to compare the read data of the readout circuit 15 with the write data stored in the data register 28. Since the data register 28 and the data comparator 16 are circuits used for controlling the WSM 27, they are included in the internal control circuit for convenience, but they may be handled as independent circuits.

  As shown in FIG. 11, the block arrangement on the chip includes internal control circuits 25 to 28 excluding the data comparator 16, high voltage supply circuit 29, input / output interfaces (address input buffer 21, data input buffer 23, control input buffer 22). , The data output buffer 24, etc.) and the memory core region of the memory array 11 and its associated row selection circuit 12, column selection circuits 13, 14 and data comparator 16 are divided into two areas, thereby improving the area efficiency. A good layout.

  Next, the memory operation of the flash memory including the internal control circuits 16 and 25 to 28 shown in FIG. 10 will be briefly described by taking the case of the write operation as an example.

  First, the operation sequence of the flash memory is such that a command corresponding to an operation mode such as a write operation or an erase operation is sent via a data signal line S2 in synchronization with a data input cycle defined by a predetermined control input signal. 23. The input command (write command) is transferred to the CUI 26 via the data input buffer 23. The CUI 26 recognizes the transferred command as a write command, and outputs a control signal indicating the input of the write command to the WSM 27. Thereby, the WSM 27 starts a control procedure in the write operation mode. As a result, a write setup state is entered in which write data can be input in the next data input cycle.

  In the next data input cycle, write data is input to the data input buffer 23 via the data signal line S2, and an address to be written is input to the address input buffer 21 via the address signal line S1. The address to be written is converted into an internal address signal of a row address and a column address and input to the row address decoder 12 and the column address decoder 13, respectively. In parallel with this, write data is stored in the data register 28 from the data input buffer 23.

  The row address decoder 12 selects a word line corresponding to the row address to be written based on the input row address, and the column address decoder 13 and the data register 28 respectively store the input column address and the stored write. Based on the data, the column selection gate connected to the bit line corresponding to the bit to be written in the column address to be written is activated. Thereby, a memory cell to be written is selected.

  The WSM 27 activates the high voltage supply circuit 29 and shifts the high voltage supply circuit 29 to the write mode to generate a voltage necessary for the write operation, so that the row selection circuit 12, the column selection circuits 13 and 14, etc. Supply. As a result, a high voltage for write operation is applied to the selected word line and bit line via the row selection circuit 12 and the column selection circuits 13 and 14, respectively. As a result, a predetermined write voltage is applied to the memory cell to be written, and the threshold voltage of the selected memory cell is raised.

  Subsequently, the WSM 27 stops the application of the write voltage to the selected memory cell, shifts the internal state to a read operation for write verification in order to verify the state of the increased threshold voltage, and stores the selected memory cell. Read information. The read data is compared with the expected value (write data) stored in the data register 28 by the data comparator 16, and the comparison result is output to the WSM 27. Hereinafter, the read operation for write verification and the comparison operation between the read data and the expected value are referred to as a write verify operation.

  When the comparison result output from the data comparator 16 does not match, the WSM 27 rewrites the expected value of the data register 28 so that the write voltage is applied again only to the mismatched memory cell. Rewrite (application of the write voltage for the second and subsequent times) is performed on the memory cells. Thereafter, the write verification operation is performed again, and the verification result (comparison result) is output to the WSM 27. Thereafter, the rewrite operation and the write verification operation are repeated until there is no mismatch in the verification results.

  When it is determined that the verification results match for all the write target memory cells, the WSM 27 deactivates the high voltage supply circuit 29 and outputs a write completion signal to the CUI 26. Thereafter, the CUI 26 enters a standby state for receiving the next command.

  As is clear from the above description, the write operation in the flash memory is not only a simple operation of selecting a write target memory cell and applying a write voltage, but also performing a rewrite and write verification operation on the write target memory. Since it has a complicated processing sequence of repeating until the cell is completely written, an internal control circuit such as WSM 27 and CUI 26, a high voltage supply circuit 29, etc. are incorporated in the chip in order to release the complicated processing sequence from the external processor. It is the composition to do.

JP 2001-53218 A

  Next, four bare chip 6 of 256 Mbit flash memory configured to incorporate the internal control circuit, high voltage supply circuit, and the like shown in FIG. 10 are stacked and wire bonding is used as shown in FIG. FIG. 12 shows a block configuration when a 1 Gbit capacity is realized by connecting to a substrate.

  Address signal lines S1 [A0 to A23], data signal lines S2 [DQ0 to DQ15], write control signal lines S4 [WE #], output release signal lines S5 [OE #], and resets connected to each flash memory chip 6 The signal line S6 [RST #] is connected in common between the flash memory chips 6. In order to control each flash memory chip 6 individually, individual flash memory chips 6 are selected by controlling independent chip control signal lines S31 to S34 [CE1 #, CE2 #, CE3 #, CE4 #]. It becomes possible to activate it. However, since the data signal line S2 [DQ0 to DQ15] is commonly connected to each flash memory chip 6, two or more chip control signal lines S31 to S34 [CE1 #, CE2 #, CE3 #, CE4 #] are provided. It cannot be activated at the same time. Accordingly, when only one of the four flash memory chips 6 is activated, in the activated flash memory chip, the internal control circuit, the high voltage supply circuit, etc. Although the operation according to the operation mode is performed, the remaining other inactive flash memory chips are naturally used in an inactive state. In other words, the peripheral circuit area shown in FIG. 11 is effectively used only in the active flash memory chip, whereas the memory array 11 occupying most of the memory core area is in an inactive state. However, it plays the original function of storing the written information in a nonvolatile manner. That is, the peripheral circuit area including the internal control circuit such as the WSM 27 and the CUI 26 and the high voltage supply circuit 29 is not necessarily required individually for all the chips when a plurality of chips are stacked to increase the capacity. One set is good.

  The present invention has been made in view of the above-mentioned problems, and the object thereof is released from the problem in the case of stacking chips using wire bonds, and it is possible to reduce the cost of stacked chips, which is advantageous in cost. It is in providing a high-capacity and large-capacity nonvolatile semiconductor memory device.

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device comprising one or more memory array chips and a control chip for controlling the memory array chip,
The memory array chip includes at least a memory array in which a plurality of nonvolatile memory cells are arranged in the row and column directions, and one or more memory cells to be subjected to a predetermined memory operation from the memory array in the row direction. And a row selection circuit, a column selection circuit, and a column selection circuit, each of which is selected separately along the column direction and applies a voltage necessary for the predetermined memory operation to the selected memory cell. A read circuit for reading stored information of the memory cell, and a voltage necessary for causing the row selection circuit and the column selection circuit, or the row selection circuit, the column selection circuit, and the memory array to perform a predetermined memory operation. A first voltage supply line for supplying a source; a first address signal line for supplying an internal address signal to the row selection circuit and the column selection circuit; and write data A first write data signal line for supplying a corresponding write data signal to the column selection circuit, and a first read for outputting from the read circuit a read data signal corresponding to the storage information of the selected memory cell. A data signal line and an electrode penetrating the memory array chip, the first voltage supply line, the first address signal line, the first write data signal line, and the first read data signal line; A plurality of first through electrodes connected to each other are provided,
A control circuit in which the control chip selects at least a memory operation including a read operation and a write operation with respect to the memory array chip based on an external input, and controls the memory circuit according to a predetermined operation procedure corresponding to the selected memory operation; A voltage supply circuit that supplies the memory array chip with a voltage source necessary for causing the memory array chip to perform a predetermined memory operation under control from the control circuit; and the control circuit that receives the external input and the control circuit; An input interface circuit for generating an internal signal to be supplied to the memory array chip, an output interface circuit for outputting the read data signal output from the memory array chip to the outside as an external output, and an output from the voltage supply circuit Supplying the voltage source to the memory array chip. A second voltage supply line, a second address signal line for supplying the internal address signal among the internal signals output from the input interface circuit to the memory array chip, and the control circuit. A second write data signal line for supplying the write data signal to the memory array chip, and a second for supplying the read data signal received from the memory array chip to the output interface circuit or the control circuit. Read data signal lines and electrodes penetrating through the control chip, the second voltage supply lines, the second address signal lines, the second write data signal lines, and the second read data signal lines A plurality of second through electrodes connected to each other;
The first through electrode on the memory array chip and the second through electrode on the control chip are aligned with the corresponding through electrodes when the memory array chip and the control chip are stacked. The one or more memory array chips and the control chip are stacked, and the plurality of first through electrodes of each of the memory array chips and the corresponding through electrodes of the plurality of second through electrodes of the control chip are The first feature is that the layers are stacked in the stacking direction and electrically connected to each other.

  According to the nonvolatile semiconductor memory device having the first feature, the first through electrode on the memory array chip and the second through electrode on the control chip are stacked in the stacking direction of each chip and electrically connected to each other. Therefore, the first voltage supply line, the first address signal line, the first write data signal line, the first read data signal line on the memory array chip, the second voltage supply line on the control chip, the second Corresponding ones of the address signal line, the second write data signal line, and the second read data signal line are electrically connected to each other. As a result, the memory array chip can receive the internal address signal from the input interface circuit on the control chip and supply it to the row selection circuit and the column selection circuit, and can receive the write data signal from the control circuit on the control chip and supply it to the column selection circuit. Receives the voltage source necessary for memory operation from the voltage supply circuit on the control chip and supplies it to the row selection circuit and the column selection circuit, or to the row selection circuit, the column selection circuit and the memory array, and controls the read data signal from the read circuit It can be supplied to an output interface circuit or a control circuit on the chip, and a predetermined memory operation can be performed by control from the control circuit on the control chip. In other words, a combination of a control chip and an arbitrary one of one or a plurality of memory array chips can be realized by electrically connecting the first through electrode and the second through electrode, and a non-volatile semiconductor memory device capable of independent memory operation is configured. it can.

  Further, since the control chip is provided separately from the memory array chip, peripheral circuits such as a control circuit required as a non-volatile semiconductor memory device provided on the control chip and capable of independent memory operation are provided in the memory array chip. Since the memory array chip area can be reduced accordingly, the chip area of the entire nonvolatile semiconductor memory device can be greatly reduced. The effect of reducing the chip area becomes more prominent as the number of stacked memory array chips increases, and greatly contributes to a reduction in manufacturing cost of a large-capacity nonvolatile semiconductor memory device. In addition, the storage capacity can be freely changed by increasing or decreasing the number of stacked memory array chips.

  Furthermore, when changing the function of the memory operation of the nonvolatile semiconductor memory device, it is possible to respond by changing the function of the control circuit on the control chip except for the part related to the basic characteristics of the memory cell. A non-volatile semiconductor memory device with a different function can be realized simply by exchanging the control chip using the chip.

  Furthermore, since through electrodes are used for electrical connection between chips, there is no need to perform wire bonding for each chip, and the number of wires increases as the number of stacked chips increases, and memory array chips of the same chip size can be installed. The problems of chip bonding by chip bonding, such as chip-on-wire technology and the need to add spacers between chips, are eliminated, and an increase in the latter half manufacturing cost due to an increase in the number of stacked memory array chips can be suppressed.

  Here, it should be noted that it is no longer necessary to provide a peripheral circuit such as a control circuit necessary as a complete nonvolatile semiconductor memory device provided on the control chip and capable of independent memory operation, in the memory array chip. Accordingly, the area of the memory array chip can be reduced, but the number of wires required for electrical connection between the memory array chip and the control chip is likely to increase. For example, when the internal address signal is passed between the memory array chip and the control chip as a pair with the inverted address signal which is logically inverted, the first and second address signal lines are doubled, and the normal multi-bit output In the memory device, the data input / output is shared, but the data signal line is doubled by separating the write data signal and the read data signal, and the voltage supply of the voltage source for memory operation is supplied. It can be considered that the line is increased by separating the memory operation. Therefore, if the conventional completed nonvolatile semiconductor memory device is simply divided into a memory array chip and a control chip, and the electrical connection between the chips is performed by wire bonding, the conventional completed nonvolatile semiconductor memory device is The problem of the above-mentioned wire bonding type chip stacking becomes more conspicuous than the case of stacking and interconnecting by wire bonding. That is, the non-volatile semiconductor memory device is divided into a memory array chip and a control chip, and the through electrode is used for electrical connection between the chips, so that the object of the present invention can be fully achieved. is there.

  In addition to the first feature, the nonvolatile semiconductor memory device according to the present invention further includes a second feature that the memory array chip does not include the input interface circuit and the output interface circuit included in the control chip. Features.

  According to the nonvolatile semiconductor memory device having the second feature, the chip size of the memory array chip can be reduced, and the operational effects of the first feature can be reliably exhibited. Here, the memory array chip cannot be directly connected to the outside as a normal nonvolatile semiconductor memory device, but the memory array chip can perform a memory operation via an input interface circuit and an output interface circuit included in the control chip. no problem.

  In addition to the first or second feature, the nonvolatile semiconductor memory device according to the present invention may further include a memory array chip in which the number of the internal address signals received via the first address signal line is the memory. More than the number of the internal address signals used by the row selection circuit and the column selection circuit for selection of the memory cells of the memory array provided in the array chip, the memory array chip is included in the first address signal line. A chip selection determination circuit for determining selection / non-selection of the memory array chip based on a signal level of a surplus address signal line that is not used by the row selection circuit and the column selection circuit; A third feature is that the signal level of the surplus address signal line used sometimes can be set.

  In addition to the third feature, the nonvolatile semiconductor memory device according to the present invention further includes a nonvolatile information storage means in which the chip selection determination circuit can store information on the same principle as the memory cell, A fourth feature is that a signal level of the surplus address signal line used at the time of chip selection is set in the information storage means.

  In addition to the third or fourth feature, the nonvolatile semiconductor memory device according to the present invention further includes a plurality of the memory array chips stacked, and the correspondence between the plurality of first through electrodes of each of the memory array chips. The through electrodes to be stacked are stacked in the stacking direction and electrically connected to each other so that the signal levels of the surplus address signal lines used at the time of chip selection are different from each other in the chip selection determination circuit of each memory array chip. The fifth feature is that it is set.

  According to the nonvolatile semiconductor memory device having the third to fifth features, each of the plurality of memory array chips can be selectively used by a combination of different signal levels of the surplus address signal lines output from the control chip. Therefore, each memory array chip does not need to receive an individual chip selection signal from the control chip, and the capacity can be increased by using a plurality of the same memory array chips.

  Even if the internal address signal supplied from the control chip to the memory array chip via the surplus address signal line is an internal address signal higher than the internal address signal used by the row selection circuit and the column selection circuit, Any of the decoded signals obtained by decoding the internal address signal may be used.

  In particular, according to the nonvolatile semiconductor memory device of the fourth feature, it is not necessary to prepare a separate nonvolatile storage means for setting the signal level of the surplus address signal line used at the time of chip selection. Can be used.

  In addition to any one of the first to fifth features, the nonvolatile semiconductor memory device according to the present invention further includes a single memory array chip smaller than the control circuit included in the control chip. A simple control circuit for controlling a memory operation simplified for a test in accordance with a predetermined operation procedure, and a test input signal necessary for a test on a single array chip smaller than the input interface circuit included in the control chip A simple input interface circuit for receiving a test output signal, a simple output interface circuit for outputting a test output signal necessary for a test in a single array chip smaller than the output interface circuit included in the control chip, External connection pad for passing test input signal and test output signal , And sixth aspect further comprising a.

  According to the nonvolatile semiconductor memory device of the sixth feature, since a function test can be executed on a single memory array chip, a memory array chip that has been verified to be capable of a certain basic operation is stacked and nonvolatile. Since the non-volatile semiconductor memory device can be configured, the yield rate of non-volatile semiconductor memory devices can be increased. Also, if a functional test at the wafer level with a single memory array chip is performed without a simple control circuit, an interface for exchanging address signals and data signals between the memory array chip and the tester is provided on the memory array chip side. Since this is necessary separately and the burden on the tester side is increased, such inconvenience is also eliminated.

  A circuit common to the control circuit included in the control chip and the simple control circuit included in the memory array chip is provided on the memory array chip side, so that the chip size of the control chip can be reduced.

  In addition to any one of the first to sixth features, the nonvolatile semiconductor memory device according to the present invention further includes, in the memory array chip, the memory array is divided into two groups, and the plurality A first feature is that the first through electrode is arranged in a chip central region sandwiched between the two groups.

  According to the nonvolatile semiconductor memory device of the seventh feature, when the memory array is divided into two groups, at least one of the row selection circuit and the column selection circuit is also divided into two groups. Therefore, the signal wiring length from the first through electrode to the divided row selection circuit or column selection circuit is shortened and substantially equal, so that the signal delay can be reduced and the electrical characteristics are improved.

  In addition to any of the first to seventh features, the nonvolatile semiconductor memory device according to the present invention further includes the one or more memory array chips and the control chip stacked on a mounting substrate, An external connection pad provided on the control chip that transfers the external input and the external output and an external connection terminal provided on the mounting board are electrically connected; Features.

  According to the nonvolatile semiconductor memory device of the eighth feature, it is possible to provide a nonvolatile semiconductor memory device in a form mounted on a mounting substrate, and by mounting other functional chips on the same mounting substrate, The function of the nonvolatile semiconductor memory device can be expanded.

  In the nonvolatile semiconductor memory device according to the present invention, in addition to any of the first to eighth features, the control chip further includes the memory array provided in the memory array chip, the row selection circuit, and the column. A ninth feature is that a selection circuit and the readout circuit are provided.

  According to the nonvolatile semiconductor memory device having the ninth feature, it is possible to provide a control chip simply by providing the second through electrode in a completed nonvolatile semiconductor memory device capable of independent memory operation with one conventional chip. In addition, since the control chip alone can be provided as a complete nonvolatile semiconductor memory device, it is not necessary to develop a separate control chip.

  In the nonvolatile semiconductor memory device according to the present invention, in addition to any of the first to eighth features, the control chip further includes the memory array provided in the memory array chip, the row selection circuit, and the column. A tenth feature is that the selection circuit and the readout circuit are not provided.

  According to the nonvolatile semiconductor memory device of the tenth feature, since there is no memory array in the control chip, it is not necessary to use a special manufacturing process for forming memory cells, and the manufacturing cost of the control chip is reduced. Can be planned.

  Embodiments of a nonvolatile semiconductor memory device according to the present invention (hereinafter simply referred to as “device of the present invention” as appropriate) will be described below with reference to the drawings. In the following description, for simplicity of explanation, a flash memory is assumed as a nonvolatile semiconductor memory device. However, the device of the present invention is not limited to a flash memory, and a nonvolatile memory cell based on another memory principle. The present invention can also be applied to a nonvolatile semiconductor memory device including In the drawings to be referred to in the following description, the same reference numerals are given to the same circuit components as those of the conventional general flash memory shown in FIGS.

<First Embodiment>
FIG. 1 shows a schematic block configuration of the device 1 of the present invention. FIG. 2 schematically shows a schematic cross-sectional structure of the device 1 of the present invention mounted on a stacked package. As shown in FIGS. 1 and 2, the device 1 of the present invention stacks one or a plurality of memory array chips 10 on a mounting substrate 4 in order from the bottom, and further on the uppermost memory array chip 10. One control chip 20 is laminated. When there is one memory array chip 10, it seems that there is no advantage of dividing into the control chip 20 and the memory array chip 10, but the storage capacity can be adjusted by adjusting the number of stacked memory array chips 10. Therefore, the device 1 of the present invention in which one control chip 20 and one memory array chip 10 are stacked can be provided for applications where a minimum storage capacity is sufficient.

  In FIG. 3, as an embodiment of the device 1 of the present invention, four memory array chips 10 each having a memory array 11 with a storage capacity of 256 Mbit and one control chip 20 are stacked as shown in FIG. A signal connection relationship between chips when a storage capacity of 1 Gbit is realized is shown. In the embodiment shown in FIG. 3, since the data width is 16 bits, 26 address signals A0 to A25 are input from the outside, but each memory array chip 10 is used for address selection. Are 24 of A0 to A23, and the remaining A24 and A25 are used for selecting the four memory array chips 10. In the figure, Vcc, Vpp, and GND are a main power supply terminal, a sub power supply terminal for writing / erasing, and a ground terminal, respectively.

  As shown in FIG. 2, the memory array chip 10 is provided with a plurality of first through electrodes T1 penetrating the chip, and the control chip 20 is provided with a plurality of second through electrodes T2 penetrating the chip. Yes. The plurality of first through electrodes T <b> 1 are provided at the same position in each of the plurality of memory array chips 10. In the present embodiment, the plurality of memory array chips 10 are all constituted by the same chip. The plurality of second through electrodes T2 are arranged so that the through electrodes corresponding to the plurality of first through electrodes T1 are aligned at the same position when the control chip 20 is stacked on the memory array chip 10. Yes. Therefore, in the stacked state shown in FIG. 2, the first through electrodes T1 of each layer of the four memory array chips 10 are electrically connected to each other with the corresponding through electrodes overlapping each other. The first through electrode T1 and the second through electrode T2 of the control chip 20 are electrically connected to each other with the corresponding through electrodes overlapping each other. As a result, the second through electrode T2 of the control chip 20 is electrically connected to the corresponding first through electrode T1 of the memory array chip 10 of each layer.

  Further, the control chip 20 is provided with a plurality of external connection pads T3 for electrical connection with the outside, and the external connection pads T3 are electrically connected to the external connection terminals T5 provided on the mounting substrate 4. It is connected. For the electrical connection, wire bonding is used in the embodiment shown in FIG. 2, but the present invention is not limited to wire bonding.

  The first through electrode T1 and the second through electrode T2 are formed when an insulating film is formed on the inner wall of the through hole penetrating each chip, and then the through hole is filled with an electrode material and protrudes downward from the back surface and laminated. It is configured to be able to contact the upper surface of the corresponding through electrode of the chip located on the lower side. Further, the first through electrode T1 and the second through electrode T2 are formed by a well-known method, and since the formation method is not the gist of the present invention, the detailed description is omitted.

  As shown in FIG. 1, a memory array chip 10 includes a memory array 11 in which a plurality of nonvolatile flash memory cells are arranged in the row and column directions, and a predetermined memory operation (write operation, erase operation, A row selection circuit for selecting one or a plurality of memory cells to be subjected to a read operation or the like along the row direction and the column direction and applying a voltage necessary for a predetermined memory operation to the selected memory cells. 12 and column selection circuits 13 and 14, a column selection gate 14 constituting a part of the column selection circuit, a read circuit 15 for reading storage information of the selected memory cell, read data of the read circuit 15 and the control chip 20. Data comparator 16 for comparing write data stored in the data register 28 on the side, and selection / selection of the memory array chip 10 Configured with determining chip selection judging circuit 17 selectively. The column selection circuits 13 and 14 include a column address decoder 13 and a column selection gate 14 activated by a decode signal from the column address decoder 13. The column selection gate 14 is connected to each bit line (not shown) of the memory array 11, and the output of the row address decoder constituting the row selection circuit 12 is connected to each word line (not shown) of the memory array 11. is doing. Further, on the memory array chip 10, a row selection circuit 12, column selection circuits 13 and 14, and a first voltage supply line S 11 for supplying a voltage source necessary for causing the memory array 11 to perform a predetermined memory operation; The first address signal line S12 for supplying an internal address signal to the row selection circuit 12, the column selection circuits 13, 14 and the chip selection determination circuit 17, and the write data signal corresponding to the write data are supplied to the column selection circuits 13, 14 A first write data signal line S13 for supplying the read data signal, a first read data signal line S14 for outputting a read data signal corresponding to the storage information of the selected memory cell from the read circuit 15, and a data comparator 16 A first comparison result signal line S15 for outputting the comparison result to the control chip side is provided, and the first comparison result signal line S15 is provided above the corresponding first through electrode T1. They are side and electrically connected.

  The internal address signal supplied via the first address signal line S12 includes a lower internal address signal for selecting a memory cell to be subjected to a predetermined memory operation from the memory array 11, and selection of the memory array chip 10. -It is divided into upper internal address signals for determining non-selection. The first address signal line S12 for the upper internal address signal corresponds to a surplus address signal line and is connected to the chip selection determination circuit 17, and the lower internal address signal is sent to the row address decoder 12 and the column address decoder 13. Connecting. Each internal address signal may be an address decode signal that is partially decoded in advance on the control chip 20 side.

  The chip selection determination circuit 17 includes, for example, a nonvolatile register having the same number of bits as the number of surplus address signal lines. Each bit of the non-volatile register is configured so that, for example, “1” or “0” can be set depending on the threshold voltage difference between a pair of flash memory cells, and each signal level of the surplus address signal line and the corresponding register By configuring the coincidence or mismatch logic of the set bit values, the chip selection determination circuit 17 determines that the memory array chip 10 of the chip selection determination circuit 17 is selected when all the bits of the register match or does not match. Determination is made and an activation signal S16 for activating another circuit on the memory array chip 10 is output.

  Note that the chip selection determination circuit 17 is replaced with a configuration including a nonvolatile register, for example, by communicating between the chip selection determination circuits 17 of the upper and lower memory array chips 10 at the time of startup, so that the lowest or highest The number of layers from the memory array chip 10 is automatically determined, and each bit of the volatile register having the same number of bits as the number of surplus address signal lines is set based on the position information It does not matter.

  As shown in FIG. 1, the control chip 20 selects a predetermined memory operation including a read operation and a write operation with respect to the memory array chip 10 based on an external input, and performs a predetermined operation procedure according to the selected memory operation. In accordance with the control circuit 25 to 28 for controlling the circuit operation in the device 1 according to the present invention, and the control from the write state machine (WSM) 27 in the control circuit, it is necessary for a predetermined memory operation for the memory array 11. A high voltage supply circuit 29 (corresponding to a voltage supply circuit) that generates a high voltage and supplies it to the row selection circuit 12, the column selection circuits 13, 14 and the like, an address input that receives an address input from the outside and generates an internal address signal A buffer 21 is a data input buffer that accepts input data from outside and generates an internal input data signal. A data input for outputting, as an external output, a data input from the memory array 11 or an internal status signal output from the WSM 27, etc. A buffer 24 (corresponding to an output interface circuit) is provided. The address input buffer 21, the data input buffer 23, and the control input buffer 22 correspond to input interface circuits that receive external inputs and generate internal signals to be supplied to the control circuits 26 to 28 and the memory array chip 10.

  The control circuits 25 to 28, in addition to the WSM 27 that controls memory operations such as a write operation and an erase operation for the memory array 11 according to a series of operation procedures, an address input buffer 21, a data input buffer 23, data Input / output control logic 25 for controlling activation / deactivation of the input / output interface such as the output buffer 24, etc., recognizes an external command input to the data input buffer 23 based on the internal control input signal, and outputs necessary control signals. A command user interface (CUI) 12 to be issued to the WSM 27, a data register 28 for temporarily storing write data input to the data input buffer 23, and the like are provided. Since the data register 28 is a circuit used for controlling the WSM 27, it is included in the control circuit, but may be handled as an independent circuit. Further, the high voltage supply circuit 29 may be a circuit that supplies a high voltage supplied from the outside to each part of the memory array chip 10 according to a memory operation without generating a high voltage in the control chip 20. I do not care.

  Further, on the control chip 20, a second voltage supply line S21 for supplying a voltage source output from the high voltage supply circuit 29 to the memory array chip 10 and an internal address signal output from the address input buffer 21 are provided. A second address signal line S22 for supplying to the memory array chip 10, a second write data signal line S23 for supplying the write data signal output from the data register 28 to the memory array chip 10, and the memory array chip 10 The second read data signal line S24 for supplying the read data signal received from the data input buffer 23 and the second comparison result signal for supplying the WSM 27 with the comparison result output from the data comparator 16 of the memory array chip 10. A line S25 is provided, and each of the corresponding second through electrodes T2 And it is electrically connected to the side.

  4 and 5 schematically show examples of the chip layout of the memory array chip 10 and the control chip 20, respectively. As shown in FIG. 4, the memory array 11 of the memory array chip 10 is divided into a plurality of blocks and is divided into two groups in the layout, and the center portion of the chip in which the first through electrode T1 is sandwiched between the two groups. Is arranged. As shown in FIG. 4, on the memory array chip 10, inputs for external connection pads, control circuits 25 to 28 provided in the control chip 20, address input buffer 21, data input buffer 23, control input buffer 22, and the like are input. No interface circuit or data output buffer 24 is provided. As shown in FIG. 5, when the control chip 20 is stacked on the memory array chip 10, the second through electrode T <b> 2 is disposed on the control chip 20 so as to overlap with the corresponding first through electrode T <b> 1. ing. In the present embodiment, the second through electrode T <b> 2 is also arranged at the approximate center on the control chip 20. Further, as shown in FIG. 5, the control chip 20 is provided with an external connection pad T3 on the periphery of the chip.

  As is clear from the above description, the device 1 of the present invention is electrically connected to the memory array chip 10 and the control chip 20 through the first through electrode T1 and the second through electrode T2 in one chip. Since the same circuit configuration as that of the conventional flash memory capable of operating the memory can be realized, the memory operation is the same as that of the conventional flash memory, and redundant description is omitted.

Second Embodiment
Next, a second embodiment of the device of the present invention will be described. In the first embodiment, the memory array chip 10 includes the memory array 11, the row selection circuit 12, the column selection circuits 13 and 14, the read circuit 15, the data comparator 16, and the chip selection determination circuit 17 as functional blocks. The control chip 25 includes a control circuit 25 to 28, a high voltage supply circuit 29, an input interface circuit such as an address input buffer 21, a data input buffer 23, and a control input buffer 22, and a data output buffer 24. Met. However, the inventive device 2 according to the second embodiment includes a memory array chip 10a shown in FIG. 6 instead of the memory array chip 10 of the first embodiment. As shown in FIG. 6, the memory array chip 10a controls a simplified memory operation for testing with a single memory array chip 10 smaller than the control circuits 25 to 28 included in the control chip 20, according to a predetermined operation procedure. The control chip 20 includes a simple control interface 31 for receiving a test input signal Stin required for testing a single memory array chip 10a smaller than the input interface circuit included in the control chip 20, and the control chip 20. A simple output interface circuit 33 for outputting a test output signal Stout necessary for a test in a small memory array chip 10a alone from the data output buffer 24, and a test input signal Stin and a test output signal Stout are exchanged with the outside. Equipped with external connection pad T4 Composed of Te. With such a configuration, it is possible to perform a simple test on the memory array chip 10a alone by simply exchanging a small number of test input signals Stin and test output signals Stout between the testers.

  In the second embodiment, the data comparator 16 is also used in the simple control circuit 31. Therefore, by providing the data comparator 16 on the memory array chip 10a side, the test of the memory array chip 10a alone and the control chip 20 are performed. Commonly used for both normal memory operations after coalescing.

  Since the basic parts of the control chip 20 and the memory array chip 10a are the same as those of the first embodiment, the overlapping description is omitted.

<Third Embodiment>
Next, a third embodiment of the device of the present invention will be described. In the first and second embodiments, the control chip 20 includes, as functional blocks, control interface circuits 25 to 28, a high voltage supply circuit 29, an input interface circuit such as an address input buffer 21, a data input buffer 23, and a control input buffer 22. And the memory array 11, the row selection circuit 12 and the column selection circuits 13 and 14, the read circuit 15, the data comparator 16, and the chip selection determination circuit 17. It was a configuration without. However, in the device 3 of the present invention according to the third embodiment, as shown in FIG. 7, the control chip 20a includes a memory array 11, a row selection circuit 12, column selection circuits 13 and 14, and a readout circuit included in the memory array chip 10. 15, a data comparator 16 and a chip selection determination circuit 17 are provided. That is, the control chip 20a in the third embodiment has a configuration in which the second through electrode T2 is provided in the conventional flash memory. In the third embodiment, since the chip size of the control chip 20a is larger than the memory array chip 10, as shown in FIG. 8, the control chip 20a and one or more memory array chips are arranged on the mounting substrate 4 in order from the bottom. 10 are stacked.

  Note that the basic part of the control chip 20a and the memory array chip 10 are the same as those in the first embodiment, and therefore, redundant description is omitted. In the third embodiment, it is also preferable to use the memory array chip 10 instead of the memory array chip 10a in the second embodiment.

  Next, another embodiment of the device of the present invention will be described.

  <1> In each of the above embodiments, the memory array chips 10 and 10a are assumed to be used by stacking the same chip including the memory array 11 having the same storage capacity and the chip selection determination circuit 17, but the memory array When the number of stacked chips 10 and 10a is plural, the memory array chips 10 and 10a do not necessarily have the same storage capacity. The memory array chips 10 and 10a may have the same storage capacity or differently designed chips. For example, each of the memory array chips 10 and 10a may not include the chip selection determination circuit 17 and the upper internal address signal to be selected may be fixed on the circuit in advance.

  <2> In each of the above embodiments, the data comparator 16 is provided on the memory array chip 10, 10a side. However, when the simple control circuit 31 is not provided in the memory array chip 10, the simple control circuit 31 in the second embodiment is provided. Is different from the data comparator used in the control circuits 25 to 28 on the control chip 20 side, or when the data comparator 16 does not need to be arranged close to the column selection gate 14. The comparator 16 may be provided on the control chip 20 side.

  <3> In the first embodiment, FIG. 4 and FIG. 5 schematically show examples of the chip layout of the memory array chip 10 and the control chip 20, respectively. The arrangement location of the electrode T1 and the second through electrode T2 is not limited to the center of the chip, and the arrangement location of the external connection pad T3 on the control chip 20 is not limited to the chip peripheral portion.

  The present invention can be used for a nonvolatile semiconductor memory device, and is particularly useful for a nonvolatile semiconductor memory device including one or a plurality of memory array chips and a plurality of control chips.

1 is a block diagram showing a schematic block configuration in a first embodiment of a nonvolatile semiconductor memory device according to the present invention. 1 is a cross-sectional view schematically showing a schematic cross-sectional structure of the nonvolatile semiconductor memory device according to the present invention shown in FIG. 1 mounted in a stacked package. 1 is a block diagram showing a signal connection relationship between chips in a configuration example of a nonvolatile semiconductor memory device according to the present invention. The figure which shows typically an example of the chip layout of the memory array chip | tip of the non-volatile semiconductor memory device which concerns on this invention The figure which shows typically an example of the chip layout of the control chip of the non-volatile semiconductor memory device which concerns on this invention The block diagram which shows the schematic block configuration in 2nd Embodiment of the non-volatile semiconductor memory device which concerns on this invention. The block diagram which shows the schematic block configuration in 3rd Embodiment of the non-volatile semiconductor memory device which concerns on this invention. Sectional drawing which shows typically the cross-sectional structure of the outline of the non-volatile semiconductor memory device based on this invention shown in FIG. 7 mounted in the stacked package Sectional drawing which shows typically the schematic cross-section of the flash memory mounted in the conventional stacked package of the wire bond system A block diagram showing a schematic block configuration of a general flash memory The figure which shows schematic layout arrangement | positioning on 1 chip | tip of each functional block of the flash memory shown in FIG. Block diagram showing the signal connection relationship between chips of a general flash memory mounted in a stacked package

Explanation of symbols

1-3: Device of the present invention 4: Mounting substrate 5: Bonding wire 6: Bare chip of flash memory 7: Spacer 8: Solder ball 10: Memory array chip 10a: Memory array chip 11: Memory array 12: Row selection circuit (row address) decoder)
13: Column selection circuit (column address decoder)
14: Column selection circuit (column selection gate)
15: Read circuit 16: Data comparator 17: Chip selection determination circuit 20: Control chip 20a: Control chip 21: Address input buffer (input interface circuit)
22: Control input buffer (input interface circuit)
23: Data input buffer (input interface circuit)
24: Data output buffer (output interface circuit)
25: Input / output control logic 26: Command user interface (CUI)
27: Light state machine (WSI)
28: Data register 29: High voltage supply circuit (voltage supply circuit)
31: Simple control circuit 32: Simple input interface circuit 33: Simple output interface circuit S1: Address signal line S2: Data signal line S3: Chip control signal line S31-S34: Chip control signal line S4: Write control signal line S5: Output Release signal line S6: Reset signal line S11: First voltage supply line S12: First address signal line S13: First write data signal line S14: First read data signal line S15: First comparison result signal line S16: Activation Signal S21: Second voltage supply line S22: Second address signal line S23: Second write data signal line S24: Second read data signal line S25: Second comparison result signal line Stin: Test input signal Stout: Test output signal T1 : First through electrode T2: Second through electrode T3: Control Tsu pad for external connection on the flop T4: external connection pads on the memory array chip T5: external connection terminal

Claims (10)

A non-volatile semiconductor storage device comprising one or a plurality of memory array chips and a control chip for controlling the memory array chip,
The memory array chip is at least
A memory array in which a plurality of nonvolatile memory cells are arranged in the row and column directions;
One or a plurality of memory cells to be subjected to a predetermined memory operation are individually selected from the memory array along a row direction and a column direction, and a voltage required for the predetermined memory operation with respect to the selected memory cell A row selection circuit and a column selection circuit for applying
A readout circuit connected to the column selection circuit and reading out storage information of the selected memory cell;
A first voltage supply line for supplying a voltage source necessary for causing the row selection circuit and the column selection circuit or the row selection circuit, the column selection circuit, and the memory array to perform a predetermined memory operation;
A first address signal line for supplying an internal address signal to the row selection circuit and the column selection circuit;
A first write data signal line for supplying a write data signal corresponding to the write data to the column selection circuit;
A first read data signal line for outputting a read data signal corresponding to the storage information of the selected memory cell from the read circuit;
A plurality of electrodes penetrating the memory array chip, each connected to the first voltage supply line, the first address signal line, the first write data signal line, and the first read data signal line; A first through electrode of
The control chip is at least
A control circuit that selects a memory operation including a read operation and a write operation with respect to the memory array chip based on an external input and controls the memory array chip according to a predetermined operation procedure according to the selected memory operation;
A voltage supply circuit for supplying a voltage source necessary for causing the memory array chip to perform a predetermined memory operation under the control of the control circuit;
An input interface circuit that receives the external input and generates an internal signal to be supplied to the control circuit and the memory array chip;
An output interface circuit for outputting the read data signal output from the memory array chip as an external output;
A second voltage supply line for supplying the voltage source output from the voltage supply circuit to the memory array chip;
A second address signal line for supplying the internal address signal of the internal signals output from the input interface circuit to the memory array chip;
A second write data signal line for supplying the write data signal output from the control circuit to the memory array chip;
A second read data signal line for supplying the read data signal received from the memory array chip to the output interface circuit or the control circuit;
A plurality of electrodes that pass through the control chip, each connected to the second voltage supply line, the second address signal line, the second write data signal line, and the second read data signal line; A second through electrode;
The first through electrode on the memory array chip and the second through electrode on the control chip are aligned with the corresponding through electrodes when the memory array chip and the control chip are stacked. Arranged,
The one or more memory array chips and the control chip are stacked, and the plurality of first through electrodes of each of the memory array chips and the corresponding through electrodes of the plurality of second through electrodes of the control chip are stacked in the stacking direction. A non-volatile semiconductor memory device characterized by being stacked and electrically connected to each other.   The nonvolatile semiconductor memory device according to claim 1, wherein the memory array chip does not include the input interface circuit and the output interface circuit included in the control chip. The number of the internal address signals received by the memory array chip via the first address signal line is used by the row selection circuit and the column selection circuit to select the memory cells of the memory array included in the memory array chip. More than the number of said internal address signals to
The memory array chip determines whether or not the memory array chip is selected based on a signal level of a surplus address signal line that is not used by the row selection circuit and the column selection circuit in the first address signal line. With a selection decision circuit,
The nonvolatile semiconductor memory device according to claim 1, wherein the chip selection determination circuit is configured to be able to set a signal level of the surplus address signal line used at the time of chip selection.   The chip selection determination circuit includes nonvolatile information storage means capable of storing information on the same principle as the memory cell, and sets the signal level of the surplus address signal line used at the time of chip selection in the information storage means. The nonvolatile semiconductor memory device according to claim 3. A plurality of the memory array chips are stacked, and the corresponding through electrodes of the plurality of first through electrodes of each of the memory array chips are stacked in the stacking direction and electrically connected to each other,
5. The nonvolatile memory according to claim 3, wherein in the chip selection determination circuit of each of the memory array chips, signal levels of the surplus address signal lines used at the time of chip selection are set to be different from each other. Semiconductor memory device.   A simple control circuit for controlling a memory operation, which is simplified for testing in a single memory array chip smaller than the control circuit included in the control chip, in accordance with a predetermined operation procedure; and A simple input interface circuit for accepting a test input signal required for a test in a small array chip than the input interface circuit provided, and a single array chip in a smaller scale than the output interface circuit provided in the control chip. 2. A simple output interface circuit for outputting a test output signal necessary for the test, and an external connection pad for transferring the test input signal and the test output signal to the outside. The nonvolatile semiconductor memory device according to any one of?   In the memory array chip, the memory array is divided into two groups, and the plurality of first through electrodes are arranged in a chip central region sandwiched between the two groups. The nonvolatile semiconductor memory device according to claim 1. The one or more memory array chips and the control chip are stacked on a mounting substrate,
An external connection pad provided on the control chip that transfers the external input and the external output to the outside is electrically connected to an external connection terminal provided on the mounting board. The nonvolatile semiconductor memory device according to claim 1.   9. The control chip according to claim 1, wherein the control chip includes the memory array, the row selection circuit, the column selection circuit, and the read circuit included in the memory array chip. The nonvolatile semiconductor memory device described.   9. The control chip according to claim 1, wherein the control chip does not include the memory array, the row selection circuit, the column selection circuit, and the read circuit included in the memory array chip. The nonvolatile semiconductor memory device described.

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