JP2008236301A - D/a converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a D/A converter that shortens a settling time. <P>SOLUTION: The D/A converter relating to one embodiment of this invention is provided with: a DAC for higher-order bits for outputting an analog signal corresponding to a higher-order bit of an inputted digital bit signal by dividing reference voltage for higher-order bits by a plurality of resistances for higher-order bits of a resistance value R<SB>M</SB>, wherein the plurality of resistances for higher-order bits are connected in series; a DAC for lower-order bits for outputting an analog signal corresponding to a lower-order bit of the inputted digital signal by dividing reference voltage for lower-order bits by a plurality of resistances for lower-order bits, wherein a plurality of resistances of a resistance value R<SB>S</SB>smaller than the resistance value R<SB>M</SB>of the resistances for higher-order bits are connected in series; and an adder for adding an analog signal outputted from the DAC for higher-order bits and an analog signal outputted from the DAC for lower-order bits. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a D / A converter (hereinafter referred to as DAC) for converting a digital signal into an analog signal, and more particularly to a resistor string type DAC (hereinafter referred to as RstDAC).

  The RstDAC has a configuration in which resistors having the same resistance value are connected in series, and outputs a voltage at a connection point of each resistor as an analog voltage with respect to a digital input signal. For this reason, when the number of bits of the digital input signal is increased, the number of resistors and switch circuits is drastically increased, which is a serious adverse effect on the recent demand for reducing the area of the semiconductor chip. Therefore, an upper / lower bit division type RstDAC has been considered as a method corresponding to the increase in the number of bits without increasing the number of resistors and switch circuits (Patent Document 1). The upper / lower bit division type RstDAC divides a digital input signal into upper bits and lower bits, adds the outputs of the upper bit DAC and the lower bit DAC, and outputs an analog voltage. In the conventional upper / lower bit division type RstDAC, the speed of the lower bit DAC is a problem, and it is required to meet the high-speed requirement of the RstDAC without increasing the power consumption.

  Here, the configuration of the conventional upper / lower bit division type RstDAC described in Patent Document 1 will be described with reference to FIG. FIG. 6 is a diagram showing a configuration of a conventional upper / lower bit division type RstDAC. As shown in FIG. 6, the conventional upper / lower bit division type RstDAC has an upper bit DAC 1, a lower bit DAC 2, and an analog adder 3. The conventional RstDAC divides input data (N bits) 15 into upper K bits of input data 16 and lower L bits of input data 17, and an analog output voltage 22 of the upper bit DAC1 and an analog output voltage of the lower bit DAC2. 23 is added by the analog adder 3.

The upper bit DAC 1 includes a voltage dividing circuit 8 including a plurality of reference resistors 12, a decoder 6, and a switch circuit 10. The upper bit DAC 1 D / A converts the upper K bits of the input data (N bits) 15. Voltage dividing circuit 8, a reference resistor 12 of resistance R _M is 2 ^K pieces resistor string connected in series. Voltage dividing circuit 8, a voltage value of the first reference power supply signal 18 _{V R1,} the voltage value of the second reference power supply signal 19 and _{V R2,} divide the voltage between the reference supply voltage _{V R1} and _{V R2} .

The lower bit DAC 2 includes a voltage dividing circuit 9 including a plurality of reference resistors 13, a decoder 7, and a switch circuit 11. The lower bit DAC 2 performs D / A conversion on the lower L bits of the input data (N bits) 15. The voltage dividing circuit 9 is a resistor string in which 2 ^L reference resistors 13 having a resistance value _RS are connected in series. The voltage dividing circuit 9 is connected in parallel to the lowest-order resistor of the voltage dividing circuit 8 of the upper bit DAC 1.

The voltage value of the analog output signal 22 of the upper bit DAC 1 is V _UP , the voltage value of the analog output signal 23 of the lower bit DAC 2 is V _DOWN , and the voltage value of the analog output signal 26 of RstDAC is V _OUT . High-order and low-order bits split RstDAC, by adding the analog output voltage _{V DOWN} of the analog output voltage _{V UP} and the lower bit DAC2 upper bits for DAC1 at the analog adder 3, the final RstDAC analog output voltage Outputs _VOUT . In the conventional example, by creating the resistance value R _M of the reference resistor 12 of the voltage dividing circuit 8 and the resistance value R _S of the reference resistor 13 of the voltage dividing circuit 9 as R _S >> R _M , the upper bit and the lower bit The conversion error at the switching point is reduced.

Next, the operation of the conventional RstDAC will be described. In the upper bit DAC 1, the digital input data 16 of upper K bits out of the N bits of input data 15 is input to the decoder 6. The switch circuit 10 is composed of a plurality of transmission switches composed of transistors. The plurality of transmission switches are respectively connected to connection points of the reference resistors 12 of the voltage dividing circuit 8. Based on the decoding result output signal 20 output from the decoder 6, any one transmission switch of the switch circuit 10 is turned on, and the analog output voltage _VUP is output.

In the lower bit DAC 2, digital input data 17 of lower L bits of the input data (N bits) 15 is input to the decoder 7. The switch circuit 11 is composed of a plurality of transmission switches composed of transistors. The plurality of transmission switches are respectively connected to the connection points of the reference resistors 13 of the voltage dividing circuit 9. Based on the decoding result output signal 21 output from the decoder 7, any one transmission switch of the switch circuit 11 of the voltage dividing circuit 9 is turned ON, and the analog output voltage _VDOWN is output. Finally, by adding the respective analog output voltages of the high-order bit for DAC1 and lower bit DAC2 in analog adder 3, the analog output voltage _{V OUT} of RstDAC is obtained.

Here, in order to consider the output resistance in the DAC for the upper and lower bits, an equivalent circuit relating to the resistance element in the circuit of the conventional example is shown in FIG. As shown in FIG. 7, in this example, the voltage dividing circuit 8 is divided by R _M1 and R _M2 , and the voltage dividing circuit 9 is divided by R _S1 and R _S2 . In this case, the output resistance of the upper bit DAC 1 is R _UP , and the output resistance of the lower bit DAC 2 is R _DOWN .

C _LOAD is a parasitic capacitance added to each output part of the higher-order and lower-order bit DACs, and is a total of wiring capacitance, transistor gate capacitance, source / drain capacitance, and the like. Originally, the capacitance value is different between the higher-bit DAC and the lower-bit DAC, but the same capacitance value is used for simplicity.

  Next, the operation of resistance voltage division in the example shown in FIG. 7 will be described. In the switch circuit 10 for the upper bit DAC 1 and the switch circuit 11 for the lower bit DAC 2, one of the transmission switches is turned on in accordance with the upper and lower digital input data 16 and 17, and the voltage dividing circuits 8 and 9 use resistors. Divided pressure. The DAC settling operation in this case will be described below.

の関係が成り立つ。分圧回路８の最下位の基準抵抗Ｒ_Ｍと、分圧回路９を構成する抵抗値Ｒ_Ｓの基準抵抗を２^Ｌ個直列接続した抵抗ストリングとの並列接続回路の合成抵抗をＲ_Ｘ１とした場合、

と表せる。式（２）をＲ_Ｘ１について展開すると、

となる。Ｒ_Ｓ＞＞Ｒ_Ｍであるので、合成抵抗Ｒ_Ｘ１は分圧回路８の基準抵抗の抵抗値Ｒ_Ｍとほぼ等しくなる。上位ビット用ＤＡＣ１の出力抵抗Ｒ_ＵＰが最大となるＲ_Ｍ１とＲ_Ｍ２の条件は、

となり、式（１）と（４）から、Ｒ_ＵＰについて展開すると、式（５）となる。

The DAC has the longest settling time when the output resistances of the upper and lower bit DACs 1 and 2 are the maximum. In this case, the output resistance R _UP of the upper bit DAC 1 and the output resistance of the lower bit DAC 2 R _DOWN will be described. Since the output resistance R _UP of the upper bit DAC 1 is divided by R _M1 and R _{M2 in the} voltage dividing circuit 8,

The relationship holds. A reference resistance R _M of the bottom of the voltage divider circuit 8, the combined resistance of the parallel connection circuit of the resistor string a reference resistor connected 2 ^L number series resistance R _S constituting the voltage dividing circuit 9 and the R _X1 If

It can be expressed. Expanding equation (2) for R _X1 ,

It becomes. Since R _S >> R _M , the combined resistance R _X1 is almost equal to the resistance value R _M of the reference resistance of the voltage dividing circuit 8. The conditions of R _M1 and R _M2 that maximize the output resistance R _UP of the upper bit DAC 1 are:

From Equations (1) and (4), when expanding for R _UP , Equation (5) is obtained.

の関係が成り立つ。合成抵抗Ｒ_Ｘ２は、

と表せる。式（７）をＲ_Ｘ２について展開すると、

となる。下位ビット用ＤＡＣ２の出力抵抗Ｒ_ＤＯＷＮが最大となるＲ_Ｓ１とＲ_Ｓ２の条件は、

であるから、式（６）、（８）、（９）から、Ｒ_ＤＯＷＮについて展開すると、式（１０）となる。

On the other hand, the voltage dividing circuit 9 of the lower-bit DAC ₂ is divided into R _S1 and R _S2 . A reference resistance R _M of the bottom of the voltage divider circuit 8, the combined resistance of the parallel connection circuit of the other 2 ^K -1 single resistor value resistor string connected to R _M in series When R _X2,

The relationship holds. The combined resistance R _X2 is

It can be expressed. Expanding equation (7) for R _X2 ,

It becomes. The conditions of R _S1 and R _S2 that maximize the output resistance R _{DOWN of the} DAC 2 for the lower bit are:

_Therefore , when R _DOWN is expanded from Equations (6), (8), and (9), Equation (10) is obtained.

入力電圧Ｖ_ＩＮと出力電圧Ｖ_ＯＵＴの差分をセトリング誤差電圧Ｖ_ＥＲＲとすると、式（１１）の第２項が、セトリング誤差電圧Ｖ_ＥＲＲとなるため、これを時間ｔで展開すると、式（１２）となる。

Next, settling time in each of the upper bit DAC1 and the lower bit DAC2 will be described. In a transient response characteristic in a general RC circuit, the relationship of Expression (11) is established between the input voltage V _IN and the output voltage V _OUT .

If the difference between the input voltage V _IN and the output voltage V _OUT is settling error voltage V _ERR , the second term of the equation (11) becomes the settling error voltage V _ERR. )

  In a circuit configuration in which N-bit input data is divided into upper K bits and lower L bits, the conversion accuracy of the upper bit DAC 1 requires N bit accuracy, but the lower bit DAC 2 conversion accuracy is L bit accuracy. The time for convergence to the allowable error voltage, that is, the settling time is different between the upper and lower levels.

_Assuming that the settling error voltages in the upper bit DAC1 and the lower bit DAC2 are V _{ERR_UP} and V _{ERR_DOWN} , when the settling error error in LSB (Least Significant Bit) notation is ERR, Equation (13) is established.

となる。 When the settling times of the upper bit DAC 1 and the lower bit DAC 2 are t _UP and t _DOWN , respectively, the ON resistances of the transistors in the switch circuits 10 and 11 are ignored for the sake of simplicity. 13)

It becomes.

In the conventional example, the resistance value R _S of the reference resistor of the voltage dividing circuit 9 is compared with the resistance value R _M of the reference resistor of the voltage dividing circuit 8 in order to reduce the conversion error at the switching point between the upper bit and the lower bit. It is created as extremely large, that is, R _S >> R _M. Conversion error in the output level of the lower bit DAC2 includes a reference resistance R _M of the bottom of the voltage dividing circuit 8, a resistor string of the reference resistance of the resistance value R _S 2 to ^{the L} series connection constituting a voltage divider circuit 9 When the combined resistance of the parallel connection circuit is R _X , it can be expressed by Expression (15).

従って、誤差の値は小さくなっているが、誤差を完全に無くすことまではできない。
特開平４−９４２２０号公報 For example, considering a 10-bit RstDAC in which the upper and lower bits are divided into 5 bits, and R _M = 20Ω and R _S = 400Ω, the conversion error at the output level of the lower-bit DAC 2 is the synthesis of Equation (15). Since the resistance _RX is expressed by the formula (2), it is as follows.

Therefore, although the error value is small, the error cannot be completely eliminated.
JP-A-4-94220

As can be seen from equation (14), the settling time in the upper and lower bit DACs depends on the respective output resistances. Further, as can be seen from the equations (5) and (10), the output resistance depends on the reference resistances R _M and R _S of the respective voltage dividing circuits. In the prior art, although the conversion error in the switching point of the upper and lower bits is reduced, creating extremely large resistance value than the reference resistance R _S of the voltage divider circuit 9 to the reference resistance R _M of the voltage dividing circuit 8 For this reason, the output resistance of the lower-bit DAC 2 is large, and the settling time of the lower-bit DAC 2 is increased, so that the settling time of the entire RstDAC is increased.

D / A converter according to one embodiment of the present invention, a plurality of a high-order bit resistance of the resistance value R _M are connected in series, by a corresponding plurality of upper bits resistance, by applying a reference voltage for upper bits minute, upper bits for DAC that outputs an analog signal corresponding to the upper bits of the input digital signal, connected to the plurality of lower bit resistance in series of the resistance value for the upper bit resistance R _M less resistance R _S than The lower-bit reference voltage is divided by the plurality of lower-bit resistors, and the lower-bit DAC that outputs an analog signal corresponding to the lower-order bits of the input digital signal is output from the upper-bit DAC. And an adder for adding the analog signal output from the lower bit DAC. As a result, by reducing the resistance value _RS of the reference resistance of the lower-bit voltage dividing circuit 9, the output resistance R _DOWN of the lower-bit DAC 2 in Expression (10) can be reduced, so that Expression (14) As can be seen, the settling time of the lower bit DAC 2 can be shortened.

  ADVANTAGE OF THE INVENTION According to this invention, the D / A converter which shortened settling time can be provided.

Embodiment 1 FIG.
The configuration of the D / A converter (DAC) according to Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a diagram illustrating a configuration of a DAC according to the present embodiment. The DAC according to the present invention divides input data into upper bits and lower bits, and adds an output voltage obtained by D / A conversion of the upper bits and an output voltage obtained by D / A conversion of the lower bits. This is an upper / lower divided resistor string D / A converter (RstDAC) that performs D / A conversion of data.

  As shown in FIG. 1, the DAC according to the present embodiment includes an upper bit DAC 1, a lower bit DAC 2, and an analog adder 3. The DAC according to the present embodiment divides input data (N bits) 15 into upper K-bit input data 16 and lower L-bit input data 17, and the analog output voltage 22 of the upper-bit DAC 1 and the lower-bit DAC 2. The analog output voltage 23 is added by the analog adder 3.

The upper bit DAC 1 includes a voltage dividing circuit 8 including a plurality of reference resistors 12, a decoder 6, and a switch circuit 10. The upper bit DAC 1 D / A converts the upper K bits of the input data (N bits) 15. Voltage divider circuit 8 is a reference resistor 12 of resistance R _M 2 ^K -1 or the resistor 14 of the resistance value n × R _M a resistor string connected in series. Here, n is an integer greater than 1. The resistor 14 is the lowest resistance of the voltage dividing circuit 8. Voltage dividing circuit 8, a voltage value of the first reference power supply signal 18 _{V R1,} the voltage value of the second reference power supply signal 19 and _{V R2,} divide the voltage between the reference supply voltage _{V R1} and _{V R2} .

The lower bit DAC 2 includes a voltage dividing circuit 9 including a plurality of reference resistors 13, a decoder 7, and a switch circuit 11. The lower bit DAC 2 performs D / A conversion on the lower L bits of the input data (N bits) 15. The voltage dividing circuit 9 is a resistor string in which 2 ^L reference resistors 13 having a resistance value _RS are connected in series. Dividing circuit 9 is connected in parallel to the lowest resistance value n × resistance R _M 14 of the voltage divider circuit 8 of the upper bits for DAC1.

の関係となるように作成する。 In the present invention, the least significant n × R _M of the resistor 14 of the voltage divider circuit 8, the synthesis of the parallel connection circuit of the reference resistor and 2 ^L number series connected resistor string in the resistance R _S of the voltage dividing circuit 9 resistance is created to be equal to the resistance value R _M of the reference resistor of the voltage divider circuit 8. That is, if the number of bits of the lower bit DAC 2 is L and n is a number greater than 1,

Create a relationship.

となり、本発明における式（１７）に示す回路構成とすることで、分圧回路８、９の基準抵抗の関係はＲ_Ｓ＜Ｒ_Ｍとすることができる。従って、従来では、基準抵抗１３の抵抗値Ｒ_Ｓが基準抵抗１２の抵抗値Ｒ_Ｍよりも大きい（Ｒ_Ｓ＞＞Ｒ_Ｍ）のに対し、本発明では、基準抵抗１２の抵抗値Ｒ_Ｍが基準抵抗１３の抵抗値Ｒ_Ｓよりも大きい（Ｒ_Ｍ＞Ｒ_Ｓ）。 When Expression (17) is expanded with respect to the reference resistance R _S of the voltage dividing circuit 9,

Thus, by adopting the circuit configuration shown in Expression (17) in the present invention, the relationship between the reference resistances of the voltage dividing circuits 8 and 9 can be R _S <R _M. Therefore, conventionally, the resistance value R _S of the reference resistor 13 is larger than the resistance value R _M of the reference resistor 12 (R _S >> R _M ), whereas in the present invention, the resistance value R _M of the reference resistor 12 is It is larger than the resistance value R _S of the reference resistor 13 (R _M > R _S ).

Here, the operation of the DAC according to the first embodiment will be described. In the upper bit DAC 1, the digital input data 16 of upper K bits out of the N bits of input data 15 is input to the decoder 6. The switch circuit 10 is composed of a plurality of transmission switches composed of transistors. The plurality of transmission switches are respectively connected to connection points of the reference resistors 12 of the voltage dividing circuit 8. Based on the decoding result output signal 20 output from the decoder 6, any one transmission switch of the switch circuit 10 is turned on, and the analog output voltage _VUP is output.

In the lower-bit DAC 2, among the N-bit input data 15, the lower L-bit digital input data 17 is input to the decoder 7. The switch circuit 11 is composed of a plurality of transmission switches composed of transistors. The plurality of transmission switches are respectively connected to the connection points of the reference resistors 13 of the voltage dividing circuit 9. Based on the decoding result output signal 21 output from the decoder 7, any one transmission switch of the switch circuit 11 of the voltage dividing circuit 9 is turned ON, and the analog output voltage _VDOWN is output. Finally, by adding the respective analog output voltages of the high-order bit for DAC1 and lower bit DAC2 in analog adder 3, the analog output voltage _{V OUT} of RstDAC is obtained.

Next, consider the output resistance R _{UP in the} upper bit DAC 1 and the output resistance R _DOWN in the lower bit DAC 2. When the switch is selected in the switch circuit 10 of the higher-bit DAC 1 and the switch circuit 11 of the lower-bit DAC 2 in the same manner as the resistance voltage division shown in FIG. 7, the output resistance R _UP and lower-order of the higher-bit DAC 1 The output resistance R _DOWN of the bit DAC 2 is obtained as follows.

Since the voltage dividing circuit 8 is divided into R _M1 and R _M2 , the relationship of Expression (1) is established for the output resistance R _UP of the upper bit DAC 1.

上位ビット用ＤＡＣ１の出力抵抗Ｒ_ＵＰは、従来例と同一の式（５）で表せる。

In the present embodiment, the resistance of the least significant n × R _M of the voltage dividing circuit 8, combined resistance of the parallel connection circuit of the reference resistor and 2 ^L number series connected resistor string in the resistance R _S of the voltage dividing circuit 9 and it is equal to the resistance value R _M of the reference resistor of the voltage divider circuit 8. For this reason, the condition that the output resistance R _UP of the upper bit DAC 1 is maximized is the same as the expression (4).

The output resistance R _UP of the upper bit DAC 1 can be expressed by the same equation (5) as in the conventional example.

の関係が成り立つ。合成抵抗Ｒ_Ｙ１は、

と表せる。式（２０）をＲ_Ｙ１について展開すると、

となる。下位ビット用ＤＡＣ２の出力抵抗Ｒ_ＤＯＷＮが最大となるＲ_Ｓ１とＲ_Ｓ２の条件は、式（９）と同様であるから、

である。従って、式（１９）と（２１）と（９）から、Ｒ_ＤＯＷＮについて展開すると、式（２２）となる。

On the other hand, the voltage dividing circuit 9 of the lower-bit DAC ₂ is divided into R _S1 and R _S2 . The resistance of the lowest n × R _M of the voltage divider circuit 8, the combined resistance of the parallel connection circuit of the other 2 ^K -1 single resistor value resistor string connected to R _M in series When R _Y1,

The relationship holds. The combined resistance R _Y1 is

It can be expressed. Expanding equation (20) for R _Y1 ,

It becomes. Since the conditions of R _S1 and R _S2 at which the output resistance R _DOWN of the lower-bit DAC 2 is maximized are the same as those in Expression (9),

It is. Therefore, when R _DOWN is expanded from Equations (19), (21), and (9), Equation (22) is obtained.

なお、説明のため、上位ビット用ＤＡＣと下位ビット用ＤＡＣとで容量値は異なるが、簡単の為に同じ容量値としている。 _Assuming that C _LOAD is the parasitic capacitance added to the output units of the upper and lower bit DACs, and that the settling times of the upper and lower bit DACs are t _UP and t _DOWN , respectively, the settling error error in LSB notation is ERR. In this case, it can be expressed by the same formula as formula (14).

For the sake of explanation, the capacitance value differs between the higher-bit DAC and the lower-bit DAC, but the same capacitance value is used for simplicity.

FIG. 2 shows output waveforms of the analog output signal 22 of the upper bit DAC 1, the analog output signal 23 of the lower bit DAC 2, and the analog output signal 26 of the entire DAC in this embodiment. FIG. 2 shows an output waveform after D / A conversion when N-bit digital input data 15 is input at time t = 0. In FIG. 2, the horizontal axis represents time t, and the vertical axis represents voltage V. The ideal analog input voltages of the N-bit digital input data 15, the upper K-bit digital input data 16, and the lower L-bit digital input data 17 are V _IN , V _{IN_UP} , and V _{IN_DOWN} , respectively. A value obtained by adding the analog output voltage V _UP of the upper bit DAC 1 and the analog output voltage V _DOWN of the lower bit DAC 2 becomes the analog output voltage V _OUT of the RstDAC with respect to the N-bit digital input voltage _VIN .

In the conventional example, the settling time t _{DAC of} RstDAC is determined by the settling time t _DOWN of the lower bit _{DAC 2} . However, in the present embodiment, the resistance value R _S of the reference resistor 13 is smaller than the resistance value R _M of the reference resistor 12 (R _M > R _S ) as compared with the conventional example. Therefore, the output resistance R _DOWN of the lower bit DAC 2 can be reduced, and the settling time t _DOWN of the lower bit DAC 2 can be shortened. As a result, as shown in FIG. 2, the settling time t _{DAC of the} entire _DAC is determined by the settling time t _UP of the upper bit _{DAC 1} . For this reason, the settling time of the entire DAC can be shortened as compared with the conventional example. It should be noted that although the delay time of the operational amplifier circuit in the analog adder 3 is originally added to the settling time t DAC of the entire _DAC, it is considered to be sufficiently shorter than the settling time in the resistor string portion. I can ignore it.

Further, the power consumption _{P Rst} consumed by voltage divider RstDAC includes a difference voltage _{V Rst} between the first reference power supply voltage _{V R1} of the upper bit dividing circuit 8 and the second reference power supply voltage _{V R2} , a synthetic resistance 2 ^K × R _M of the reference resistance of the resistance value R _M constituting the upper bit dividing circuit 8 2 ^K number serially connected resistor string, represented by the formula (23).

Power P _Rst is determined by the combined resistance of the reference resistor R _M upper bits dividing circuit 8, power consumption by reducing the resistance R _S of the reference resistance of the lower bit dividing circuit 9 is not changed Therefore, in the present invention, it is possible to increase the speed of the DAC without increasing the power consumption.

As shown in equation (17), in this embodiment, the resistance of the least significant n × R _M of the voltage dividing circuit 8, and the reference resistance of the resistance value R _S of the voltage dividing circuit 9 connected 2 ^L number series the combined resistance of the parallel connection circuit of the resistor string, is set to be equal to the resistance value R _M of the lowest of the reference resistor of the voltage divider circuit 8. Therefore, as can be seen from the equation (15), a conversion error at the switching point between the upper bit and the lower bit does not theoretically occur, and the correction resistor _RH for correcting the conversion error is not required.

As described above, in the present embodiment, a circuit configuration in which a conversion error at the switching point between the upper bit and the lower bit does not theoretically occur. However, when the relative accuracy in the layout pattern between the reference resistors R _M and R _S is poor, there is a concern that a conversion error may occur.

Therefore, in this embodiment, the reference resistance 12, 13 of the voltage divider circuit 8 and 9 are each the same reference resistor R _P to the original, it is created a plurality of reference resistor R _P in series connection or parallel connection . Thereby, the layout can be performed while maintaining the relative accuracy between the reference resistances R _M and R _S. Furthermore, the reference resistor R _M, the R _S, by creating to align the number of parallel connections connected in series the number of the reference resistor R _P, it is possible to suppress an increase in layout area due to an increase in the total number of the reference resistor R _P .

となる。このため、従来例とは異なり、Ｒ_Ｓ＜Ｒ_Ｍとなる。従って、上位ビット用ＤＡＣ１、下位ビット用ＤＡＣ２のセトリング時間は、式（１４）を解いて、ｔ_ＵＰ≒１４.７７ｎｓｅｃ、ｔ_ＤＯＷＮ≒１.１２ｎｓｅｃとなる。 For example, a 10-bit RstDAC obtained by dividing 10-bit input data into upper 5 bits and lower 5 bits, R _M = 20Ω, C _LOAD = 10 pF, n = 2, and settling allowable error ERR is set to 0.1 LSB. In this case, from equation (18), the resistance value R _S of the reference resistance of the voltage dividing circuit 9 for lower bits is

It becomes. Therefore, unlike the conventional _example, the _R S <R _M. Accordingly, the settling times of the upper bit DAC 1 and the lower bit DAC 2 are t _UP ≈14.77 nsec and t _DOWN ≈1.12 nsec by solving Equation (14).

On the other hand, in the conventional example, when R _M = 20Ω and R _S = 400Ω, t _UP ≈14.77 nsec and t _DOWN ≈184.87 nsec, and the settling time of the lower bit DAC 2 is equal to that of the upper bit DAC 1. It was 10 times longer. Therefore, according to the present invention, the settling time of the lower bit DAC 2 can be greatly reduced.

FIG. 3 is a diagram illustrating an example of the configuration of the reference resistors 12 and 13 in the above numerical example. As shown in FIG. 3, the reference resistor 12 of the voltage divider circuit 8 is composed of four reference resistor R _P of resistance 5Ω connected in series. Therefore, the reference resistance R _M of the upper bit voltage dividing circuit 8 is R _M = R _P × 4 = 20Ω. The reference resistor 13 of the voltage divider circuit 9 is composed of four reference resistor R _P of resistance 5Ω connected in parallel. Therefore, the reference resistance R _S of the voltage dividing circuit 9 for lower bits is R _S = R _P ÷ 4 = 1.25Ω. In this way, the reference resistors 12 and 13 can be created with the same resistance value and the same number of resistors, respectively, so that layout is performed while maintaining the relative accuracy between the reference resistors R _M and R _S. be able to.

Incidentally, the total number of the reference resistance R _P in the lower bit dividing circuit 9, four × 2 ⁵ pieces = 128 pieces, the total number of the reference resistance R _P in the upper bit dividing circuit 8, the least significant resistance since the 2 × R _M, 4 pieces × 2 ⁵ pieces + 4 pieces = 132 pieces and it can be laid by suppressing an increase in resistance number.

Unlike configurations of the reference resistor 12, 13 of the present invention, for example, if you create a reference resistor 13 of resistance _{R S} of the reference resistor _{R P} to lower bit dividing circuit 9, _i.e., the R P = _{R S} If you, the total number of the reference resistance R _P of the lower bit dividing circuit 9, it is possible to reduce the total number of reference resistor 13 of resistance R _S equals 2 ⁵ = 32 and. However, the total number of the reference resistance _{R P} of the upper bit dividing circuit 8, when created with reference resistor _R P of the same resistance value (= _{R S)} is 16 × ^{2 5} pieces + 16 = 528 and This increases the resistance layout area. Further, if the resistance value of the reference resistor 12 of the upper bit voltage dividing circuit 8 is made small, an increase in the resistance layout area can be suppressed, but in this case, the relative accuracy between the reference resistors 12 and 13 is maintained. It becomes difficult.

Embodiment 2. FIG.
A DAC according to the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a diagram illustrating the configuration of the DAC according to the second embodiment. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, differences between the present embodiment and the first embodiment will be described.

  In the present embodiment, it is possible to arbitrarily select a location for taking out the reference voltage of the lower bit voltage dividing circuit 9 from locations other than the lowest order of the upper bit voltage dividing circuit 8. Therefore, the reference voltage of the lower-bit voltage dividing circuit 9 can be extracted even from the center portion of the resistor string, which is assumed to have a relatively high relative accuracy of the reference resistor when the layout is created.

An analog subtractor 4 is provided on the output side of the switch circuit 11. The analog subtracter 4 receives the analog output signal 24 from the lower bit DAC 2 and the reference voltage signal extracted from the upper bit voltage dividing circuit 8. The voltage value of the analog output signal 24 of the lower bit DAC2 _{V DOWN} 'and, when the reference voltage value taken out from the upper bit dividing circuit 8 and _{V REF,} the analog subtractor _{4, V DOWN'} to _{V REF} from The subtracted analog output signal 23 is output to the analog adder 3.

Next, the operation of the DAC according to this embodiment will be described. Here, differences from the first embodiment will be described below. In the lower bit DAC 2, digital input data 17 of lower L bits of the input data (N bits) 15 is input to the decoder 7. One transmission switch of the switch circuit 11 connected to the reference voltage of the voltage dividing circuit 9 is turned on by the decoding result output signal 21 of the decoder 7. As a result, an analog output voltage 24 obtained by adding the reference voltage _VREF at the location where the upper bit voltage dividing circuit 8 is taken out is obtained. Then, an analog output voltage V _DOWN obtained by subtracting the reference voltage V _REF from the analog output voltage 24 (V _DOWN ') by the analog subtractor 4 is input to the analog adder 3. Thereafter, the analog adder 3 adds the voltage value V _DOWN of the analog output signal 23 input from the analog subtractor 4 and the voltage value V _UP of the analog output signal 22 of the higher-bit DAC 1 to obtain a final value. and it outputs an analog output voltage _{V OUT} of RstDAC.

  In the present embodiment, the output resistance and settling time of the upper bit DAC 1 and the lower bit DAC 2 can be expressed by the same equations as in the first embodiment. However, although the delay time of the operational amplifier circuit in the analog subtractor 4 is originally added to the settling time of the lower bit DAC 2, it is sufficient compared to the settling time in the resistor string portion of the lower bit DAC 2. Since it can be considered small, it is ignored. Therefore, also in the present embodiment, as in the first embodiment, the settling time can be shortened without increasing the power consumption, and the occurrence of a conversion error can be prevented.

Embodiment 3 FIG.
A DAC according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 5 is a diagram showing the configuration of the DAC according to the present embodiment. In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, differences between the present embodiment and the first embodiment will be described.

の関係になるように、分圧回路８、９の基準抵抗が作成される。式（２４）を、分圧回路９の基準抵抗Ｒ_Ｓについて展開すると、

となる。このため、本実施の形態における分圧回路９の基準抵抗Ｒ_Ｓの抵抗値は、実施の形態１（式（１８））の分圧回路９の基準抵抗Ｒ_Ｓの抵抗値のｎ倍となる。 In this embodiment, the resistor 14 of the resistance value n × R _M is n pieces provided from the lowest of the voltage dividing circuit 8. The combined resistance of the parallel connection circuit of the n resistors 14 and the resistor string in which 2 ^L reference resistors 13 having the resistance value R _S of the voltage dividing circuit 9 are connected in series is the resistance of the reference resistor 12 of the voltage dividing circuit 8. as equal to n times the resistance value _{R M,} the reference resistor 12, 13 of the voltage dividing circuit 8, 9 has been created. Therefore, if the number of bits of the lower bit DAC2 is L and n is an integer of 2 or more,

The reference resistances of the voltage dividing circuits 8 and 9 are created so that When Expression (24) is expanded for the reference resistance R _S of the voltage dividing circuit 9,

It becomes. Therefore, the resistance value of the reference resistor R _S of the voltage dividing circuit 9 in the present embodiment is n times the resistance value of the reference resistor R _S of the voltage dividing circuit 9 of the first embodiment (Formula (18)). .

In the first embodiment, although the aim of the reference resistor R speed by a resistance value to reduce the _S, the resistance of the reference resistor R _S in accordance with the number of bits increases becomes smaller and the layout pattern and manufacturing of There are adverse effects such as the limit of the minimum resistance value and the layout pattern becoming large in order to avoid this, and it may be difficult to lay out the reference resistor accurately. Therefore, as in the present embodiment, the resistance value R _S of the reference resistor 13 of the voltage dividing circuit 9 is set so that the settling time t _DOWN in the lower bit DAC 2 is smaller than the settling time t _UP of the upper bit DAC 1. Sometimes it is better to make it larger.

In the present embodiment, the 1 / n circuit 5 is provided on the output side of the switch circuit 11. The 1 / n circuit 5 multiplies the analog output signal 25 of the input lower bit DAC 2 by 1 / n. Therefore, if the voltage value of the analog output signal 25 of the lower bit DAC 2 in the third embodiment is V _DOWN ″, the 1 / n circuit 5 sets the analog output voltage V _DOWN ″ of the lower bit DAC 2 to 1 / The analog output signal 23 multiplied by n is input to the analog adder 3. The analog adder 3 adds the voltage value V _DOWN of the analog output signal 23 input from the 1 / n circuit 5 and the voltage value V _UP of the analog output signal 22 of the upper bit DAC 1 to obtain a final RstDAC. The analog output voltage V _OUT is output.

Next, the operation of the DAC according to this embodiment will be described. The output resistances of the higher-bit DAC 1 and the lower-bit DAC 2 in the third embodiment will be described below in the same case as the resistance voltage division example shown in FIG. As described above, in the present embodiment, the n n × R _M resistors of the voltage dividing circuit 8 and the resistor string in which 2 ^L reference resistors of the resistance value R _S of the voltage dividing circuit 9 are connected in series are arranged in parallel. the combined resistance of the connecting circuit, and equal to n times the resistance value R _M of the reference resistor of the voltage divider circuit 8. Therefore, the output resistance R _UP of the upper bit DAC 1 can be expressed by the same equation (5) as in the conventional example and the first embodiment.

の関係が成り立つ。合成抵抗Ｒ_Ｚ１は、

と表せる。式（２７）をＲ_Ｚ１について展開すると、

となり、下位ビット用ＤＡＣ２の出力抵抗Ｒ_ＤＯＷＮが最大となるＲ_Ｓ１とＲ_Ｓ２の条件は式（９）と同様であるから、

である。従って、式（２６）と（２８）と（９）から、Ｒ_ＤＯＷＮについて展開すると、式（２９）となる。

On the other hand, the voltage dividing circuit 9 of the lower-bit DAC ₂ is divided into R _S1 and R _S2 . _Assuming that the combined resistance of the parallel connection circuit of n n × R _M resistors of the voltage dividing circuit 8 and the other 2 ^K− n resistance values R _M connected in series is R _Z1 , The output resistance R _DOWN of the bit DAC 2 is

The relationship holds. The combined resistance R _Z1 is

It can be expressed. Expanding equation (27) for R _Z1 ,

Since the conditions of R _S1 and R _S2 that maximize the output resistance R _DOWN of the lower bit DAC ₂ are the same as those in Expression (9),

It is. Therefore, when R _DOWN is expanded from Expressions (26), (28), and (9), Expression (29) is obtained.

In the third embodiment, the combined resistance of the parallel connection circuit of the n ² × R _M resistor of the voltage dividing circuit 8 and the resistor string of the voltage dividing circuit 9 is the resistance value R _M of the reference resistor of the voltage dividing circuit 8. Since the voltage is n times, a reference voltage n times the minimum resolution voltage of the voltage dividing circuit 8 is divided by the voltage dividing circuit 9. Therefore, the analog output voltage V _DOWN ″ of the lower bit _{DAC 2} is n times the ideal analog input voltage V _{IN_DOWN} of the lower L bits of the digital input data. multiplied analog output voltage _{V DOWN} is input to analog adder 3, the analog output voltage _{V OUT} of RstDAC is obtained.

  The settling time of the upper and lower bit DACs can be expressed by the same equation as in the first embodiment. However, although the delay time of the 1 / n circuit 5 is originally added to the settling time of the lower bit DAC 2, it is considered to be sufficiently shorter than the settling time in the resistor string portion of the lower bit DAC 2. I can ignore it because I can. Therefore, the settling time can be shortened compared to the conventional case.

となる。このため、実施の形態１と比較すると、下位ビット用分圧回路９の基準抵抗１３の抵抗値は、２倍となっている。上位、下位ビット用ＤＡＣのセトリング時間は、式（１４）を解いて、ｔ_ＵＰ≒１４.７７ｎｓｅｃ、ｔ_ＤＯＷＮ≒２.１７ｎｓｅｃとなる。このため、下位ビット用ＤＡＣ２のセトリング時間ｔ_ＤＯＷＮも実施の形態１に比べて２倍程度長くなる。しかしながら、ＤＡＣ全体のセトリング時間ｔ_ＤＡＣは、上位ビット用ＤＡＣ１のセトリング時間ｔ_ＵＰで決定されるため、実施の形態３で下位ビット用ＤＡＣ２のセトリング時間ｔ_ＤＯＷＮが２倍長くなっても、ＤＡＣ全体のセトリング時間には影響は無い。 Next, features of the third embodiment will be described below. For example, consider a 10-bit RstDAC in which the upper and lower bits are divided into 5 bits, and when R _M = 20Ω, C _LOAD = 10 pF, n = 2, and the settling allowable error ERR is 0.1 LSB, the equation (24) Thus, the resistance value R _S of the reference resistance of the voltage dividing circuit for lower bits 9 is

It becomes. For this reason, as compared with the first embodiment, the resistance value of the reference resistor 13 of the lower-bit voltage dividing circuit 9 is doubled. The settling times of the upper and lower bit DACs are t _UP ≈14.77 nsec and t _DOWN ≈2.17 nsec by solving equation (14). For this reason, the settling time t _DOWN of the lower bit DAC 2 is about twice as long as that in the first embodiment. However, since the settling time t DAC of the entire _DAC is determined by the settling time t _UP of the upper bit _DAC 1, even if the settling time t _DOWN of the lower bit DAC 2 is doubled in the third embodiment, the entire DAC There is no effect on the settling time.

The arrangement of the resistors in the third embodiment, when considered in the same manner as FIG. 3, the total number of the reference resistance R _P in the lower bit dividing circuit 9, a two × 2 ⁵ pieces = 64. Also, the total number of the reference resistance R _P in the upper bit dividing circuit 8, the resistance value from the least significant to the two from becoming twice, four × 2 ⁵ pieces + 4 pieces × 2 = 136 pieces and become The total number of resistors is smaller than that of the first embodiment, and there is an advantage that the resistance layout area can be reduced.

In the third embodiment, the resistance value R _S of the reference resistance of the low-order bit voltage dividing circuit 9 can be doubled as compared with the first embodiment, so that the resistance value R _S is halved. Even if the resistance value is the same as that of the first embodiment, it is possible to maintain the resistance layout accuracy. For this reason, the resistance values R _M and R _S of the reference resistors of the voltage dividing circuits 8 and 9 can be respectively set to 1/2 times. As a result, from the equations (5) and (14), the settling time in the upper bit DAC 1 can be halved and the settling time of the entire DAC can be halved.

Also in the third embodiment, as in the second embodiment, it is possible to arbitrarily select a location for extracting the reference voltage V _REF from locations other than the lowest order of the voltage dividing circuit 8 for upper bits. It is possible to take the reference voltage V _REF even from the central portion of the resistor string, where the relative accuracy of the reference resistor is relatively high.

  As described above, according to the present invention, it is possible to increase the overall speed of the DAC by increasing the speed of the lower-bit DAC. In addition, the speed of the DAC can be increased without increasing power consumption. Furthermore, theoretically, no conversion error occurs at the switching point between the upper bits and the lower bits. By creating the reference resistance of the voltage dividing circuit for the upper bits and the reference resistance of the voltage dividing circuit for the lower bits with the same resistance value and the same number of resistors, it is possible to The relative accuracy between the reference resistors can be maintained. In addition, it is possible to suppress an increase in the number of reference resistors of the voltage dividing circuit of the upper bit and the lower bit.

1 is a diagram illustrating a configuration of a DAC according to Embodiment 1. FIG. FIG. 3 is a diagram illustrating output waveforms of respective units in the DAC according to the first embodiment. FIG. 3 is a diagram illustrating a resistor arrangement in a DAC according to the first embodiment. 6 is a diagram illustrating a configuration of a DAC according to Embodiment 2. FIG. 6 is a diagram illustrating a configuration of a DAC according to Embodiment 3. FIG. It is a figure which shows the structure of the conventional DAC. It is a figure which shows the resistance partial pressure of the conventional DAC.

Explanation of symbols

1 DAC for upper bits
2 DAC for lower bits
3 Analog Adder 4 Analog Subtractor 5 1 / n Circuit 6 Upper Bit Decoder 7 Lower Bit Decoder 8 Upper Bit Divider 9 Lower Bit Divider 10 Upper Bit Switch Circuit 11 Lower Bit Switch Circuit 12 Reference resistance R _{M of} voltage dividing circuit 8 for upper bits
13 Reference resistance R _{S of} voltage dividing circuit 9 for lower bits
14 n × _{R M} resistance 15 N bits of the input data 16 upper K bits of the input data 17 lower L bits of the input data 18 first reference power supply signal 19 and the second reference power supply signal 20 decodes the upper bit decoder 6 Result signal 21 Decoding result signal 22 of lower bit decoder 7 Analog output signal 23 of upper bit DAC 1 Analog output signal 24 of lower bit DAC 2 Analog output signal 25 of lower bit DAC 2 in the second embodiment The analog output signal 26 of the lower bit DAC2 at RstDAC

Claims (11)

More for the upper bit resistance of the resistance value R _M are connected in series, the resistance for the plurality of upper bit, the upper bit reference voltage by dividing an analog signal corresponding to the upper bits of the input digital signal An upper bit DAC to be output;
Wherein a plurality of lower bits of the small resistance value R _S than the resistance value R _M for the upper bit resistance resistor is connected in series, by a corresponding plurality of lower bit resistance, by applying a reference voltage for lower bit partial input A lower-bit DAC that outputs an analog signal corresponding to the lower-order bits of the digital signal,
An adder for adding the analog signal output from the upper bit DAC and the analog signal output from the lower bit DAC;
D / A converter with D according to claim 1 in which the resistance of the resistance value n × R _M provided on the lowest potential side of the resistor for the upper bits, a resistor string comprising a plurality of lower bit resistor is connected in parallel / A converter. Wherein the resistance of the resistance value n × R _M, the combined resistance value when the resistance string consisting for the lower bit number lower bit pieces of the resistance R _S resistance connected in parallel is, the upper bit resistance of the resistance value D / a converter according to claim 2, characterized in that is equivalent to R _M. When the number of bits of the lower-bit DAC is L and n is a number greater than 1,

The D / A converter according to claim 2, wherein the D / A converter is expressed by the following formula. A resistor for the upper bit, the a lower bit resistance, D / A according to respective reference resistor having the same resistance value R _P to claim 1, wherein the creating in series connection or parallel connection converter. D / A converter according to claim 5, wherein the said series connections or parallel connections of the reference resistance of the resistance value R _P for the upper bit resistance and resistance for the lower bits are equal. Claims, characterized in that the series connections of the reference resistor of the resistance value R _P for upper bits resistor, the parallel connections of the reference resistor of the resistance value R _P of the lower bit resistance R _S is equal Item 6. The D / A converter according to Item 5.   8. The point according to claim 1, wherein a part for extracting the reference voltage for the lower bit can be arbitrarily selected from places other than the lowest part of the voltage dividing circuit for the upper bit. D / A converter. Claims a resistor string comprising resistors of lowest potential resistance provided n pieces from side n × R _M of resistance for the high-order bit, a resistor string comprising a plurality of lower bit resistor is connected in parallel Item 2. The D / A converter according to Item 1. A resistor string comprising resistors of the n resistance n × R _M, the combined resistance value when the resistance string consisting for the lower bit number lower bit pieces of the resistance R _S resistance connected in parallel is, the D / a converter according to claim 9, characterized in that is n times the equivalent of the resistance value R _M for the upper bit. If the number of bits of the lower bit DAC is L and n is an integer of 2 or more,

The D / A converter according to claim 9, wherein the D / A converter is expressed by the following formula.

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