JP2008234584A - Reference voltage generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generation circuit having sufficient power supply ripple rejection characteristics. <P>SOLUTION: The reference voltage generation circuit is equipped with: a first depression type insulating gate field effect transistor M<SB>D21</SB>of which the first electrode is connected to a first potential line 11 and the control electrode is connected to a first power supply 12; a second depression type insulating gate field effect transistor M<SB>D22</SB>of which the first electrode is connected to a second electrode of the first insulating gate field effect transistor M<SB>D21</SB>and the control electrode is connected to a second electrode and an enhancement type insulating gate field effect transistor M<SB>E2</SB>of which the first electrode is connected to a second electrode of the second insulating gate field effect transistor M<SB>D22</SB>, the control electrode G is connected to the first electrode and the second electrode is connected to a second potential line 13. The power supply ripple rejection characteristics are raised by utilizing gm=ΔId/ΔVgs of the first depression type insulating gate field effect transistor M<SB>D21</SB>. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a reference voltage generation circuit.

  Conventionally, a depletion type MOS transistor having a gate and a source connected is used as a constant current source, and an enhancement type MOS transistor having a gate and a drain connected to each other is connected in series so as to be driven by the constant current. There is known a reference voltage generation circuit that outputs the difference between the threshold voltages of the MOS transistor and the enhancement type MOS transistor as a reference voltage.

However, the depletion type MOS transistor in which the gate, which is a constant current source, is connected to the source operates only with the mutual conductance gmb due to the substrate effect, so that there is a problem that the mutual conductance becomes small.
As a result, this reference voltage generating circuit has a problem that the power supply ripple rejection characteristic indicating the fluctuation ratio of the reference voltage with respect to the fluctuation of the power supply voltage is poor.

  There is also known a reference voltage generation circuit in which a depletion type MOS transistor having a gate and a source connected is used as a constant current source, and two or more enhancement type MOS transistors having different threshold voltages are connected in series to the depletion type MOS transistor. (For example, refer to Patent Document 1).

The reference voltage generation circuit disclosed in Patent Document 1 includes a floating gate and a control gate, and includes a MOS transistor whose threshold voltage is determined by a difference in coupling coefficient between the floating gate and the control gate.
As a result, the dependence on process variations and temperature changes is small, and the reference voltage can be adjusted in a process close to completion of the semiconductor device.

However, the reference voltage generation circuit disclosed in Patent Document 1 adjusts the reference voltage by shifting the threshold voltage of the MOS transistor afterwards, and does not disclose anything about the power supply ripple rejection characteristics. There is no effect.
JP 2002-110917 A

  An object of the present invention is to provide a reference voltage generation circuit having sufficient power supply ripple reject characteristics.

  The reference voltage generation circuit of one embodiment of the present invention includes a first depletion type insulated gate field effect transistor in which a first electrode is connected to a first potential line and a control electrode is connected to a first power supply, A second depletion type insulated gate field effect transistor connected to the second electrode of the first depletion type insulated gate field effect transistor and having a control electrode connected to the second electrode, and a first electrode serving as the second insulated gate field effect transistor And an enhancement-type insulated gate field effect transistor having a control electrode connected to the first electrode and a second electrode connected to the second potential line.

  According to the present invention, a reference voltage generating circuit having sufficient power supply ripple rejection characteristics can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  A reference voltage generation circuit according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a reference voltage generation circuit, and FIG. 2 is an equivalent circuit diagram for power supply ripple rejection characteristic analysis.

As shown in FIG. 1, in the reference voltage generation circuit 10 of this embodiment, the drain (first electrode) is connected to the power supply line (first potential line) 11 and the gate (control electrode) is connected to the first power supply 12. and n first depletion type MOS transistor channel (insulated gate field effect transistor) MD21, which is a drain connected to the source (second electrode) of the first depletion type MOS transistor _{M D21,} n having a gate connected to a source a second depletion type MOS transistor _{M D22} channel, a drain connected to a second source of the depletion type MOS transistor _{M D22,} the gate is connected to the drain, a source connected to the ground line (second potential line) 13 and an n-channel enhancement type MOS transistor M _E2 .

Back gates (not shown) that are substrates of the first depletion type MOS transistor M _D21 , the second depletion type MOS transistor M _D22, and the enhancement type MOS transistor M _E2 are connected to the ground line 13, respectively.

The reference voltage Vref2 is obtained as a difference between the second threshold voltage of the depletion type MOS transistor _{M D22} and the threshold voltage of the enhancement type MOS transistor _{M E2.}

By supplying the input voltage Vin to the voltage input terminal 14, the reference voltage Vref2 from a connection node between the drain of the second depletion type MOS transistor _M source and an enhancement-type MOS transistors ME2 of _D22 is, the voltage output terminal 15 as an output voltage Vout Is output to the outside via

Since the gate of the first depletion type MOS transistor _MD21 is connected to the first power supply 12, the mutual conductance gm = ΔId / ΔVgs indicating the change amount of the drain current Id with respect to the change amount of the gate-source voltage Vgs and the substrate The operation is based on the mutual conductance gmb = ΔId / ΔVbs indicating the change amount of the drain current Id with respect to the change amount of the inter-source voltage Vbs.

The second depletion type MOS transistor _{M D22} is, the gate is connected to the source, gm = 0, and the only work with gmb.

  Here, gm and gmb due to the substrate effect have a relationship of gmb = ηgm. η depends on manufacturing process parameters and is generally about η≈0.1 to 0.9.

Potential E1 of the first power supply 12, the gate-source voltage of the first depletion type MOS transistor _{M D21} is in the range first depletion type MOS transistor _{M D21} is operational, such as greater than the threshold voltage, range smaller than the pinch-off voltage If it is, it will not be specifically limited.

  Next, the operation of the reference voltage generation circuit 10 will be described assuming that the potential E1 of the first power supply 12 is 0 V (ground potential GND).

Since the first depletion type MOS transistor M _D21 , the second depletion type MOS transistor M _D22, and the enhancement type MOS transistor M _E2 are connected in series, the drain current Id of each transistor is equal and is expressed by the following equation.

Here, K _E2 , K _D21 , and K _D22 are conductance factors of the respective transistors. Vth _E2 , Vth _D22 , and Vth _D21 are threshold voltages of the respective transistors. V _SD21 is the gate-source voltage of the first depletion type MOS transistor _{M D21} (E1-Vb).
The reference voltage Vref2 is expressed by the following equation when attention is paid to the enhancement type MOS transistor M _E2 and the second depletion type MOS transistor _MD22 .

As shown in FIG. 2, a power ripple rejection characteristic (Power Ripple Suppression Ratio: hereinafter also referred to as PSR) analysis equivalent circuit 20 of the reference voltage generation circuit 10 is a first depletion type having a gate connected to a first power supply 12. A parallel circuit of a constant current source 21 having an impedance Z _D21 showing a MOS transistor M _D21 and a mutual conductance gm _D21 , an impedance Z _D22 showing a second depletion type MOS transistor M _D22 whose gate is connected to the source, and mutual effects due to the substrate effect a parallel circuit of the constant current source 22 having a conductance _{gmb D22,} it is revealed by a series circuit of an impedance _{Z E2} indicating the enhancement type MOS transistor _{M E2} having a gate connected to the drain.

Thereby, the power supply ripple rejection characteristic PSR2 of the reference voltage generating circuit 10 is expressed by the following equation.

On the other hand, as a comparative example, the gate of the first depletion type MOS transistor M _D21 is not the first power source 12, PSR1 of the reference voltage generating circuit connected to the source, as in equation (3), the current by the following formula Is done.

The ratio between the PSR2 of the reference voltage generating circuit 10 of the present embodiment and the PSR1 of the reference voltage generating circuit of the comparative example is obtained using the relationship of Expression (3), Expression (4), and gmb = ηgm.

Since Accordingly, eta is smaller than 1, the reference voltage generating circuit 10 having a first depletion type MOS transistor M _D21 to the gate of this embodiment is connected to the first power supply 12, the gate of the comparative example is connected to a source The PSR is smaller than that of the reference voltage generating circuit having the first depletion type MOS transistor _MD21 , and the power supply ripple rejection characteristic can be improved.

For example, by using a first depletion type MOS transistor _{M D21} of about eta ≒ 0.2, PSR2 of the reference voltage generating circuit 10 of the present embodiment, 1/5 next PSR1 of the reference voltage generating circuit of the comparative example An improvement effect of about 5 times is expected. Therefore, it is preferable that η is small for improving the power supply ripple rejection characteristic.

Further, a condition for obtaining a stable reference voltage Vref2 independent of temperature is expressed by the following equation.

Now, as shown in the following equation, the ratio of the square root of the conductance factor _{K E2} of the second depletion type MOS transistor _M conductance factor _{K D22} of _D22 and the enhancement-type MOS transistor _{M E2} is the second depletion type MOS transistor _{M D22} A stable reference voltage Vref2 having no temperature dependency is obtained by setting the threshold voltage Vth _D22 to be equal to the ratio between the temperature dependency of the threshold voltage Vth _{D22 and} the temperature dependency of the threshold voltage Vth _E2 of the enhancement type MOS transistor M _E2. Is possible.

FIG. 3 is a circuit diagram showing a series regulator using the reference voltage generation circuit 10.
As shown in FIG. 3, the series regulator 30 has a p-channel MOS transistor M1 having a source connected to the voltage input terminal 31 and a drain connected to the voltage output terminal 32, and one end connected to the voltage output terminal 32. A voltage dividing circuit 34 that has a series circuit of a resistor R1 and a resistor R2 having one end connected to the ground terminal 33, divides the output voltage Vout of the voltage output terminal 32 and outputs a feedback voltage Vf, and a non-inverting input terminal Is connected to the voltage dividing point of the voltage dividing circuit 34, and a differential amplifier 35 is connected to the reference voltage generating circuit 10 whose inverting input terminal departs the reference voltage Vref2.

  The differential amplifier 35 drives the MOS transistor M1 so that the feedback voltage Vf obtained by dividing the output voltage Vout becomes equal to the reference voltage Vref2, and the output voltage Vout is controlled.

  By using the reference voltage generation circuit 10 that supplies the reference voltage Vref2 having sufficient power supply ripple reject characteristics and temperature characteristics, a stable output voltage Vout can be supplied to the load.

  The apparatus and apparatus to which the reference voltage generation circuit 10 is applied are not limited to the series regulator described above, and can be applied to any apparatus that requires a stable reference voltage Vref2.

As described above, the reference voltage generating circuit 10 of the present embodiment connects the gate of the first depletion type MOS transistor _MD21 to the first power supply 12.
As a result, the first depletion type MOS transistor _{M D21} is operated by the mutual conductance gm = .DELTA.Id / .DELTA.Vgs showing the variation of the drain current Id with respect to the amount of change in gate-source voltage Vgs, transconductance gmb = .DELTA.Id by the substrate effect It has a transconductance larger than / ΔVbs. Therefore, the reference voltage generation circuit 10 having sufficient power supply ripple rejection characteristics can be obtained.

Furthermore, the ratio of the square root of the conductance factor _{K E2} of the second depletion type MOS transistor _M conductance factor _{K D22} of _D22 and the enhancement-type MOS transistor _{M E2} is a second depletion-type temperature dependence of the MOS transistor _{M D22} threshold voltage _{Vth D22} The reference voltage generation circuit 10 having sufficient temperature characteristics can be obtained by setting it to be equal to the ratio between the characteristics and the temperature dependence of the threshold voltage Vth _E2 of the enhancement type MOS transistor M _E2 .

Here, the case where the conductivity type of the first depletion type MOS transistor M _D21 , the second depletion type MOS transistor M _D22, and the enhancement type MOS transistor M _E2 is an n channel has been described, but a p channel may be used.

That is, as shown in FIG. 4, the reference voltage generation circuit 40 has a drain (first electrode) connected to the ground line (first potential line) 13 and a gate (control electrode) connected to the first power supply 41. A p-channel first depletion type MOS transistor M _D31 , an n-channel second depletion type MOS transistor M _D32 having a drain connected to the source of the first depletion type MOS transistor M _D31 and a gate connected to the source, a drain A p-channel enhancement type MOS transistor M whose (first electrode) is connected to the source of the second depletion type MOS transistor _MD32, whose gate is connected to the drain, and whose source is connected to the power supply line (second potential line) 11. _E3 .

The reference voltage Vref3 from the connection node between the source and the drain of the enhancement-type MOS transistor _{M E3} of the second depletion type MOS transistor _{M D32,} is output to the power line 11 to the reference.

Back gates (not shown), which are substrates of the first depletion type MOS transistor M _D31 , the second depletion type MOS transistor M _D32, and the enhancement type MOS transistor M _E3 , are respectively connected to the power supply line 11.

  Thereby, like the reference voltage generation circuit 10, the reference voltage generation circuit 40 having sufficient power supply ripple reject characteristics can be obtained.

  A reference voltage generation circuit according to Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 5 is a circuit diagram showing a reference voltage generation circuit, and FIG. 6 is an equivalent circuit diagram for power supply ripple rejection characteristic analysis.

In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.
This embodiment differs from the first embodiment in that the control electrode of the second depletion type MOS transistor is connected to the second power source.

That is, as shown in FIG. 5, in the reference voltage generation circuit 50 of this embodiment, the gate of the second depletion type MOS transistor _MD22 is connected to the second power supply 51.

Thus, the second depletion type MOS transistor _{M D22} is operated by the mutual conductance gm = .DELTA.Id / .DELTA.Vgs showing the variation of the drain current Id with respect to the amount of change in gate-source voltage Vgs, the change of the voltage Vbs between the substrate and the source The mutual conductance is larger than the mutual conductance gmb = ΔId / ΔVbs depending on the amount of change in the drain current Id with respect to the amount.

Potential E2 of the second power source 51, the gate-source voltage of the second depletion type MOS transistor _{M D22} is, second depletion type MOS transistor _{M D22} is operable range, e.g., greater than the threshold voltage, range smaller than the pinch-off voltage If it is, it will not be specifically limited.

  Therefore, the potential E2 of the second power source 51 may be equal to or different from the potential E1 of the first power source 12.

  Next, the operation of the reference voltage generation circuit 50 will be described when the potential E1 of the first power supply 12 and the potential E2 of the second power supply 61 are both 0 V (ground potential GND).

Since the first depletion type MOS transistor M _D21 , the second depletion type MOS transistor M _D22, and the enhancement type MOS transistor M _E2 are connected in series, the drain current Id of each MOS transistor is equal and is expressed by the following equation.

The reference voltage Vref2 is expressed by the following equation, focusing on the enhancement type MOS transistor M _E2 and the second depletion type MOS transistor M _D22 .

As shown in FIG. 6, the power supply ripple rejection characteristics analysis equivalent circuit 60 of the reference voltage generating circuit 50, Inpitansu Z _D22 and transconductance of a second Depuresshoku type MOS transistor M _D22 having a gate connected to the second power supply 51 It has a parallel circuit with a constant current source 61 having gm _D22 .

Thereby, the power supply ripple rejection characteristic PSR2 of the reference voltage generation circuit 50 is expressed by the following equation.

The power supply ripple rejection characteristic PSR2 of the reference voltage generation circuit 50 is compared with the power supply ripple rejection characteristic PSR1 of the reference voltage generation circuit of the comparative example shown in Expression (4).

Here, the following equation is obtained by setting so as to satisfy gm _D12 Z _E1 >> ₁ .

Thus, the reference voltage generation circuit having the first depletion type MOS transistor M _D21 whose gate is connected to the first power source 51 and the second depletion type MOS transistor M _D22 whose gate is connected to the second power source 51 in this embodiment. 50, the PSR is smaller than that of the reference voltage generation circuit having the first depletion type MOS transistor M _{D21 having the} gate connected to the source and the second depletion type MOS transistor M _D22 having the gate connected to the source. Furthermore, it is possible to improve the power supply ripple reject characteristic.

For example, by using a first depletion type MOS transistor _{M D21} and the first depletion type MOS transistor _{M D22} of about eta ≒ 0.2, PSR2 of the reference voltage generating circuit 50 of this embodiment, the reference voltage of the comparison example It becomes 1/25 of PSR1 of the generation circuit, and an improvement effect of about 25 times is expected.

  Conditions for obtaining a stable reference voltage Vref2 that does not depend on temperature are expressed in the same manner as in equations (7) and (8).

As described above, the reference voltage generation circuit 50 of this embodiment connects the gate of the second depletion type MOS transistor _MD22 to the second power supply 51.
As a result, the second depletion type MOS transistor _{M D22} is operated by the mutual conductance gm = .DELTA.Id / .DELTA.Vgs showing the variation of the drain current Id with respect to the amount of change in gate-source voltage Vgs, transconductance gmb = .DELTA.Id by the substrate effect It has a transconductance larger than / ΔVbs. Therefore, the reference voltage generation circuit 50 having higher power supply ripple reject characteristics can be obtained.

Here, the case where the conductivity type of the first depletion type MOS transistor M _D21 , the second depletion type MOS transistor M _D22, and the enhancement type MOS transistor M _E2 is an n channel is described, but a p channel may be used.

That is, as shown in FIG. 7, in the reference voltage generation circuit 70, the gate of the p-channel first depletion type MOS transistor _MD31 is connected to the first power supply 41, and the gate of the second depletion type MOS transistor _MD32 is the first. Two power sources 71 are connected.

  As a result, the power supply ripple rejection characteristic can be further increased as with the reference voltage generation circuit 50.

1 is a circuit diagram showing a reference voltage generating circuit according to Embodiment 1 of the present invention. 3 is an equivalent circuit for analyzing a power supply ripple reject characteristic of the reference voltage generating circuit according to the first embodiment of the present invention. 1 is a circuit diagram showing a series regulator using a reference voltage generating circuit according to Embodiment 1 of the present invention. FIG. 3 is a circuit diagram illustrating another reference voltage generating circuit according to the first embodiment of the invention. FIG. 6 is a circuit diagram showing a reference voltage generating circuit according to Embodiment 2 of the present invention. 6 is an equivalent circuit for analyzing a power supply ripple reject characteristic of a reference voltage generating circuit according to a second embodiment of the present invention. FIG. 6 is a circuit diagram showing another reference voltage generation circuit according to Embodiment 2 of the present invention.

Explanation of symbols

10, 40, 50, 70 Reference voltage generation circuit 11 Power line 12, 41 First power supply 13 Ground line 14 Voltage input terminal 15 Reference voltage output terminal 16 Ground terminal 20, 60 PSR analysis equivalent circuit 21, 22, 61 Constant current Source 30 Series regulator 51, 71 Second power supply Vref2, Vref3 Reference voltage M _D21 n-channel first depletion type MOS transistor M _D22 n-channel second depletion type MOS transistor M _D31 p-channel first depletion type MOS transistor M _D32 pn-channel first 2-depletion type MOS transistor M _E2 n-channel enhancement type MOS transistor M _E3 p-channel enhancement type MOS transistor

Claims (5)

A first depletion type insulated gate field effect transistor having a first electrode connected to a first potential line and a control electrode connected to a first power source;
A second depletion type insulated gate field effect transistor having a first electrode connected to the second electrode of the first depletion type insulated gate field effect transistor and a control electrode connected to the second electrode;
An enhancement type insulated gate field effect transistor having a first electrode connected to a second electrode of the second insulated gate field effect transistor, a control electrode connected to the first electrode, and a second electrode connected to a second potential line When,
A reference voltage generating circuit comprising:   The reference voltage generation circuit according to claim 1, wherein a control electrode of the second depletion type insulated gate field effect transistor is connected to a second power source.   2. The reference voltage generating circuit according to claim 1, wherein the potential of the first power source is equal to the potential of the second potential line.   3. The reference voltage generation circuit according to claim 2, wherein the potential of the second power source is equal to the potential of the second potential line.   The square root of the ratio of the conductance factor of the second depletion type insulated gate field effect transistor to the conductance factor of the enhancement type insulated gate field effect transistor is the temperature dependence of the threshold voltage of the second depletion type insulated gate field effect transistor. 3. The reference voltage generation circuit according to claim 1, wherein the reference voltage generation circuit is equal to a ratio to a temperature dependency of the enhancement type insulated gate field effect transistor.

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