JP2008220056A - Rush current prevention circuit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a rush current prevention circuit which solves a problem that a load is not activated normally, or failed in activation. <P>SOLUTION: The rush current prevention circuit comprises: partial pressure resistors 2, 3 connected between a positive potential terminal and a negative potential terminal of a DC power supply 1; a capacitor 4 connected between a connecting point of the resistors and the negative potential terminal; Zener diodes 5 and a resistor 6 which are connected in series between the connecting point of the resistors and the negative potential terminal; a bipolar transistor 7 in which a base is connected to a connecting point of the Zener diode and the resistor, an emitter is connected to the negative potential terminal, and a collector is connected to an activation signal terminal 13; a MOSFET 8 in which a gate is connected to the connecting point of the resistors, a source is connected to the negative potential terminal, and a drain is connected to an output terminal 12; and a capacitor 9 and a resistor 10 which are connected in series between the gate and the drain of the MOSFET. When applying DC power, an activation signal is outputted from the activation signal terminal to the load 14 after a rush current limit operation is completed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an inrush current prevention circuit and method.

  The inrush current prevention circuit is provided in a power supply circuit or the like in order to suppress an inrush current generated when a direct current is applied. As this type of inrush current prevention circuit, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2005-45957) discloses a configuration as shown in FIG. 3 in order to keep the inrush current low with a simple configuration.

  Referring to FIG. 3, a load 25 connected to the DC power supply 16 and an input capacitor 26 connected in parallel with the load 25 are provided, and the inrush current prevention circuit 201 suppresses an inrush current to the input capacitor 26. A MOSFET (MOS field effect transistor) 20, a time constant circuit having bias resistors 17 and 18 and a capacitor 19 for generating a gate voltage of the MOSFET 20, and a capacitor connected in series between the drain terminal and the gate terminal of the MOSFET 20 21 and a resistor 22 are provided.

  An outline of the operation of the inrush current prevention circuit 201 shown in FIG. 3 will be described. When the switch 27 is closed and the DC power supply is applied, the gate voltage of the MOSFET 20 gradually increases due to the charging operation from the resistor 17 to the capacitor 19. When the gate voltage of the MOSFET 20 reaches the threshold value (VTH), the MOSFET 20 is turned on, current starts to flow between the drain and the source, and the drain-source voltage (VDS) starts to decrease. At this time, the fluctuation of the voltage drop at the drain terminal is fed back to the gate terminal of the MOSFET 20 via the feedback circuit of the capacitor 21 and the resistor 22, and the gate voltage of the MOSFET 20 is maintained at a substantially constant value. As a result, the current flowing through the MOSFET 20 (drain-source current) is controlled to a substantially constant value, and the terminal voltage waveform of the input capacitor 26 is gradually charged with the ramp waveform.

  Next, as a configuration for supplying a charging completion signal indicating completion of charging of the input capacitor to the DC / DC converter, for example, Patent Literature 2 shows a configuration as shown in FIG. Referring to FIG. 4, in this switching power supply device, a closing circuit for supplying power to a DC / DC converter (DC / DC converter) 41 is a capacitor 39 (connected in parallel to the positive / negative electronic input terminal of the DC / DC converter 41. The DC / DC converter 41 has a signal input terminal d for inputting a charging completion signal indicating completion of charging the capacitor 39. The input circuit includes a resistor 31 and a Zener diode 36 connected in series between the positive and negative potential terminals of the DC power supply 40, and a primary side element 37 of the photocoupler connected in parallel between the terminals of the Zener diode 36 and an NPN type. A series circuit of bipolar transistors 34, a MOSFET 35 connected between the negative potential terminal of the DC power supply 40 and the negative potential terminal of the input circuit, and a resistor 33 connected between the drain and source of the MOSFET 35 are provided. The base of the transistor 34 is connected to the negative terminal of the capacitor 39 via the resistor 32, and the output of the secondary element 38 of the photocoupler is connected to the charge completion signal terminal of the DC / DC converter 41 as a charge completion signal.

  An outline of the operation of the input circuit shown in FIG. 4 will be described below. When a stepped DC voltage is applied to the switching power supply device, a voltage waveform obtained by differentiating the stepped DC voltage appears at a point c in FIG. 4, the transistor 34 is turned on, the gate terminal of the MOSFET 35 is set to a threshold value or less, and the MOSFET 35 Turns off. The photocouplers (37, 38) are turned on by the transistor 34, the charge completion signal terminal of the DC / DC converter 41 is held at the LOW level, and the fact that the capacitor 39 has not been charged is transmitted. When the potential at the point c decreases and becomes lower than the base-emitter voltage (VBE) of the transistor 34, the transistor 34 is turned off, and a current is supplied to the Zener diode 36 through the resistor 31. (Zener voltage) is applied as the gate-source voltage of the MOSFET 35. At this time, the charging of the capacitor 39 is completed, and when the transistor 34 is turned off, the photocouplers (37, 38) are also turned off, and the charging completion signal terminal of the DC / DC converter 41 is set to the HIGH level.

JP 2005-45957 A JP-A-4-88827

  However, the above-described conventional circuit has the following problems.

  In the configuration of FIG. 3, when the load 25 is a DC / DC converter or the like, the inrush current prevention circuit 201 is charging the input capacitor 26, and the terminal voltage of the input capacitor 26 has reached the input voltage (DC power supply voltage). In some cases, the load 25 may start operating. At this time, the MOSFET 20 of the inrush current prevention circuit 201 performs an operation of limiting the charging current of the input capacitor 26, and a current exceeding the limit current of the MOSFET 20 is generated by the operation of the load 25 (DC / DC converter). The current sufficient for the operation of the load 25 (DC / DC converter) cannot be supplied, and the terminal voltage of the input capacitor 26 is lowered. As a result, the load 25 (DC / DC converter) does not operate normally. Alternatively, there arises a problem that startup fails due to disclosure of operation from a low voltage.

  In the configuration of FIG. 3, the gate-source voltage of the MOSFET 20 varies according to the input voltage from the DC power supply 16. That is, the operating point of the MOSFET 20 varies according to the input voltage, and there is a problem in terms of operational stability. In particular, the absolute maximum rating of the gate voltage of the MOSFET 20 may be exceeded due to an abnormal rise in the input voltage or the like, which may cause damage.

  On the other hand, in the case of the configuration shown in FIG. 4, when a voltage is applied from the DC power supply 40 to the power supply terminal to the DC / DC converter 41, a minute current due to a bias current or the like flows to the internal circuit of the DC / DC converter 41. If so, the current may flow into the base of the transistor 34 via the resistor 32 of the input circuit, and the transistor 34 may be turned on. In this case, after the capacitor 39 is charged, the transistor 34 is not turned off, the photocouplers (37, 38) are turned on, and a malfunction that the charge completion signal terminal holds the LOW level occurs. That is, even after the capacitor 39 is charged, the charge completion signal may not be set to the active state (HIGH level).

  Accordingly, an object of the present invention is to provide an inrush current prevention circuit and method which solves the problem that the load does not start normally or fails to start.

  Another object of the present invention is to provide an inrush current preventing circuit and a method for realizing a stable operation even when an input voltage changes in a wide range while eliminating the above object.

  Still another object of the present invention is to provide an inrush current preventing circuit and a method for avoiding malfunction due to a minute current generated on the load side and improving reliability while eliminating the above object.

  In order to solve the above-described problems, the invention disclosed in the present application is generally configured as follows.

The inrush current prevention circuit according to the present invention includes a first transistor that limits an inrush current to an input capacitor connected in parallel to a load that receives power from a DC power supply,
A time constant circuit having a voltage dividing resistor and a first capacitor, which divides an input voltage from the DC power source and outputs a divided time constant;
With
The control terminal of the first transistor is connected to the output of the time constant circuit, and is connected to the terminal of the first transistor connected to the load through a feedback circuit including a second capacitor. And
When the inrush current limiting operation is completed and the voltage of the control terminal of the first transistor reaches a predetermined voltage, the second transistor is turned on and outputs a start signal for starting the load as an active state. The transistor is further provided.

  In the present invention, a circuit is provided for controlling the voltage of the control terminal of the first transistor to be maintained at a predetermined voltage after the activation signal in the active state is output.

A constant voltage element inserted between a control terminal of the first transistor and a control terminal of the second transistor;
In the present invention, a resistor connected between a control terminal of the second transistor and a terminal of the first transistor connected to the DC power source is provided.

  The inrush current preventing circuit according to the present invention includes first and second input terminals connected to first and second power output terminals of a DC power source, and first and second power input terminals of a load, respectively. First and second output terminals connected to each other and an activation signal terminal for supplying an activation signal to the load, and an input capacitor is connected in parallel to the first and second power input terminals of the load. The first input terminal and the first output terminal are connected to each other. The present invention provides a first transistor connected between the second input terminal and the second output terminal, and a time constant by dividing the input voltage between the first and second input terminals. And a time constant circuit having a voltage dividing resistor and a first capacitor, and the control terminal of the first transistor is connected to the output of the time constant circuit, and the second capacitor is The terminal is connected to the terminal connected to the second output terminal of the first transistor through a feedback circuit including the feedback circuit. The present invention further includes a constant voltage element having one end connected to a control terminal of the first transistor, a resistor connected between the other end of the constant voltage element and the second input terminal, and the start-up A second transistor which is inserted between a signal terminal and the second input terminal and whose control terminal is connected to a connection point of the constant voltage element and the resistor.

  In the present invention, when the voltage obtained by subtracting the inter-terminal voltage of the constant voltage element from the voltage of the control terminal of the first transistor reaches a voltage at which the second transistor is turned on, the second transistor is turned on, An activation signal output to the load is activated from the activation signal terminal.

  In the present invention, when a DC power supply is applied, a divided voltage waveform generated by the time constant circuit is applied to the control terminal of the first transistor, and the voltage of the control terminal of the first transistor is set to a threshold value. The first transistor is turned on, and when the voltage of the terminal connected to the second output terminal of the first transistor starts to decrease, the first transistor is connected to the first transistor via the feedback circuit. Control is performed so that the control terminal is kept constant, and the current flowing through the first transistor is controlled to a constant value.

  In the present invention, the first transistor is a MOSFET.

  In the present invention, the second transistor is a bipolar transistor.

  In the present invention, the feedback circuit includes a resistor connected in series to the second capacitor.

A method according to the present invention is an inrush current prevention method for limiting an inrush current to an input capacitor connected in parallel to a load that receives power supply from a DC power supply,
The voltage from the DC power supply is divided to give a divided voltage to the control terminal of the first transistor that is inserted between the DC power supply and the load and limits the inrush current to the input capacitor,
The terminal voltage of the first transistor connected to the connection point of the input capacitor and the load is negatively fed back to the control terminal of the first transistor,
Outputting an activation signal for activating the load when the inrush current limiting operation is completed and the voltage of the control terminal of the first transistor reaches a predetermined voltage;
Each step is included.
The method according to the present invention includes a step of controlling the voltage of the control terminal of the first transistor to be maintained at a predetermined voltage after the activation signal is output.

  According to the present invention, it is possible to avoid the problem that the operation of the load starts during the charging operation of the input capacitor and the load does not start normally or fails to start. This is because in the present invention, the load is started after the inrush current limiting operation by the inrush current prevention circuit is completed.

  Further, according to the present invention, stable operation is realized even when the input voltage changes over a wide range.

  Furthermore, according to the present invention, it is possible to avoid a malfunction that a start signal is not transmitted due to a minute current or the like generated on the load side, and to improve operation reliability.

  The above-described present invention will be described with reference to the accompanying drawings in order to explain in more detail. The inrush current preventing circuit according to the present invention includes first and second input terminals connected to first and second power supply output terminals of a DC power supply (1), and first and second inputs of a load (14). And a start signal terminal (13) for supplying a start signal to the load (14), each of which is connected to the power input terminal of the load, and a load (14). An input capacitor (15) is connected in parallel to the first and second power input terminals, the first input terminal of the own circuit and the first output terminal (11) are connected, and the second input of the own circuit. The time constant is obtained by dividing the input voltage between the first and second input terminals of the own circuit and the MOSFET (8) which is connected between the terminal and the second output terminal (12) and forms the first transistor. A time constant circuit having a voltage dividing resistor (2, 3) and a first capacitor (4) for output. Eteiru. The gate terminal (control terminal) of the MOSFET (8) is connected to the output of the time constant circuit (2, 3, 4), and via the feedback circuit including the second capacitor (9), the MOSFET (8). Are connected to a terminal (drain) on the side connected to the second output terminal (12). Furthermore, the constant voltage element (5) having one end connected to the gate terminal of the MOSFET (8), the other end of the constant voltage element (5), and a terminal connected to the second input terminal of the MOSFET (8) Inserted between the resistor (6) connected to the (source), the start signal terminal (13), and the terminal (source) connected to the second input terminal of the MOSFET (8), A base (control terminal) is connected to a connection point between the constant voltage element (5) and the resistor (6), and includes a bipolar transistor (7) forming a second transistor.

  The inrush current prevention circuit of the present invention limits the inrush current generated to the input capacitor (15) when the input DC power is applied, and after the charging of the input capacitor (15) is completely completed, In response to (14), an activation signal is sent from the signal terminal (13). Hereinafter, description will be made with reference to examples.

  FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. The inrush current prevention circuit 101 of the present embodiment is connected between a terminal connected to the negative potential terminal of the DC power supply 1 and the output terminal 12 having a negative potential, for limiting the inrush current to the input capacitor 15. A time constant circuit composed of a resistor 2 and a resistor 3 and a capacitor 4 for dividing the voltage of the MOSFET 8 and the voltage of the DC power supply 1 to provide a time constant to generate the gate voltage of the MOSFET 8, and an output of the time constant circuit (resistors 2, 3 And a node between the capacitor 4 and the gate of the MOSFET 8. A resistor 6 connected to the source), an emitter connected to the source of the MOSFET 8, and a base connected to the connection point of the Zener diode 5 and the resistor 6. An N-type bipolar transistor 7 are connected in series between the drain and the gate of the MOSFET 8, and a capacitor 9, a resistor 10 for feeding back the drain voltage to the gate. The positive potential terminal of the DC power supply 1 is connected to the output terminal 11. The collector of the bipolar transistor 7 is connected to the activation signal terminal 13. The load 14 has a positive potential terminal and a negative potential terminal connected to the output terminals 11 and 12 of the inrush current prevention circuit 101, and inputs the terminal 13 as an activation signal. In FIG. 1, as in FIG. 3, a switch may be provided between the resistor 3 and the negative potential terminal of the DC power supply 1. As a feedback circuit between the drain and gate of the MOSFET 8, only the capacitor 9 may be provided.

  A time constant circuit composed of the resistors 2 and 3 and the capacitor 4 generates a gate voltage of the MOSFET 8.

  The zener diode 5, the resistor 6 and the transistor 7 detect that the gate voltage of the MOSFET 8 is sufficiently biased, and send out an activation signal e.

  In this embodiment, when a DC voltage is applied from the DC power source 1, the inrush current generated to the input capacitor 15 is limited and the charging to the input capacitor 15 is completed and then the load 14 is activated. Send a signal. That is, the gate voltage of the MOSFET 8 that limits the inrush current is detected by the Zener diode 5, the resistor 6, and the transistor 7. The inrush current limiting operation is completed in the MOSFET 8, and the gate voltage of the MOSFET 8 is sufficiently biased to prevent the inrush current. Since the start signal is sent after the operation of the circuit is completed, it is possible to prevent the load from operating during the operation of the inrush current prevention circuit and the load from starting normally or failing to start. can do.

  Next, the operation of the circuit of this embodiment shown in FIG. 1 will be described with reference to the time chart shown in FIG. When a DC power supply is applied, a step-like voltage as shown in FIG. 2A is applied to the input of the inrush current prevention circuit 101. The gate voltage of the MOSFET 8 is charged from the resistor 2 to the capacitor 4, The ramp waveform is as shown in FIG. 2b (see voltage waveform b in the T1 period in FIG. 2).

  Next, when the gate voltage of the MOSFET 8 reaches the threshold value (VTH), the MOSFET 8 is turned on, current starts to flow between the drain and the source, and the drain-source voltage of the MOSFET 8 decreases as the on-resistance of the MOSFET 8 decreases. (Refer to the voltage waveform c in the period T2 in FIG. 2). At that time, the lowering of the drain-source voltage is fed back to the gate terminal of the MOSFET 8 through the capacitor 9 and the resistor 10, and the gate voltage of the MOSFET 8 is maintained at a substantially constant value (in the period T2 in FIG. 2). Voltage waveform b). Therefore, the drain-source current of the MOSFET 8 is controlled to a substantially constant value (see the current waveform d in the period T2 in FIG. 2), and the charging current to the input capacitor 15 is kept constant (inrush current limit). Operation). As a result, the charging voltage waveform of the input capacitor 15 also becomes a ramp waveform.

  After the inrush current limiting operation, the gate voltage of the MOSFET 8 starts to rise again (see the voltage waveform b in the period T3 in FIG. 2), and the gate voltage of the MOSFET 8 is equal to the operating voltage of the Zener diode 5 (Zener voltage VZ). When the sum of the base-emitter voltage (VBE) is reached (after period T4 in FIG. 2), the bipolar transistor 7 is turned on, the potential of the start signal terminal 13 is set to LOW level, and the load 14 is set to LOW level. An activation signal (active state) is sent out. Although not particularly limited, in this example, the start signal terminal 13 connected to the collector of the bipolar transistor 7 is pulled up to a HIGH potential on the load 14 side, for example, and the start signal terminal is turned on when the bipolar transistor 7 is turned on. 13 transitions to the LOW level. Needless to say, the circuit configuration of FIG. 1 may be modified as appropriate so that the activation state of the activation signal is set to the HIGH level.

  As described above, in the present invention, the gate voltage of the MOSFET 8 that limits the inrush current is detected by the zener diode 5, the resistor 6, and the transistor 7, and the inrush current limiting operation in the MOSFET 8 is completed, and the gate voltage of the MOSFET 8 is After the operation of the inrush current prevention circuit is completed after being sufficiently biased, the start signal e is sent to the load 14 to prevent the load from operating during the operation of the inrush current prevention circuit, and the load starts normally. It can prevent the start failure. For example, when a DC / DC converter is used as the load 14, it is possible to avoid the problem that the load does not start because the input voltage is low. On the side of the load 14 that receives the start signal, the start signal may be used as an activation control signal (operation enable signal) or the like of an internal circuit (analog circuit or the like) (not shown) in the load 14, or illustrated in the load 14. It may be used as a reset signal for a logic circuit that is not set, or may be configured to be input to a start-up circuit (not shown) in the load 14 to start operation. Of course, in the present invention, the load 14 is not limited to a DC / DC converter.

  As described above, in the configuration of Patent Document 1, there is a possibility that the gate voltage of the MOSFET 20 exceeds the absolute maximum rating and is damaged due to an abnormal increase in the input voltage. On the other hand, the present invention has a constant voltage function based on the Zener voltage of the Zener diode 5 and the base-emitter voltage of the transistor 7 so that the gate-source voltage of the MOSFET 5 can be determined even if the input voltage fluctuates over a wide range. The voltage is maintained, thereby ensuring stable operation.

  Further, in the configuration of Patent Document 2, a malfunction that a charge completion signal (start-up signal) cannot be activated even after completion of charging of the input capacitor may occur due to the influence of a minute current on the load side. . On the other hand, according to the present invention, since the MOSFET 8 is operated at a constant current to charge the input capacitor 15, even if a minute current is generated in the internal circuit of the load 14, the MOSFET 8 is combined with the charging current. After the charging is completed, the MOSFET 8 is completely turned on, and the supply of a minute current from the load 14 can be continued. Furthermore, in the present invention, the circuit for transmitting the start signal (the transistor 7 and the Zener diode 5) is separated from the circuit through which a minute current flows, and the gate voltage of the MOSFET 8 (the minute current on the load 14 side). Therefore, the activation signal is activated in response to the influence of a minute current flowing through the load 14 and the activation signal is not activated after the capacitor 15 is charged. ing.

  In the configuration of FIG. 1, the MOSFET 8 is an N-channel MOSFET, and the source and drain are connected to the negative potential input terminal (input terminal connected to the negative potential terminal of the DC power supply 1) and the output terminal 12, respectively. Although the transistor 7 is an NPN bipolar transistor, it is needless to say that the polarity of the transistor may be changed. For example, the MOSFET 8 is a P-channel type, the source and drain are connected between the positive potential input terminal (input terminal connected to the positive potential terminal of the DC power supply 1) of the own circuit and the output terminal 11, respectively. And the output terminal 12 are connected to each other, the transistor 7 is a PNP type bipolar transistor, the emitter is connected to the positive potential input terminal of the circuit, one end of the resistor 2 is connected to the negative potential input terminal, and one end of the resistor 3 is connected to the positive potential input terminal. Connected to the potential input terminal (to which the source of the P-channel MOSFET is connected), one end of the capacitor 4 and the resistor 6 is also connected to the positive potential input terminal, and one end of the resistor 10 is connected to the output terminal 11 (of the P-channel MOSFET) The drain may be connected).

  Although the present invention has been described with reference to the above-described embodiments, the present invention is not limited to the configurations of the above-described embodiments, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, including modifications.

It is a figure which shows the structure of one Example of this invention. It is a wave form diagram explaining operation | movement of one Example of this invention. It is a figure which shows the structure of the inrush current prevention circuit of patent document 1 (Unexamined-Japanese-Patent No. 2005-45957). It is a figure which shows the structure of the making circuit of patent document 2 (Unexamined-Japanese-Patent No. 4-88827).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,16 DC power supply 2, 3, 6, 10, 17, 18, 22 Resistance 4, 9, 19, 21 Capacitor 5 Zener diode 7 NPN type bipolar transistor 8, 20 MOSFET
DESCRIPTION OF SYMBOLS 11, 23 Positive potential terminal 12, 24 Negative potential terminal 13 Start signal terminal 14, 25 Load 15, 26 Input capacitor 27 Switch 31, 32, 33, 36 Resistance 34 NPN type bipolar transistor 35 MOSFET (N channel type MOSFET)
36 Zener diode 37, 38 Photocoupler 39 Capacitor 40 DC power supply 41 DC / DC converter 42 Load 101, 201 Inrush current prevention circuit

Claims (11)

A first transistor for limiting inrush current to an input capacitor connected in parallel to a load that receives power from a DC power supply;
A time constant circuit having a voltage dividing resistor and a first capacitor, which divides an input voltage from the DC power source and outputs a divided time constant;
With
The control terminal of the first transistor is connected to the output of the time constant circuit, and is connected to the terminal of the first transistor connected to the load through a feedback circuit including a second capacitor. And
When the inrush current limiting operation is completed and the voltage of the control terminal of the first transistor reaches a predetermined voltage, the second transistor is turned on and outputs a start signal for starting the load as an active state. An inrush current prevention circuit, further comprising: a transistor.   2. The inrush current according to claim 1, further comprising a circuit that controls the voltage of the control terminal of the first transistor to be maintained at a predetermined voltage after the activation signal in the active state is output. Prevention circuit. A constant voltage element inserted between a control terminal of the first transistor and a control terminal of the second transistor;
A resistor connected between a control terminal of the second transistor and a terminal of the first transistor connected to the DC power source;
The inrush current prevention circuit according to claim 1, comprising: First and second input terminals connected to first and second power output terminals of the DC power source, respectively;
First and second output terminals connected to first and second power input terminals of the load, respectively;
An activation signal terminal for supplying an activation signal to the load;
With
An input capacitor is connected in parallel to the first and second power input terminals of the load,
The first input terminal and the first output terminal are connected to each other;
A first transistor connected between the second input terminal and the second output terminal;
A time constant circuit having a voltage dividing resistor and a first capacitor that divides an input voltage between the first and second input terminals and outputs a divided time voltage;
With
The control terminal of the first transistor is connected to the output of the time constant circuit and connected to the second output terminal of the first transistor via a feedback circuit including a second capacitor. Connected to the
A constant voltage element having one end connected to the control terminal of the first transistor;
A resistor connected between the other end of the constant voltage element and the second input terminal;
A second transistor inserted between the activation signal terminal and the second input terminal and having a control terminal connected to a connection point of the constant voltage element and the resistor;
An inrush current prevention circuit comprising:   When the voltage obtained by subtracting the inter-terminal voltage of the constant voltage element from the voltage of the control terminal of the first transistor reaches a voltage at which the second transistor is turned on, the second transistor is turned on, and the start signal terminal 5. The inrush current preventing circuit according to claim 4, wherein a start signal output to the load is activated.   When a DC power supply is applied, a divided voltage waveform generated by the time constant circuit is applied to the control terminal of the first transistor, and when the voltage of the control terminal of the first transistor reaches a threshold value, the first transistor When the first transistor is turned on and the voltage of the terminal connected to the second output terminal of the first transistor starts to decrease, the control terminal of the first transistor becomes constant via the feedback circuit. The inrush current prevention circuit according to claim 4, wherein the current maintained in the first transistor is controlled and the current flowing through the first transistor is controlled to a constant value.   5. The inrush current prevention circuit according to claim 1, wherein the first transistor is a MOSFET.   5. The inrush current preventing circuit according to claim 1, wherein the second transistor is a bipolar transistor.   The inrush current prevention circuit according to claim 1, wherein the feedback circuit includes a resistor connected in series to the second capacitor. An inrush current prevention method for limiting an inrush current to an input capacitor connected in parallel to a load that receives power from a DC power supply,
A voltage divided from the DC power supply is divided into a control terminal of a first transistor that is inserted between the DC power supply and the load and limits an inrush current to the input capacitor.
The terminal voltage of the first transistor connected to the connection point of the input capacitor and the load is negatively fed back to the control terminal of the first transistor,
Outputting an activation signal for activating the load when the inrush current limiting operation is completed and the voltage of the control terminal of the first transistor reaches a predetermined voltage;
A method for preventing inrush current, comprising each step.   11. The inrush current prevention method according to claim 10, wherein after the start signal is output, control is performed so that the voltage at the control terminal of the first transistor is maintained at a predetermined voltage.

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