JP2008294649A - Switch semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switch semiconductor integrated device for changing step-up scaling factor in a boosting circuit depending on a use state of the circuit and reducing a consumption current. <P>SOLUTION: In a charge pump circuit 12, first to fourth depression type FETs 31 to 34, being charging and discharging field-effect transistors, can be on-off-controlled by boosting control signals Vcp1, Vcp2 output from a logic circuit 2. By selecting accordingly on-off states of the first to fourth depression type FETs 31 to 34, charging or discharging operations of first to fourth charging and discharging capacitors 5 to 8 can be selected. As a result, the step-up scaling factor can be changed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a so-called antenna switch for switching a connection between an antenna of a communication device and a transmission circuit or a reception circuit in a mobile phone terminal, a mobile communication device, etc., and more particularly to a switch semiconductor integrated circuit including a booster circuit. The present invention relates to the reduction of power consumption.

In recent years, communication devices such as mobile phone terminals have become widespread and demand has increased. In these wireless devices, antenna switches are widely used for switching transmission / reception, switching frequency bands associated with multiband switching, and switching communication methods. Also, in order to improve the transmission / reception sensitivity of the antenna, a plurality of antenna terminals may be required to switch between the plurality of antennas. In such a case, the antenna switch is configured so that a plurality of antennas can be selected. Is done.
As an element used for such an antenna switch, a PIN diode, a GaAsFET, a MOSFET, or the like is used. Among these, when an FET is used, there are advantages that the IC can be easily downsized and the current consumption can be reduced.
By the way, the performance required for the antenna switch includes an insertion loss characteristic, an isolation characteristic, a low current consumption, a distortion characteristic, and the like.

As the antenna switch, a semiconductor element such as a diode or an FET as described above is used, and thus nonlinear characteristics occur. Therefore, when the transmission signal of the mobile phone terminal passes through the antenna switch, distortion due to this nonlinear characteristic occurs.
For example, a frequency that is an integral multiple of the transmission frequency is called a harmonic, but the power level at which the harmonic is unnecessarily radiated from the antenna is regulated by law, and is extremely low compared to the transmission power. Suppression is required.

  In addition, the WCDMA (Wide Band CDMA) system used in the third generation mobile phones has a specification called blocking characteristics, which is an important index of distortion characteristics. In WCDMA and cdma systems, transmission and reception are performed simultaneously, but when a specific frequency signal is mixed into the antenna switch as an interference signal from the outside, a signal in the reception frequency band is generated due to the distortion characteristics of the antenna switch. End up. Since this causes reception interference, an extremely low level is required as a level for generating an interference reception signal due to distortion. This characteristic is called an IMD (Inter Modulation Distortion) characteristic.

As described above, the antenna switch is strongly required to suppress distortion such as harmonics and IMD.
In order to realize low distortion characteristics in an antenna switch using an FET, a method of cascading transistors constituting the switch circuit in multiple stages and a method of increasing the operating voltage of the FET are conceivable.
The former is easy in design, but has the disadvantage that the area of the IC chip constituting the switch becomes very large and the cost increases. On the other hand, the latter has the advantage that the area of the IC chip constituting the switch can be reduced, but the cell phone terminal has a limitation on the battery voltage, so low voltage operation is required, and the antenna switch is externally provided. It is not possible to simply adopt the technique of increasing the operating voltage of the FET by increasing the supplied power supply voltage.

As described above, as a solution to the two methods having advantages and disadvantages in realizing low distortion characteristics, a booster circuit is built in the antenna switch to boost the power supply voltage supplied from the outside. It is conceivable to increase the operating voltage for actually driving the switch.
As a switch semiconductor integrated circuit including a booster circuit for increasing the operating voltage, for example, Patent Document 1 and Patent Document 2 disclose a circuit including a booster circuit using a clock generator and a charge pump. .

FIG. 4 shows an example of such a conventional circuit. Hereinafter, the conventional circuit will be described with reference to FIG.
This conventional switch semiconductor integrated circuit includes a switch circuit 3A, a logic circuit (denoted as “DEC1” in FIG. 4) 2A for controlling the operation thereof, and a booster circuit 1A for realizing low distortion characteristics. It is configured.

In the switch circuit 3A, the switches S11A and S12A are opened and closed by the two control voltages Vcnt1 and Vcnt2 output from the logic circuit 2A, and the transmission circuit connection terminal 21A or the reception circuit connection terminal 22A is alternatively connected to the antenna terminal 20A. It has come to be.
The logic circuit 2A is supplied with the power supply voltage VDD via the power supply terminal 61A, and outputs control voltages Vcnt1 and Vcnt2 for controlling the opening / closing of the switch S11A or S12A according to the control signal VCTL from the outside. It is configured.
As described above, since the switch circuit 3A is required to have a low distortion characteristic, a high voltage higher than the power supply voltage VDD needs to be supplied from the logic circuit 2A. Is.

The booster circuit 1A shown in FIG. 4 is a configuration example of a five-fold booster circuit. The booster circuit 1A includes a clock generator 11A that outputs rectangular wave signals CLK1 and CLK2 of mutually opposite phases at a predetermined frequency, and a charge pump circuit 12A. It is configured as the main component.
The charge pump circuit 12A includes charging / discharging capacitors C1 to C4, backflow prevention diodes Dx1 to Dx5 to the power supply terminal 61A, and a capacitor C5 for holding a boosted voltage.

In such a configuration, the booster circuit 1A operates as follows.
For example, when one output CLK1 of the clock generator 11A is a voltage (0V) corresponding to the logic value Low, the capacitor C1 is charged with a voltage at the connection point 42A, that is, a voltage substantially equal to the power supply voltage VDD. .
When one output CLK1 of the clock generator 11A becomes a voltage corresponding to the logic value High from the logic value Low, that is, a voltage substantially equal to VDD, the voltage is added to the voltage charged in the capacitor C1, and the connection point A voltage equal to or higher than VDD is output to 43A.

  On the other hand, the charge / discharge timing of the capacitor C2 to which the other output CLK2 of the clock generator 11A is applied at one end is opposite to the charge / discharge timing of the capacitor C1 because CLK2 is in the opposite phase to CLK1. When the connection point 43A is boosted by the capacitor C1, the capacitor C2 is charged with the voltage at the connection point 43A. When the capacitor C2 is discharged, the connection point 44A is further boosted.

As a result of boosting the capacitors C3 and C4 as well as the capacitors C1 and C2, the boosted output Vout of the booster circuit 1A is a voltage obtained by boosting the power supply voltage VDD five times. Since this boosted output Vout is supplied to the switches S11A and S12A via the logic circuit 2A, the switch circuit 3A has a large maximum transmittable power and can obtain good distortion characteristics.
Japanese Patent Application Laid-Open No. 11-55156 (page 5-8, FIGS. 1 to 5) Japanese Patent Laying-Open No. 2005-303337 (page 10-16, FIGS. 1 to 11)

However, in the booster circuit in the above-described conventional switch semiconductor integrated circuit, a voltage higher than the power supply voltage can be obtained, and the switch circuit can obtain very good distortion characteristics, but, for example, low distortion is not required. Even when such a communication method is used, since the voltage is continuously boosted at the time of reception and transmission, there is a problem that the current consumption becomes very large.
For example, Patent Document 2 discloses a switch semiconductor integrated circuit that enables the booster circuit to be turned on / off, stops the operation of the booster circuit in the reception mode, and reduces power consumption. An appropriate boost output cannot be obtained according to the conditions of the time.

  The present invention has been made in view of the above-described situation, and the boosting ratio in the boosting circuit can be varied according to the degree of demand for low distortion characteristics, and the current consumption can be limited according to the use state of the circuit. A switch semiconductor integrated circuit is provided.

In order to achieve the above object of the present invention, a switch semiconductor integrated circuit according to the present invention comprises:
At least one common input / output terminal, two or more individual input / output terminals, and a field effect transistor provided corresponding to each of the individual input / output terminals are alternatively selected in accordance with an external switching control signal. A switching circuit configured to be connected to the individual input / output terminal corresponding to the field effect transistor in the conductive state and the common input / output terminal.
A step-up circuit that generates and outputs a voltage to be a switching control signal of a field-effect transistor constituting the switch circuit;
Based on the operation switching control signal from the outside, the output voltage of the booster circuit is output as the switching control signal to one of the field effect transistors constituting the switch circuit, while based on the operation switching control signal from the outside. A logic circuit configured to output a boost control signal for setting a boost ratio of the booster circuit, and a switch semiconductor integrated circuit comprising:
The booster circuit includes:
A clock generator that repeatedly outputs signals having opposite phases to each other, and a charge pump circuit;
The charge pump circuit is provided with a plurality of diodes connected in series between a power supply and an output holding capacitor, and the connection points of the plurality of diodes are provided according to the number of the connection points. One end of each capacitor is connected, and the output signal of the clock generator can be applied to the other end of each capacitor so that the output signals of the clock generator are in opposite phases to each other in the adjacent capacitors. And
The switch element includes a charge / discharge field effect transistor provided so that the capacitor can be connected to an output stage of the clock generator via a source and a drain. A boost control signal of the logic circuit can be applied to the gate via at least two gate resistors connected in series, and one of the gate resistors connected in series has a gate connected to the ground. The gate control field effect transistors connected to each other are connected in parallel,
By making it possible to select on / off of the charge / discharge field effect transistor in accordance with the boost control signal, the boost magnification can be varied.

  According to the present invention, in the charge pump circuit constituting the booster circuit, the boosting magnification can be varied by configuring the capacitor to be charged / discharged so that a particularly high maximum transmission is possible during transmission. When a communication system that requires power or sufficiently low distortion characteristics is used, the boost ratio of the booster circuit is increased, while a communication system that does not require high maximum transmittable power or good distortion characteristics even during transmission Is used, the boosting ratio of the booster circuit can be lowered so that the necessary minimum boosted voltage can be obtained, thereby preventing the generation of unnecessary current consumption as current consumption according to the circuit usage state, There is an effect that power saving can be realized.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a basic configuration example of a switch semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to FIG.
The switch semiconductor integrated circuit according to the embodiment of the present invention includes a switch circuit 3 that switches a high-frequency signal passing path, and a logic circuit (denoted as “DEC1” in FIG. 1) 2 that controls the operation of the switch circuit 3. Thus, the booster circuit 1 is roughly divided into components.

  The switch circuit 3 is constituted by first and second switches (indicated as “S11” and “S12” in FIG. 1) 15 and 16 as main components. The first and second switches 15 and 16 are made of semiconductor elements such as field effect transistors, and the first and second switches 15 and 16 are switched control signals Vcnt1 input from the logic circuit 2. , Vcnt2 are selectively turned on to connect either the transmission circuit connection terminal 21 or the reception circuit connection terminal 22 as an individual input / output terminal and the antenna 20 as a common input / output terminal. It can become a state.

  In this configuration example, one end of each of the first and second switches 15 and 16 is connected to each other and connected to the antenna 20, while the other end of the first switch 15 is connected to a transmission circuit connection terminal. 21, the other end of the second switch 16 is connected to the receiving circuit connection terminal 22. The first switch 15 is switched by a switching control signal (switching control voltage) Vcnt1 output from the logic circuit 2 as described later, and the second switch 16 is switched by a switching control voltage output from the logic circuit 2. The conduction and non-conduction are controlled by Vcnt2, respectively. The switch circuit 3 has basically the same configuration as the conventional one.

The logic circuit 2 receives the supply of the power supply voltage VDD through the power supply terminal 61 and outputs the output voltage of the booster circuit 1 to be described later in accordance with an operation switching control signal VCTL input from the outside through the control signal terminal 62. Are output as switching control voltages Vcnt1 and Vcnt2 for opening and closing the first and second switches 15 and 16.
The logic circuit 2 outputs two boost control signals Vcp1 and Vcp2 for controlling the boost operation of the boost circuit 1 in accordance with the operation switching control signal VCTL (details will be described later).

The operation switching signal VCTL in the embodiment of the present invention is, for example, a 4-bit digital signal, and each bit is set to the above four signals, that is, the switching control voltage Vcnt1, the switching control voltage Vcnt2, and the boosting control signal. It is preferable to correspond to Vcp1 and the boost control signal Vcp2.
It is arbitrary which bit corresponds to which signal. For example, when the most significant bit (MSB) to the least significant bit (LSB) are expressed as MSB, B2, B1, and LSB for convenience. MSB may correspond to the switching control voltage Vcnt1, B2 to the switching control voltage Vcnt2, B1 to the boost control signal Vcp1, and LSB to the boost control signal Vcp2.

When the switching control signal Vcnt1 is a voltage corresponding to the logical value High and the switching control voltage Vcnt2 is a voltage corresponding to the logical value Low, MSB = 1 and B2 = 0. When the control signal Vcnt1 is a voltage corresponding to the logic value Low and the switching control voltage Vcnt2 is a voltage corresponding to the logic value High, MSB = 0 and B2 = 1 are set, and the logic circuit 2 is configured to correspond thereto. Just do it.
Similarly, when the boost control signal Vcp1 is set to the logical value High and the boost control signal Vcp2 is set to the logic value Low, the switching control signal VCTL is set to B1 = 1 and LSB = 0, but conversely, the boost control. In the case where the signal Vcp1 is set to the logic value Low and the boost control signal Vcp2 is set to the logic value High, the logic circuit 2 may be configured to correspond to B1 = 0 and LSB = 1. Since the configuration of such a logic circuit is conventionally known and well known, a detailed description thereof will be omitted here.

Unlike the prior art, the booster circuit 1 has a variable boosting factor function (details will be described later). In the embodiment of the present invention, a clock generator (denoted as “CLK” in FIG. 1) 11 is used. And a charge pump circuit (denoted as “CP” in FIG. 1) 12.
The clock generator 11 has basically the same configuration as the conventional one, and outputs rectangular wave signals CLK1 and CLK2 having opposite phases to each other in a predetermined cycle. These two rectangular wave signals CLK1 and CLK2 are output. Is input to the charge pump circuit 12.

  The charge pump circuit 12 boosts the rectangular wave signals CLK1 and CLK2 of the clock generator 11 by a so-called charge pump operation according to the boost control signals Vcp1 and Vcp2 from the logic circuit 2, and supplies the boosted voltage to the logic circuit 2. Vout is output.

2 shows a basic circuit configuration example of the charge pump circuit 12, and FIG. 3 shows a more specific circuit configuration example. Hereinafter, the charge pump circuit 12 will be described with reference to these drawings. I will explain.
First, in the basic circuit configuration example shown in FIG. 2, the charge pump circuit 12 includes charge / discharge path switching switch elements S1 to S4 and charge / discharge capacitors (in FIG. 2, "C1" and "C2", respectively). , “C3” and “C4”) 5 to 8 and backflow prevention diodes (in FIG. 2, “Dx1”, “Dx2”, “Dx3”, “Dx4”, and “Dx5”, respectively) 25 To 29 and an output holding capacitor (indicated as “C5” in FIG. 2) 9 are configured as main components.

In FIG. 2, the charge / discharge path switching elements S1 to S4 are represented by switch circuit symbols. FIG. 3 shows a field effect as a specific configuration example of the charge / discharge path switching elements S1 to S4. An example of a circuit configuration in the case where a transistor (hereinafter referred to as “FET”) is used is shown. Except for this portion, the configuration of other circuit portions is the same in any figure.
Therefore, a specific circuit configuration example of the charge pump circuit 12 will be described below with reference to FIG.

  In the circuit configuration example shown in FIG. 3, the charge / discharge path switching elements S1 to S4 (see FIG. 2) are first to fourth depletion type FETs (in FIG. 3) as charge / discharge field effect transistors. Are denoted by “D1”, “D2”, “D3”, “D4”) 31 to 34, and fifth to eighth depletion type FETs (in FIG. 3, respectively) as field control transistors for gate control. “D5”, “D6”, “D7”, “D8”) 35 to 38 and first to eighth gate resistors (in FIG. 3, “R1”, “R2”, “R3”, respectively) , “R4”, “R5”, “R6”, “R7”, and “R8”) 51 to 58).

Hereinafter, the circuit connection will be specifically described. First, the first and third depletion type FETs 31 and 33 are connected to each other at their sources (or drains), and one rectangular wave signal of the clock generator 11 is connected. CLK1 is applied.
The drain (or source) of the first depletion type FET 31 is at one end of the first charge / discharge capacitor 5, and the drain (or source) of the third depletion type FET 33 is at the third charge / discharge. Each of the capacitors 7 is connected to one end.

On the other hand, the first to fifth backflow prevention diodes 25 to 29 are arranged in the forward direction from the power supply terminal 61 to the logic circuit 2 between the power supply terminal 61 and the input stage of the logic circuit 2. First to fifth backflow prevention diodes 25 to 29 are connected in series in this order from the power supply terminal 61 side. That is, the anode of the first backflow prevention diode 25 is connected to the power supply terminal 61, and the cathode of the fifth backflow prevention diode 29 is connected to the input stage of the logic circuit 2.
An output holding capacitor 9 is connected between the connection point between the cathode of the backflow prevention diode 29 and the input stage of the logic circuit 2 and the ground.

  The other end of the first charging / discharging capacitor 5 is connected to a connection point 42 between the cathode of the first backflow prevention diode 25 and the anode of the second backflow prevention diode 26. The other end of the capacitor 7 is connected to a connection point 44 between the cathode of the third backflow prevention diode 27 and the anode of the fourth backflow prevention diode 28.

On the other hand, the boost control signal Vcp1 from the logic circuit 2 is applied to the gate of the first depletion type FET 31 via the first and second gate resistors 51 and 52 connected in series. Yes.
Further, a fifth depletion type FET 35 is connected to the first gate resistor 51 in parallel. That is, the source of the fifth depletion type FET 35 is at one end of the first gate resistor 51, and the drain is the other end of the first gate resistor 51 (the first gate resistor 51 and the second gate resistor 52). And the gate is connected to the ground, respectively.

The boost control signal Vcp2 from the logic circuit 2 is applied to the gate of the third depletion type FET 33 via the fifth and sixth gate resistors 55 and 56 connected in series.
Further, a seventh depletion type FET 37 is connected in parallel to the fifth gate resistor 55. That is, the source of the seventh depletion type FET 37 is one end of the fifth gate resistor 55, and the drain is the other end of the fifth gate resistor 55 (the fifth gate resistor 55 and the sixth gate resistor 56. And the gate is connected to the ground, respectively.

The second and fourth depletion type FETs 32 and 34 are connected to each other at their sources (or drains) so that the other rectangular wave signal CLK2 of the clock generator 11 is applied.
The drain (or source) of the second depletion type FET 32 is at one end of the second charge / discharge capacitor 6, and the drain (or source) of the fourth depletion type FET 34 is at the fourth charge / discharge. Each of the capacitors 8 is connected to one end.
In this way, the first to fourth depletion type FETs 31 to 34 are applied with the rectangular wave signal CLK1 or CLK2 so that the signals from the clock generator 11 to the adjacent ones are in reverse phase with each other. It has become.

Further, the other end of the second charge / discharge capacitor 6 is connected to a connection point 43 between the cathode of the second backflow prevention diode 26 and the anode of the third backflow prevention diode 27, and the fourth charge / discharge capacitor 8. Are connected to a connection point 45 between the cathode of the fourth backflow prevention diode 28 and the anode of the fifth backflow prevention diode 28, respectively.
On the other hand, the boost control signal Vcp1 from the logic circuit 2 is applied to the gate of the second depletion type FET 32 via the third and fourth gate resistors 53 and 54 connected in series. Yes.
A sixth depletion type FET 36 is connected in parallel to the third gate resistor 53. That is, the source of the sixth depletion type FET 36 is at one end of the third gate resistor 53, and the drain is the other end of the third gate resistor 53 (the third gate resistor 53 and the fourth gate resistor 54). And the gate is connected to the ground, respectively.

The boost control signal Vcp2 from the logic circuit 2 is applied to the gate of the fourth depletion type FET 34 via the seventh and eighth gate resistors 57 and 58 connected in series.
In addition, an eighth depletion type FET 38 is connected in parallel to the seventh gate resistor 57. That is, the source of the eighth depletion type FET 38 is at one end of the seventh gate resistor 57, and the drain is at the other end of the seventh gate resistor 57 (the seventh gate resistor 57 and the eighth gate resistor 58). And the gate is connected to the ground, respectively.

Next, the operation of the switch semiconductor integrated circuit having such a configuration will be described focusing on the operation of the booster circuit 1 in particular.
In the booster circuit 1 according to the embodiment of the present invention, the boosting factor can be varied by opening and closing the first to fourth depletion type FETs 31 to 34, and the boosting can be performed up to 5 times.
Specifically, first, in the switch circuit 3, at the time of transmission, that is, the first switch 15 is turned on (conductive state), the second switch 16 is turned off (non-conductive state), and the antenna 20 When the transmission circuit connection terminal 21 is in a conductive state, the maximum transmittable power must be large.

Further, when a communication method requiring low distortion characteristics is applied, the switch circuit 3 needs to be supplied with a sufficiently high voltage. Therefore, in such a case, the booster circuit 1 needs to be operated at a five-fold boost, which is the maximum boost magnification.
In this case, the boost control signals Vcp1 and Vcp2 from the logic circuit 2 are both set to voltages corresponding to the logic value High, and as a result, the first to fourth depletion type FETs 31 to 34 are all turned on.

The first to fourth charging / discharging capacitors 5 to 8 are all charged / discharged by the boost control signals Vcp1 and Vcp2 output from the clock generator 11, so that the voltage boosted five times is supplied to the booster circuit. 1 is output to the logic circuit 2 as the output voltage Vout of 1.
A more detailed operation in this case will be described by paying attention to the first depletion type FET 31.

First, when one boost control signal Vcp1 of the logic circuit 2 is set to a voltage corresponding to the logic value High, the source of the first depletion type FET 31 includes:
As the rectangular wave signal CLK1 of the clock generator 11, a voltage corresponding to the logic value High and a voltage corresponding to the logic value Low are alternately applied at a predetermined repetition period, and the gate is set to the logic value by the boost control signal Vcp1. Since it is High, the gate-source voltage VSG of the first depletion type FET 31 is zero, and it is turned on when CLK1 is the logical value High.

Here, when CLK1 is in the logic low state, the first charging / discharging capacitor 5 is connected to the voltage at the connection point 42, that is, the power supply voltage VDD applied via the first backflow prevention diode 25. Is charged to a voltage approximately equal to.
When CLK1 becomes a logic value High and the first depletion type FET 31 is turned on, the first charge / discharge capacitor 5 adds the logic of the rectangular wave signal CLK1 to the voltage charged at that time. The connection point 42 is boosted by being charged with a voltage corresponding to the value High, and the voltage is applied to the connection point 43 via the second backflow prevention diode 26.

On the other hand, the charging / discharging timing of the second charging / discharging capacitor 6 is such that the rectangular wave signal CLK2 applied to the second depletion type FET 32 has a phase opposite to that of CLK1, so that when the connection point 43 is boosted, The second charging / discharging capacitor 6 is charged by the voltage of the connection terminal 43, and when the rectangular wave signal CLK2 is discharged with the logical value High, the connection terminal 44 is further boosted.
The second to fourth charging / discharging capacitors 6 to 8 are charged / discharged in the same manner as the first charging / discharging capacitor 5 described above. As a result, the output holding capacitor 9 has a power supply. A voltage boosted five times with respect to the voltage VDD is held and output to the logic circuit 2.

  Here, when the boost control signal Vcp1 is a logical value High, the fifth depletion type FET 35 is applied with a voltage corresponding to the logical value High on its source, while its gate is connected to the ground. A negative voltage is applied to the inter-gate voltage VSG, and the fifth depletion type FET 35 is turned off. Therefore, a voltage corresponding to the logical value High of the boost control signal Vcp1 is applied to the gate of the first depletion type FET 31 via the first and second gate resistors 51 and 52 that are set to high resistance values. Will be applied.

When the first and second gate resistors 51 and 52 have high resistance values, the rectangular wave signal CLK1 of the clock generator 11 is prevented from leaking from the drain and source of the first depletion type FET 31 to the gate. The Therefore, the good ON characteristic of the first depletion type FET 31 is maintained, the first charge / discharge capacitor 5 can be efficiently functioned, and the boosted output voltage is reliably held at the connection point 42.
The operation of the fifth depletion type FET 35 as described above and the functions of the first and second gate resistors 51 and 52 are the same as those of the sixth to eighth depletion type FETs 36 to 38, the third and eighth depletion type FETs. The same applies to the gate resistors 53 to 58.

By the way, even at the time of transmission, the maximum transmittable power must be large, but when a communication method that does not require low distortion characteristics is used, for example, a boosting factor of the booster circuit 1 is sufficient to be three times. In this case, the boosting magnification is determined as described below, and a desired boosted voltage can be obtained.
First, the boost control signal Vcp1 from the logic circuit 2 is set to the logic value High, and the boost control signal Vcp2 is set to the logic value Low.
Accordingly, the first and second depletion type FETs 31 and 32 are turned on, while the third and fourth depletion type FETs 33 and 34 are turned off.

Therefore, only the first and second charging / discharging capacitors 5 and 6 are charged / discharged by the rectangular wave signals CLK1 and CLK2 of the clock generator 11. As a result, the output holding capacitor 9 has a voltage boosted three times. Can be obtained.
At this time, the fifth and sixth gate resistors 55 and 56, the seventh and eighth gate resistors 57 and 58 connected to the gates of the third and fourth depletion type FETs 33 and 34, and the seventh The eighth depletion type FETs 37 and 38 function so that the third and fourth depletion type FETs 33 and 34 can maintain good off characteristics.

That is, when the boost control signal Vcp2 from the logic circuit 2 is the logic value Low, the source of the third depletion type FET 33 is set to the potential corresponding to the logic value High and the logic level by the rectangular wave signal CLK1 of the clock generator 11. While the potential is alternately changed to the potential corresponding to the value Low, the gate has the logic value Low.
When the rectangular wave signal CLK1 is a logical value High, the gate-source voltage VGS of the third depletion type FET 33 is a negative voltage, and therefore the third depletion type FET 33 is turned off.

By turning off the third depletion type FET 33, the third charging / discharging capacitor 7 is not charged regardless of the change of the rectangular wave signal CLK1, and therefore the connection terminal 44 is not boosted.
At this time, the source of the seventh depletion type FET 37 is the logic value Low by the boost control signal Vcp2 and the gate is connected to the ground, so the gate-source voltage VGS becomes zero, and the seventh depletion type FET 37 The type FET 37 is turned on and both ends of the fifth gate resistor 55 are short-circuited.

Therefore, the boost control signal Vcp2 is applied to the gate of the third depletion type FET 33 only through the sixth gate resistor 56. In this case, since only the sixth gate resistor 56 is applied, the resistance value is low as compared with the case where the boost control signal is applied via the fifth and sixth gate resistors 55 and 56.
As the gate resistance of the third depletion type FET 33 is lowered in this way, the gate potential is more reliably fixed to a potential corresponding to the logical value Low of the boost control signal Vcp2.
The same applies to the fourth depletion type FET 34. That is, the boost control signal Vcp <b> 2 is applied to the gate of the fourth depletion type FET 34 only through the eighth gate resistor 58.

Further, the rectangular wave signal CLK2 of the clock generator 11 leaks from the source of the fourth depletion type FET 34 to the gate, and the gate potential of the third depletion type FET 56 is shaken in a state of being superimposed on the boost control signal Vcp2. Is prevented by the low resistance sixth and eighth gate resistors 56 and 58. Therefore, the third depletion type FET 33 can maintain a good off characteristic.
In this way, the third and fourth charging / discharging capacitors 7 and 8 are not charged and are not boosted, so that power consumption is suppressed. Therefore, transmission with low power consumption is possible as compared with the case of five times boosting.

On the other hand, at the time of reception, that is, when the first switch 15 is turned off and the second switch 16 is turned on and the antenna 20 and the receiving circuit connection terminal 22 are brought into conduction, large power does not pass through. Also, low distortion characteristics are not required.
Therefore, it is not necessary to supply a high voltage to the switch circuit 3, and in the booster circuit 1, it is appropriate to suppress the power consumption by setting so as not to boost. Therefore, in this case, the boost control signals Vcp1 and Vcp2 of the logic circuit 2 are both set to voltages corresponding to the logic value Low, and as a result, all of the first to fourth depletion type FETs 31 to 34 are turned off.

The first to fourth charging / discharging capacitors 5 to 8 are not charged / discharged by the rectangular wave signals CLK1 and CLK2 of the clock generator 11, and the output holding capacitor 9 has a voltage substantially close to the power supply voltage VDD. Is maintained, and the boost ratio is 1 (not boosted).
As described above, in the switch semiconductor integrated circuit according to the embodiment of the present invention, the boosting rate of the booster circuit 1 is variable in order to supply an appropriate voltage to the switch circuit 3 at the time of transmission, reception, and communication method. Thus, since unnecessary boosting is not performed, power consumption can be suppressed, and in particular, a mobile phone terminal or the like can meet the demand for low current consumption of mobile communication devices.

  In the embodiment of the present invention, the example in which the maximum boosting magnification of the booster circuit 1 is set to 5 has been shown, but it is needless to say that the present invention is not limited to this, and other magnifications may be used. is there.

It is a block diagram which shows the example of a basic composition of the switch semiconductor integrated circuit in embodiment of this invention. It is a block diagram which shows the basic structural example of a booster circuit. It is a circuit diagram which shows the specific circuit structural example of a booster circuit. It is a circuit diagram which shows the structural example of a conventional circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Booster circuit 2 ... Logic circuit 3 ... Switch circuit 11 ... Clock generator 12 ... Charge pump circuit

Claims (1)

At least one common input / output terminal, two or more individual input / output terminals, and a field effect transistor provided corresponding to each of the individual input / output terminals are alternatively selected in accordance with an external switching control signal. A switching circuit configured to be connected to the individual input / output terminal corresponding to the field effect transistor in the conductive state and the common input / output terminal.
A step-up circuit that generates and outputs a voltage to be a switching control signal of a field-effect transistor constituting the switch circuit;
Based on the operation switching control signal from the outside, the output voltage of the booster circuit is output as the switching control signal to one of the field effect transistors constituting the switch circuit, while based on the operation switching control signal from the outside. A logic circuit configured to output a boost control signal for setting a boost ratio of the booster circuit, and a switch semiconductor integrated circuit comprising:
The booster circuit includes:
A clock generator that repeatedly outputs signals having opposite phases to each other, and a charge pump circuit;
The charge pump circuit is provided with a plurality of diodes connected in series between a power supply and an output holding capacitor, and the connection points of the plurality of diodes are provided according to the number of the connection points. One end of each capacitor is connected, and the output signal of the clock generator can be applied to the other end of each capacitor so that the output signals of the clock generator are in opposite phases to each other in the adjacent capacitors. And
The switch element includes a charge / discharge field effect transistor provided so that the capacitor can be connected to an output stage of the clock generator via a source and a drain. A boost control signal of the logic circuit can be applied to the gate via at least two gate resistors connected in series, and one of the gate resistors connected in series has a gate connected to the ground. The gate control field effect transistors connected to each other are connected in parallel,
A switch semiconductor integrated circuit, wherein a step-up magnification can be varied by making it possible to select on / off of the charge / discharge field effect transistor in accordance with the step-up control signal.

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