JP2008288538A - p-TYPE LAYER FOR GROUP III NITRIDE LIGHT EMITTING DEVICE - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device including a semiconductor structure having a light emitting region, a p-type region and an n-type region. <P>SOLUTION: The semiconductor structure includes the light emitting region, the p-type region arranged on a first side of the light emitting region and the n-type region arranged on a second side of the light emitting region. At least 10% of the thickness of the semiconductor structure on the first side of the light emitting region contains an indium. Some examples of such a semiconductor light emitting device can be formed by growing the n-type region, growing the p-type region and growing a light emitting layer arranged between the n-type region and the p-type region. The temperature difference between a part of growing temperature of the n-type region and a part of growing temperature of the p-type region is at least 140°C. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a p-type layer in a group III nitride light-emitting device.

  Semiconductor light emitting devices, including light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes (VCSELs), and edge emitting lasers are among the most efficient light sources currently available. . In producing high brightness light-emitting devices that can operate in the entire visible spectrum, material systems of current interest are III-V semiconductors, in particular gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials. 2 component, 3 component, and 4 component alloys. Group III nitride light emitting devices typically use sapphire, silicon carbide, group III nitride, or metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial methods. Manufactured by epitaxially growing a stack of semiconductor layers with various compositions and dopant concentrations on other suitable substrates. The stack includes one or more n-type layers, eg, doped with Si, formed on a substrate, a light emitting or active region formed on the n-type layer, and an active region. Often includes one or more p-type layers formed, for example doped with Mg. A III-nitride device formed on a conductive substrate can have p and n contacts formed on both sides of the device. III-nitride devices are often fabricated on an insulating substrate such as sapphire with both contacts on the same side of the device.

  FIG. 1 shows a conventional III-nitride LED grown on an insulating substrate. The device of FIG. 1 includes a GaN or AlN buffer layer 31, an n-type GaN layer 32, an InGaN active layer 33, a p-type AlGaN layer 34, and a p-type GaN layer 35, which are sequentially stacked on the upper surface of the sapphire substrate 30. A part of the layers 33, 34 and 35 is removed by etching to expose a part of the n-type GaN layer 32, and then an n-side electrode 6 is formed on the exposed part of the n-type GaN layer 32. The A p-side electrode 5 is formed on the upper surface of the remaining p-type GaN layer 35.

  After the growth of the n-type layer 32, the growth temperature is lowered in order to grow the active layer 33. The growth temperature affects the incorporation of InN into the active layer 33. In general, the lower the growth temperature, the more indium is incorporated into the layer, so a lower growth temperature is required to incorporate indium at the desired level. After growing the active layer 33 at a low temperature, the temperature is raised to grow the p-type AlGaN layer 34 and the p-type GaN layer 35.

  In an embodiment of the present invention, a semiconductor structure includes a light emitting region, a p-type region disposed on a first side of the light emitting region, and an n-type region disposed on a second side of the light emitting region. Including. At least 10% of the thickness of the semiconductor structure on the first side of the light emitting region comprises indium. Some examples of such semiconductor light emitting devices are formed by growing an n-type region, growing a p-type region, and growing a light-emitting layer disposed between the n-type region and the p-type region. Can do.

  FIG. 2 illustrates a portion of a semiconductor structure incorporated into a device, according to an embodiment of the present invention. The n-type region 20 is typically first grown on a suitable growth substrate. The n-type region 20 may be, for example, a preparation layer, such as a buffer layer or a nucleation layer, which may be n-type or not intentionally doped, and after a growth substrate removal or substrate removal. A release layer designed to facilitate thinning of the semiconductor structure, and an n-type device layer designed for specific optical or electrical properties desirable for the light emitting region to emit light efficiently Many layers with various compositions and dopant concentrations can be included.

The light emitting region 22 is grown on the n-type region 20. The light emitting region can include one or more thick light emitting layers or thin light emitting layers. Examples of suitable light emitting regions are, for example, light emitting regions comprising a single light emitting layer having a thickness greater than 50 angstroms, and a thickness separated between 20 angstroms and 30 angstroms each separated by a barrier layer, for example. And a multiple quantum well light emitting region including a multiple quantum well light emitting layer having a thickness. In a III-nitride device configured to emit visible light, particularly light from near ultraviolet to green, the light emitting layer can be InGaN.
A p-type region 24 is grown on the light emitting region 22. Similar to the n-type region 20, the p-type region 24 can include many layers with various compositions, thicknesses, and dopant concentrations.

  The n-type region in III-nitride light emitting devices is often GaN that is typically grown at temperatures above 1000 ° C. The InGaN light emitting layer must be grown at a temperature much lower than the growth temperature of the n-type region so as to capture a sufficient amount of indium. For example, a light-emitting layer configured to emit light from near ultraviolet to green can have an InN composition between 8% and 20% and is grown at a temperature between 850 ° C. and 700 ° C. Often grown at temperatures between 800 ° C. and 715 ° C. V-shaped pit defects are often formed on the growth surface due to the low growth temperature of the light emitting layer relative to the growth temperature of the n-type region.

  If V-shaped pit defects are present on the device surface, these V-shaped pit defects can degrade the performance of the device, for example by interrupting the metallization layer formed on the recessed surface. There is. In general, it is desirable for the p-type layer to have a smooth device surface. Thus, to promote lateral growth and fill any pit defects, the growth temperature of the p-type AlGaN layer or p-type GaN layer 34 adjacent to the active region 33 in the device of FIG. It is higher than the growth temperature of the active region, such as higher than 900 ° C.

However, if the growth temperature of the p-type layer 34 is significantly higher than the growth temperature of the active region 33, other structural defects that may degrade device performance are present in the light emitting layer or in the multiple quantum well active region. It may be formed at the interface between the quantum well layer and the barrier layer.
According to embodiments of the present invention, the growth conditions under which the p-type region is grown, such as the composition of the p-type region and the growth temperature relative to the growth temperature of other parts of the device, the environment, and the precursor used, Selected to improve device performance.

Use of an InN-containing p-type layer rather than a normal p-type GaN layer improves device reliability by preventing or reducing pit expansion and / or formation during the growth of the p-type region. Can do. The InN-containing p-type layer can be grown in an N ₂ environment, an H ₂ environment, or a mixed N ₂ and H ₂ environment. In various embodiments, typically in an InGaN layer or an AlInGaN layer, at least 10%, at least 25%, at least 50%, or at least 60% of the total thickness of the semiconductor structure on the p-side of the light emitting region is indium. including. In some embodiments, a portion of the semiconductor structure on the p-side of the light emitting region is a thin layer superlattice containing InN interleaved with thin layers not containing InN, such as a GaN layer, or It consists of a superlattice of thin layers of relatively high InN composition interleaved with thin layers of relatively low InN composition. In some examples, such superlattices can have an average InN composition across the superlattice layer up to 4% InN.

  In some embodiments, the n-type region is grown at a much higher temperature than the p-type region. A portion of the n-type region is grown at the first temperature, and a portion of the p-type region is grown at the second temperature. The difference between the first temperature and the second temperature is at least 140 ° C, more preferably at least 150 ° C. The second temperature is typically lower than the first temperature. As described above, the n-type region 20 can include a number of layers with different dopant concentrations grown at different temperatures, including layers that are intentionally undoped. The first temperature described above is the growth temperature for a single crystal n-type layer, such as a layer that performs optical or electrical functions such as spreading current or providing an electrical path to a metal contact. . The first temperature described above is not the growth temperature for the nucleation layer or buffer layer, which is often grown at a much lower temperature than the single crystal layer and can be undoped. In some embodiments, the first temperature is at least 1000 ° C. and the n-type layer grown at the first temperature is GaN, AlGaN, or AlInGaN. In some embodiments, the n-type region includes at least one InN-containing layer, such as an InGaN layer or an AlInGaN layer, grown at a temperature below 1000 ° C. In embodiments where the n-type region includes an InN-containing layer, the difference between the growth temperature of a portion of the p-type region (often an InN-containing layer) and the growth temperature of the light emitting layer is less than 150 ° C.

  In some embodiments, a portion of the p-type region 24 grown at a temperature that differs by at least 140 ° C. from the growth temperature in the n-type region is grown at a temperature of at least 830 ° C. In one example, a portion of the p-type region 24 is InGaN having a composition between 0% InN and 4% InN grown at a temperature between 840 ° C. and 910 ° C.

  The p-type region 24 often includes a number of regions that are optimized for different purposes and can include an undoped layer. For example, adjacent to the light emitting region 22, one or more layers for confining current in the light emitting region and capping the light emitting region can be disposed. Such capping and / or confinement layers can have a thickness of less than 100 angstroms, or on the order of about several hundred angstroms, for example from 200 angstroms to 600 angstroms. One or more layers for current spreading and filling of the pits caused by the growth of the light emitting region can be formed on the region closest to the light emitting region. Such a current spreading layer can have a thickness on the order of hundreds to thousands of angstroms, for example, 500 angstroms to 1200 angstroms. One or more contact layers in which metal contacts can be placed can be formed on the current spreading layer. Such a contact layer can have a thickness on the order of several hundred angstroms, for example, from 100 angstroms to 400 angstroms. In some embodiments, the portion of the p-type region 24 grown at a temperature that differs by at least 140 ° C. from the growth temperature in the n-type region is a p-type layer, resulting from current spreading and light emitting region growth. Part or all of the area for the filling of the triggered pits. In various embodiments, a portion of the p-type region 24 grown at a temperature of 140 ° C. that differs from the growth temperature in the n-type region by at least 140 ° C. is the total thickness of the semiconductor structure on the p-side of the light emitting region. It occupies at least 10%, at least 25%, at least 50%, or at least 60%.

  In some embodiments, the p-type region includes an InN-containing layer, such as an InGaN layer or an AlInGaN layer, grown at a temperature below 910 ° C. The temperature mentioned here is the carrier temperature, that is, the temperature of the carrier on which the wafer is placed in the reactor. During the growth of the p-type region, for example, from a relatively low temperature at which the light emitting layer is grown to a relatively high temperature at which the InN-containing p-type layer is grown, or, for example, GaN or low InN near the light emitting region The temperature can be ramped from a relatively high temperature at which the composition layer is grown to a relatively low temperature at which the InN-containing p-type layer is grown. For example, from a relatively high InN composition in the light-emitting layer to a relatively low InN composition in the InN-containing p-type layer, or from, for example, GaN or a low InN composition layer near the light-emitting region in the InN-containing p-type layer The InN composition can be graded up to a relatively high InN composition.

  3 and 4, a “high” warm p-type layer refers to a device in which the difference between the p-layer growth temperature and the n-layer growth temperature is less than 140 ° C., and a “low” warm p-type layer is a p-layer. Refers to a device according to an embodiment of the present invention wherein the difference between the growth temperature and the n-layer growth temperature is at least 140 ° C.

  FIG. 3 is a plot of external quantum efficiency as a function of wavelength for devices incorporating high temperature p-type GaN layers (stars in FIG. 3) and devices incorporating low temperature p-type lnGaN layers (triangles in FIG. 3). It is. External quantum efficiency is the product of device extraction efficiency and device internal quantum efficiency. Internal quantum efficiency is defined as the ratio of photons generated by a light emitting region to carriers given to the light emitting region. The extraction efficiency of the device shown in FIG. 3 is constant, so an increase in external quantum efficiency between the devices shown in FIG. 3 indicates an increase in internal quantum efficiency.

  As shown in FIG. 3, the low temperature p-type lnGaN layer provides improved quantum efficiency over devices having high temperature p-type GaN layers. At a wavelength of 525 nm, for example, a device with a high temperature p-type GaN layer has a relative external quantum efficiency of about 1. For low temperature p-type InGaN layers, the relative external quantum efficiency improves above 1.6. The improvement of the external quantum efficiency is due to the fact that the structural defect is formed in the light emitting layer or at the interface between the quantum well layer and the barrier layer in the active region as a result of the lower growth temperature of the p-type region. This is because it decreases.

  FIG. 4 is a plot of forward voltage at a constant current density as a function of wavelength for a device incorporating a high temperature p-type GaN layer and a device incorporating a low temperature p-type lnGaN layer. As shown in FIG. 4, the forward voltage does not increase significantly when the low temperature p-type layer is replaced with a high temperature p-type GaN layer. For example, at 525 nm, a device with a high temperature p-type GaN layer had a voltage of about 2.89V. The device with the low temperature p-type lnGaN layer had a forward voltage between 2.94V and 2.97V.

An atomic force microscope image of the device providing the data shown in FIGS. 3 and 4 confirms that the pits remain open at the surface of the device in the device with the low temperature p-type lnGaN layer. Those skilled in the art believe that these pits can cause reliability problems for devices having a low temperature p-type layer, but the inventor believes that when the low temperature p-type layer is replaced with a high temperature p-type GaN layer, No significant change in reliability was observed.
The semiconductor structure shown in FIG. 2 can be included in any configuration of the light emitting device. 5 and 6 show a flip chip type device incorporating the structure of FIG. FIG. 7 shows a thin layer device incorporating the structure of FIG.

  FIG. 5 is a plan view of a large bonded device (ie, an area greater than or equal to 1 square millimeter). 6 is a cross-sectional view of the device shown in FIG. 5 as viewed from the axial direction shown. 5 and 6 also show the arrangement of contacts that can be used with the semiconductor structure shown in FIG. The device of FIGS. 5 and 6 is described in more detail in US Pat. No. 6,828,586, which is hereby incorporated by reference. The entire semiconductor structure shown in FIG. 2 and described above in various examples is shown in FIG. 6 as an epitaxial structure 110 grown on a growth substrate 10 that remains as part of the finished device. A plurality of vias are formed such that the n-type contact 114 is in electrical contact with the n-type region 20 of FIG. The p-type contact 112 is formed in the remaining part of the p-type region 24 of FIG. Individual n-type contacts 114 formed in the vias are electrically connected by conductive regions 118. The device may be inverted relative to the orientation shown in FIGS. 5 and 6 and mounted on a mount (not shown) with the contact side down so that light is extracted from the device through the substrate 10. N-type contact 114 and conductive region 118 are in electrical contact with the mount by n-type connection region 124. Under the n-type connection region 124, the p-type contact 112 is insulated from the n-type contact 114, the conductive region 118, and the n-type connection region 124 by a dielectric 116. The p-type contact 112 is in electrical contact with the mount through the p-type connection region 122. Under the p-type connection region 122, the n-type contact 114 and the conductive region 118 are insulated from the p-type connection region 122 by the dielectric 120.

  FIG. 7 is a cross-sectional view of a thin layer device from which the growth substrate is removed. The device shown in FIG. 7 can be formed by growing the semiconductor structure 57 of FIG. 7 on a regular growth substrate 58, bonding the device layer to the host substrate 70, and then removing the growth substrate 58. . For example, the n-type region 20 is grown on the substrate 58. The n-type region 20 includes an optional preparatory layer such as a buffer layer or a nucleation layer, and an optional release layer for promoting growth substrate peeling or thinning of the epitaxial layer after removal of the substrate. be able to. The light emitting region 22 is grown on the n-type region 20 and subsequently grown on the p-type region 24. For example, one or more metal layers 72 including an ohmic contact layer, a reflective layer, a barrier layer, and a junction layer are deposited over the p-type region 24.

  Next, the device layer is bonded to the host substrate 70 through the exposed surface of the metal layer 72. One or more bonding layers (not shown), typically metal, can function as a compatible material for thermocompression or eutectic bonding between the epitaxial structure and the host substrate. Examples of suitable bonding layer metals include gold and silver. The host substrate 70 provides mechanical support for the epitaxial layer after the growth substrate has been removed and provides electrical contact to the p-type region 24. Host substrate 70 generally has a coefficient of thermal expansion (CTE) that matches the coefficient of thermal expansion of the epitaxial layer to be thermally conductive, such as being conductive (ie, less than about 0.1 Ωcm). And sufficiently flat to form a strong wafer bond (ie, the root mean square roughness is less than about 10 nm). Suitable materials include metals such as Cu, Mo, Cu / Mo, and Cu / W and ohmic contacts that include, for example, one or more of Pd, Ge, Ti, Au, Ni, Ag. Semiconductors with metal contacts, such as Si with ohms and ohmic contacts, and ceramics such as AlN, compressed diamond, or diamond layers grown by chemical vapor deposition.

  The device layer can be bonded to the host substrate 70 on a wafer scale, with the entire device wafer bonded to the host wafer, and then individual devices can be cut after bonding. Alternatively, the device wafer can be cut into individual devices and then each device bonded to the host substrate 70 on a die scale.

  In order to form a durable bond at the interface between the host substrate 70 and the metal layer 72, such as a durable metal bond formed at the interface between the metal bonding layers (not shown), for example. And the semiconductor structure 57 is pressure-bonded to each other at high temperature and high pressure. The lower temperature and pressure range for bonding is limited by the strength of the bond produced, and the upper limit is limited by the stability of the host substrate structure, metallization, and epitaxial structure. For example, high temperatures and / or high pressures can cause epitaxial layer decomposition, delamination of metal contacts, breakdown of diffusion barriers, or outgassing of constituent materials of the epitaxial layer. A suitable temperature range is, for example, from about 200 ° C. to about 500 ° C. A suitable pressure range is, for example, from about 100 psi to about 300 psi. Next, the growth substrate 58 is removed.

To remove the sapphire growth substrate, a portion of the interface between the substrate 58 and the semiconductor structure 57 is exposed through the substrate 58 to a high fluence pulsed ultraviolet laser in a step-and-repeat pattern method. . The exposed portion can be isolated by a trench etched through the crystal layer of the device to block the shock wave caused by laser irradiation. The photon energy of the laser is higher than the band gap of the crystal layer adjacent to sapphire (GaN in some embodiments), so the pulse energy is effective for thermal energy within the first 100 nm of the epitaxial material adjacent to sapphire. Is converted to At sufficiently high fluence (ie, greater than about 500 mJ / cm ² ), under conditions where the photon energy is higher than the band gap of GaN and lower than the absorption edge of sapphire (ie, between about 3.44 eV and about 6 eV). The initial temperature within 100 nm rises on a nanosecond scale to a temperature above 1000 ° C., which is high enough for GaN to decompose into gallium and nitrogen gas and release the epitaxial layer from the substrate 58. The resulting structure has a semiconductor structure 57 bonded to the host substrate 70. In some embodiments, the growth substrate can be removed by other means such as etching, lapping, or combinations thereof.

  After the growth substrate is removed, the semiconductor structure 57 can be thinned, for example, to remove the n-type region 20 and the low-material portion closest to the substrate 58. The epitaxial layer can be thinned, for example, by chemical mechanical polishing, normal dry etching, or photoelectrochemical etching (PEC). The top surface of the epitaxial layer can be textured or roughened to increase the amount of light extracted. Next, a contact (not shown) is formed on the exposed surface of n-type region 20. The n contact can be, for example, a grid. The layer directly under the N contact can be implanted with hydrogen, for example, to prevent light emission from a portion of the light emitting region 22 directly under the n contact. To further improve the brightness or conversion efficiency, auxiliary optical elements such as dichroic elements or polarizers known in the art can be applied to the emitting surface.

  FIG. 8 is an exploded view of the packaged light emitting device described in more detail in US Pat. No. 6,274,924. The heat dissipating slug 100 is disposed in the lead frame that has been insert-molded. The insert molded lead frame is, for example, a filled plastic material 105 molded around a metal frame 106 that provides an electrical path. The slug 100 can include an optional reflective cup 102. The light emitting device die 104 may be any of the devices described in the above embodiments, but is attached directly to the slug 100 or indirectly through a thermally conductive auxiliary mount 103. A cover 108, which may be an optical lens, can also be added.

  Although the present invention has been described in detail, those skilled in the art will recognize that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the invention described herein. Will. Accordingly, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.

1 illustrates a prior art group III-nitride LED. 2 shows a device according to an embodiment of the invention. FIG. 6 is a plot of external quantum efficiency as a function of wavelength for devices incorporating a high temperature p-type GaN layer and devices incorporating a low temperature p-type lnGaN layer. FIG. 5 is a plot of forward voltage as a function of wavelength for devices incorporating a high temperature p-type GaN layer and devices incorporating a low temperature p-type lnGaN layer. 1 is a plan view of a large bonded flip chip light emitting device. 1 is a cross-sectional view of a large bonded flip chip light emitting device. 1 shows a thin layer light emitting device. FIG. 4 is an exploded view of a packaged light emitting device.

Explanation of symbols

20 n-type region 22 light-emitting region 24 p-type region 57 semiconductor structure 58 substrate 70 host substrate 72 metal layer

Claims (24)

A semiconductor structure including a light emitting region, a p-type region disposed on a first side of the light emitting region, and an n-type region disposed on a second side of the light emitting region;
A device wherein at least 10% of the thickness of the semiconductor structure on the first side of the light emitting region comprises indium.   The device of claim 1, wherein at least 25% of the thickness of the semiconductor structure on the first side of the light emitting region comprises indium.   The device of claim 1, wherein at least 50% of the thickness of the semiconductor structure on the first side of the light emitting region comprises indium.   The device of claim 1, wherein at least 60% of the thickness of the semiconductor structure on the first side of the light emitting region comprises indium.   The device of claim 1, wherein the light emitting region is configured to emit light having a peak wavelength of at least 500 nm. A portion of the n-type region is grown at a first temperature;
A portion of the indium-containing region on the first side of the light emitting region is grown at a second temperature;
The device of claim 1, wherein the difference between the first temperature and the second temperature is at least 140 degrees Celsius.   The device of claim 1, wherein the region comprising indium on the first side of the light emitting region is one of InGaN and AlInGaN. A method of manufacturing a semiconductor light emitting device, comprising:
Growing a portion of the n-type region at a first temperature;
Growing a portion of the p-type region containing indium at a second temperature;
Growing a group III nitride light emitting layer disposed between the n-type region and the p-type region,
The difference between the first temperature and the second temperature is at least 140 ° C .;
A method characterized by that.   The method of claim 8, wherein the difference between the first temperature and the second temperature is at least 150 degrees Celsius.   The method of claim 8, wherein the first temperature is at least 1000 ° C.   The method of claim 8, wherein the second temperature is at least less than 900 degrees Celsius.   The method of claim 8, wherein the portion of the p-type region grown at the second temperature is AlInGaN.   The method of claim 8, wherein the portion of the p-type region grown at the second temperature is InGaN.   14. The method of claim 13, wherein the InN composition of the portion of the p-type region grown at the second temperature is less than 4%. The method of claim 8, wherein growing the portion of the p-type region comprises growing the portion of the p-type region in an environment comprising N ₂ . The method of claim 8, wherein the group III nitride light-emitting layer is a first quantum well layer.
Growing a barrier layer overlying the first quantum well;
Growing a second quantum well overlying the barrier layer;
A method further comprising:   The method of claim 8, wherein the emissive layer is configured to emit light having a peak wavelength of at least 500 nm. Forming a contact electrically connected to the n-type region and the p-type region;
Placing a cover over the light emitting area;
The method of claim 8, further comprising:   The method of claim 8, wherein the n-type region is a single crystal region. The p-type region is disposed on a first side of the light emitting layer, and the n-type region is disposed on a second side of the light emitting layer;
9. The method of claim 8, wherein the portion of the p-type region grown at the second temperature is at least 10% of the thickness of all semiconductor layers on the first side of the light emitting layer. . A method of manufacturing a semiconductor light emitting device, comprising:
Growing an n-type region comprising at least one layer comprising indium;
Growing a portion of the p-type region at a first temperature;
Growing a group III nitride light emitting layer disposed between the n-type region and the p-type region at a second temperature;
Including
The method wherein the difference between the first temperature and the second temperature is less than 150 ° C.   The method of claim 21, wherein the first temperature is less than 900 degrees Celsius.   The method of claim 21, wherein the portion of the p-type region grown at the first temperature comprises indium.   The method of claim 21, wherein the emissive layer is configured to emit light having a peak wavelength of at least 500 nm.

Images