JP2008271484A - Pulse radio receiving apparatus and synchronization method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse radio receiving apparatus and synchronization method, in which even a non-return-to-zero (NRZ)-coded pulse signal can be synchronized and the number of fingers is reduced, as compared with conventional Early/Late DLL scheme. <P>SOLUTION: A relative difference calculating means 1505 comprises maximum value detecting means 1551A, 1551B, minimum value detecting means 1552A, 1552B and addition means 1553A, 1553B, 1554. The maximum value detecting means 1551A detects a maximum value from among (n) pieces of continuous sample values 1504A inputted from a sample means 1504 and outputs a maximum value Amax. A synchronization control means 1506 generates a delay control signal for controlling the phase of a clock signal so as to synchronize an envelope signal and the clock signal in timing, on the basis of a relative amplitude difference signal iV from the relative difference calculating means 1505, and outputs the delay control signal to a delay means 1503. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a pulse radio receiving apparatus using pulse radio for communication and a synchronization method.

  Pulse wireless communication is a communication method in which communication is performed using extremely short pulses of 1 nanosecond or less. In pulse wireless communication, high-speed communication is possible by transmitting pulses using a wide frequency band of several GHz.

  One problem in communication using such very short pulses is that it is difficult to establish time synchronization. In the pulse radio communication system, the reception side extracts data from the signal transmitted from the transmission side. In order to accurately extract data from the received signal on the receiving side, it is necessary to synchronize the clock on the transmitting side and the clock on the receiving side.

  But usually not synchronized. Therefore, in order to extract desired data on the receiving side, it is necessary to first synchronize with the transmitting side. In addition, in order to improve the throughput, high-speed synchronization establishment is desired. In pulse wireless communication, since the pulse width is as short as 1 nanosecond or less, the jitter at the time of tracking tracking must be suppressed to several hundred picoseconds or less.

  As one of conventional synchronization methods, there is an Early / Late DLL (Delay-Locked Loop) method (see Patent Document 1). FIG. 35 is a diagram showing the configuration of the receiving device described in Patent Document 1. In FIG. As shown in FIG. 35, the received signal is branched into three fingers called “Early”, “On-time”, and “Late” fingers, respectively. Each finger is provided with a correlator, and a local signal having a different phase is input to each correlator to perform a correlation operation with a received signal.

  The phase difference between the “Early” finger and the “On-time” finger is equal to the phase difference between the “Late” finger and the “On-time” finger. The synchronization is realized by controlling the timing of the local signal based on the correlation value between the “Early” finger and the “Late” finger.

  Synchronization is established when the correlation value of the “Early” finger is equal to the correlation value of the “Late” finger. At this time, since the “On-time” finger is located at the peak point of the received signal, data can be demodulated using the correlation value of the “On-time” finger.

  On the other hand, on-off keying (OOK) is known as one of modulation methods used for pulse radio communication. When OOK modulation is used for pulse radio communication, envelope detection can be used as a detection method instead of the correlator as described above. Since envelope detection does not use a local signal, there is an advantage that the configuration is simpler than the detection method using a correlator.

  In pulse wireless communication, an RZ (Return to Zero) code or an NRZ (Non Return to Zero) code may be used as a pulse waveform. In general, an RZ-encoded pulse has a pulse width shorter than a symbol length and a potential returns to 0. An NRZ-encoded pulse is a pulse having the same symbol length and pulse width (see FIG. 2).

Therefore, when NRZ-encoded pulses are transmitted continuously, the potential does not return to 0 between pulses, and a constant amplitude level continues. When NRZ codes are used, pulses can be transmitted without gaps. Therefore, when signals having the same pulse width are used, NRZ codes can improve the transmission rate compared to RZ codes.
US Pat. No. 7,110,473 (FIGS. 5 and 14)

  However, the conventional Early / Late DLL system requires two fingers for synchronization and one finger for demodulation, so that there is a problem that the circuit scale is large and the power consumption is large.

  The present invention has been made in view of the above points, and can be synchronized with an NRZ-encoded pulse signal, and has a reduced number of fingers compared to the conventional Early / Late DLL system. And to provide a synchronization method.

  A first invention is a pulse radio receiving apparatus that receives an NRZ-encoded OOK modulated signal and synchronizes the internally generated clock signal with the received signal, and detects the envelope of the received signal to detect the envelope signal. And a sampling means for sampling the detected envelope signal and outputting a sample value. The phase difference between the sample timings of the two sampling means is set to half the symbol length. With the configuration as described above, the two sample values are compared to adjust the timing of the clock signal.

  At the time of synchronization pull-in, when the difference between the two sample values satisfies a predetermined standard, the sample value of the two sampling means can be exchanged to shorten the time for synchronization pull-in. When the synchronization pull-in is completed, the sample timing of one sample means is at the peak point of the envelope signal, so that the sample value of this sample means can be used for OOK data demodulation.

  At the time of synchronization tracking, the pulse radio receiver further uses a synchronization threshold. This threshold value may be equal to the code determination threshold value used for OOK data demodulation. In order to detect the rising and falling edges of the envelope signal, the sample value of the sample means whose sample timing is at the peak point of the envelope signal is compared with the synchronization threshold. Then, at the detected rising edge and falling edge, the sample value of the other sample means is compared with the synchronization threshold value to perform synchronization tracking.

  In the first invention, the receiving apparatus can accurately synchronize even if ISI (intersymbol interference) occurs in the envelope signal in both the synchronization pull-in and the synchronization tracking. Moreover, the pull-in time in synchronous pull-in can be shortened by exchanging the sample values of the two sample means according to a predetermined standard.

  A second invention is a pulse radio receiving apparatus that receives an NRZ-encoded OOK modulated signal and synchronizes the internally generated clock signal and the received signal, and detects the envelope of the received signal, Detection means for outputting a line signal, automatic gain control means for controlling the amplitude of the received signal so that the input signal level to the detection means is constant, clock generation means for generating a clock signal, and the envelope The first sample means for sampling the signal at the first timing and outputting the first sample value, the magnitude of the first sample value is compared with a predetermined threshold value, and the first comparison result is output. A first threshold value judging means; a second sample means for sampling the envelope signal at a second timing different from the first sample means and outputting a second sample value; and the second sample means. A second threshold value judging means for comparing the magnitude of the threshold value with a predetermined threshold value and outputting a second comparison result; detecting a rising edge of the envelope signal based on the second comparison result; Based on the edge detection means for outputting the detection signal, the first comparison result and the edge detection signal, the amplitude becomes equal to the predetermined threshold at the timing of the clock signal and the rising edge of the envelope signal A first synchronization control means for outputting a first delay control signal, a variable delay means for delaying a clock signal in accordance with the first delay control signal, and the variable delay means so that the timings of the points are aligned. Delay means for further delaying the delayed clock signal and outputting the delayed clock signal to the second sampling means is provided.

  In the second invention, the sample timing of the first sample means is synchronized with the vicinity of the changing point of the envelope signal, so that the sample timing of the second sample means is synchronized with the vicinity of the peak point of the envelope signal. Therefore, the received signal can be demodulated by determining the threshold value of the sample value of the second sampling means by the second threshold value determining means. Further, since the first sample means does not perform demodulation, the operation speed of the first sample means can be slowed down and the power consumption can be suppressed.

  According to a third invention, in the second invention, when the edge detection signal is inputted, hold means for holding the second sample value and outputting the hold value, and delaying the hold value by a predetermined time Second delay means for calculating, a difference between the hold value and the delayed hold value, an adding means for outputting a calculation result, the first delay control signal and the calculation result based on the calculation result. A second delay control signal for controlling the delay amount of the second variable delay means so that the timing of the clock signal inputted to the second sampling means and the timing of the peak point of the envelope signal are aligned. A synchronization control means is further provided.

  In the third invention, the second variable delay means is used to change the phase difference between the clock signal input to the first sample means and the clock signal input to the second sample means, thereby Since the sample timing of the second sampling means can be synchronized near the peak point, it is possible to suppress the degradation of the demodulation performance even when the waveform of the received signal is distorted.

  A fourth invention is a pulse radio receiving apparatus that receives an NRZ-encoded OOK modulated signal and synchronizes the internally generated clock signal with the received signal, and detects an envelope of the received signal to generate an envelope Detecting means for outputting a signal; clock generating means for generating a clock signal; delay means for controlling the phase of the clock signal in accordance with an input delay control signal and generating clock signals of different phases; Sample means for sampling an envelope signal with a clock signal for each different phase and converting it into a sample value for each different phase; and detecting a maximum value and a minimum value from consecutive n sample values for each different phase; Based on the relative amplitude difference signal, a relative difference calculation unit that obtains a difference between the maximum value and the minimum value and generates a relative amplitude difference signal between sample points of different phases based on the difference. As the timing of the envelope signal and the clock signal are synchronized, and a synchronization control unit for the clock generating means generates a delay control signal for controlling the phase of the clock signal generated and output to the delay unit.

  In the fourth invention, since synchronization control is performed based on the relative amplitude difference, synchronization is possible without depending on the received signal strength.

  A fifth invention according to the fourth invention further comprises a synchronization state detection unit that detects a synchronization state based on a relative amplitude difference signal from the relative difference calculation unit and a predetermined threshold, and the synchronization control means includes the synchronization control unit, Based on the synchronization state detected by the synchronization state detection means, the control of the phase of the clock signal is held when the synchronization state is established.

  In the fifth invention, since the phase control of the clock signal in the delay means is held when the clock signal and the received signal are synchronized, the synchronization tracking can be stabilized.

  According to a sixth invention, in the fourth invention, based on the relative amplitude difference signal obtained by the relative difference calculation unit, a plurality of sample values of different phases from the sampling means are selected to obtain binary demodulated data. Demodulating means for generating is further provided.

  In the sixth invention, by using the sample value from the sample means for demodulation, demodulation can be performed simultaneously with synchronization tracking.

  As described above, according to the first invention, in both the synchronization pull-in and the synchronization tracking, the receiving apparatus can accurately synchronize even when the envelope signal has ISI (intersymbol interference). Moreover, the pull-in time at the time of synchronous pull-in can be shortened by exchanging the sample values of the two sample means according to a predetermined standard.

  Further, according to the second invention, the sample timing of the first sample means can be synchronized with the vicinity of the peak point by synchronizing the sample timing of the first sample means in the vicinity of the change point, The received signal can be demodulated by determining the threshold value of the sample value of the second sampling means by the second threshold value determining means. Further, since the first sampling means does not perform demodulation, the operating speed of the first sampling means can be slowed down and the power consumption can be suppressed.

  Further, according to the third invention, the second variable delay means is used, and the phase difference between the clock signal input to the first sample means and the clock signal input to the second sample means is made variable. As a result, the sample timing of the second sampling means can be synchronized with the vicinity of the peak point, so that deterioration in demodulation performance can be suppressed even when the waveform of the received signal is distorted.

According to the fourth aspect of the invention, since synchronization control is performed based on the relative amplitude difference, synchronization is possible without depending on the received signal strength.
According to the fifth aspect of the invention, when the clock signal and the received signal are synchronized, the phase control of the clock signal in the delay means is held, so that synchronization tracking can be stabilized. Furthermore, according to the sixth aspect, by using the sample value from the sample means for demodulation, demodulation can be performed simultaneously with synchronous tracking.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiment, the same components are denoted by the same reference numerals, and the description thereof will be omitted because it is duplicated. The signal used for communication is assumed to be OOK modulated and NRZ encoded.

  Before describing the embodiment of the present invention, the reason why synchronization is difficult when the conventional Early / Late DLL method is applied to an NRZ-encoded pulse will be described with reference to FIG.

  FIG. 36 is a diagram showing an envelope signal when the NRZ-encoded OOK modulation signal “101” is received and the positional relationship between the Early finger and the Late finger on the time axis. In the figure, the sample values of each finger at times T1 and T2 are E1, L1 and E2, L2.

  The Early / Late DLL method is a method for controlling the timing of a local signal in accordance with the magnitude relationship between E1 and L1, and E2 and L2, but at time T1, E1> L1, whereas time At T2, E2 <L2. As described above, since the Early / Late determination results are contradictory at times T1 and T2, synchronization becomes difficult.

  Although not shown, when the NRZ format OOK modulation signal “1” is continuously received, interdetection interference (ISI) occurs between adjacent pulses in the detection means, so that the detection means is substantially flat. Output envelope signal. The amplitude of the envelope signal is substantially equal to the amplitude at the peak point of the envelope signal when only one OOK modulation signal “1” is received.

  At this time, according to the synchronization method of the prior art, it is difficult to obtain the amplitude difference between the Early finger and the Late finger, so that synchronization is also difficult.

(Embodiment 1)
FIG. 1 is a block diagram of a pulse radio transmission apparatus 100 that uses OOK modulation. In FIG. 1, the transmission apparatus 100 includes a channel encoder 104, an interleaver 106, an OOK modulator 108, a pulse generator 110, an oscillator 112, a power amplifier 114, and an antenna 116.

  Bit string 102 represents input data. This data includes any one or combination of text, video, image, audio, and the like. The bit string 102 is sent to the channel encoder 104. The channel encoder 104 performs all kinds of forward error correction (FEC) encoding such as a block code and a convolutional code on the bit sequence 102, and outputs encoded bits.

  The interleaver 106 may be used after the channel encoder 104 to distribute the coded bits, and can prevent burst errors in the received signal at the receiving device. Interleaver 106 is optional and can be excluded from transmitter 100 in other embodiments. The OOK modulator 108 modulates the interleaved bit string using an RZ format or NRZ format OOK modulation method, and outputs an OOK modulation signal 109.

  Next, the OOK modulation signal 109 is sent to the pulse generator 110, and a transmission pulse 111 is generated based on a predetermined pulse waveform (for example, a Gaussian pulse). The oscillator 112 converts the output transmission pulse 111 to a predetermined frequency band at the carrier frequency fc.

  Next, the transmission pulse 111 is input to the power amplifier 114. The power amplifier 114 is designed to increase the transmission power to a predetermined level. Finally, the amplified signal 118 is radiated by the antenna 116.

  FIG. 2 shows a pulse train 200 of an OOK modulated signal 109 that has been OOK-modulated in the RZ format and the NRZ format. In this case, the interleaved bit train is “01011010”. OOK is a simple modulation scheme. In this case, the OOK modulator 108 sends a pulse when the input bit is “1”, and sends nothing when the input bit is “0”.

  In OOK modulation, the symbol length Ts202 and the bit length Tb (not shown) are the same. Each pulse has a constant pulse width Tp, but Tp is different between RZ type OOK modulation and NRZ type OOK modulation.

  In the NRZ OOK modulation, the pulse width Tp is equal to Ts during the period in which the pulse amplitude shown in FIG. 2 is A_N204. On the other hand, in the RZ format OOK modulation, the pulse width Tp is T206 in a period in which the pulse amplitude is A_R208, and 0 <T <Ts. When the signal power is made equal between the RZ format and the NRZ format, the product (T206 * A_R208) and the product (Ts202 * A_N204) are made equal. The pulse width is a period in which the pulse amplitude is A_R208 as described above. In other words, the pulse width is a period from the amplitude 0 to the next amplitude 0 in the RZ format OOK modulation.

  The pulse train 200 is input to the pulse generator 110, and a transmission pulse 111 having a carrier frequency fc like the pulse train 300 of FIG. 3 is obtained. The parameters Ts202, T206, A_N204, and A_R208 do not change, and the rectangular pulse of bit “1” becomes a sine wave signal having the carrier frequency fc302.

  FIG. 4 is a block diagram of a pulse radio receiving apparatus 400 having OOK demodulation and envelope detection. In FIG. 4, a receiving apparatus 400 includes an antenna 402, a band filter (BPF) 404, an automatic gain control means (AGC) 406, a detection means 408, a comparison means 410, a synchronization control means 412, a clock generation means 414, and a deinterleaver 416. And a channel decoder 418.

  The transmission signal is received by the antenna 402 and sent to a BPF 404 having a carrier frequency fc302 and a predetermined bandwidth BW. The BPF 404 can remove noise other than the desired frequency band [fc−BW / 2, fc + BW / 2] and other interference signals. AGC 406 adjusts the amplitude of the received signal based on channel measurements such as signal-to-noise ratio (SNR).

  Next, the detection means 408 detects the envelope signal 409 of the received signal. The comparison unit 410 samples the envelope signal 409 with the timing signal 411 received from the synchronization device 412. The comparison means 410 compares the sample value of the envelope signal 409 with a predetermined threshold Th in order to perform OOK data demodulation. When the sample value is greater than or equal to the threshold Th, bit “1” is detected. Bit “0” is detected when the sample value is less than the threshold Th. The threshold Th may be constant or may be adjustable according to channel quality measurement.

  Therefore, in order for the comparison unit 410 to accurately demodulate the OOK data, the accurate timing signal 411 is extremely important. The detection unit 408 outputs an envelope signal 409 to the synchronization control unit 412 in order to capture and follow the timing of the received signal. The clock generation unit 414 supplies the clock signal 413 to the synchronization control unit 412.

  Here, the clock signal 413 has a clock frequency equal to the symbol rate Rs of the transmission device 100 (Rs = 1 / Ts). The synchronization control means 412 synchronizes the timing of the received envelope signal 409 and the timing of the clock signal 413 and outputs the timing signal 411 to the comparison means 410 as data sampling timing.

  In the subsequent stage of the comparison unit 410, the deinterleaver 416 deinterleaves the demodulated bits 415, and the channel decoder 418 decodes the deinterleaved signal and outputs decoded information bits 420.

(Envelope detection of NRZ OOK modulation signal with ISI)
FIG. 5 shows an example of the detection means 408. The detection means 408 includes a diode 502 and a low pass filter (LPF) 504. Further, the detection means 408 can detect the envelope of the received signal 506 in FIG. 5 even with other circuit configurations. For example, when the transmission signal 118 of the bit string “01011010” is received by the receiving device 400, the envelope signal 409 output from the LPF 504 is as shown in FIG.

  Here, when the transmission signal 118 is modulated by RZ format OOK modulation (T <α * Ts), an envelope having pulses 602, 604, 606, and 608 of bit “1” is obtained at the output of the LPF 504. Assume that That is, the pulse width T_R610 <Ts of the output of the LPF 504. α is a predetermined ratio within the range of (0, 1). Each pulse has a complete cycle with a rising edge from amplitude 0 to peak point P and a falling edge from peak point P to amplitude 0. The pulse width T_R610 of each pulse is equal to or shorter than the code duration Ts202. In the present embodiment, in the RZ format OOK modulation, the pulse width T_R610 indicates a period from amplitude 0 to the next amplitude 0 as shown in FIG.

  The clock signal 413 generates a sampling frequency Rs for sampling the envelope signal 409. Since each pulse 602, 604, 606 and 608 has a complete cycle without ISI, the prior art DLL uses the amplitude difference between the samples from the Early and Late fingers to determine the received signal for synchronization. The timing can be adjusted.

  When synchronization is established, the data sampling time T_sample 612 is precisely the timing of the peak points P of the pulses 602, 604, 606 and 608. As a result, the comparison unit 410 can compare the sample value from T_sample with the threshold value Th and accurately detect data.

However, when the transmission signal is modulated by the NRZ format OOK modulation, the envelope signal of bit “1” output from the LPF 504 becomes pulses 614, 616, 618 and 620 shown in FIG. Here, pulse 614 has a complete cycle with a rising edge from amplitude 0 to peak point P and a falling edge from peak point P to amplitude 0. The pulse width T_N 622 is larger than the symbol length Ts202.
In contrast, pulses 616, 618 and 620 in FIG. 6 are not complete cycles due to ISI with consecutive bits “1” because pulse width T_N 622 is greater than symbol length Ts202.

  As illustrated in FIG. 6, severe ISI occurs in pulses 616, 618 and 620 when bit "1" continues. Therefore, the falling edge of pulse 616 overlaps with the rising edge of pulse 618, and the falling edge of pulse 618 overlaps with the rising edge of pulse 620. Note that, in the pulses 616, 618, and 620, the pulse width is the same as that of the T_N 622, but since the pulses are continuous, the pulse widths also overlap.

  Finally, the rising and falling edges of pulses 616, 618 and 620 are indistinguishable except for the rising edge of pulse 616 and the falling edge of pulse 620. Thus, envelope signal 409 has a substantially flat amplitude level within the falling edge of pulse 616 and the rising edge of pulse 620.

  As a result, in the prior art DLL, it is difficult to accurately adjust the timing of the received signal even if the amplitude difference between samples by the Early finger and the Late finger is used. If the synchronization is not accurate, the data sampling time T_sample 624 will not be at the timing of the peak point P of the pulses 614, 616, 618 and 620. Eventually, a large amount of detection errors occur in the data detection by the threshold value comparison of the comparison means 410.

  At the output of the LPF 504, the pulse width (T_R610 or T_N622) of the single bit “1” depends on the pulse width Tp of the received OOK signal and the transfer function of the LPF 504. When Tp = T206> = α * Ts in RZ OOK modulation, the pulse width T_R610 of bit “1” may be larger than the symbol length Ts.

  Therefore, even if RZ-type OOK modulation is performed, if bit “1” continues, ISI may occur. The RZ-format OOK modulation ISI in the case of T> = α * Ts can be handled in the same manner as the NRZ-format OOK modulation ISI.

(Synchronizer with two sample means)
In the present invention, in the NRZ format OOK modulation or the RZ format OOK modulation, T> = α * Ts, and in order to realize accurate synchronization even in the presence of ISI, A corresponding synchronization method is proposed. This synchronization method is applicable to both synchronization pull-in and synchronization tracking for signals over multipath channels or noisy channels. The time difference between the sample timings of the two sampling means is fixed to be half the symbol length as "Ts / 2".

  FIG. 7 is a block diagram showing a synchronizer having two sample means. In FIG. 7, the synchronization device 412 includes a splitter 701, two analog-to-digital converters (ADC) 704 and 706, a variable delay unit 708, a fixed delay unit 710, and a delay control unit 712.

  The envelope signal 409 is branched into two identical envelope signals 702 and 703 at the output of the splitter 701. One envelope signal 702 is input to the ADC (A) 704, and the other envelope signal 703 is input to the ADC (B) 706. The ADC (A) 704 samples the envelope signal 702 at the timing of the signal 709 and converts an analog signal into a digital signal 705. The ADC (B) 706 samples the envelope signal 703 at the timing of the signal 711 and converts the analog signal into a digital signal 707.

  The two digital signals 705 and 707 are input to the delay control means 712 for synchronization processing. The delay control means 712 outputs a timing signal 411 to the comparison means 410 for detecting OOK data. The delay control unit 712 also detects a timing shift between the clock signal 413 and the peak point of the envelope signal 409 and sends a delay control signal 713 to the variable delay unit 708 in order to align the timings of both.

  The variable delay unit 708 receives the clock signal 413 from the clock generation unit 414 and adjusts the timing of the clock signal 413 based on the delay control signal 713 from the delay control unit 712. The clock signal 413 is a square pulse train having a clock frequency Rs, and the pulse width of each square pulse is smaller than Ts. Both the rising edge and falling edge of each square pulse can be used as the sampling timing of the timing signal 709.

  The time difference between the sample timings of the two ADCs is Ts / 2, and the fixed delay means 710 delays the timing signal 709 by Ts / 2 and outputs the timing signal 711.

  In the present invention, the threshold value Th is also used for synchronous tracking. This threshold Th may be fixed to a predetermined value, or may be adjustable based on channel quality. Thus, in FIG. 7, there is an optional input signal 714 for the delay control means 712. When the threshold value is fixed, the input signal 714 is not necessary. However, when the threshold value is adjusted, the threshold value Th adjusted using the input signal 714 must be sent to the delay control means 712.

  FIG. 8 is a block diagram of another synchronizer 720 similar to synchronizer 700 of FIG. The only difference between FIG. 7 and FIG. 8 is that the fixed delay means 710 is moved between the splitter 701 and the ADC (B) 706. Therefore, the fixed delay means 710 gives a timing delay of Ts / 2 to the envelope signal 703. Next, the same timing signal 709 is sent to ADC (A) 704 and ADC (B) 706 in FIG.

(OOK Modulation Signal Capture Method with ISI)
Synchronization pull-in is a processing stage in which a transmission signal is acquired at the time of link setup. The synchronization at this stage is usually coarse, but the acquisition time is fast. The bit sequence of the preamble portion of each data packet can also be designed to make signal acquisition fast and accurate. In the present invention, this bit string is designed so that the bit “1” does not continue so that the synchronization accuracy does not deteriorate due to the influence of ISI.

  For example, in the case of synchronous pull-in, the bit string is set as “1010... 10”. When bits “1” and “0” are alternated, as shown in FIG. 6, in the NRZ OOK modulation, the ISI can be reduced when the pulse width T_N <= 2Ts (Ts: symbol length). When the pulse width T_N 622 is longer than 2Ts, more bits “0” can be inserted between two bits “1” in a bit string such as “1001001... 100”.

  An example of the sampling of the envelope signal by the two ADCs of the synchronization device 700 (FIG. 7) in the synchronization pull-in is shown in FIG. FIG. 9 shows an envelope signal 409 of the NRZ format OOK modulation signal when the bit string “1010... 10” is transmitted.

  Each bit “1” corresponds to one pulse (eg, pulses 802, 804 and 806) in envelope signal 409. That is, as in the pulses 616, 618, and 620 in FIG. 6, the case where “1” continues is excluded, and the pulse width of each pulse is T_cycle808 or less, and in this case, T_cycle = 2 * Ts. The pulse width indicates a period from amplitude 0 to the next amplitude 0. In addition, timing signals in the ADC (A) 704 and the ADC (B) 706 are also shown by the sampling frequency Rs in FIG.

  The time difference between the timing signal of ADC (A) 704 and the timing signal of ADC (B) 706 is Ts / 2 810,812. For each T_cycle, two consecutive sample values A1 and A2 from the ADC (A) 704 and two consecutive sample values B1 and B2 from the ADC (B) 706 are obtained.

  FIG. 10 is an example of a flowchart of the synchronization pull-in method of the synchronization device 700 of FIG. First, in S902, within the same T_cycle, the ADC (A) 704 samples two consecutive sample values A1 and A2 using, for example, the rising edge of the timing signal 709, and the ADC (B) 706 The signal 711 is used to sample two consecutive sample values B1, B2.

  Next, in S904 and S906, | A1-A2 | and | B1-B2 | are compared in the same T_cycle. For example, in FIG. 10a, | newA1-newA2 | is compared with | newB1-newB2 |. Here, if | A1-A2 | is larger than | B1-B2 | as shown in FIG. 10A, the sample values from ADC (A) 704 and ADC (B) 706 are exchanged in S910. That is, the delay control unit 712 replaces the sample values A1, A2, B1, and B2. As a result, subsequent calculations can be shared.

  For example, as shown in FIG. 10a, the current A1 (newA1), B2 (oldB2) in the previous T_cycle, the current A2 (newA2), B1 in the previous T_cycle (oldB1), and the current B1 (newB1) A1 (oldA1), current B2 (newB2) in the previous T_cycle, and A2 (oldA2) in the previous T_cycle are switched. The reason for exchanging sample values will be described later.

  In S906, as shown in FIG. 10b, when | A1-A2 | is smaller than | B1-B2 |, the flow of processing proceeds to S912 without performing the replacement (replacement) of the sample values by the delay control unit 712. . As shown in FIG. 10c, if | A1-A2 | is equal to | B1-B2 |, in S908, the delay control means 712 generates a delay control signal 713 of ¼ of Ts (described later). Ts / 4) and sent to the variable delay means 708 to adjust the timing of the clock signal 413.

  Next, the processing flow returns to S902, and the next four sample values A1, A2, B1, and B2 are sampled at the next T_cycle using the adjusted timing signals 709 and 711, respectively.

  In S912, the result of | A1-A2 | is compared with a predetermined value X. In this case, X is 0 or a predetermined positive number. If | A1-A2 | is less than or equal to X, a signal is captured and the process flow proceeds to end S924.

  If | A1-A2 | is greater than X, no signal is captured. Therefore, in order to send the delay control signal 713 to the variable delay means 708 and adjust the timing of the clock signal 413, the process proceeds to the following steps.

  In S914, S916, and S920, the amplitudes of the sample values A1 and A2 are compared with each other, and the amplitudes of the sample values B1 and B2 are also compared with each other. When the result of (A1 <A2 and B1 <B2) or (A1> A2 and B1> B2) is obtained, the delay control signal 713 is set to a predetermined negative value “−D” described later in S918. Then, the signal is sent to the variable delay means 708 to shift the timing of the clock signal 413 forward.

  If the result of (A1 <A2 and B1> B2) or (A1> A2 and B1 <B2) is obtained, the delay control signal 713 is set to a predetermined positive value “+ D” in S922, and the variable delay is set. It sends to the means 708 and shifts the timing of the clock signal 413 backward.

  After S918 or S922, the process flow returns to S902 to use the adjusted timing signals 709 and 711 to sample the next four sample values A1, A2, B1, B2 at the next T_cycle.

  When the signal is finally captured in S924, the sampling time of ADC (B) 706 is at the timing of the peak point P of each pulse.

  Note that the amplitude of these four sample values may be distorted due to channel noise. When the amplitude is distorted, synchronization accuracy becomes insufficient due to synchronization pull-in. In order to reduce noise distortion, a method of using an average value of a plurality of sampled sample values has been conventionally used. For example, N T_cycles can be grouped and averaged by synchronous pull-in.

  Since four sample values A1, A2, B1, and B2 are obtained for each T_cycle, N sample values A1 are obtained for N T_cycles. The average value (A1_ave) can be obtained by calculating the sum of N sample values A1 and dividing the sum by N. Using the same averaging method, average values A2_ave, B1_ave and B2_ave can be obtained from N sample values A2, N sample values B1 and N sample values B2, respectively.

  Therefore, when averaging is performed, synchronous pull-in becomes possible by replacing these four average values A1_ave, A2_ave, B1_ave, and B2_ave with the sample values A1, A2, B1, and B2 of FIG. When averaging is performed, it can be seen that only one delay adjustment is performed for N T_cycles. If no averaging is performed, the N T_cycles can perform N delay adjustments. Therefore, it is difficult to achieve both accurate synchronization and fast acquisition time.

  Here, the predetermined value D in S918 or S922 indicates the size of the delay adjustment step in the synchronization pull-in. As D is larger, the delay adjustment step for the variable delay means 708 can be increased to shorten the acquisition time. However, when the timing of the clock signal 413 is close to the timing of the peak point of the envelope signal 409, the variation from the peak point increases as D increases.

  Further, the magnitude D of the delay adjustment step may be fixed or may vary. When the variable D is appropriately designed, the fluctuation from the peak point of the envelope signal 409 can be reduced while shortening the acquisition time. For example, initially, the step D is increased to increase the synchronous pull-in speed, and as the pull-in is performed, the magnitude of the value D can be gradually decreased to reduce the fluctuation.

  As a supplementary explanation of the flowchart of FIG. 10, here, a synchronization pull-in method when “010101” is transmitted will be described. In S902, the envelope signal 409 is sampled in the ADC (A) 704 and the ADC (B) 706 to obtain sample values A1, A2, B1, and B2, respectively. At this time, the magnitude relationship between the sample values A1, A2, B1, and B2 is as shown in, for example, FIGS. 10_a, 10_b, and 10_c.

  In step S904, it is determined whether “| A1-A2 |> | B1-B2 |” is satisfied. In the case of FIG. 10A, since this condition is satisfied, the determination is “Yes” and the process proceeds to S910. On the other hand, in the case of FIG. 10B or FIG. 10C, “No” determination is made, and the process proceeds to S906.

  In step S906, it is determined whether “| A1-A2 | <| B1-B2 |”. In the case of FIG. 10B, since this condition is satisfied, “Yes” determination is made, and the process proceeds to S912. On the other hand, in the case of FIG. 10C, “No” determination is made, and the process proceeds to S908.

  Referring to FIG. 10_c, the relationship between the sample values A1, A2, B1, and B2 is “| A1-A2 | = | B1-B2 |”. At this time, ADC (A) 704 and ADC (B) 706 It can be seen that the sample timing is exactly Ts / 4 shifted from the peak point of the envelope signal 409. Accordingly, in S908, the timing of the clock signal is shifted by Ts / 4 in the variable delay means 708. By doing so, either the ADC (A) 704 or ADC (B) 706 sample timing comes to the timing of the peak point of the envelope signal. Thereafter, the process returns to S902.

In S910, the sample values A1, A2, B1, and B2 are exchanged. The relationship between the sample values in S910 is as shown in FIG. FIG. 10a shows the pre-replacement procedure. In this state, when sample values are exchanged according to the above-described exchange procedure, the result is as shown in FIG.
Here, comparing FIG. 10_d and FIG. 10_b, it can be seen that the magnitude relationships of the sample values A1, A2, B1, and B2 match. That is, in S910, the sample value replacement process (replacement) is performed in order to unify (unify) the process (calculation formula) in the next S912. Next, the process proceeds to S912.

  In S912, it is determined whether “| A1-A2 | <= X”. For example, FIG. 10_e and FIG. 10_f may be used as the magnitude relationship between the sample values in S912. In the case of FIG. 10_f, since this condition is satisfied, the determination is “Yes”, the process proceeds to S924, the synchronization pull-in is completed, and the process proceeds to S924. On the other hand, in the case of FIG. 10_e, “No” determination is made, and the process proceeds to S914.

  In S914, it is determined whether “A1 <A2”. In S912, there is a case in FIG. 10_g where “| A1-A2 | <= X” is not satisfied. The difference between FIG. 10_e and FIG. 10_g is the magnitude relationship between A1 and A2. In S914, FIG. 10_e and FIG. 10_g are distinguished. In the case of FIG. 10E, since the condition “A1 <A2” is satisfied, “Yes” determination is made, and the process proceeds to S916. On the other hand, in the case of FIG. 10_g, “No” determination is made, and the process proceeds to S920.

  In S916, it is determined whether “B1 <B2”. The state satisfying “A1 <A2” in S914 may be the case of FIG. The difference between FIG. 10_e and FIG. 10_h is the magnitude relationship between B1 and B2. In the case of FIG. 10_h, since the condition “B1 <B2” is satisfied, the determination is “Yes” and the process proceeds to S918. On the other hand, in the case of FIG. 10_e, “No” determination is made, and the process proceeds to S922.

  Also in S920, it is determined whether “B1 <B2”. In S914, “A1 <A2” may not be satisfied in FIG. The difference between FIG. 10_g and FIG. 10_i is the magnitude relationship between the samples B1 and B2. In the case of FIG. 10_i, since this condition is satisfied, the determination is “Yes” and the process proceeds to S922. On the other hand, in the case of FIG. 10_g, “No” determination is made, and the process proceeds to S918.

  In S918, clock signal timing control is performed. In S918, the timing of each sample value is in the state of FIG. 10_g or FIG. 10_h. In these two states, the sampling timing of the sample value B1 is delayed with respect to the peak position of the envelope signal 409. Therefore, the variable delay means 708 performs control (−D) to reduce the delay amount. Thereafter, the process returns to S902 again.

  Also in S922, the timing control of the clock signal is performed. In S922, the timing of each sample value is in the state of FIG. 10_e or FIG. 10_i. In these two states, the sampling timing of the sample value B2 is advanced with respect to the peak position of the pulse. Therefore, the variable delay means 708 performs control (+ D) to increase the delay amount. Thereafter, the process returns to S902 again.

(Tracking method of NRZ OOK modulation signal with ISI)
Synchronous tracking is a processing step of tracking the transmission signal after synchronization pull-in. Synchronization tracking is usually required to achieve fine synchronization control based on information messages in the data payload. Since the bit string of the data payload cannot be predicted, the synchronization tracking method must be effective for random bit strings.

  This is different from the synchronous pull-in in which the bit string can be designed so that the bit “1” is not continuous. In synchronization tracking, it is inevitable that consecutive bits “1” are received in the information bit string of the data payload.

  The synchronization tracking method of the present invention uses the synchronization threshold Th and uses the same synchronizer configuration as in FIG. 7 or FIG. The synchronization threshold Th may be constant or may be adjustable based on channel quality. When adjusting the synchronization threshold, an input signal 714 to the delay control means 712 is required as shown in FIGS. In a simple implementation, the synchronization threshold Th may be equal to the OOK data detection threshold.

  As described with reference to FIG. 6, in the NRZ format OOK modulation signal, the amplitude level becomes substantially flat when the bit “1” continues, so that it is difficult for the prior art DLL to accurately synchronize the timing of the received signal. It is. This is because it is difficult to distinguish the rising edge and falling edge of the pulses 616, 618 and 620 except for the rising edge of the pulse 616 and the falling edge of the pulse 620.

  In the present invention, the threshold value Th is used to detect a rising edge and a falling edge of a pulse in a random bit string. Then, the received signal is synchronously tracked using only the ADC sample value when the rising edge and falling edge of the pulse are detected. Other sample values are simply removed from synchronous tracking.

  FIG. 11 shows an envelope signal 409 when the bit string “01011010” is received. ADC (A) 704 and ADC (B) 706 sample the envelope signal 409 at regular time intervals Ts / 21022, 1004. For each T_cycle, two consecutive samples from ADC (A) 704 and two consecutive samples from ADC (B) 706 are obtained.

First, rising detection will be described.
In the present invention, when the synchronization pull-in is completed, the ADC (B) 706 sample timing (eg, sample timing 1014, 1016, 1018, 1020, 1022, 1024, 1026) is at the timing of the peak point P of each symbol. Shall. That is, the sample value B1 or B2 coincides with the peak point P of each symbol. FIG. 11 shows the synchronization threshold Th1028. In order to detect the rising and falling edges of the received pulse, the sample value from ADC (B) 706 is compared with a threshold Th1028.

  A rising edge is detected when ADC (B) 706 has a sample that is less than threshold Th1028 and then has another sample that is greater than threshold Th1028. For example, in FIG. 11, since the sample value B1 1014 has an amplitude smaller than Th (amplitude 0) and the subsequent sample value B2 1016 (peak point P) has an amplitude larger than Th, the sample value B1 1014 And a rising edge between the sample value B2 1016 is detected.

  On the other hand, a falling edge is detected when ADC (B) 706 has a sample larger than Th1028 and then has another sample smaller than Th1028. For example, in FIG. 11, sample value B2 1024 has an amplitude greater than Th (peak point P), and thereafter sample value B1 1026 has an amplitude smaller than Th (amplitude 0), so sample value B2 1024 And a falling edge between the sample value B1 1026 is detected.

  Note that when ADC (B) 706 has two consecutive samples and their amplitudes are both larger (or smaller) than Th1028, neither rising edge nor falling edge is detected. For example, since sample values B2 1020, B1 1022 and B2 1024 are all greater than threshold Th1028, no rising or falling edge is detected between these samples.

  Next, the detected rising edge and the subsequent detected falling edge are grouped as a pair of detection edges. For example, as a pair, the rising edge from the sample value B1 1014 to the sample value B2 1016 , The falling edge from sample value B2 1016 to sample value B1 1018 is grouped. As another pair, the rising edge from the sample value B1 1018 to the sample value B2 1020 and the falling edge from the sample value B2 1024 to the sample value B1 1026 are grouped.

Next, signal tracking will be described.
First, only the sample values of the ADC (A) 704 at the detected rising edge and falling edge are used for signal tracking. Other sample values from ADC (A) are removed. For example, in FIG. 11, sample values A1 1015, A2 1017, A1 1019, A2 1025 are utilized, but sample values A2 1021 and A1 1023 are removed.

  In synchronous tracking, the samples from ADC (A) 704 are paired. That is, comparisons are made between samples at the grouped rising and falling edges. For example, in FIG. 11, a pair of sample values A1 1015 and A2 1017 are compared with each other, and another pair of sample values A1 1019 and A2 1025 are compared with each other.

  FIG. 12 is an example of a flowchart of the tracking method of the synchronization device 700 of FIG. First, in S1102, ADC (A) 704 and ADC (B) 706 each sample two samples A_x and B_x within the same Ts. In this embodiment, it is assumed that the synchronization tracking process starts from the rising edge.

Therefore, in order to detect the rising edge, it is necessary to match B_x with Th in S1104. When Bx> = Th, the rising edge cannot be detected, and the process flow returns to S1102, and A_x and B_x are sampled at the next Ts.
If Bx <Th, ADC (A) 704 and ADC (B) 706 continue to sample two other samples A_y and B_y respectively at the next Ts in S1106.

  In step S1108, B_y is checked against Th. When B_y <Th, the rising edge is not detected, and the process flow returns to S1106 to sample new A_y and B_y at the next Ts. If By> = Th, a rising edge is found. In S1110, the value of A_y is recorded as a rising edge sample A_L.

  After the rising edge is found, the next falling edge must be examined to form a pair of rising and falling edges. At the next Ts, ADC (A) 704 and ADC (B) 706 sample two samples A_y and B_y in S1112.

  Next, in S1114, B_y is collated with Th. If B_y> = Th, the falling edge is not detected, and the flow returns to S1112 to sample new A_y and B_y at the next Ts. If B_y <Th, a falling edge is detected and A_y is recorded as a falling edge sample A_T in S1116.

  This provides a pair of rising and falling edges. In S1118, signal tracking can be examined by checking | A_LA-T_ | with X, where X is 0 or a predetermined positive number as in the case of synchronous pull-in.

  When | A_LA−A_T | <= X, it is determined that the synchronization is complete, and no delay adjustment is necessary. Then, the process flow proceeds to S1126, where it is confirmed whether another signal is coming. If no signal is received, the process flow proceeds to end S1128. If another signal is received, the process flow returns to S1106 to detect the next pair of rising and falling edges.

  If | A_LA−T |> X in S1118, the timing of the clock signal is adjusted to perform synchronization tracking. Next, in S1120, A_L is compared with A_T. When A_L <A_T, it is detected that the clock signal 413 is advanced with respect to the envelope signal, and in S1122, the delay control signal 713 is set to a predetermined positive value (+ D), and the variable delay means 708 is set. The timing of the clock signal 413 is shifted backward.

  In the case of A_L> A_T, it is detected that the clock signal 413 is delayed with respect to the envelope signal. In S1124, the delay control signal 713 is set to a predetermined negative value (−D), and the variable delay means 708 is set. The timing of the clock signal 413 is shifted forward. After the delay adjustment in S1122 or S1124, the process flow proceeds to S1126, and it is confirmed whether or not the synchronization tracking process should be continued for the input signal.

  As in the case of synchronous pull-in, the predetermined value D in S1122 or S1124 indicates the size of the delay adjustment step. The step size D may be fixed or variable depending on various requirements. Increasing the step size D can speed up the response to the timing difference between the envelope signal and the clock signal, but may increase the fluctuation when synchronization is achieved. Furthermore, an averaging algorithm can be used as in the case of synchronization pull-in to reduce the influence of noise during the synchronization tracking operation.

  In the case of averaging, the delay control signal 713 is determined by collecting consecutive N pairs of rising and falling edges. N sample values A_L of N pairs are averaged to obtain A_L_ave, and N sample values A_T are averaged to obtain A_T_ave. Next, in FIG. 12, synchronous tracking can be performed by replacing sample values A_L and A_T with average values A_L_ave and A_T_ave.

As a supplementary explanation of the flowchart of FIG. 12, here, a synchronization tracking method when “01011010” is transmitted will be described. In S1102, the envelope signal 409 is sampled by ADC (A) 704 and ADC (B) 706 at Ts1 as shown in FIG. 12_a, and sample values A_x and B_x are obtained, respectively. Thereafter, the process proceeds to S1104.
In FIG. 12a, since the interval between the sampling timings of ADC (A) and ADC (B) is Ts / 2, when B_X is a peak point, A_X is half the amplitude and coincides with the threshold Th. To do.

  In step S1104, the delay control unit 712 determines whether “B_x <Th”. In the case of FIG. 12A, since this condition is not satisfied, the determination is “No” and the process returns to S1102. If the condition is satisfied at this point, the process proceeds to S1106. S1102 and S1104 are repeated until “B_x <Th” is satisfied. Returning to S1102 and sampling at the next Ts2, sample values A_x and B_x as shown in FIG. 12_b are obtained.

  In step S1104, the delay control unit 712 determines “B_x <Th” again. In FIG. 12B, since the condition is satisfied, “Yes” determination is made, and the process proceeds to S1106. In S1106, the delay control unit 712 acquires sample values A_y and B_y at the next Ts3 as shown in FIG. 12_c. Thereafter, the process proceeds to S1108.

  In step S1108, the delay control unit 712 determines whether “B_y <Th”. In the case of FIG. 12_c, since this condition is not satisfied, “No” determination is made, and the process proceeds to S1110. If “Yes” is determined here, the process returns to S1106 to acquire A_y and B_y in the next Ts. S1106 and S1108 are repeated until “B_y <Th” is not satisfied.

  In S1110, the delay control unit 712 detects the rising edge in the envelope signal at Ts3, and thus records the value of A_y at the rising edge (A_y in FIG. 12_c) as A_L. Then, it progresses to S1112. In S1112, the delay control unit 712 acquires the sample values A_y and B_y at the next Ts4 as shown in FIG. Then, it progresses to S1114.

  In step S1114, the delay control unit 712 determines whether “B_y <Th”. In FIG. 12_d, since this condition is not satisfied, the determination is “No”, and the process returns to S1112. S1112 and S1114 are repeated until “B_y <Th” is satisfied. As can be seen from FIGS. 12_e and 12_f, “No” determination is made at Ts5, and “Yes” determination is made at Ts6. If “Yes” determination is made in S1114, the process proceeds to S1116.

  In S1116, since the delay control unit 712 has detected a falling edge in the received signal at Ts6, the value of A_y at the falling edge (A_y in FIG. 12_f) is recorded as A_T. Thereafter, the process proceeds to S1118.

  In step S1118, the delay control unit 712 determines whether “| A_L−A_T | <= X”. The relationship between A_L and A_T in S1118 may be that in FIG. 12_g and FIG. 12_h in addition to FIG. 12_f. In the case of FIG. 12_f, since this condition is satisfied, the determination is “Yes” and the process proceeds to S1126. In the case of FIG. 12_g and FIG. 12_h, “No” determination is made, and the process proceeds to S1120.

  In S1120, the delay control unit 712 determines whether “A_L <A_T”. In the case of FIG. 12_h, “Yes” determination is made, and the process proceeds to S1122. On the other hand, in the case of FIG. 12_g, “No” determination is made, and the process proceeds to S1124.

  In step S1122, the delay control unit 712 controls the timing of the clock signal. In S1122, since A_L <A_T as shown in FIG. 12_i, the sample timing of ADC (B) is ahead of the peak point, that is, the timing of the sample value B is relative to the peak point of the envelope signal 409. It can be determined that Therefore, the delay control means 712 performs control (+ D) to increase the delay amount of the variable delay means 706 of FIGS. Thereafter, the process proceeds to S1126.

  Also in S1124, the delay control means 712 controls the timing of the clock signal 413. In S1124, the delay control unit 712, as shown in FIG. 12_j, contrary to S1122, since A_L> A_T, the sample timing of ADC (B) is delayed from the peak point, that is, the sample value B It can be determined that the timing is delayed from the peak position of the pulse. Therefore, the delay control unit 712 performs control (−D) to reduce the delay amount to the variable delay unit 706. Thereafter, the process proceeds to S1126.

  In S1126, the delay control unit 712 determines whether there is still a received signal. If there is a received signal, the determination is “Yes” and the process returns to S1106 to repeat the synchronization tracking process. If there is no received signal, the determination is “No”, the process proceeds to S1128, and the synchronization tracking process is terminated.

  FIG. 13 is a block diagram showing another configuration of pulse radio reception apparatus 1200 having OOK demodulation and envelope detection. The block diagram of the receiving device 1200 is similar to the block diagram of the receiving device 400 in FIG. 4, the only difference being that in FIG. 13 there is no envelope signal 409 output from the detection means 408 to the comparison means 410. is there.

  By using the present invention, the sample timing of ADC (B) 706 becomes the peak point P when synchronization is achieved, as in FIG. Therefore, in the threshold comparison, the sample from ADC (B) 706 is the same as the data sample for OOK data detection.

In place of the timing signal 411 being sent to the comparison means 410 in FIG. 4, the sample value from the ADC (B) 706 is sent to the comparison means 410 by the synchronization control means 412 in the signal 1202 of FIG. 13. As a result, the receiving apparatus 1200 can simplify the circuit configuration by removing one ADC or a sampling circuit including a comparator from the comparison unit 410.
In the case where the sampling in the comparison unit 410 of FIG. 4 is configured by a comparator, the envelope signal 409 is compared with the threshold value Th and then sampled by the timing signal 411. The envelope signal 409 is sampled by the timing signal 411 and then compared with the threshold Th.

(Embodiment 2)
In the first embodiment, since both ADCs may be synchronized with the peak point of the envelope signal, both ADCs had to operate at the same speed as the symbol rate. In the second embodiment, a configuration for reducing power consumption by dividing the roles of the two ADCs into synchronization and data demodulation will be described.
In this embodiment, a pulse signal having a waveform shown in FIG. 14 is used. FIG. 14 shows the waveform of the pulse signal when the code “010” is OOK modulated in the NRZ format. In FIG. 14, C is the amplitude of the peak point of the pulse, U is the symbol length, the amplitude of the changing point is C / 2, and the time width from the changing point to the peak point is U / 2.

  FIG. 15 is a block diagram of pulse radio receiving apparatus 1300 according to Embodiment 2 of the present invention. As shown in the figure, the receiving apparatus 1300 includes an antenna 1301, automatic gain control means 1302, detection means 1303, first fixed delay means 1304, first sample means 1305, second sample means 1306, clock generation means 1307. , Variable delay means 1308, third fixed delay means 1309, first threshold determination means 1310, second threshold determination means 1311, edge detection means 1312, second fixed delay means 1313, and synchronization control means 1314. Yes.

  16 is a diagram showing an output signal of each means when the code “1010... 10” is received, and FIG. 19 is a flowchart showing a synchronization procedure of the receiving apparatus 1300.

  The antenna 1301 receives a signal transmitted from a transmission device (not shown) and outputs the received signal to the automatic gain control means 1302. The automatic gain control means 1302 controls the gain of the received signal so that the input signal level of the detection means 1303 is constant.

  Detection means 1303 performs envelope detection on the signal received via antenna 1301 and outputs an envelope signal. This envelope signal is branched into two, one is delayed by a symbol length: U by the first fixed delay means 1304 and sent to the first sample means 1305, and the other is directly sent to the second sample. Sent to means 1306. Envelope detection can be realized, for example, by removing high-frequency components by half-wave rectification using a diode and a low-pass filter.

  The first sampling means 1305 samples the envelope signal input via the first fixed delay means 1304 and holds the value until the next sampling is performed (FIG. 19, step 4). The sample timing is determined by the clock signal input through the variable delay means 1308 and the edge detection signal input from the edge detection means 1312. Specifically, the first sampling unit 1305 performs the sampling operation only when an edge detection signal is input. The timing is the timing when the rising edge of the clock signal is input.

  The second sampling means 1306 samples the envelope signal and holds the value until the next sampling is performed (FIG. 19, step 1). The sample timing is the timing at which the rising edge of the clock signal input via the variable delay means 1308 and the third fixed delay means 1309 is input.

  The clock generation unit 1307 generates a clock signal having the same cycle as the symbol length U and outputs the clock signal to the variable delay unit 1308. The variable delay means 1308 delays the input clock signal. The delay amount is determined by a delay control signal input from the synchronization control means 1314. The clock signal delayed by the variable delay means 1308 is branched into two, one is sent to the first sample means 1305, and the other is delayed by U / 2 by the third fixed delay means 1309 and the second is delayed. Sent to the second sample means 1306.

  FIG. 17 is a diagram showing the positional relationship between the envelope signal and the clock signal on the time axis when synchronization is established. By setting the delay amount of the third fixed delay means 1309 to U / 2 which is half the symbol length, the first sample means 1305 samples the vicinity of the changing point, and the second sample means 1306 near the peak point. Can be sampled.

The first threshold value determination unit 1310 compares the sample value i input from the first sample unit 1305 with a predetermined threshold value, and outputs the comparison result to the synchronization control unit 1314 (FIG. 19, step 5). Specifically, the first threshold determination unit 1310 outputs “1” as the threshold determination result i when the sample value i of the first sample unit 1305 is larger than the threshold, and determines the threshold when it is smaller. “0” is output as the result i.

The predetermined threshold is a threshold used for code determination at the time of demodulation, and the value is C / 2. In FIG. 16, since the sample value i of the first sample unit 1305 is larger than C / 2 at time t6, the first threshold value determination unit 1310 outputs “1” as the threshold value determination result i. . At time t2, t4, and t8, since the sample value i is smaller than C / 2, the first threshold value determination unit 1310 outputs “0” as the threshold value determination result i.

The second threshold value determination means 1311 compares the sample value i input from the second sample means 1306 with a predetermined threshold value, and outputs the comparison result to the edge detection means 1312 (FIG. 19, step 2). Specifically, the second threshold determination unit 1311 outputs “1” as the threshold determination result i when the sample value i of the second sample unit 1306 is larger than the threshold, and “0” when the sample value i is smaller. Is output as a threshold determination result i.

  The predetermined threshold is a threshold used for code determination at the time of demodulation, and the value is C / 2. Further, as described above, since the sample point of the second sampling unit 1306 is near the peak point of the envelope signal when synchronization is established, the output of the second threshold determination unit 1311 is used as demodulated data. Can do.

In FIG. 16, since the sample value i of the second sample means 1306 is larger than C / 2 at times t0, t1, t3, t5, and t7, the second threshold value judging means 1311 sets “1”. The threshold determination result i is output, and “0” is output as the threshold determination result i at other times.

The edge detection unit 1312 detects the rising edge of the received signal using the determination result input from the second threshold determination unit 1311 (FIG. 19, step 3). Specifically, the rising edge is detected when the threshold determination result i of the second threshold determination means 1311 continues to be “01”. The edge detection unit 1312 outputs an edge detection signal when detecting the rising edge.

  The edge detection signal is branched into two, one is sent to the first sampling means 1305, and the other is delayed by U / 2 by the second fixed delay means 1313 and sent to the synchronization control means 1314. . In FIG. 16, rising edges are detected at times t1, t3, t5, and t7.

  The synchronization control unit 1314 controls the delay amount of the variable delay unit 1308. The amount of delay is determined based on the determination result of the first threshold determination unit 1310 and the edge detection signal input via the second fixed delay unit 1313. Specifically, the synchronization control unit 1314 changes the delay amount of the variable delay unit 1308 only when the edge detection signal is input, and outputs “0” when the edge detection signal is not input and is variable. The delay amount of the delay means 1308 is held (FIG. 19, step 8).

A case where the delay amount of the variable delay means 1308 is changed will be described with reference to FIG. Ai in the figure is the sample value i of the first sample means 1305. In the case of FIG. 18A, the first threshold value determination unit 1310 determines that Ai> C / 2. At this time, since the clock signal is delayed with respect to the envelope signal, the synchronization control means 1314 outputs “−1” and controls the variable delay means 1308 so as to advance the timing of the clock signal (FIG. 19, FIG. 19). Step 6).

On the other hand, in the case of FIG. 18B, the first threshold value determination unit 1311 determines that Ai <C / 2. At this time, since the clock signal is advanced with respect to the envelope signal, the synchronization control means 1314 outputs “1” and controls the variable delay means 1308 to delay the timing of the clock signal (FIG. 19, step). 7).

In FIG. 16, at times t2, t4, and t8, the output of the first threshold value determination unit 1311 is “0”, that is, Ai <C / 2, so the synchronization control unit 1314 outputs “1”. At time t6, since the output of the first threshold value determination unit 1311 is “1”, that is, Ai> C / 2, the synchronization control unit 1314 outputs “−1”. When Ai = C / 2, the synchronization control means 1314 outputs “0” and holds the delay amount of the variable delay means 1308 (FIG. 19, step 8).

By performing the control as described above, the clock signal sent to the first sampling means 1305 can be synchronized and tracked near the changing point of the envelope signal. The clock signal sent to the second sampling means 1306 is synchronized with the vicinity of the peak point of the envelope signal. Therefore, the received signal can also be demodulated by determining the threshold value of the sample value i of the second sample means 1306 by the second threshold value determination means 1311. Further, since the demodulation is not performed with the sample value i of the first sample means 1305, the operation speed of the first sample means 1305 can be slowed down and the power consumption can be suppressed.

(Embodiment 3)
In the second embodiment, the case where the pulse waveform has a shape as shown in FIG. 14 has been described. However, in an actual communication environment, noise is added to the received signal. When noise is added to the received signal, the pulse waveform is distorted due to the influence of the noise half-wave rectified by the detection means 1303. FIG. 20 is a diagram showing a pulse signal when the waveform is distorted due to the influence of noise. In the figure, the waveform shown by the solid line is a distorted waveform, and the amplitude level of the sign “0” is raised.

  The method shown in the second embodiment is a method of synchronizing the clock signal of the first sampling unit 1305 with reference to the changing point, that is, the intersection of the envelope signal and the sign determination threshold. Therefore, when the pulse waveform is distorted, the intersection of the received signal and the code determination threshold is shifted, so that the sample point of the first sampler 1305 in FIG. 20 is shifted from t11 to t10.

  In FIG. 15, since the delay amount of the third fixed delay means 1309 is fixed to U / 2, the sample point of the second sample means 1306 in FIG. 20 also shifts from t13 to t12. This means that the demodulation performance is degraded. Therefore, in this embodiment, a method for suppressing deterioration in demodulation performance when the pulse waveform is distorted due to the influence of noise will be described.

  FIG. 21 is a block diagram of a pulse radio receiving apparatus according to the sixth embodiment of the present invention. As shown in the figure, the receiving apparatus 1400 includes a second variable delay means 1409 instead of the third fixed delay means 1309, and includes a hold means 1415, an addition means 1416, a fourth fixed delay means 1417, and a second fixed delay means 1417. The point that a synchronization control unit 1418 is newly provided is different from the receiving apparatus 1300 of FIG.

  FIG. 22 is a diagram showing an output signal of each means when the code “1010... 10” is received, and FIG. 23 is a flowchart showing a synchronization procedure of the receiving apparatus 1400.

The second variable delay means 1409 delays the clock signal input via the first variable delay means 1308. The amount of delay is determined by the delay control signal i input from the second synchronization control means 1418. The clock signal delayed by the second variable delay means 1409 is sent to the second sample means 1306.

  The hold unit 1415 holds the sample value input from the second sample unit 1306 when the edge detection signal is input from the edge detection unit 1312 (FIG. 23, step 19). This hold value is branched into two, one being sent to the adding means 1416 and the other being delayed by the symbol length: U by the fourth fixed delay means 1417 and sent to the adding means 1416.

  In FIG. 22, rising edges are detected at times t14, t16, t18, t20, and t22, and the hold means 1415 holds the sample values Aii_1, Aii_2, Aii_3, Aii_4, and Aii_5 of the second sample means 1306 at that time. is doing.

  The adder 1416 calculates the difference between the hold value input from the hold unit 1415 as it is and the hold value delayed by the symbol length U by the fourth fixed delay unit 1417, and the calculation result is used as the second synchronization control. It outputs to the means 1418 (FIG. 23, step 20).

  The second synchronization control means 1418 controls the delay amount of the second variable delay means 1409 (FIG. 23, step 21). The delay amount is determined based on the calculation result of the adding unit 1416 and the delay control signal i input from the first synchronization control unit 1314.

  When the calculation result of the adding means 1416 is “0”, the following two cases can be considered. (1) The delay control of the first variable delay means 1308 was not performed. (2) As a result of performing the delay control of the first variable delay means 1308, the sample point of the second sample means 1306 exceeds the peak point of the envelope signal, but it happens to have the same amplitude. When the calculation result is “positive”, the sample point of the second sample unit 1306 approaches the peak point of the envelope signal by the delay control of the first variable delay unit 1308. Therefore, when the calculation result is 0 or more, the second synchronization control unit 1418 outputs “0” and holds the delay amount of the second variable delay unit 1409 (FIG. 23, step 22).

On the contrary, when the calculation result of the adding means 1416 is “negative”, the sample point of the second sampling means 1306 is moved away from the peak point of the envelope signal by controlling the timing of the first variable delay means 1308. It will be. In this case, the delay control signal i obtained by inverting the polarity of the delay control signal i is output, and the sample point of the second sampling means 1306 is returned to the timing before being delayed by the first variable delay means 1308 (FIG. 23, Step 23).

This means that the interval between the sample points of the first sample means 1305 and the sample points of the second sample means 1306 is variable.
In FIG. 22, the calculation result of the adding means 1416 shows a positive value at time t15. This is because the sample point of the second sample means 1306 approaches the peak point by controlling the timing of the first variable delay means 1308 at time t14, and the sample point Aii_1 in the envelope signal of the second sample means This is because Aii_2 is Aii_1 <Aii_2.

  At time t16, since the output of the adding means 1416 is positive, the second synchronization control means 1418 outputs “0”. Next, at time t18, the output of the adding means shows a negative value. This is because the sample point of the second sampling unit 1306 is moved away from the peak point by the control of the delay amount of the first variable delay unit 1308 at time t16, and Aii_2> Aii_3.

At this time, since the delay control signal i at time t16 is “1”, the second synchronization control means 1418 outputs “−1” with the polarity inverted as the delay control signal i. In this way, the sample point of the second sample means 1306 is synchronized with the vicinity of the peak point.

  By performing the control as described above, the sample point of the second sample means 1306 can be always synchronized with the vicinity of the peak point, so that deterioration in demodulation performance can be suppressed even when the pulse waveform is distorted.

(Embodiment 4)
In the first, second, and third embodiments, synchronization pull-in and synchronization tracking are performed by comparing the amplitude level of the sample value obtained from the sample means with a predetermined threshold value. However, in Embodiment 4, the maximum value and the minimum value are detected from the sample values, and the synchronization control is performed based on the difference between the maximum value and the minimum value, so that synchronization is achieved without depending on the received signal strength. explain.
FIG. 24 is a block diagram showing a main configuration of the pulse radio receiving apparatus according to Embodiment 4 of the present invention. As shown in FIG. 24, the pulse radio receiving apparatus 1500 includes a detection unit 1501, a clock generation unit 1502, a delay unit 1503, a sample unit 1504, a relative difference calculation unit 1505, and a synchronization control unit 1506. FIG. 25 is a flowchart showing a synchronization procedure of pulse radio receiving apparatus 1500.

  The detection means 1501 detects the envelope of the received modulation signal, that is, a line that smoothly connects the maximum points of the modulation signal, and outputs it to the sampling means 1504 as an envelope signal. The clock generation unit 1502 generates a clock signal at a frequency equivalent to the transmission rate of the received signal and outputs it to the delay unit 1503.

  The delay unit 1503 includes a variable delay unit 1531 and a fixed delay unit 1532. The variable delay unit 1531 performs variable delay control on the clock signal from the clock generation unit 1502 based on the delay control signal provided from the synchronization control unit 1506, and generates the synchronous clock signal 1503 A synchronized with the envelope signal as the fixed delay unit 1532. Generates a synchronous clock signal 1503B obtained by delaying the synchronous clock signal 1503A from the variable delay means 1531 by a fixed amount, and outputs it to the sample means 1504 (FIG. 25, step 34, step 35).

  The sample means 1504 includes two A / D converters 1541 and 1542. The A / D converters 1541 and 1542 convert the envelope signal detected by the detection unit 1501 based on the respective synchronous clock signals 1503A and 1503B from the delay unit 1503 from an analog signal to a digital signal, and sample values 1504A , 1504B is output (FIG. 25, step 31).

  The relative difference calculation unit 1505 includes maximum value detection units 1551A and 1551B, minimum value detection units 1552A and 1552B, and adders 1553A, 1553B and 1554. The maximum value detection unit 1551A detects the maximum value from n consecutive sample values 1504A input from the sample unit 1504 and outputs the maximum value Amax. The minimum value detection unit 1552A detects the minimum value from the consecutive n sample values 1504A input from the sample unit 1504, and outputs the minimum value Amin.

  The maximum value detection unit 1551B detects the maximum value from the n consecutive sample values 1504B input from the sample unit 1504, and outputs the maximum value Bmax. The minimum value detection unit 1552B detects a minimum value from n consecutive sample values 1504B input from the sample means 1504, and outputs a minimum value Bmin.

  Adders 1553A and 1553B respectively add | Amax− based on respective maximum values Amax and Bmax from maximum value detection means 1551A and 1551B and minimum values Amin and Bmin from minimum value detection means 1552A and 1552B. Amin | and | Bmax−Bmin | are obtained and output to the adder 1554.

The adder 1554 obtains | Amax−Amin | − | Bmax−Bmin | based on | Amax−Amin | and | Bmax−Bmin | given from the adders 1553A and 1553B, and compares the relative values between the different phase sample points. The amplitude difference signal iV is output to the synchronization control means 1506 (FIG. 25, step 32).

Based on the relative amplitude difference signal ΔV from the relative difference calculation unit 1505, the synchronization control unit 1506 generates a delay control signal that controls the phase of the clock signal so that the timing of the envelope signal and the clock signal are synchronized. And output to the delay means 1503. Specifically, the synchronization control means 1506 first determines the polarity of the relative amplitude difference signal ΔV sent from the relative difference calculation means 1505 (FIG. 25, step 33).

FIG. 26 is a diagram illustrating timing control of a clock signal. IV ≧ 0 as shown in FIG.
In this case, a delay control signal for advancing the timing of the clock signal is output to the delay means 1503 (FIG. 25, step 34). On the other hand, when ΔV <0 as shown in FIG. 26B, a delay control signal for delaying the timing of the clock signal is output to the delay means 1503 (FIG. 25, step 35). By performing such control, the timing of the synchronous clock signals 1503A and 1503B can be synchronized with the peak point of the envelope signal.

  As described above, in the fourth embodiment of the present invention, synchronization control is performed based on the relative amplitude difference between sample values for different phases. This makes it possible to synchronize with an NRZ-encoded pulse signal. Further, synchronization is possible without depending on the received signal strength.

The relative difference calculating unit 1505 detects the maximum value and the minimum value, but the relative difference calculating unit 1505 may detect only the maximum value as shown in FIG. At this time, since the value of the relative amplitude difference signal iV is smaller than that in the configuration of FIG. 24, the Early / Late determination performance may be deteriorated due to the influence of noise or the like. However, the minimum value detection means 1552A, 1552B, the adder 1553A , 1553B is not necessary, so that the circuit scale and power consumption can be reduced.

  The relative difference calculation means 1505 detects the maximum value and the minimum value from the n consecutive sample values, but the maximum value is determined from the consecutive m sample values (m <n). The minimum value may be searched and the maximum value and the minimum value may be averaged n / m times and detected. By doing in this way, the influence of the noise in maximum value and minimum value detection can be reduced, and synchronous tracking performance can be improved.

(Embodiment 5)
In the fourth embodiment, the case where the timing of the clock signal is “advanced” or “delayed” based on the relative amplitude difference signal has been described. However, in a state where synchronization is established, the timing of the clock signal coincides with the timing of the peak point of the received signal, so it is desirable to control so that the clock signal does not move more than necessary. Therefore, in the present embodiment, a method for maintaining the phase control of the clock signal when the synchronization state is detected will be described.

  FIG. 28 is a block diagram showing a main configuration of the pulse radio receiving apparatus according to the fifth embodiment of the present invention. As shown in FIG. 28, pulse radio reception apparatus 1500 is different from pulse radio reception apparatus 1500 in FIG. 24 in that synchronization state detection means 1507 is newly provided. FIG. 29 is a flowchart showing the synchronization detection procedure of pulse radio receiving apparatus 1500.

The synchronization state detection unit 1507 includes an absolute value calculation unit 1571 and a comparison unit 1572. The absolute value calculation means 1571 is a relative amplitude difference signal iV given from the relative difference calculation means 1505.
Absolute value | ΔV | is calculated (FIG. 29, step 36). The comparison unit 1572 detects the synchronization state between the clock signal and the envelope signal by comparing | ΔV | given from the absolute value calculation unit 1571 with a predetermined threshold value X (step 37 in FIG. 29).

  FIG. 30 is a diagram showing a positional relationship between the envelope signal and the synchronization clock signal when synchronization is established. In the state of being synchronized as shown in FIG. 30, | Amax−Amin | = | Bmax−Bmin |, that is, ΔV = 0. However, in an actual communication environment, since the waveform is distorted due to the influence of noise or the like, ΔV = 0 is rare. Therefore, considering the waveform distortion, when | ΔV | ≦ X (X is a positive value), the synchronization state detection unit 1507 detects the synchronization state and outputs a synchronization detection signal to the synchronization control unit 1506. To do.

  When the synchronization control unit 1506 receives the synchronization detection signal from the synchronization detection unit 1507, the synchronization control unit 1506 transmits a delay control signal to the variable delay unit 1531 to control the timing of the clock signal (FIG. 29, step 38). . When the synchronization detection signal is not received, the process proceeds to step 33 in FIG. By performing such control, the synchronization state is detected, and when the synchronization state is reached, the timing of the clock signal is held.

As described above, in the fifth embodiment of the present invention, the absolute value | iV of the relative amplitude difference signal iV
The synchronization state is detected by comparing | with a predetermined threshold value X. Here, the stability of synchronization tracking can be improved by maintaining the timing of the clock signal when the synchronization state is reached.

When the synchronization state is detected, not only the timing of the clock signal is held, but also the phase difference between the synchronization clock signals 1503A and 1503B input to the sampling means 1504 is switched between the asynchronous state and the synchronization state. Also good. Generally, when the synchronization is pulled in, the relative amplitude difference ΔV can be increased by increasing the phase difference. At this time, the fixed delay means 1532 is replaced with a variable delay means as shown in FIG. The delay amount may be switched.

There is another case where | ΔV | ≦ X is satisfied. Figure 32 shows that iV is not synchronized
It is the figure which showed the state which is | <= X. As shown in FIG. 32, | ΔV | ≦ X also holds when the clock signal is synchronized with the changing point of the envelope signal. This state is called pseudo synchronization. In order to avoid this pseudo synchronization, pseudo synchronization detection means may be further provided.

  The difference between the synchronized state and the pseudo-synchronized state can be understood by comparing FIG. 30 and FIG. In the synchronized state in FIG. 30, the sample value 1504A of the A / D converter 1541 and the sample value 1504B of the A / D converter 1542 are substantially equal. On the other hand, in the quasi-synchronized state in FIG. 32, since the pulse slope is sampled, the sample value 1504A and the sample value 1504B are not equal.

  That is, the difference between the synchronized state and the pseudo-synchronized state is the size of the sample values of the A / D converter 1541 and the A / D converter 1542 at a certain same time. In FIG. 30 (synchronized state), since the flat part of the pulse is sampled, values such as Amax1, Bmax1 (or Amin1, Bmin1) are output from each A / D converter. In FIG. 32 (pseudo-synchronized state), since the slope of the pulse is sampled, values such as Amax2, Bmin2 (or Amin2, Bmax2) are output from each A / D converter. This difference can be used to distinguish the synchronization state from the pseudo synchronization state.

  FIG. 33 shows the configuration of a pulse radio receiving apparatus provided with pseudo-synchronization detecting means 1508. The pseudo synchronization detection unit 1508 includes an adder 1581, an absolute value calculation unit 1582, a comparison unit 1583, and an averaging unit 1584. The adder 1581 calculates the difference between the sample values 1504A and 1504B given from the sample means 1504. The absolute value calculation unit 1582 calculates the absolute value | 1504A-1504B | of the difference value. The comparing unit 1583 detects the pseudo-synchronized state by comparing | 1504A-1504B | given from the absolute value calculating unit 1582 with a predetermined threshold Y. That is, | Amax2-Bmini2 | or | Amin2-Bmax2 | in FIG.

  Specifically, when | 1504A-1504B |> Y is satisfied, comparing means 1583 detects the pseudo-synchronization state and outputs a pseudo-synchronization detection signal. The averaging unit 1584 can reduce the influence of noise and the like by averaging the pseudo synchronization detection signal from the comparison unit 1583, and can improve the detection accuracy of the pseudo synchronization state. When the pseudo-synchronized state is detected, the synchronization control unit 1506 controls the variable delay means 1531 so that the timing of the clock signal is forcibly shifted to escape from the pseudo-synchronized state.

(Embodiment 6)
In the sixth embodiment, a method for performing data demodulation simultaneously with synchronization tracking will be described. FIG. 34 is a block diagram showing a main configuration of the pulse radio receiving apparatus according to Embodiment 3 of the present invention. 34 differs from pulse radio reception apparatus 1500 shown in FIGS. 24 and 28 in that pulse radio reception apparatus 1500 further includes demodulation means 1509.

The demodulation unit 1509 includes a selection unit 1591 and a comparison unit (binarization) 1592. The selection unit 1591 selects one of the sample values 1504A and 1504B from the sample unit 1504 based on the relative amplitude difference signal iV given from the relative difference calculation unit 1505, and outputs the selected sample value to the comparison unit 1592. To do. The comparison unit 1592 binarizes the sample value by comparing the sample value given from the selection unit 1591 with a predetermined threshold value, and obtains demodulated data.

  The demodulator 1509 includes a selector 1591 and selects a sample value input from the sampler 1504 based on the relative amplitude difference signal. However, the demodulator 1509 includes an adder instead of the selector 1591. A value obtained by adding the sample values may be output to the comparison unit 1592. By doing so, a diversity effect can be obtained and the demodulation performance can be improved as compared with the case where the sample value is selected and used.

(Embodiment 7)
FIG. 37 is a block diagram showing a main configuration of the pulse radio receiving apparatus according to the seventh embodiment. In the present embodiment, it is assumed that a transmission signal modulated by OOK (ASK) or BPSK is transmitted as a modulation method from a transmission apparatus of a communication partner (not shown), and modulated by OOK (ASK) or BPSK. The example which applied this invention to the pulse radio | wireless receiver which receives a modulation signal is shown.

  The pulse radio receiving apparatus shown in FIG. 37 includes a detection unit 2100, two AD (Analog to Digital) converters 2101-1 and 2101-2, a fixed delay unit 2102, a clock generation unit 2103, a variable delay unit 2104, and a delay control unit. 2105 and demodulating means 2106.

  The detection means 2100 detects the received signal by a predetermined detection method. There are various predetermined detection methods such as envelope detection when the modulation method is OOK (ASK), and synchronous detection and delay detection when phase modulation such as BPSK is used, but there is no particular limitation.

  The two AD converters 2101-1 and 2101-2 respectively sample the amplitudes of the detection signals detected by the detection unit 2100 at the timings of clocks output from the variable delay unit 2104 and the fixed delay unit 2102, respectively. The sampled result is binarized according to the amplitude and output.

  The fixed delay means 2102 shifts the clock generated by the clock generation means 2103 and delayed by the variable delay means 2104 described later by an arbitrary timing.

  Clock generation means 2103 generates a clock whose clock rate is equal to the symbol rate of the received signal. Therefore, the output signal of the detection means 2100 is sampled at two different timings in one symbol by the two AD converters 2101-1 and 2101-2.

  The variable delay unit 2104 delays the clock generated by the clock generation unit 2103 based on the delay control signal output from the delay control unit 2105.

  The delay control means 2105 is based on the outputs (binary data) from the two AD converters 2101-1 and 2101-2, and is the center of the symbol of the output signal of the detection means 2100 (here, the timing at which the amplitude becomes maximum). The delay amount of the variable delay means 2104 is controlled so that the sample timing of any one of the AD converters does not deviate from the center of the symbol). In practice, the delay control means 2105 outputs a delay control signal for bringing the symbol center and the sample timing closer to the variable delay means 2104. The variable delay unit 2104 controls the delay amount of the clock output from the clock generation unit 2103 based on this delay control signal. A specific method of controlling the delay amount of the variable delay unit 2104 by the delay control unit 2105 will be described later.

  The demodulation means 2106 demodulates by extracting only the output from the AD converter that samples the vicinity of the center of the symbol from the binary data output from the two AD converters 2101-1 and 2101-2. Select data. That is, when the AD converter 2101-1 samples the vicinity of the center of the symbol, the output of the AD converter 2101-1 is used as demodulated data. Similarly, when the AD converter 2101-2 samples the vicinity of the center of the symbol, the output of the AD converter 2101-2 is used as demodulated data. Here, of the two AD converters 2101-1 and 2101-2, which is sampling the vicinity of the center of the symbol ("pulling result" in the figure) is the delay control means 2105 (FIG. 38 described later). This is notified from the delay amount determination unit 2105-6).

  FIG. 38 is a diagram showing a detailed configuration of the delay control means 2105. In FIG. 38, the delay control means 2105 includes a symbol change detection unit 2105-1, a first counter 2105-2, an inter-finger difference detection unit 2105-3, a second counter 2105-4, and an Early / Late determination unit 2105. 5 and a delay amount determination unit 2105-6.

  The symbol change detection unit 2105-1 uses the output from the AD converter that samples the vicinity of the center of the symbols of the two AD converters 2101-1 and 2101-2, and indicates that the received data symbol has changed. Is detected. Here, information on which AD converter samples the vicinity of the center of the symbol (“drawing result” in the figure) is notified from the delay amount determination unit 2105-6.

  The first counter 2105-2 counts the number of times that the symbol change detection unit 2105-1 detects that the received data symbol has changed.

  When the symbol change detector 2105-1 detects that the received data symbol has changed, the inter-finger difference detector 2105-3 detects the vicinity of the center of the symbol at that time (for example, timing A2 in FIG. 39). Compare the previous output from the AD converter being sampled (for example, A1 in FIG. 39) with the latest output from the other AD converter (for example, B1 in FIG. 39). Detect that Here, information on which AD converter samples the vicinity of the center of the symbol (“drawing result” in the figure) is notified from the delay amount determination unit 2105-6.

  The second counter 2105-4 counts the number of times that the inter-finger difference detection unit 2105-3 detects that the outputs are different as a result of the comparison.

  The Early / Late determination unit 2105-5 has a fixed time (for example, until the count value of the first counter 2105-2 reaches N. Or until the number of received symbols reaches N. Here, N is 2 or more. The Early / Late is determined from the ratio between the count value of the first counter 2105-2 and the count value of the second counter 2105-4. A detailed determination method will be described later.

  The delay amount determination unit 2105-6 outputs a delay control signal based on the determination result by the Early / Late determination unit 2105-5 to the variable delay unit 2104. Also, the delay amount determination unit 2105-6 notifies the demodulation unit 2106 and the inter-finger difference detection unit 2105-3 of the pull-in result based on the determination result by the Early / Late determination unit 2105-5.

  Also, as an initial state, which sample timing of the two AD converters 2101-1 and 2101-2 is closer to the center of the symbol is controlled by pulling in symbol synchronization. It is assumed that the delay amount determination unit 2105-6 knows which AD converter is sampling around the center of the symbol when the symbol synchronization pull-in is completed. Here, the method of pulling in symbol synchronization is not particularly limited.

  Hereinafter, the operation of the pulse radio receiving apparatus configured as described above will be described mainly with respect to the operation of the delay control unit 2105 with reference to FIGS.

  39 and 40 are diagrams for explaining the concept of the delay control method by the delay control means 2105. FIG. 39 and 40 show the detection signal waveform output from the detection means 2100 and the sample timing (hereinafter also referred to as “finger”) by the two AD converters 2101-1 and 2101-2. Of the two AD converters 2101-1 and 2101-2, one sample timing is A1 (or A2) and the other sample timing is B1 (or B2). The delay amount of the fixed delay means 2102 is 0.5 symbols.

  FIG. 39 shows a case where sample timings A1 and A2 (hereinafter collectively referred to as “finger A”) are closer to the center of the symbol than sample timings B1 and B2 (hereinafter also collectively referred to as “finger B”). Is shown. In the synchronized state (hereinafter also referred to as “Sync”) (FIG. 39a), the output results of the AD converters in the fingers A1 and B1 (or fingers A2 and B2) differ from the case where they are equal due to subtle time fluctuations in the detection waveform. And appear randomly. On the other hand, in the Early state (FIG. 39b), the probability that the output results of the AD converters in the fingers A1 and B1 (or fingers A2 and B2) are equal increases. In the Late state (FIG. 39c), there is a high probability that the output results of the AD converters in the fingers A1 and B1 (or fingers A2 and B2) are different.

  In the state of FIG. 39, symbol change detection section 2105-1 uses the output of the AD converter corresponding to finger A to indicate that the received data symbol has changed, that is, “the output result of AD converter in A1 ≠ A2 It is detected that the output result of the AD converter at Further, the inter-finger difference detection unit 2105-3 detects that “the output result of the AD converter in A1 ≠ the output result of the AD converter in B1”. Further, the demodulating means 2106 employs the output result of the AD converter corresponding to the finger A as the demodulation result.

  FIG. 40 shows a case where the sample timings B1 and B2 are closer to the center of the symbol than the sample timings A1 and A2. In a synchronized state (hereinafter also referred to as “Sync”) (FIG. 40 a), a case where the output results of the AD converters in the fingers B <b> 1 and A <b> 2 are equal and different from each other appears at random due to a subtle time variation of the detection waveform. On the other hand, in the Early state (FIG. 40b), the probability that the output results of the AD converters in the fingers B1 and A2 are equal increases. In the Late state (FIG. 40c), there is a high probability that the output results of the AD converters in the fingers B1 and A2 are different.

  In the state of FIG. 40, symbol change detection section 2105-1 uses the result of the output result of the AD converter corresponding to finger B to indicate that the received data symbol has changed, that is, “the output of the AD converter in B1. It is detected that the result ≠ the output result of the AD converter in B2. Further, the inter-finger difference detection unit 2105-3 detects that “the output result of the AD converter in B1 ≠ the output result of the AD converter in A2”. Further, the demodulating means 2106 employs the output result of the AD converter corresponding to the finger B as the demodulation result.

  As an initial state, which of finger A or finger B is closer to the center of the symbol is controlled by pulling in symbol synchronization. In addition, it is assumed that the delay amount determination unit 2105-6 knows which finger A or finger B is near the center of the symbol when the pull-in is completed. The method for pulling in symbol synchronization is not particularly limited.

  As described above, in each of the Sync state, the Early state, and the Late state, the probability that the output results of the AD converters at the finger A and the finger B are equal (or different) when the received data symbol changes is changed. . The delay control unit 2105 implements delay control using this characteristic.

  FIG. 41 shows a flow of delay control by the delay control means 2105. Hereinafter, the flow will be described in order from the top.

  First, the symbol change detection unit 2105-1 changes the received symbol by using the output from the AD converter that samples the vicinity of the center of the symbol among the two AD converters 2101-1 and 2101-2. It is determined whether or not (S3001). When a change in the received symbol is detected (S3001: Yes), the symbol change detection unit 2105-1 increments the first counter 2105-2 (initial value is zero) by one (S3002), and changes in the received symbol Is detected to the inter-finger difference detecting unit 2105-3. The symbol change detection unit 2105-1 repeats this process.

  When the inter-finger difference detection unit 2105-3 receives a notification from the symbol change detection unit 2105-1 that a change in the received symbol has been detected, the inter-finger difference detection unit 2105-3 detects the vicinity of the center of the symbol at that time (for example, timing A2 in FIG. 39). Compare the previous output from the AD converter being sampled (for example, A1 in FIG. 39) with the latest output from the other AD converter (for example, B1 in FIG. 39). It is determined whether or not (different or not) (S3003). As a result of the above, when an output difference is detected (S3003: Yes), the inter-finger difference detection unit 2105-3 increments the second counter 2105-4 (initial value is zero) by one (S3004). The inter-finger difference detection unit 2105-3 repeats this process.

  The Early / Late determination unit 2105-5 performs an Early / Late determination process when a predetermined time has elapsed since the start of the above process or the previous execution of the Early / Late determination process (S3005: Yes). The Early / Late determination unit 2105-5 has an arbitrary value X in which the ratio of the count value of the second counter 2105-4 to the count value of the first counter 2105-2 is greater than 0.5 and less than or equal to 1. When it is above (S3006: Yes), it determines with Late (S3007). The Early / Late determination unit 2105-5 determines that the ratio of the count value of the second counter 2105-4 to the count value of the first counter 2105-2 is smaller than X (S3006: No) and is 0 or more. If it is equal to or smaller than an arbitrary value Y smaller than 0.5 (S3008: Yes), it is determined to be Early (S3009). Further, the Early / Late determination unit 2105-5 determines that the ratio of the count value of the second counter 2105-4 to the count value of the first counter 2105-2 is not equal to or greater than X or less than Y (S3008: No). , Sync is determined (S3010). Finally, the Early / Late determination unit 2105-5 resets the values of the first counter 2105-2 and the second counter 2105-4 to zero, and outputs the determination result (S3011).

  The delay amount determination unit 2105-6 selects a delay control amount based on the determination result by the Early / Late determination unit 2105-5 (S3012). That is, the delay amount determination unit 2105-6 sets + A as the delay amount when the determination result is Early, zero as the delay amount when the determination result is Sync, and −A as the delay amount when the determination result is Late. Select (S3013). Here, A is an arbitrary value smaller than 0.5 symbols and larger than 0. Finally, the delay amount determination unit 2105-6 outputs a delay control signal corresponding to the selected delay amount to the variable delay means 2104 (S3014).

(Embodiment 8)
FIG. 42 is a block diagram showing a main configuration of the pulse radio receiving apparatus according to the eighth embodiment. 42, the same components as those in FIG. 37 are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, it is assumed that a transmission signal modulated by OOK (ASK) or BPSK is transmitted as a modulation method from a transmission apparatus of a communication partner (not shown), and modulated by OOK (ASK) or BPSK. The example which applied this invention to the pulse radio | wireless receiver which receives a modulation signal is shown.

  The first difference between the pulse radio receiver of the eighth embodiment (FIG. 42) and the pulse radio receiver of the seventh embodiment (FIG. 37) is that the clock generation means 2103a has a clock rate of the received signal. A clock equal to twice the symbol rate is generated.

  The second difference from the pulse radio receiving apparatus of the seventh embodiment (FIG. 37) is that there is only one AD converter 2101-1. Therefore, the fixed delay means 2102 does not exist.

  That is, the detection signal sampling operation in the present embodiment has the same behavior as the detection signal sampling operation in the case where the delay amount of the fixed delay means 2102 is 0.5 symbols in the seventh embodiment (FIG. 37). Become.

  As a third difference from the pulse radio receiving apparatus of the seventh embodiment (FIG. 37), the demodulation means 2106a corresponds to the sample timing near the center of the symbol from the output from only one AD converter 2101-1. Only the values that have been selected are extracted. That is, two outputs from the AD converter 2101-1 are obtained for one symbol. Of these, the demodulator 2106a employs only the output corresponding to the sample timing close to the center of the symbol as demodulated data. Here, of the two sample timings, information indicating which is closer to the center of the symbol ("pulling result" in the figure) is notified from the delay control means 2105a (delay amount determining unit 2105-6 shown in FIG. 43). .

  FIG. 43 is a diagram showing a detailed configuration of delay control section 2105a in the pulse radio receiving apparatus according to the present embodiment. The same components as those in FIG. 38 are denoted by the same reference numerals and description thereof is omitted.

  The first difference from the delay control unit 2105 in FIG. 38 is that the symbol change detection unit 2105a-1 has only a value corresponding to the sample timing near the center of the symbol in the output from the AD converter 2101-1. To detect that the received data symbols have changed. That is, two outputs from the AD converter 2101-1 are obtained for one symbol. Of these, the symbol change detection unit 2105a-1 uses only the output corresponding to the sample timing close to the center of the symbol for detection processing. Here, information about which of the two sample timings is closer to the center of the symbol (“drawing result” in the figure) is notified from the delay amount determination unit 2105-6.

  As a second difference from the delay control unit 2105 of FIG. 38, the inter-finger difference detection unit 2105a-3 performs difference detection using the output from only one AD converter 2101-1. That is, when the symbol change detection unit 2105a-1 detects that the received data symbol has changed, at the time (for example, the timing of A2 in FIG. 39), the output immediately before the AD converter 2101-1 ( For example, B1) in FIG. 39 is compared with the previous output of AD converter 2101-1 (for example, A1 in FIG. 39), and it is detected that they are different.

  In addition, the delay control method by the delay control means 2105a is the same as in the seventh embodiment.

(Embodiment 9)
FIG. 44 is a block diagram showing a main configuration of the pulse radio receiving apparatus according to the ninth embodiment. 44, the same components as those in FIG. 37 are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, it is assumed that a transmission signal modulated by QPSK is transmitted as a modulation scheme from a transmission apparatus (not shown), and a pulse radio reception apparatus that receives an orthogonal modulation signal modulated by QPSK Shows an example of applying the present invention.

  The configuration of delay control means 2105 in the present embodiment is the same as that in the seventh embodiment (FIG. 38).

  As a first difference from the pulse radio receiving apparatus of the seventh embodiment (FIG. 37), the detection means 2100b detects a quadrature modulation signal and separates it into an I component and a Q component. There are various detection methods such as synchronous detection and delayed detection, but there is no particular limitation.

  As a second difference from the pulse radio receiving apparatus of the seventh embodiment (FIG. 37), an AD converter 2101-3 for sampling a Q component (or I component) detection signal is further provided.

  In the ninth embodiment, delay control is realized using a detection signal of either the I component or the Q component. The delay control method is the same as in the seventh embodiment. FIG. 44 shows a configuration in the case where an I component detection signal is used for delay control. The use of the Q component detection signal for delay control can be realized by reversing the outputs (I and Q) of the detection means 2100b.

  In FIG. 44, the delay control of the variable delay means 2104b is performed using the I component detection signal, and the result is reflected in the sample clock to the AD converter 2101-3 that samples the Q component detection signal. . In the configuration of FIG. 44, it is assumed that the sample timing of the AD converter 2101-1 is closer to the center of the symbol than the sample timing of the AD converter 2101-2. Therefore, the sample timing of the AD converter 2101-3 is also near the center of the symbol. When the sample timing of the AD converter 2101-2 is closer to the center of the symbol than the sample timing of the AD converter 2101-1, a fixed delay is used as a sample clock input to the AD converter 2101-3. By adopting the output of the means 2102, the sample timing of the AD converter 2101-3 can be set near the center of the symbol.

  Further, when the synchronization of the symbol synchronization is completed, the delay control unit 2105 (delay amount determination unit 2105) determines which of the sample timings of the AD converter 2101-1 and AD converter 2101-2 is closer to the center of the symbol. -6) shall be known. Therefore, as shown in FIG. 45, a selector 2107 is further provided for selecting a sample clock to be input to the AD converter 2101-3 in accordance with the state when the pull-in is completed, and the delay control means 2105 controls the selector 2107. It can also be taken. In this case, the selector 2107 supplies the output of the fixed delay unit 2102 or the variable delay unit 2104b to the AD converter 2101-3 as a sample clock in accordance with the control of the delay control unit 2105.

  The demodulating means 2106b in this embodiment performs demodulation using the output of the AD converter for the I component and the Q component. In the case of FIG. 44, since the AD converter 2101-1 and AD converter 2101-3 each sample the vicinity of the center of the symbol, these outputs are used for demodulation. Here, when the sample timing of the AD converter 2101-2 is closer to the center of the symbol than the sample timing of the AD converter 2101-1, the outputs of the AD converter 2101-2 and the AD converter 2101-3 are output. May be used for demodulation. Here, of the two AD converters 2101-1 and 2101-2, which sample timing is closer to the center of the symbol ("drawing result" in the figure) is the delay control means 2105 (delay amount determining unit). 2105-6).

  In addition, the delay control method by the delay control means 2105 is the same as that of the seventh embodiment.

(Embodiment 10)
FIG. 46 is a block diagram showing a main configuration of the pulse radio receiving apparatus according to the tenth embodiment. In FIG. 46, the same components as in FIG. 42 or FIG. In the present embodiment, it is assumed that a transmission signal modulated by QPSK is transmitted as a modulation scheme from a transmission apparatus (not shown), and a pulse radio reception apparatus that receives an orthogonal modulation signal modulated by QPSK Shows an example of applying the present invention.

  In the present embodiment, the clock generation means 2103a generates a clock whose clock rate is equal to twice the symbol rate of the received signal. That is, the sampling operation of the I component detection signal in FIG. 46 has the same behavior as the sampling operation of the I component detection signal when the delay amount of the fixed delay means 102 is 0.5 symbols in FIG.

  The configuration of delay control means 2105a in the present embodiment is the same as that in the eighth embodiment (FIG. 43).

  In FIG. 46, the delay control is realized by using the I component detection signal, but the Q component detection signal is changed by changing the input to the delay control means 2105 to the output of the AD converter 2101-3. It can correspond to the delay control used.

  Demodulating means 2106b in the present embodiment extracts only values corresponding to the sample timing near the center of each symbol from the outputs of AD converters 2101-1 and 2101-3, and uses them for demodulation. That is, two outputs from the AD converters 2101-1 and 2101-3 are obtained for each symbol. Of these, the demodulator 2106b uses only the output corresponding to the sample timing close to the center of the symbol for demodulation. Here, information about which of the two sample timings is closer to the center of the symbol ("pulling result" in the figure) is notified from the delay determining means 2105a (delay amount determining unit 2105-6 shown in FIG. 43). .

  In addition, the delay control method by the delay control means 2105a is the same as in the seventh embodiment.

  Note that the delay control method according to the present invention can cope with a case where the duty ratio of the received signal is not 0.5. That is, as shown in FIG. 47, even when the duty ratio of the detection signal is not 0.5 (the time when output = 1 is shorter than the time when output = 0), the Sync state (FIG. 47a) The cases where the output results of the AD converters at the fingers A1 and B1 (or fingers A2 and B2) are equal and different appear randomly depending on the received data pattern. On the other hand, in the Early state (FIG. 47b), the probability that the output results of the AD converters in the fingers A1 and B1 (or fingers A2 and B2) are equal increases. Further, in the Late state (FIG. 47c), there is a high probability that the output results of the AD converters in the fingers A1 and B1 (or fingers A2 and B2) are different.

(Embodiment 11)
In the eleventh embodiment, the synchronization preamble is composed of a signal sequence in which a known signal sequence of length N (N is an integer of 2 or more) symbols is repeated M (M is an integer of 1 or more) times. To do. The symbol length is T.

  FIG. 48 is a block diagram showing a main configuration of pulse radio receiving apparatus 4000 in the eleventh embodiment. As shown in FIG. 48, the pulse radio receiving apparatus 4000 includes an antenna 4100, detection means 4101, sampling means 4102, demodulation means 4103, synchronization control means 4104, variable delay means 4105, and clock generation means 4106.

  The antenna 4100 receives a signal transmitted from a transmission device (not shown) and passes the received signal to the detection unit 4101.

  The detection unit 4101 includes, for example, a low-pass filter, detects an envelope of the received signal, that is, a line that smoothly connects the maximum points of the received signal, and outputs the detected signal to the sample unit 4102 as an envelope signal.

  The clock generation unit 4106 generates a clock signal at a frequency equivalent to the transmission rate of the received signal and outputs it to the variable delay unit 4105.

  The variable delay unit 4105 performs variable delay control on the clock signal from the clock generation unit 4106 based on the delay control signal provided from the synchronization control unit 4104, and outputs a synchronization clock signal synchronized with the envelope signal to the sample unit 4102. .

  The sample means 4102 is composed of, for example, an A / D converter having a resolution of n (n is an integer of 1 or more) bits, and is detected by the detection means 4101 at the timing when the synchronous clock signal from the variable delay means 4105 is input. The envelope signal thus converted is converted from an analog signal to a digital signal, and the sample value is output to the demodulation means 4103 and the synchronization control means 4104. Since the transmission rate of the synchronous clock signal is the same as the transmission rate of the detection signal, the sampling means 4102 outputs one sample value per symbol.

  The demodulating means 4103 is constituted by a comparator, for example, and demodulates the received signal by comparing the sample value given from the sample means 4102 with a predetermined threshold value, and obtains a demodulation result.

  The synchronization control unit 4104 is configured as shown in FIG. 49, for example, and includes a memory 4104-1, a correlation calculation unit 4104-2, an identification point detection unit 4104-3, and a delay control unit 4104-4.

  The memory 4104-1 stores N consecutive sample values given from the sample unit 4102. When N sample values are accumulated, the stored N sample values are output to the correlation calculation unit 4104-2. .

  The correlation calculation means 4104-2 performs a correlation calculation between the N sample values given from the memory 4104-1 and the known signal sequence, and outputs the correlation value to the discrimination point detection means 4104-3. Accordingly, the correlation value is output once every N symbols.

  The discrimination point detection means 4104-3 detects the timing of the discrimination point, that is, the center of the symbol based on the continuous M correlation values given from the correlation calculation means 4104-2, and delays timing information indicating the location of the discrimination point. It outputs to the control means 4104-4. Therefore, the timing information is output once for N × M symbols.

Delay control means 4104-4 changes the delay amount of variable delay means 4105 by iT (iT <T) in N symbol periods when pulse radio receiving apparatus 4000 starts synchronization pull-in.
The delay control means 4104-4 sets the delay amount of the variable delay means 4105 to i after the lapse of the N × M symbol period, that is, when timing information is input from the discrimination point detection means 4104-3.
In order to change only τ, a delay control signal is output to the variable delay means 4105.

  With the configuration as described above, the pulse radio receiving apparatus 4000 realizes symbol synchronization, that is, processing for aligning the timing of the envelope signal and the clock signal.

  FIG. 50 is a flowchart showing the symbol synchronization operation of pulse radio receiving apparatus 4000 in the eleventh embodiment of the present invention. Pulse radio receiving apparatus 4000 receives the received signal in Step 5001 and starts symbol synchronization. Next, at Step 5002, the sampling means 4102 samples the envelope signal, and outputs the sample value to the demodulating means 4103 and the synchronization control means 4104. Next, in Step 5003, the synchronization control means 4104 determines whether or not N sample values are stored in the memory 4104-1. If N sample values are not stored (Step 5003: No), the process returns to Step 5002, and the sampling means 4102 samples the envelope signal. When N sample values are accumulated in the memory 4104-1 (Step 5003: Yes), the memory unit 4104-1 outputs N sample values to the correlation calculation unit 4104-2.

Next, in Step 5004, a correlation value between the N sample values and the known signal sequence is calculated by the correlation calculation means 4104-2. The calculated correlation value is output to the discrimination point detection means 4104-3. Next, in Step 5005, the synchronization control means 4104 determines whether M correlation values have been obtained. When the number of obtained correlation values is less than M (Step 5005: No), in Step 5006, the delay control unit 4104-4 outputs a delay control signal to the variable delay unit 4105, and the delay amount of the variable delay unit 4105 is set to ΔT. Just change. Step 50 until M correlation values are obtained
Repeat the process from 02 to Step5005. When M correlation values are obtained (Step 5005: Yes), in Step 5007, the position of the discrimination point is detected by the discrimination point detection means 4104-3.

Here, a method for detecting an identification point will be described. As an example, it is assumed that the known signal sequence is “10110100” of N = 8 symbols, and the preamble is a signal sequence obtained by repeating the known signal sequence M = 8 times. Also, ΔT = T / 8. If the sample is overwritten while shifting the timing by ΔT in Step 5006, the result is as shown in FIG. T _{1 to} T ₈ in the figure represent sample timings, and it is as if one symbol is oversampled. Actually, since T ₁ to T ₈ span a plurality of symbols, the state of the sample is as shown in FIG. 52, and the sample is performed at the timing of T _{1 in} the first known signal sequence. The next known signal, the timing of the sample the sample is performed at the timing of T ₂ because it is ΔT shifted. In the eighth known signal in the same manner a sample at the timing of T ₈ is performed. Since the sample timing differs for each known signal sequence, the horizontal axis represents the sample timing and the vertical axis represents the correlation value, as shown in FIG. From Figure 53, highest correlation value in the T ₅ is a timing close to the decision point is maximized, it can be seen that the correlation value in T ₁ closest to the change point is minimized. The position of the identification point can be detected using the characteristic of the correlation value. As the simplest method, there is a method of detecting the timing when the correlation value becomes maximum as the position of the identification point. Another method may be a method in which a change point, that is, a timing at which the correlation value is minimized is detected, and a timing shifted by T / 2 from that timing is detected as the position of the identification point. When the waveform of the envelope approaches a trapezoidal shape, the difference in correlation value near the identification point becomes small, and it may be difficult to detect the identification point. In such a case, the latter method of detecting the change point is effective. The position of the identification point is detected as described above.

When the position of the discrimination point is detected, the discrimination point detection unit 4104-3 outputs timing information indicating the location of the discrimination point to the delay control unit 4104-4 in Step 5007. In this example the timing of T ₅ is the position of the identification point. Next, in Step 5008, the delay control unit 4104-4 calculates the delay amount Δτ of the variable delay unit 4105 in order to align the timings of the clock signal and the detection signal. Δτ is calculated as follows. Sample timing at the time the position of the identification point is detected is T _8. Since the position of the identification point is T _5, Δτ = T ₈ −T ₅ = −3
ΔT. Since the sample timing must be shifted forward, it has a minus sign. The delay control signal calculated in this way is given to the variable delay means 4105, and the timing of the clock signal is shifted by Δτ. Then, symbol synchronization ends (Step 5009).

  When the resolution of the A / D converter constituting the sample means 4012 is n = 1 bit, the A / D converter outputs only a binary value, so that a comparator is used instead of the A / D converter. Can do. In this case, the demodulating means 4103 at the subsequent stage is not necessary. At this time, since there is no difference in the correlation value at the sample timing near the discrimination point, the discrimination point detection means 4104-3 detects the change point, and the position shifted by T / 2 from the change point position is set as the discrimination point position. We will use the method to do. Further, in an environment where the SNR is very high, even if the timing slightly deviated from the change point is sampled, a difference in the correlation value with the vicinity of the identification point is less likely to appear. This is because when the SNR is high, bit errors are less likely to occur near the change point. Therefore, in order to easily cause a bit error, the offset voltage of the input signal to the A / D converter and the threshold value of the comparator may be intentionally shifted from the values used for demodulation during symbol synchronization.

  When the method of detecting change points in the discrimination point detection means 4104-3 is adopted, the difference between the change points and other correlation values becomes smaller as the number of change points in the known signal sequence decreases. Therefore, it is desirable to make the difference between the detection signal change point and the other amplitude difference as large as possible. To achieve this, during symbol synchronization, the cut-off frequency of the low-pass filter of the detection means 4101 is set higher than the value during normal communication operation, and the detection signal changes near the change point by making the slope of the detection signal steep. The point and other amplitude differences may be made larger.

(Embodiment 12)
FIG. 54 is a block diagram showing a configuration of pulse radio receiving apparatus 4000a according to the twelfth embodiment, where a plurality of sample means 4102 (sample means 4102-1 and 4102-2) are provided in parallel. Different from Form 11. In FIG. 54, sampling means 4102-1 and 4102-2 are composed of an n = 1 bit A / D converter or a comparator. The output signal of the sample means 4102-1 and 4102-2 becomes demodulated data. Therefore, the selector 4108 is provided in the subsequent stage of the sample means 4102-1 and 4102-2, and one of the output signals of the two sample means 4102-1 and 4102-2 is selected. If the sampling means used as demodulated data is determined in advance, the selector 4108 is unnecessary. Further, a predetermined phase difference is given to the synchronous clock signal supplied to the two sampling means 4102-1 and 4102-2 by the fixed delay means 4107. For example, this phase difference is iT.

  As shown in FIG. 55, the synchronization control means 109 includes an XOR operation means 4109-1, an identification point detection means 4109-2, and a delay control means 4109-3. The XOR operation means 4109-1 detects whether the demodulated data given from the two sample means 4102-1 and 4102-2 are the same or different, and outputs the detection result to the discrimination point detection means 4109-2. Since it is an XOR operation, “0” is output if the two demodulated data are the same, and “1” is output if they are different. The discrimination point detection means 4109-2 regards the sample timing when “1” is input from the XOR operation means 4109-1 as the change point position, regards the position shifted by T / 2 as the discrimination point position, and identifies the discrimination point. The timing information indicating the position is output to the delay control means 4109-3.

The state of the sample is shown in FIG. Since there are two sample means 4102, two sample values can be obtained per symbol. In FIG. 56, for example, sample values at (T ₁ , T ₂ ) indicated by black arrows are sample values obtained simultaneously. Since sampling is performed while the sample timing is shifted by ΔT, the sample values at the black arrows (T ₂ , T ₃ ) are obtained simultaneously. Similarly, (T ₃ , T ₄ ) indicated by white arrows are sample values obtained simultaneously. When the sample is repeated while shifting the timing by ΔT in this way, the synchronous clock signal supplied to the two sample means 4102-1 and 4102-2 as indicated by white arrows (T ₇ and T ₈ ) changes. Straddle. At this time, the demodulated data of the sample values obtained from the two sample means 4102-1 and 4102-2 indicate different results, and the output of the XOR operation means 4109-1 becomes “1”. Symbol synchronization is realized by detecting change points as described above. That is, the discrimination point detection means 4109-2 uses the sample timing when “1” is input from the XOR operation means 4109-1 as described above as the change point position, and the position shifted by T / 2 from the sample timing as the discrimination point. Timing information indicating the position of the identification point is output to the delay control means 4109-3.

Note that the center of the section where the demodulated data from the two sample means 4102-1 and 4102-2 are the same may be detected as the timing of the identification point. In actual wireless communication, the duty ratio of the pulse fluctuates as shown in FIG. 57 due to intersymbol interference, delayed wave interference, etc., and the position of the changing point changes. For this reason, there is a possibility that symbol synchronization cannot be performed properly by the method of detecting the position of the discrimination point from the position of the change point. On the other hand, the position of the discrimination point does not change if the symbol rate is constant. Therefore, as shown in FIG. 58, the center of the section where the two demodulated data are the same is set as the timing of the identification point. In FIG. 58, the timing of black circles or white circles is the section where the demodulated data is the same. Therefore, the timing from T ₃ to T ₁₀ is the timing when the demodulated data is the same, and the center (T ₃ -T ₁₀ ) / 2 is the position of the discrimination point.

(Embodiment 13)
The configuration of the pulse radio receiving apparatus according to the thirteenth embodiment is basically the same as that shown in FIG. 54, but the configuration of synchronization control means 4109 is different. FIG. 59 shows the configuration of synchronization control means 4109b in the thirteenth embodiment. In the thirteenth embodiment, the sampling means 4102 is an A / D converter having a resolution of n (n is an integer of 1 or more) bits, and the delay amount of the fixed delay means 4107 is T / 2.

  As shown in FIG. 59, the synchronization control means 4109b includes subtraction means 4109-4, absolute value calculation means 4109-5, minimum value detection means 4109-6, subtraction means 4109-7, absolute value calculation means 4109-8, identification. Point detection means 4109-9 and delay control means 4109-10 are provided. The subtracting means 4109-4 subtracts V shown in FIG. 60 from the sample values from the two sample means 4102-1 and 4102-2. Here, V is a value representing the amplitude level of the changing point. Therefore, the output of the subtracting means 4109-4 represents the amplitude difference between the change point and the sample point. The subtraction means 4109-4 outputs the subtraction result to the absolute value calculation means 4109-5. The absolute value calculation means 4109-5 calculates the absolute value of the subtraction result given from the subtraction means 4109-4 and outputs it to the minimum value detection means 4109-6. The minimum value detection means 4109-6 detects the minimum value from the absolute values given from the absolute value calculation means 4109-5, and outputs the detected minimum value to the subtraction means 4109-7.

  The subtracting means 4109-7 calculates the difference between the two minimum values given from the minimum value detecting means 4109-6, and outputs the calculation result to the absolute value calculating means 4109-8. The absolute value calculation means 4109-8 calculates the absolute value of the subtraction result given from the subtraction means 4109-7 and outputs it to the discrimination point detection means 4109-9. The discrimination point detection means 4109-9 detects the position of the discrimination point based on the absolute value given from the absolute value calculation means 4109-8. The discrimination point detection means 4109-9 detects the timing of the sample means having the larger sample value at the sample timing at which the absolute value is maximized as the discrimination point position, and delays timing information indicating the discrimination point position. It outputs to the control means 4109-10.

FIG. 60 shows a sample. In the thirteenth embodiment, since the delay amount of the fixed delay means 4107 is T / 2, the sample timing phase difference between the two sample means 4102-1 and 4102-2 is T / 2. Therefore, in FIG. 60, the combinations of (T ₁ , T ₅ ), (T ₂ , T ₆ ), (T ₃ , T ₇ ), (T ₄ , T ₈ ) are sample values obtained simultaneously. When the sample value at the timing T _n and S _n, to calculate the S _n -V In subtraction means 4109-4. Although it is seen from Figure 60, the S _n -V = 0 when the sample change point. Since the sign of the subtraction result of the subtracting means 4109-4 is inverted depending on whether the bit sampled by the sampling means 4102-1 and 4102-2 is “1” or “0”, the absolute value calculating means 4109-5 The size | S _n −V | of the subtraction result of 4109-4 is extracted.

Then a minimum value detecting means 4109-6, | detects the S _n -V | minimum value Min of (| | S _n -V). Because the sample means 4102 samples more than once at the same timing, if the signal is such as that NRZ reduction, the same bit is continuous, even as the sample timing was in the change point, the value of S _n -V 0 do not become. Therefore, in order to correctly detect the timing of the change point, a minimum value detection means 4109-6 is provided.

Next, the subtracting means 4109-7 calculates the difference of Min (| S _n −V |) obtained from the respective sample means 4102-1 and 4102-2. For example, in the case of a combination of (T ₁ , T ₅ ), Min (| S ₁ −V |) −Min (| S ₅ −V |) is calculated. As can be seen from FIG. 60, the value of Min (| S ₁ −V |) −Min (| S ₅ −V |) becomes maximum or minimum when the two sample timings are at the change point and the discrimination point. Therefore, in the next absolute value calculation means 4109-8, the absolute value of Min (| S ₁ -V |) -Min (| S ₅ -V |) | Min (| S ₁ -V |) -Min (| S ₅ -V |) | The discrimination point detection means 4109-9 detects a combination of timings at which | Min (| S ₁ −V |) −Min (| S ₅ −V |) | In FIG. 60, the maximum value is detected when the combination is (T ₁ , T ₅ ). Further discrimination point detection unit 4109-9 determines the timing towards the amplitude of the sample value is greater in the T ₁ and T _5, to detect the timing of the more greater as the position of the identification point. Since more of Figure 60 in T ₅ is larger amplitude discrimination point detection unit 4109-9 detects a T ₅ as the position of the identification point. Symbol synchronization is realized as described above.

Block diagram of pulse radio transmission apparatus having OOK modulation in Embodiment 1 of the present invention Pulse train of OOK modulator output having RZ modulation and NRZ OOK modulation in Embodiment 1 of the present invention Pulse train of transmission signal having carrier frequency fc in Embodiment 1 of the present invention Block diagram of pulse radio receiving apparatus having OOK demodulation and envelope detection in Embodiment 1 of the present invention The figure of the detection means which has the diode and low-pass filter in Embodiment 1 of this invention The figure which shows the signal envelope of the LPF output of the bit string "01011010" in Embodiment 1 of this invention The figure of the synchronizer which has two sample means in Embodiment 1 of this invention Another block diagram of the synchronizing device having two sample means in the first embodiment of the present invention The figure which shows the sample of the signal envelope in the two sample means of the synchronizer of FIG. 7 in Embodiment 1 of this invention. 7 is a flowchart of the synchronization pull-in method of the synchronization device of FIG. 7 in Embodiment 1 of the present invention. The figure which shows the waveform of the pulse signal at the time of synchronous drawing in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous drawing in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous drawing in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous drawing in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous drawing in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous drawing in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous drawing in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous drawing in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous drawing in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the envelope signal of the LPF output in the synchronous tracking in Embodiment 1 of this invention 7 is a flowchart of the synchronization tracking method of the synchronization device of FIG. 7 in Embodiment 1 of the present invention. The figure which shows the waveform of the pulse signal at the time of synchronous tracking in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous tracking in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous tracking in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous tracking in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous tracking in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous tracking in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous tracking in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous tracking in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous tracking in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention The figure which shows the waveform of the pulse signal at the time of synchronous tracking in the synchronizing apparatus of FIG. 7 in Embodiment 1 of this invention Another block diagram of a pulse radio receiving apparatus having OOK demodulation and envelope detection according to Embodiment 1 of the present invention The figure which shows the waveform of the pulse signal in Embodiment 2 of this invention The block diagram which shows the structure of the pulse radio | wireless receiver in Embodiment 2 of this invention. The figure which shows the output signal of each means of the receiver in Embodiment 2 of this invention The figure which shows the positional relationship on the time-axis of the envelope signal and clock signal when the synchronization establishment in Embodiment 2 of this invention is established The figure which shows the example of control of the delay amount of the variable delay means 1308 in Embodiment 2 of this invention. The flowchart which shows the synchronous operation | movement of the receiver in Embodiment 2 of this invention The figure which shows the waveform of the pulse signal in Embodiment 3 of this invention The block diagram which shows the structure of the receiver in Embodiment 3 of this invention. The figure which shows the output signal of each means of the receiver in Embodiment 3 of this invention The flowchart which shows the synchronous operation of the receiver in Embodiment 3 of this invention The block diagram which shows the structure of the pulse radio | wireless receiver in Embodiment 4 of this invention. The flowchart which shows the synchronous operation | movement of the pulse radio | wireless receiver in Embodiment 4 of this invention The figure which shows the timing control of the clock signal in Embodiment 4 of this invention The block diagram which shows the other structure of the pulse radio | wireless receiver in Embodiment 4 of this invention Block diagram showing a configuration of a pulse radio receiving apparatus according to a fifth embodiment of the present invention The flowchart which shows the synchronous state detection operation | movement of the pulse radio | wireless receiver in Embodiment 5 of this invention The figure which shows the synchronous state in Embodiment 5 of this invention The block diagram which shows the other structure of the pulse radio | wireless receiver in Embodiment 5 of this invention. The figure which shows the pseudo-synchronization state in Embodiment 5 of this invention The block diagram which shows the other structure of the pulse radio | wireless receiver in Embodiment 5 of this invention. Block diagram showing a configuration of a pulse radio receiving apparatus according to Embodiment 6 of the present invention The figure which shows the structure of the conventional receiver The figure which shows the received signal after envelope detection at the time of transmitting NRZ-encoded pulse signal “101” The block diagram which shows the principal part structure of the pulse radio | wireless receiving apparatus in Embodiment 7 of this invention. The figure which shows the detailed structure of the delay control means in Embodiment 7 of this invention. FIG. (1) for explaining the concept of the delay control method by the delay control means in the seventh embodiment of the present invention; FIG. (1) for explaining the concept of the delay control method by the delay control means in the seventh embodiment of the present invention; FIG. (1) for explaining the concept of the delay control method by the delay control means in the seventh embodiment of the present invention; FIG. (2) for explaining the concept of the delay control method by the delay control means in the seventh embodiment of the present invention; FIG. (2) for explaining the concept of the delay control method by the delay control means in the seventh embodiment of the present invention; FIG. (2) for explaining the concept of the delay control method by the delay control means in the seventh embodiment of the present invention; Flowchart of delay control method by delay control means in Embodiment 7 of the present invention The block diagram which shows the principal part structure of the pulse radio | wireless receiver in Embodiment 8 of this invention. The figure which shows the detailed structure of the delay control means in Embodiment 8 of this invention. The block diagram which shows the principal part structure of the pulse radio | wireless receiver in Embodiment 9 of this invention. The block diagram which shows the other example of the principal part structure of the pulse radio | wireless receiver in Embodiment 9 of this invention. FIG. 10 is a block diagram showing a main configuration of a pulse radio receiving apparatus according to the tenth embodiment of the present invention. The figure for demonstrating the concept of the delay control method by the delay control means in Embodiment 10 of this invention. The figure for demonstrating the concept of the delay control method by the delay control means in Embodiment 10 of this invention. The figure for demonstrating the concept of the delay control method by the delay control means in Embodiment 10 of this invention. The block diagram which shows the principal part structure of the pulse radio | wireless receiver in Embodiment 11 of this invention The block diagram which shows the detailed structure of the synchronous control means in Embodiment 11 of this invention. The flowchart which showed the symbol synchronization operation | movement of the pulse radio | wireless receiver in Embodiment 11 of this invention FIG. (1) for explaining a discrimination point detection method according to Embodiment 11 of the present invention; FIG. (2) for explaining the discrimination point detection method according to Embodiment 11 of the present invention; FIG. (3) for explaining a discrimination point detection method according to Embodiment 11 of the present invention; The block diagram which shows the principal part structure of the pulse radio | wireless receiver in Embodiment 12 of this invention. The block diagram which shows the detailed structure of the synchronous control means in Embodiment 12 of this invention. The figure for demonstrating the detection method of the change point in Embodiment 12 of this invention. FIG. 12 is a diagram (1) for explaining another example of the discrimination point detection method according to the twelfth embodiment of the present invention. FIG. (2) for explaining another example of the discrimination point detection method according to the twelfth embodiment of the present invention. Block diagram showing a detailed configuration of the synchronization control means according to the thirteenth embodiment of the present invention. The figure for demonstrating the detection method of the identification point in Embodiment 13 of this invention.

Explanation of symbols

100 pulse radio transmitter 104 channel encoder 106 interleaver 108 OOK modulator 110 pulse generator 112 oscillator 114 power amplifier 116 antenna 202 symbol length 302 carrier frequency 408 detection means 400, 1200, 1300, 1400, 1500 pulse radio receiver 410 comparison Means 412 Synchronization control means 414 Clock generation means 416 Deinterleaver 418 Channel decoder 502 Diode 504 Low pass filter 701 Splitter 704, 706 AD converter 708 Variable delay means 710 Fixed delay means 712 Delay control means 1300 Pulse wireless receiver 1301 Antenna 1302 Automatic Gain control means 1303 Detection means 1304 First fixed delay means 1305 First sampling means 1 06 Second sampling means 1307 Clock generation means 1308 First variable delay means 1309 Third fixed delay means 1310 First threshold judgment means 1311 Second threshold judgment means 1312 Edge detection means 1313 Second fixed delay means 1314 Synchronization control means 1409 Second variable delay means 1415 Hold means 1416 Addition means 1417 Fourth fixed delay means 1418 Second synchronization control means 1501 Detection means 1502 Clock generation means 1503 Delay means 1504 Sample means 1505 Relative difference calculation means 1506 Synchronization Control unit 1507 Synchronization state detection unit 1508 Pseudo synchronization detection unit 1509 Demodulation unit 1531 Variable delay unit 1532 Fixed delay unit 1541, 1542 A / D converter 1551 Maximum value detection unit 1552 Minimum value detection unit 1571, 1582 Absolute value calculation means 1572, 1583 Comparison means 1584 Averaging means 2100, 2100b, 4101 Detection means 2101-1, 2, 3 AD converter 2102, 4107 Fixed delay means 2103, 2103a, 4106 Clock generation means 2104, 2104b , 4105 Variable delay means 2105, 2105a Delay control means 2105-1, 2105a-1 Symbol change detection section 2105-2 Counter 1
2105-3, 2105a-3 inter-finger difference detection unit 2105-4 counter 2
2105-5 Early / Late determination unit 2105-6 Delay amount determination unit 2106, 2106a, 2106b, 4103 Demodulation unit 4000, 4000a Pulse radio receiver 4100 Antenna 4102, 4102-1, 4102-2 Sample unit 4104, 4109, 4109b Synchronization Control means 4104-1 Memory 4104-2 Correlation calculation means 4104-3, 4109-2, 4109-9 Discrimination point detection means 4104-4, 4109-3, 4109-10 Delay control means 4109-1 XOR calculation means 4109-4 , 4109-7 Subtraction means 4109-5, 4109-8 Absolute value calculation means 4109-6 Minimum value detection means

Claims (16)

Detecting means for detecting an envelope signal of the OOK modulation signal;
Clock generating means for generating a reference clock signal;
Synchronization control means for performing timing synchronization between the OOK modulation signal and the reference clock signal;
A pulse radio receiver comprising:
The synchronization control means includes
First sampling means for sampling the envelope signal at a first sample timing and generating a first sample value;
A second sample means for sampling the envelope signal at a second sample timing to generate a second sample value;
Delay control means for generating a delay control signal using the first and second sample values;
First delay means for generating the first sample timing and the second sample timing in response to the delay control signal from the reference clock signal;
Second delay means for generating a delay of a predetermined time between the first sample timing and the second sample timing;
A pulse radio receiver comprising: The first sample timing is:
A delayed clock signal output from the first delay means;
The second sample timing is:
A delayed clock signal output from the second delay means;
The radio reception apparatus according to claim 1, wherein the second delay unit further delays the delayed clock signal output from the first delay unit. The second delay means includes
Delay the envelope signal;
The first sample timing is:
A delayed clock signal output from the first delay means;
The second sample timing is:
The radio reception apparatus according to claim 1, wherein the delay clock signal is output from the first delay means. The delay control means includes
The radio reception according to any one of claims 1 to 3, wherein the delay control signal is generated using an amplitude difference between two consecutive first sample values and an amplitude difference between two consecutive second sample values. apparatus. The second delay means includes
4. The pulse radio receiving apparatus according to claim 1, wherein the first sample timing or the envelope signal is delayed by a half of a symbol length of the OOK modulation signal. 5. A synchronization method for performing timing synchronization between an NRZ-encoded OOK modulation signal and a reference clock signal,
Grouping rising and falling edges of an envelope signal having the same sign as a pair of detection edges;
Performing synchronous tracking with the detected pair of detected edges;
A synchronization method. A first threshold value judging means for comparing the first sample value with a predetermined threshold value and outputting a first judgment signal indicating a difference from a peak point of the envelope signal;
A second threshold value judging means for comparing the second sample value with the threshold value and outputting a second judgment signal indicating a difference from the change point of the envelope signal;
Further comprising
The delay control means includes
The radio reception apparatus according to any one of claims 1 to 3, wherein a first delay control signal for adjusting the first delay means is output using the first determination signal and the second determination signal. The second delay control means for outputting a second delay control signal for adjusting the second delay means using the second determination signal and the first delay control signal. Wireless receiver.   The pulse radio receiving apparatus according to claim 7, wherein the second comparison result output from the second threshold determination unit is used as demodulated data. A relative difference calculating means for generating a relative amplitude difference signal indicating a difference between the maximum value of the first sample value and the maximum value of the second sample value;
The delay control means includes
The radio reception apparatus according to claim 1, wherein a delay control signal for controlling a delay amount of the first delay means is output based on the relative amplitude difference signal. A first difference is detected from the maximum and minimum values of the first sample value, a second difference is detected from the maximum and minimum values of the second sample value, and the first and second differences are detected. And a relative difference calculating means for generating a relative amplitude difference signal based on
The delay control means includes
The radio reception apparatus according to claim 1, wherein a delay control signal for controlling a delay amount of the first delay means is output based on the relative amplitude difference signal.   Synchronization state detection for detecting that the received signal and the first and second synchronization clock signals are in a synchronized state when the value of the relative amplitude difference signal output from the relative difference calculating means is equal to or less than a predetermined threshold value. The pulse radio receiver according to claim 11, comprising means.   13. The pulse radio receiving apparatus according to claim 12, wherein the synchronization control means holds control of the phase of the clock signal when it is in a synchronization state based on the synchronization state detected by the synchronization state detection means.   When the difference between the first and second sample values output from the sample means is equal to or greater than a predetermined threshold, it is detected that the received signal and the first and second synchronous clock signals are in a pseudo-synchronized state. The pulse radio receiving apparatus according to claim 12, further comprising pseudo-synchronized state detecting means.   15. The pulse radio receiving apparatus according to claim 14, wherein, when the pseudo-synchronization state detection unit detects the pseudo-synchronization state, the synchronization control unit outputs a phase control signal to the delay unit to avoid the pseudo-synchronization state. .   Demodulating means for generating binary demodulated data by selecting the first and second sample values outputted from the sampling means based on the relative amplitude difference signal outputted from the relative difference calculating means. The pulse radio receiving apparatus according to claim 11.

Images