JP2008252748A - Receiving frame processor and receiving frame processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiving frame processor which can enhance memory use efficiency, reduce the latency of a frame, and can decrease a load of a CPU, and a receiving frame processing system. <P>SOLUTION: The receiving frame processor receives a frame of a variable length from a network 2, and transfers the frame to a buffer group 42 provided on a system memory 4 as a shared area to a CPU 5. The buffer group 42 is configured of a plurality of buffers, and when the buffer group 42 receives a second frame before a certain time period passes after the buffer group 42 has transferred a first frame to a first buffer, the buffer group 42 transfers the second frame to the first buffer. Further, when the buffer group 42 receives the second frame before a certain time period or longer passes after the buffer group 42 has transferred the first frame to the first buffer, the buffer group 42 transfers the second frame to a second buffer after the right of ownership of the first buffer is granted to the CPU 5. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a received frame processing apparatus and a received frame processing system, and more particularly to a received frame processing apparatus and a received frame processing system for processing a variable-length frame received from a network.

  In communication systems such as Ethernet (registered trademark), IEEE 1394, and USB, communication is performed by transmitting and receiving data in units of variable-length frames. In general, when a computer system (hereinafter simply referred to as a system) captures data from a network, the received frame is temporarily stored in a buffer provided in the system memory, and a necessary frame is stored in the buffer from a predetermined frame. A method of reading according to the rules is used.

  As a conventional typical buffer management method, a management method for storing only one frame in one buffer (hereinafter referred to as an unpack mode) and a management method for storing one or more frames in one buffer (hereinafter referred to as an unpacking mode) , Indicated as pack mode).

  In the conventional unpacking mode, only one frame is stored for each buffer, and even if there is free space, the next frame is not packed and stored. Therefore, there is a problem that the use efficiency of the buffer memory is lowered.

  Even in the conventional unpacking mode, it is possible to improve the use efficiency of the buffer memory by reducing the buffer size. However, since the number of buffers increases as the buffer size decreases, another problem arises that the buffer management area increases.

  In the conventional pack mode, one buffer is packed and stored in one buffer. Therefore, the buffer that stores the frame is not released when there is sufficient free space (ownership is not transferred to the system side). Therefore, particularly when the frame reception interval is long, there is a problem that a delay time (hereinafter referred to as latency) from reception of a frame to processing becomes large.

  Even in the conventional pack mode, the system performs a time-out process, and when frame reception does not occur for a certain period of time, it ignores the ownership of the buffer and forcibly reads the contents of the frame stored in the buffer to reduce latency. It is possible to make it smaller. However, in that case, it is necessary to prepare a time-out mechanism on the system side, and it is necessary to store the frame portion read from the buffer for which ownership is not acquired on the system side.

  Furthermore, when the same buffer is read next time the ownership is transferred to the system side, it is necessary to perform processing such as skipping the already read frame. Regardless of the ownership of the buffer, it is possible to reduce the latency even in the packed mode by reading the buffer from the system side, but there is another problem that the processing on the system side becomes complicated To do.

  Further, in the conventional buffer management technique, when a system notifies the arrival of a frame when an interrupt occurs, an interrupt is often generated for each frame. If an interrupt is generated each time a frame is received, the interrupt frequency increases and the CPU load increases as the frame reception frequency increases.

  Conventionally, as a reception frame processing apparatus that handles a variable-length frame, a reception frame processing apparatus that has a plurality of buffers having different lengths and switches a buffer to be stored according to the length of the received frame has been proposed. (For example, refer to Patent Document 1).

  According to the proposal described in Patent Document 1, on the premise that one frame is stored in one buffer, the length and the number of buffers are prepared by predicting the length of a frame to be received in advance. . However, if the length of the actually received frame is significantly different from the length of the prepared buffer, for example, it is short despite having prepared a number of long buffers in anticipation of receiving long frames. When a large number of frames are received, a short frame is stored in a long buffer, and there is a problem in that the use efficiency of the buffer memory is lowered. Further, when a large number of short buffers are prepared, the number of buffers increases, and there is a problem that a memory area for storing buffer information and managing the buffers increases.

Furthermore, when consecutive frames of different sizes are received, the respective frame storage locations are scattered at positions that are skipped on the system memory. Compared to the case where the frames are continuously arranged on the system memory, the CPU cache does not function efficiently and the load on the CPU becomes high when the frames are arranged at skipped positions. There was a problem. Another problem is that a mechanism for selecting a buffer of an appropriate size from among the free buffers is required.
JP 2002-185466 A

  The present invention has been made in view of the above points. A reception frame processing device and a reception frame processing system capable of improving memory use efficiency, reducing frame latency, and reducing the load on the CPU. The purpose is to provide.

  A received frame processing apparatus according to an aspect of the present invention is a received frame processing apparatus that receives a variable-length frame from a network and transfers the frame to a buffer area that is provided on a system memory and is a shared area with a CPU. The buffer area is composed of a plurality of buffers, and when the second frame is received before a predetermined time has passed since the first frame was transferred to the first buffer, The first frame is transferred to the first buffer, and the second frame is received after a lapse of a predetermined time after the first frame is transferred to the first buffer. The second frame is transferred to the second buffer after the ownership of the buffer is transferred to the CPU.

  The memory use efficiency can be improved, the frame latency can be reduced, and the load on the CPU can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
First, the configuration of the reception frame processing apparatus 1 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of a reception frame processing apparatus 1 according to an embodiment of the present invention.

  As shown in FIG. 1, the received frame processing apparatus 1 according to the present embodiment uses a communication method such as Ethernet (registered trademark) to communicate data with a network 2 and a computer system. Are electrically connected to the system bus 3 for transmitting and receiving the data. The system bus 3 is also connected to a frame received from the network 2 via the received frame processing device 1 and a system memory 4 for storing various data, and a CPU 5 for performing various processes using these frames and data. ing.

  In the reception frame processing device 1, a frame received from the network 2 is temporarily stored in the small capacity memory 11 via the frame processing unit 12. The small-capacity memory 11 is generally composed of a FIFO or the like, and mainly performs burst transfer to the system memory 4 via the system bus 3 (transfer method for continuously sending frames to the system bus 3). Used as a buffer for Even if there is a frame arriving from the network 2, the frame cannot be immediately transferred to the system memory 4 when the system bus 3 is busy. In such a case, once the frame is temporarily stored in the small-capacity memory 11, burst transfer is performed.

  In addition, since the clock (operating frequency) is often different between the network 2 and the system bus 3, the small capacity memory 11 is also used as a buffer memory for exchanging frames between different clock domains.

  The frame received from the network 2 is output to the frame processing unit 12 and analyzed, and the frame length, the frame interval, and the like are detected and measured. The frame stored in the small capacity memory 11 may be directly received from the network 2 without going through the frame processing unit 12.

  Information about the frame analyzed by the frame processing unit 12 is output to the main control unit 13. In the main control unit 13, the frame storage method in the system memory 4 is determined based on the acquired frame information, in particular, the frame length and the frame reception interval, and various control information / status information stored in the register unit 15. decide. That is, it is determined whether the frame to be output next is stored in the same buffer as the frame output immediately before or in a different buffer. Note that a counter 21 is also connected to the main control unit 13 so that the counter 21 can be used for measurement of frame reception intervals and the like.

  Based on the determined frame storage method, the main control unit 13 outputs the frames temporarily stored in the small capacity memory 11 to a predetermined buffer of the system memory 4 via the DMA control unit 14 and the system bus 3. To do.

  An interrupt control unit 16 is also connected to the main control unit 13. The interrupt control unit 16 is connected to an interrupt controller (not shown) or the like, and notifies the CPU 5 of the occurrence of an interrupt via the interrupt controller at a predetermined timing. In some cases, the interrupt occurrence is directly notified to the CPU 5 incorporating the interrupt controller without using an interrupt controller (not shown).

  As shown in FIG. 2, the system memory 4 includes an area of a buffer group 42 for storing frames received from the reception frame processing device 1, and a buffer management information group 41 for storing information about the buffer group 42. An area is secured in advance. FIG. 2 is a schematic diagram illustrating the configuration of the system memory 4. The areas of the buffer management information group 41 and the buffer group 42 are shared between the reception frame processing device 1 and the CPU 5.

  The buffer group 42 includes a plurality of buffers 42a to 42d, and frames received from the reception frame processing device 1 are stored in the buffers 42a to 42d. The buffer management information group 41 is composed of the same number of buffer management information 41a to 41d as the buffers included in the buffer group 42, and each buffer management information 41a to 41d includes various information about the corresponding buffers 42a to 42d ( Ownership, storage mode, stored frame location, etc.).

  Here, the ownership of the buffer is information indicating whether the access right (update right) of the corresponding buffer is in the reception frame processing device 1 or the CPU 5. The side that owns the buffer has the access right (update right) to the buffer management information corresponding to the buffer, and when the processing for the buffer and the buffer management information is completed, the ownership is transferred to the other side. The In this way, the reception frame processing device 1 and the CPU 5 are configured to transmit and receive information to and from each other via the system memory 4.

  The storage mode is information indicating whether the mode can store a plurality of frames in the corresponding buffer (hereinafter referred to as pack mode) or the mode in which only one frame can be stored (hereinafter referred to as unpack mode). is there.

  The buffer management information 41a can be expressed in various ways, for example, as follows. First, the case where all the frames to be received have a fixed length and are stored in different locations as offset values will be described with reference to FIG. FIG. 3 is a diagram for explaining a specific example of buffer management information when a frame has a fixed length. FIG. 3 shows a case where up to four frames can be stored in one buffer.

  First, mode information 410 indicating whether the storage mode of the corresponding buffer 42a is the packed mode or the unpacked mode is written at the head. Subsequently, the start offset value 411a and the end offset value 411b are written for the frame stored in the buffer 42a. When a plurality of frames are stored, the start offset values 412a, 413a, and 414a and the end offset values 412b, 413b, and 414b are written for each frame in the stored order. Finally, an ownership bit 415 indicating whether the received frame processing device 1 or the CPU 5 has ownership of the corresponding buffer 42a is written.

  Note that when the number of frames stored in the buffer 42a is two or three, a mechanism is provided to indicate that no frames are stored thereafter. For example, the start offset value of the portion in which no frame is stored (the start offset value 413a of the third frame when the number of stored frames is two, and the fourth frame when the number of stored frames is three A predetermined value such as 0 is written in the start offset value 414a).

  Next, a case where a received frame has a variable length will be described with reference to FIGS. FIG. 4 is a diagram illustrating a specific example of buffer management information when the frame is variable length and the storage mode is unpacked mode. FIG. 5 is a buffer management information when the frame is variable length and the storage mode is packed mode. It is a figure explaining the specific example of.

  When the storage mode is the unpacking mode and only one frame is stored in the corresponding buffer 42a, as shown in FIG. 4, the buffer management information 41a indicates that the storage mode of the corresponding buffer 42a is the unpacking mode. Is written at the top. Subsequently, the frame length 416 of the frame stored in the buffer 42a is written.

  Further, a frame head bit 417 indicating whether or not the head portion of the frame is included and a frame tail bit 418 indicating whether or not the tail portion of the frame is included are written. When the frame length is larger than the buffer length, the frame is divided and stored in a plurality of buffers. However, when the CPU 5 performs processing using a frame, it is necessary to access the entire frame, so the buffer in which the frame is stored is identified with reference to the frame head bit 417 and the frame end bit 418.

  For example, when both the frame head bit 417 and the frame end bit 418 are on, it is identified that the entire frame is stored in the buffer 42a. For example, when the frame start bit 417 is ON but the frame end bit 418 is OFF, a part of the frame is stored in the buffer 42a, and the rest of the frame is stored after the subsequent buffer 42b. Is identified.

  At the end of the buffer management information 41a, an ownership bit 415 indicating the ownership of the buffer 42a is written.

  When the storage mode is the pack mode and there is a possibility that a plurality of frames are stored in the corresponding buffer 42a, the system memory 4 is provided with an area for storing the frame management information group 43. The information is stored in the buffer management information 41a and the frame management information group 43 as shown in FIG.

  In the buffer management information 41a, mode information 410 indicating that the storage mode of the corresponding buffer 42a is the unpacking mode is written at the head. Subsequently, in the frame management information 43, a head address 419 of the frame management information group 43 (hereinafter referred to as a frame information head address) is written in order to specify a description position of information relating to the frame stored in the buffer 42a. .

  FIG. 5 shows an example in which three variable length frames are stored in the corresponding buffer 42a. Each frame is stored in the frame management information group 43 as frame management information 43a to 43c. In this case, the head address of the frame management information 43a is written in the frame information head address 419 of the buffer management information 41a.

  The frame information 43a to 43c includes a frame management ownership bit 417 indicating the length 416 of the stored frame and whether the received frame processing device 1 or the CPU 5 has ownership of the frame management information. And a termination bit 418 indicating whether or not the frame is the last frame stored in the buffer 42a. In the example shown in FIG. 5, since three frames are stored in the buffer 42a, the end bit 418 of the frame information 43a and 43b is OFF, and the end bit of the frame information 43c is written ON.

  At the end of the buffer management information 41a, an ownership bit 415 indicating the ownership of the buffer 42a is written.

  Note that the buffer management information shown in FIG. 5 can also be used in the unpack mode. For example, when the variable length frame is stored in the buffer 42a in the unpack mode, the received frame processing device has the stored frame length 416 and the ownership of the frame management information in the frame information 43a. A frame management possession bit 417 indicating whether the frame is 1 or the CPU 5 and a termination bit 418 indicating whether the frame is the last frame stored in the buffer 42a are written. In the example shown in FIG. 5, since one frame is stored in the buffer 42a, the end bit of the frame information 43a is written as ON.

  Next, a received frame processing method (a method for storing received frames in the buffer group 42) in the above-described received frame processing apparatus 1 will be described with reference to FIG. FIG. 6 is a flowchart for explaining a received frame processing procedure according to the first embodiment of the present invention.

  First, in step S1, each part of the reception frame processing device 1 is initialized. As a specific work of this initialization, for example, a work in which various setting values are written by the CPU 5 can be cited.

  At the same time as step S 1, the CPU 5 secures an area for the buffer group 42 and the buffer management information group 41 from the system memory 4 and sets the ownership to the reception frame processing device 1. When this operation and the writing of each set value are finished, the CPU 5 writes a location in the register unit 15 to send a signal to start the operation to the reception frame processing device 1. The reception frame processing device 1 that has received the operation start signal resets the counter 21 and the like by the main control unit 13 and starts the operation.

  Next, in step S2, the first buffer management information 41a is referred to from the buffer management information group 41 of the system memory 4, and the address of the corresponding buffer 42a is acquired. Subsequently, in step S3, a frame arrival from the network 2 is waited.

  When the frame arrives, the process proceeds to step S4 to start receiving the frame. In this step, the received frames are sequentially written into the small capacity memory 11. Also, the time interval between the frame and the frame received immediately before (hereinafter referred to as the previous frame) (specifically, the time from the end of reception of the previous frame to the start of reception of the frame, the following The frame processing unit 12 calculates the frame interval). If the frame is the first frame received from the network 2 and there is no previous frame, the frame interval is set to zero.

  In step S5, the main control unit 13 compares the frame interval calculated in step S4 with a preset threshold value Tth. Here, the threshold value Tth is a value used to switch the storage mode of the received frame, and the network speed, the minimum frame gap of the network, the frame size at which the processing load of the CPU 5 per unit time is the largest, and the processing time of the CPU 5 , Etc. The threshold value Tth is stored in the register unit 15 or the like, and can be reset as appropriate.

  If it is determined in step S5 that the frame interval is less than the threshold value Tth, the main control unit 13 determines to store the received frame in the pack mode. In this case, the process proceeds to step S6, and the transfer of the received frame is started to the buffer whose address is acquired as the frame storage destination. Specifically, under the control of the main control unit 13, the frame written in the small capacity memory 11 is output to the system bus 3 via the DMA control unit 14 and is written in the buffer prepared in the system memory 4.

  This step is usually executed while the small-capacity memory 11 is receiving a frame from the network 2. That is, the small capacity memory 11 receives the frame from the network 2 and sequentially outputs the received frame to the system bus 3 via the main control unit 13 and the DMA control unit 14.

  On the other hand, when it is determined in step S5 that the frame interval is equal to or greater than the threshold Tth, the main control unit 13 determines to store the received frame in the unpacked mode. In this case, the process proceeds to step S7, where a necessary part of the buffer management information 41a is updated, and the ownership is returned to the CPU 5. Subsequently, the process proceeds to step S8, the next buffer management information 41b is referred to from the buffer management information group 41 of the system memory 4, the address of the corresponding buffer 42b is acquired, and the process proceeds to step S6.

  In step S6, frame transfer to an appropriate buffer in the system memory 4 is started, and when a predetermined time has elapsed, writing of the frame from the network 2 to the small capacity memory 11 is completed (step S9). In step S9, in order to measure the frame interval between the frame and the frame that arrives immediately after the frame (hereinafter, referred to as the next frame), when reception of the frame in the small capacity memory 11 is completed Thus, the counter for the frame interval timer provided in the counter 21 is reset by the main control unit 13, and the measurement of the frame interval is started immediately.

  Subsequently, in step S10, when the frame transfer to the appropriate buffer of the system memory 4 is completed, the reception status (during the frame transfer is successful, the frame has been transferred normally) is stored in the buffer management information corresponding to the buffer storing the frame. Information that identifies an error etc.) is written.

  Subsequently, in step S11, it is determined whether or not there is free space in the buffer in which the frame is written. If it is determined in step S11 that the buffer boundary has not been reached and the buffer has free space, the process proceeds to step S12 and waits for the next frame to arrive.

  On the other hand, if it is determined in step S11 that the buffer boundary has been reached and there is no free space in the buffer, the process proceeds to step S13, where necessary portions of the buffer management information corresponding to the buffer are updated, and ownership is granted. Return to CPU5. Subsequently, returning to step S2, the next buffer management information is referred to from the buffer management information group 41 of the system memory 4, the address of the corresponding buffer is obtained, and the arrival of the next frame is awaited.

  In step S12, when the frame arrives, the process returns to step S4 to start receiving the frame. On the other hand, when the frame does not arrive, the process proceeds to step S14, and it is determined whether or not the frame interval timer that started the measurement in step S9 has timed out. Specifically, the value of the frame interval timer at that time is compared with a threshold value Tth, and if the timer value is equal to or greater than the threshold value Tth, it is determined that a timeout has occurred.

  When the reception interval of frames received from the network 2 is long, if the frame is stored in the buffer in the pack mode, the ownership of the buffer is not transferred to the CPU 5 until the buffer memory is used up. It will decline. Therefore, by using a frame interval timer and generating a sign as a timeout when a frame is not received for a certain period of time, the ownership of the buffer can be transferred to the CPU 5 to improve the frame latency.

  If it is determined in step S14 that the frame interval timer has not timed out, the process returns to step S12 and waits for the arrival of the next frame. On the other hand, if it is determined in step S14 that the frame interval timer has timed out, the process proceeds to step S15, where the main control unit 13 resets the counter for the frame interval timer. In step S13, a necessary part of the buffer management information corresponding to the buffer is updated, and the ownership is returned to the CPU 5.

  While the reception frame processing device 1 is in operation, the processes in steps S2 to S15 described above are repeatedly executed, and the frames received from the network 2 are written into appropriate buffers in the buffer group 42 of the system memory 4.

  The received frame processing method described with reference to the flowchart of FIG. 6 will be described in more detail using specific examples shown in FIGS. FIG. 7 is a time chart for explaining an example of a situation in which a frame is received from the network 2. In FIG. 7, the horizontal axis indicates an elapsed time t after the reception frame processing device 1 starts operating. FIG. 8 is a schematic diagram for explaining the storage position when the received frame is stored in the buffer group 42.

  First, when the reception frame processing device 1 starts operation and initialization (step S1) is completed, the first buffer management information 41a is referred to from the buffer management information group 41 of the system memory 4, and the first arriving frame is stored. First, the address of the corresponding buffer 42a is acquired (step S2). Subsequently, in step S3, a frame arrival from the network 2 is waited.

Frame 0 arrives at the received frame processing device 1 starts the reception time t _{0 s} in step S4, the frame interval is measured. Here, the frame 0 is a frame that first arrives at the reception frame processing apparatus 1, and since there is no previous frame, the frame interval is zero. Next, in step S5, the frame interval (= zero) calculated in step S4 is compared with a preset threshold value Tth.

Here, since 0 <Tth, the process proceeds to step S6, and the transfer of the received frame 0 is started to the buffer 42a that has acquired the address as the frame storage destination. When the predetermined time elapses and time _t0e is reached, reception of frame 0 from the network 2 ends (step S9).

In step S9, a counter for a frame interval timer provided in the counter 21 to measure the frame interval (= _Tg10 ) between the frame (= frame 0) and the next frame (= frame 1). Is reset by the main control unit 13 and immediately starts measurement of the frame interval.

  In step S10, when the transfer of frame 0 to the buffer 42a is completed, the reception status is written in the buffer management information 41a. Subsequently, in step S11, it is determined whether or not there is free space in the buffer 42a in which the frame 0 is written. In the case of the example of FIG. 7, as shown in FIG. 8, the buffer 42a has free space even after storing frame 0, so the process proceeds to step S12 and waits for the arrival of the next frame (= frame 1). .

In the example of FIG. 7, since the next frame (= frame 1) does not arrive immediately, the process proceeds to step S14, and it is determined whether or not the frame interval timer that has started measurement in step S9 has timed out. In the example of FIG. 7, since frame 1 does not arrive even after Tth has elapsed since the reception of frame 0 has ended, it is determined that the frame interval timer has timed out at time t = t _0e + Tth, and the process _{proceeds to} step S15. Then, the main controller 13 resets the counter for the frame interval timer. In step S13, a necessary part of the buffer management information 41a is updated, and the ownership of the buffer 42a is returned to the CPU 5.

  Subsequently, returning to step S2, the next buffer management information 42b is referred from the buffer management information group 41, the address of the buffer 42b is acquired as the storage destination of the next frame (= frame 1), and the arrival of the next frame is awaited. (Step S3).

When frame 1 arrives at reception frame processing apparatus 1 and reception starts at time t _{1 s} in step S4, the frame interval is measured. The frame interval between frame 1 and the previous frame (= frame 0) is _Tg10 , but the frame interval timer becomes zero because the counter for the frame interval timer is reset in step S15.

Next, in step S5, the frame interval (= zero) calculated in step S4 is compared with a preset threshold value Tth. Here, since 0 <Tth, the process proceeds to step S6, and the transfer of the received frame 1 is started to the buffer 42b which has acquired the address as the frame storage destination. When the predetermined time has elapsed and time t _1e is reached, reception of frame 1 from the network 2 ends (step S9).

In step S9, a counter for a frame interval timer provided in the counter 21 in order to measure the frame interval (= T _g21 ) between the frame (= frame 1) and the next frame (= frame 2). Is reset by the main control unit 13 and immediately starts measurement of the frame interval.

  In step S10, when the transfer of frame 1 to the buffer 42b is completed, the reception status is written in the buffer management information 41b. Subsequently, in step S11, it is determined whether or not there is a free capacity in the buffer 42b in which the frame 1 is written. In the case of the example of FIG. 7, as shown in FIG. 8, since the buffer 42b has free space after storing frame 1, the process proceeds to step S12 and waits for the arrival of the next frame (= frame 2). .

In the example of FIG. 7, since the next frame (= frame 2) does not arrive immediately, the process proceeds to step S14, and it is determined whether or not the frame interval timer that started the measurement in step S9 has timed out. In the example of FIG. 7, since the frame 2 arrives before Tth elapses after the reception of the frame 1 ends (t _2s <t _1e + Tth), the process proceeds from step S14 to step S12 and step S4.

Frame 2 arrives at the reception frame processing apparatus 1 starts the reception time t _2s in step S4, the frame interval T _g21 is measured. In step S5, the frame interval _Tg21 calculated in step S4 is _compared with a preset threshold value Tth. Here, since T _g21 <Tth, the process proceeds to step S6, and the transfer of the received frame 2 is started to the buffer 42b that has acquired the address as the frame storage destination. That is, frame 2 is stored in the same buffer 42b as frame 1.

When the predetermined time elapses and time _t2e is reached, reception of frame 2 from network 2 ends (step S9). In step S9, in order to measure the frame interval (= _Tg32 ) between the frame (= frame 2) and the next frame (= frame 3), a counter for the frame interval timer provided in the counter 21 Is reset by the main control unit 13 and immediately starts measurement of the frame interval.

  In step S10, when the transfer of frame 2 to the buffer 42b is completed, the reception status is written in the buffer management information 41b. Subsequently, in step S11, it is determined whether or not there is a free space in the buffer 42b in which the frame 2 is written. In the case of the example of FIG. 7, as shown in FIG. 8, since the buffer 42b has free space even after the frame 2 is stored, the process proceeds to step S12 and waits for the arrival of the next frame (= frame 3). .

In the example of FIG. 7, since the next frame (= frame 3) does not arrive immediately, the process proceeds to step S14, and it is determined whether or not the frame interval timer that started the measurement in step S9 has timed out. In the example of FIG. 7, since the frame 3 does not arrive even after Tth has elapsed since the reception of the frame 2 has ended, it is determined that the frame interval timer has timed out at the time t = t _2e + Tth, and the process proceeds to step S15. Then, the main controller 13 resets the counter for the frame interval timer. In step S13, a necessary part of the buffer management information 41b is updated, and the ownership of the buffer 42b is returned to the CPU 5.

  Subsequently, returning to step S2, the next buffer management information 42c is referred to from the buffer management information group 41, the address of the buffer 42c is acquired as the storage destination of the next frame (= frame 3), and the arrival of the next frame is awaited. (Step S3).

When frame 3 arrives at reception frame processing apparatus 1 and reception starts at time _t3s in step S4, the frame interval is measured. The frame interval between the frame 3 and the previous frame (= frame 2) is _Tg32 . However, since the counter for the frame interval timer is reset in step S15, the frame interval becomes zero.

Next, in step S5, the frame interval (= zero) calculated in step S4 is compared with a preset threshold value Tth. Here, since 0 <Tth, the process proceeds to step S6, and the transfer of the received frame 3 is started to the buffer 42c that has acquired the address as the frame storage destination. When the predetermined time elapses and time _t3e is reached, reception of frame 3 from network 2 ends (step S9).

  In step S9, in order to measure the frame interval between the frame (= frame 3) and the next frame, the counter for the frame interval timer provided in the counter 21 is reset by the main control unit 13 and immediately. Start frame interval measurement.

  In step S10, when the transfer of the frame 3 to the buffer 42c is completed, the reception status is written in the buffer management information 41c. Subsequently, in step S11, it is determined whether or not there is a free space in the buffer 42c in which the frame 3 is written. In the case of the example of FIG. 7, as shown in FIG. 8, the buffer 42c has free space even after the frame 3 is stored, so the process proceeds to step S12 and waits for the arrival of the next frame.

  In this way, while the received frame processing device 1 is operating, the above-described steps S2 to S15 are repeatedly executed, and the frame received from the network 2 is written into an appropriate buffer in the buffer group 42 of the system memory 4. Go. That is, in the example of FIG. 7, frame 0 is stored in the buffer 42a, frame 3 is stored in the buffer 42c in the unpacked mode, and frames 1 and 2 are stored in the buffer 42b in the packed mode (see FIG. 8).

  As shown in FIG. 9, when all the frames 0 to 3 are stored in the buffers 42a to 42d in the unpacking mode, unused memory areas in which no frames are stored in the used buffers (= buffers 42a to 42d). As shown in FIG. 8, the sum is larger than the sum of unused memory areas in which frames are not stored in the used buffers (= buffers 42a to 42c) in this embodiment. FIG. 9 is a schematic diagram for explaining the storage position when all received frames are stored in the buffer group 42 in the unpacked mode.

  From this, it can be seen that the reception frame processing device 1 of the present embodiment has improved memory use efficiency compared to the reception frame processing device that stores frames in the buffer in the conventional unpacking mode.

  On the other hand, as shown in FIG. 10, when all the frames 0 to 3 are stored in the buffer 42a in the pack mode, the sum of the unused memory areas in which no frames are stored in the used buffer (= buffer 42a) is As shown in FIG. 8, the used buffer (= buffers 42a to 42c) in the present embodiment is smaller than the sum of unused memory areas in which no frames are stored. FIG. 10 is a schematic diagram for explaining a storage position when all received frames are stored in the buffer group 42 in the pack mode.

  Here, FIG. 11 and FIG. 12 are used to compare the received frame processing apparatus 1 of the present embodiment with the conventional viewpoint that stores frames in the buffer group 42 in the pack mode from the viewpoint of latency. View.

FIG. 11 is a time chart for explaining the latency of frame 0 in the pack mode, and FIG. 12 is a time chart for explaining the latency of frame 0 in the present embodiment. Here, the latency is from the time when the end of the frame is completely received by the small-capacity memory 11 until the copying of the frame into the system memory 4 is completed and the ownership of the buffer is transferred to the CPU 5. Say time. (From the viewpoint of transfer of ownership, latency can also be said to be the time from the completion of frame transfer to the system memory 4 until the transfer of ownership of the buffer to the CPU 5.)
11 and 12, the timing of writing a frame from the network 2 to the small capacity memory 11 of the reception frame processing device 1 is set to the upper stage, and the buffer management information group 41 and the buffer group 42 of the system memory 4 are received from the reception frame processing device 1. The timing for writing frames and various information is shown in the lower part.

As shown in FIG. 11, when all the frames are stored in the buffer group 42 in the pack mode, all four frames 0 to 3 are written to one buffer 42a, so that the writing of the frame 3 is completed. The ownership of the buffer 42a is not transferred to the CPU 5. Accordingly, the latency T _{10 ′} of the frame 0 is written in the buffer 42a from the received frame processing device 1 from the time when the small-capacity memory 11 completes the reception of the frame 0 from the network 2 (= t _0e ). This is the elapsed time from when the information such as the reception status is written in the corresponding frame management information 41a and the ownership of the buffer 42a is transferred to the CPU 5 (= t _{3be ′} ).

On the other hand, in the present embodiment, frame 0 is written in the buffer 42a in the unpacked mode, and frames 1 and after are written in the other buffers 42b and 42c. Therefore, as shown in FIG. 12, the latency T ₁₀ of the frame 0 is determined by the time-out threshold Tth after the small-capacity memory 11 completes the reception of the frame 0 from the network 2 (= t _0e ). This is the elapsed time until the time when the ownership of 42a is transferred to the CPU 5 (= t _0be ).

_Therefore , T ₁₀ <T _{10 ′} . It can be seen that the received frame processing apparatus 1 of the present embodiment has a lower latency than the received frame processing apparatus that stores frames in the buffer in the conventional pack mode. Since the latency does not depend on the sizes of the buffers 42a to 42d, the size of the buffers 42a to 42d can be increased to reduce the number of buffers included in the buffer group 42. As a result, the number of buffer management information included in the buffer management information group 41 is also reduced, so that the memory area allocated to the buffer management information group 41 can be reduced and the memory usage efficiency can be improved.

  Further, when frames are stored in the packed mode, the amount of frame management information is larger than when frames are stored in the unpacked mode. Therefore, the processing amount of the CPU 5 is increased and the load is increased. In the received frame processing apparatus 1 according to the present embodiment, the pack mode and the unpack mode are mixed, so that the load on the CPU can be reduced as compared with the case where all are processed in the pack mode.

  Thus, in this embodiment, the frame is stored in the buffer in the packed mode when the frame arrival interval is shorter than the preset threshold value Tth, and in the unpacked mode when the frame arrival interval is long. As a result, the memory usage efficiency can be improved as compared with the case where all the frames are stored in the unpacked mode, and the memory usage efficiency can be improved as compared with the case where all the frames are stored in the packed mode. The latency of the frame can be reduced and the load on the CPU can be reduced.

  In this embodiment, when reception of a frame from the network 2 is finished, information such as reception status is written in the frame management information and then processing is performed in the order of reading out the address of the buffer in which the next frame is written. As described above, the processing order may be reversed, and information such as the reception status may be written after reading the buffer address.

(Second Embodiment)
Next, a reception frame processing apparatus according to the second embodiment of the present invention will be specifically described.

  In the first embodiment described above, when the frame interval between a certain frame and the next frame exceeds a certain time, and when the buffer has run out of space, the ownership of the buffer storing the one frame is owned. The right is transferred to the CPU 5 and the next frame is stored in the next buffer. However, in this embodiment, one frame is stored even when the free space of the buffer is smaller than the frame length of the next frame. The ownership of the buffer is transferred to the CPU 5, and the next frame is stored in the next buffer.

  For example, in a situation where the buffer free space is La when frame 0 is stored in the buffer 42a, frame 1 whose frame length is Lf (> La) before the threshold Tth elapses after reception of frame 0 is completed. Arrives at the reception frame processing device 1, in the first embodiment described above, as shown in FIG. 13, the frame 1 is stored across the buffer 42a and the buffer 42b. FIG. 13 is a schematic diagram illustrating an example in which a received frame is stored across a plurality of buffers.

  When frame 1 is stored across a plurality of buffers 42a and 42b as shown in FIG. 13, in detail, frame 1-0, which is a part of frame 1, is stored in buffer 42a and is the remaining part of frame 1. When the frame 1-1 is stored in the buffer 42b, even if the ownership of the buffer 42a is transferred to the CPU 5 when the frame 1 is received, the ownership of the buffer 42b is retained by the reception frame processing device. The CPU 5 cannot process the entire frame 1. Accordingly, the latency of a frame stored across a plurality of buffers such as frame 1 is larger than that of a frame stored in one buffer.

  Further, in order to process the entire frame stored across a plurality of buffers, the CPU 5 performs processing in order to obtain the addresses of all the buffers in which the frame is stored and to construct a context. Will increase the load.

  Therefore, in this embodiment, when the free space of the buffer for storing the next frame is smaller than the frame length of the next frame, the frame is stored in a plurality of buffers by switching the frame storage destination to the next buffer. Reduce the rate of storage across.

  Since the configuration of the reception frame processing apparatus in the present embodiment is the same as that of the reception frame processing apparatus 1 of the first embodiment described with reference to FIG. 1, only the reception frame processing method will be described here and the same. About the component of these, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  In the received frame processing method according to the first embodiment described with reference to FIG. 6, frame reception is started (step S4), the frame interval is compared with the threshold value Tth (step S5), and then the frame interval is set to the threshold value Tth. If it is less than the frame, the frame is transferred to the buffer where the frame is to be stored (step S6).

  On the other hand, in the present embodiment, as shown in FIG. 14, after comparing the frame interval with the threshold value Tth (step S5), the buffer free space is compared with the frame length of the frame being received (step S21). When the buffer free space is equal to or longer than the frame length, the frame is transferred to the buffer where the frame is to be stored for the first time (step S6). FIG. 14 is a flowchart for explaining the processing procedure of the received frame according to the second embodiment of the present invention.

  If it is determined in step S21 that the free space of the buffer is less than the frame length, the process proceeds to step S7 as in the case where the frame interval is equal to or greater than the threshold Tth, and the necessary portion of the buffer management information is updated. The ownership is returned to the CPU 5. Subsequently, the process proceeds to step S8, the next buffer management information is referred to from the buffer management information group 41 of the system memory 4, the corresponding buffer address is acquired, and the process proceeds to step S6.

  As described above, in this embodiment, when the frame length of the frame being received is larger than the free capacity of the buffer in which the frame is to be stored, the frame is stored in a plurality of buffers by switching to the next buffer and storing it. Since the rate of storage across the frames can be reduced, the frame latency can be further reduced, and the processing load on the CPU can be further reduced.

(Third embodiment)
Next, a reception frame processing apparatus according to the third embodiment of the present invention will be specifically described.

  In the first embodiment described above, when the frame interval between a certain frame and the next frame exceeds a certain time, and when the buffer free space La runs out, the buffer storing the one frame is stored. Although the ownership is transferred to the CPU 5 and the next frame is stored in the next buffer, in the present embodiment, even when the free space La of the buffer is smaller than the minimum frame size Lmin in the specifications of the network standard. The ownership of the buffer storing one frame is transferred to the CPU 5, and the next frame is stored in the next buffer.

  When a certain frame is stored in the buffer, the free space La of the buffer is smaller than the minimum frame size Lmin in the specifications of the network standard, and the frame interval between one frame and the next frame is smaller than the threshold Tth. In this case, in the first embodiment, since the next frame is stored in the buffer in the pack mode, the next frame is stored across the buffer and the next buffer regardless of the frame length. The latency of a frame stored across a plurality of buffers becomes larger than the latency of a frame stored in one buffer, and the processing load on the CPU increases.

  Therefore, in this embodiment, when the free space of the buffer for storing the next frame is smaller than the minimum frame size Lmin in the specifications of the network standard, the frame is stored by switching the frame storage destination to the next buffer. Reduce the rate of storage across multiple buffers.

  Since the configuration of the reception frame processing apparatus in the present embodiment is the same as that of the reception frame processing apparatus 1 of the first embodiment described with reference to FIG. 1, only the reception frame processing method will be described here and the same. About the component of these, the same code | symbol is attached | subjected and description is omitted.

  In the received frame processing method according to the first embodiment described with reference to FIG. 6, the transfer of the frame to an appropriate buffer in the system memory 4 is completed, and the reception status is displayed in the buffer management information corresponding to the buffer storing the frame. After writing (step S10), it is determined whether or not the buffer in which the frame is written has a free space (step S11). If it is determined that the buffer boundary has not been reached and there is free space in the buffer, it waits for the next frame to arrive (step S12).

  On the other hand, if it is determined in step S11 that the buffer boundary has been reached and there is no free space in the buffer, the process proceeds to step S13, where necessary portions of the buffer management information corresponding to the buffer are updated, and ownership is granted. Return to CPU5. Subsequently, returning to step S2, the next buffer management information is referred to from the buffer management information group 41 of the system memory 4, the address of the corresponding buffer is obtained, and the arrival of the next frame is awaited.

  On the other hand, in this embodiment, as shown in FIG. 15, after the frame transfer to the buffer is completed and the reception status is written in the buffer management information (step S10), the free space is stored in the buffer in which the frame is written. And whether or not the free space La of the buffer is smaller than the minimum frame size Lmin is determined (step S31). If it is determined that the buffer boundary has not been reached and the buffer has a free space equal to or larger than the minimum frame size Lmin, it waits for the next frame to arrive (step S12). FIG. 15 is a flowchart for explaining the processing procedure of the received frame according to the third embodiment of the present invention.

  If it is determined in step S31 that there is no free space in the buffer in which the frame is written (= the buffer boundary has been reached) or the free space La of the buffer is smaller than the minimum frame size Lmin, the process proceeds to step S13. The necessary part of the buffer management information corresponding to the buffer is updated, and the ownership is returned to the CPU 5. Subsequently, returning to step S2, the next buffer management information is referred to from the buffer management information group 41 of the system memory 4, the address of the corresponding buffer is obtained, and the arrival of the next frame is awaited.

  As described above, in this embodiment, when the free space of the buffer that stores a certain frame is smaller than the minimum frame size in the specifications of the network standard, the storage destination of the next frame is switched to the next buffer. Since the rate at which a frame is stored across a plurality of buffers can be reduced, the latency of the frame can be further reduced and the processing load on the CPU can be further reduced.

  After the frame is stored in the buffer, the free space La of the buffer storing the frame is immediately compared with the minimum frame size Lmin according to the network standard specifications. If La <Lmin, the storage location of the next frame is determined. By switching to the next buffer and waiting for the arrival of the next frame, the ownership of the buffer storing the frame is quickly returned to the CPU, so that the latency of the frame can be further reduced.

(Fourth embodiment)
Next, a reception frame processing apparatus according to the fourth embodiment of the present invention will be specifically described.

  In the first embodiment described above, the timing at which an interrupt is generated from the reception frame processing device 1 to the CPU 5 is not specified, but normally, when reception of one frame is completed, or in the system memory 4 An interrupt is generated when transfer of one frame is completed. In this embodiment, an interrupt is generated when ownership of one buffer is transferred from the reception frame processing device to the CPU 5.

  When the buffer is managed in the pack mode, the ownership of the buffer is not transferred to the CPU 5 even if an interrupt is generated when reception of one frame is completed or writing to the buffer is completed. Therefore, the entire frame that generated the interrupt cannot be processed. However, since the CPU 5 needs to respond to an interrupt when it occurs, it causes the CU 5 to perform useless processing, resulting in an increase in processing load.

  In addition, when an interrupt is generated on a frame basis, the frequency of occurrence of an interrupt increases when the arrival frequency of the frame is high. As a result, the processing load on the CPU 5 increases as the number of interrupts increases.

  Therefore, in the present embodiment, an interrupt is generated not in units of frames but in units of buffers (when the ownership of the buffer is transferred to the CPU 5), the entire frame is processed even if the CPU 5 responds. The occurrence of interrupts that cannot be performed (hereinafter referred to as useless interrupts) is suppressed, and the processing load on the CPU 5 is reduced.

  Since the configuration of the reception frame processing apparatus in the present embodiment is the same as that of the reception frame processing apparatus 1 of the first embodiment described with reference to FIG. 1, only the reception frame processing method will be described here and the same. About the component of these, the same code | symbol is attached | subjected and description is omitted.

  The received frame processing method in this embodiment is the same as that in step S7 and step S13 of the received frame processing method of the first embodiment described with reference to FIG. The CPU 5 generates an interrupt from the unit 16 via an interrupt controller or the like.

  In the example of FIG. 7, when an interrupt is generated in units of frames, the interrupt is generated when four frames 0 to 3 are stored in the buffers 42a to 42d, respectively. This will generate a total of four interrupts.

  When all the frames are stored in the buffer in the unpacked mode, the number of invalid interrupts is zero. However, when all the frames are stored in the buffer in the pack mode, the interrupt generated when the frames 0 to 2 are stored is not transferred to the CPU 5 because the ownership of the buffer 42a is transferred. It is not possible and is an invalid interrupt. That is, out of a total of 4 interrupts, 3 interrupts are invalid interrupts.

On the other hand, in the present embodiment, in the example of FIG. 7, when the ownership of the buffer 42a storing the frame 0 is returned to the CPU 5 (= t _0be in FIG. 12), the frames 1 and 2 are stored. Interrupts are made when the ownership of the buffer 42b is returned to the CPU 5 (= t _2be in FIG. 12) and when the ownership of the buffer 42c storing the frame 3 is returned to the CPU 5 (= t _3be in FIG. 12). generate.

  This will generate a total of three interrupts, of which zero are invalid. That is, the number of occurrences of interrupts can be reduced by one, and no unnecessary interrupts are generated even if frames are stored in the pack mode as in the buffer 42b.

  As described above, in the present embodiment, by generating an interrupt for each buffer, it is possible to suppress the number of occurrences of interrupts and generation of useless interrupts, and to reduce the processing load of the CPU 5. In addition, by suppressing the number of occurrences of interrupts, the occupation ratio of the CPU 5 can be reduced, and the CPU 5 can perform other processes. Therefore, an effect of improving the processing efficiency of the CPU 5 can be expected.

(Fifth embodiment)
Next, a reception frame processing apparatus according to the fifth embodiment of the present invention will be specifically described.

  In the fourth embodiment described above, an interrupt is generated each time ownership of one buffer is returned to the CPU 5, but in this embodiment, ownership of two or more predetermined number of buffers is assigned to the CPU 5. An interrupt is generated when it is returned. Thereby, when the frame reception frequency is high, an effect of further reducing the processing load of the CPU 5 can be expected.

  In the received frame processing method of the fourth embodiment described with reference to FIG. 6, after the ownership of the buffer is returned to the CPU 5 in step S7 and step S13, the interrupt control unit 16 passes through the interrupt controller or the like. An interrupt is generated in the CPU 5, and the process proceeds to step S8 and step S2, respectively, and the address of the buffer storing the frame is read from the buffer management information.

  On the other hand, in the present embodiment, as shown in FIG. 16, after returning the ownership of the buffer to the CPU 5 in step S7 and step S13, the number of buffers that returned the ownership to the CPU 5 (hereinafter, the number of buffer returns). 1) is added (steps S41 and S44). FIG. 16 is a flowchart for explaining the processing procedure of the received frame according to the fifth embodiment of the present invention. Here, the buffer return number is the number of buffers whose ownership has been returned to the CPU 5 after the occurrence of the previous interrupt, and is measured by the counter 21, for example.

  In the subsequent step S42 or step S45, if the buffer return number is larger than the set number, the process proceeds to steps S43 and S46, respectively, and an interrupt is generated from the interrupt control unit 16 to the CPU 5 via the interrupt controller or the like to reset the buffer return number. After that, the process proceeds to steps S8 and S2, respectively, and the address of the buffer storing the frame is read from the buffer management information.

  On the other hand, if the number of buffer returns is equal to or less than the set number in step S42 or step S45, no interrupt is generated and the process proceeds to steps S8 and S2, respectively, and the address of the buffer storing the frame is read from the buffer management information.

  Note that the set number, that is, the number of buffers for generating an interrupt, can be set to a value according to the system at the time of configuration of the reception frame processing apparatus or the register unit 15.

  As described above, in the present embodiment, when the ownership of a plurality of buffers is returned to the CPU 5, an interrupt is generated to further suppress the number of occurrences of the interrupt and further reduce the processing load on the CPU 5. be able to. Further, by further reducing the number of occurrences of interrupts, the occupancy rate of the CPU 5 can be reduced and the CPU 5 can perform other processing, so that the effect of improving the processing efficiency of the CPU 5 can be further expected. .

(Sixth embodiment)
Next, a reception frame processing apparatus according to the sixth embodiment of the present invention will be specifically described. Since the configuration of the reception frame processing apparatus of this embodiment is the same as that of the reception frame processing apparatus 1 of the first embodiment described with reference to FIG. 1, only the reception frame processing method will be described here and the same. About the component of these, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  The received frame processing method of this embodiment is a combination of the first to third and fifth embodiments described above. A specific method will be described with reference to FIG. FIG. 17 is a flowchart for explaining the processing procedure of the received frame according to the sixth embodiment of the present invention.

  First, as in the first embodiment, each unit of the apparatus is initialized (step S1), and the address of the buffer storing the first frame is read from the buffer management information (step S2). In the subsequent step S3, when a frame arrives, reception of the frame is started and a frame interval is acquired (step S4).

  In the subsequent step S5, if the frame interval is smaller than the preset threshold value, the process proceeds to step S21 as in the second embodiment, and the free space of the buffer is compared with the frame length of the frame being received. If the frame length is equal to or longer than the frame length, the process proceeds to step S6 to start frame transfer.

  On the other hand, if the frame interval is greater than or equal to the threshold value in step S5, or if the free space of the buffer is less than the frame length in step S21, the process proceeds to step S7 to update the buffer management information corresponding to the buffer and The right is returned to the CPU 5. Subsequently, as in the fifth embodiment, the process proceeds to step S41, where 1 is added to the buffer return number, and the set number is compared (step S42).

  When the buffer return number is larger than the set number, the process proceeds to step S43 to generate an interrupt, the buffer return number is reset, and the process proceeds to step S8 to read the address of the next buffer as the frame storage destination. On the other hand, if the buffer return number is less than or equal to the set number, the process proceeds to step S8 without generating an interrupt. In step S6, frame transfer is started.

  As in the first embodiment, after frame transfer is started (step S6), when frame reception is completed, the frame interval timer counter is reset and frame interval measurement is started immediately (step S9). . Subsequently, when the frame transfer is completed, the reception status and the like are written in the buffer management information (step S10).

  Next, as in the third embodiment, the process proceeds to step S31, and whether or not the buffer in which the frame is written has free space and whether or not the free space La of the buffer is smaller than the minimum frame size Lmin. Determine whether or not. If it is determined that the buffer boundary has not been reached and the buffer has a free space equal to or larger than the minimum frame size Lmin, it waits for the next frame to arrive (step S12).

  If it is determined in step S31 that there is no free space in the buffer in which the frame is written (= the buffer boundary has been reached) or the free space La of the buffer is smaller than the minimum frame size Lmin, the process proceeds to step S13. The necessary part of the buffer management information corresponding to the buffer is updated, and the ownership is returned to the CPU 5.

  Subsequently, as in the fifth embodiment, the process proceeds to step S44, where 1 is added to the buffer return number, and the set number is compared (step S45). When the buffer return number is larger than the set number, the process proceeds to step S46 to generate an interrupt, the buffer return number is reset, and the process proceeds to step S2 to read the address of the next buffer as the frame storage destination. On the other hand, if the buffer return number is less than or equal to the set number, the process proceeds to step S2 without generating an interrupt.

  Hereinafter, as in the first embodiment, when a frame arrives in step S12, the process returns to step S4 to start receiving the frame. On the other hand, when the frame does not arrive, the process proceeds to step S14, and it is determined whether or not the frame interval timer that started the measurement in step S9 has timed out.

  If it is determined in step S14 that the frame interval timer has not timed out, the process returns to step S12 and waits for the arrival of the next frame. On the other hand, if it is determined in step S14 that the frame interval timer has timed out, the process proceeds to step S15, where the main control unit 13 resets the counter for the frame interval timer. In step S13, a necessary part of the buffer management information corresponding to the buffer is updated, and the ownership is returned to the CPU 5.

  While the reception frame processing device 1 is in operation, the processing of each step described above is repeatedly executed, and the frame received from the network 2 is written into an appropriate buffer in the buffer group 42 of the system memory 4.

As described above, in the present embodiment, by combining the first to third and fifth embodiments, the respective effects can be superimposed, and in particular, the processing load on the CPU is further reduced. can do.

The block diagram explaining the structure of the received frame processing apparatus 1 concerning embodiment of this invention. FIG. 3 is a schematic diagram illustrating a configuration of a system memory 4. The figure explaining the specific example of buffer management information in case a frame is fixed length. The figure explaining the specific example of buffer management information in case a frame is variable length and storage mode is unpacking mode. The figure explaining the specific example of buffer management information in case a frame is variable length and storage mode is pack mode. 4 is a flowchart for explaining a received frame processing procedure according to the first embodiment of the present invention; 4 is a time chart for explaining an example of a situation in which a frame is received from the network 2; FIG. 4 is a schematic diagram for explaining a storage position when a received frame is stored in a buffer group. Schematic explaining the storage position when all the received frames are stored in the buffer group 42 in the unpack mode. Schematic explaining the storage position when all received frames are stored in the buffer group 42 in the pack mode. The time chart explaining the latency of the frame 0 in pack mode. 4 is a time chart for explaining the latency of frame 0 in the present embodiment. Schematic explaining an example in which a received frame is stored across a plurality of buffers. The flowchart explaining the process procedure of the received frame concerning the 2nd form of this invention. The flowchart explaining the processing procedure of the received frame concerning the 3rd form of this invention. The flowchart explaining the processing procedure of the received frame concerning the 5th form of this invention. The flowchart explaining the processing procedure of the received frame concerning the 6th form of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Reception frame processing apparatus, 2 ... Network, 3 ... System bus, 4 ... System memory, 5 ... CPU, 11 ... Small capacity memory, 12 ... Frame processing part, 13 ... Main control part, 14 ... DMA control part, 15 ... Register, 16 ... Interrupt controller, 21 counter

Claims (5)

A reception frame processing device that receives a variable-length frame from a network and transfers the frame to a buffer area that is provided on a system memory and is a shared area with a CPU,
The buffer area is composed of a plurality of buffers, and when the second frame is received before a predetermined time has elapsed since the first frame was transferred to the first buffer, the second frame Is transferred to the first buffer, and when the second frame is received after a lapse of a predetermined time from the transfer of the first frame to the first buffer, A received frame processing apparatus, wherein the second frame is transferred to a second buffer after the ownership is transferred to the CPU.   If the free space of the first buffer after storing the first frame is smaller than the length of the second frame, the ownership of the first buffer is transferred to the CPU and then the second buffer is transferred. The received frame processing device according to claim 1, wherein the frame is transferred to the second buffer.   When the free capacity of the first buffer after storing the first frame is smaller than the minimum frame length according to the specifications of the network standard, the ownership of the first buffer is transferred to the CPU. The received frame processing apparatus according to claim 1 or 2, wherein the second frame is transferred to the second buffer after the transmission.   4. The received frame processing device according to claim 1, wherein an interrupt is generated when ownership of a certain number of the buffers is transferred to the CPU. 5. CPU,
System memory,
A received frame processing system comprising: a network controller which receives a variable-length frame from a network and transfers the frame to a buffer area which is provided on the system memory via a system bus and which is a shared area with the CPU. There,
The buffer area is composed of a plurality of buffers, and when the second frame is received before a predetermined time has elapsed since the first frame was transferred to the first buffer, the second frame Is transferred to the first buffer, and when the second frame is received after a lapse of a predetermined time from the transfer of the first frame to the first buffer, A received frame processing system, wherein the second frame is transferred to a second buffer after ownership is transferred to the CPU.

Images