JP2008242887A - Timing chart analysis support system, timing chart analysis support device, display controller, timing chart analysis support method, program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing chart analysis support system suitable for the understanding of a circuit operation by automatically displaying an auxiliary line on a waveform chart. <P>SOLUTION: This timing chart analysis support system 1 is configured to support the analysis of waveform charts of a plurality of signals relating to a circuit as the object of analysis, and provided with an event extraction part 13 for extracting a plurality of events satisfying prescribed event extraction conditions from the waveform data of each signal or the combination of portions of a plurality of signals; a virtual event extraction part 3 for extracting a virtual event from a signal related with each event on the basis of the circuit diagram of the circuit being the object of analysis; a dependency generation part 17 for generating the mutual dependency of the event/virtual event; and a display controller 5 for making a display device display the dependency generated by the dependency generation part 17 with the waveform data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present application relates to a timing chart analysis support system, a timing chart analysis support device, a display control device, a timing chart analysis support method, a program, and a recording medium, and particularly supports analysis of waveform data of a plurality of signals related to a circuit to be analyzed. The present invention relates to a timing chart analysis support system.

  When designing a digital logic circuit on an LSI, as the designer proceeds with the design of the target logic circuit, the designer performs a logic simulation (RTL simulation) to verify whether the design is correct, and corrects any errors. It becomes necessary. Whether or not there is an error can be determined by comparing expected values during simulation. However, it is necessary for the designer to examine the required specifications, simulation results, and design circuit at the same time to determine what the error is, what is the cause, and how to correct it. At that time, it is necessary to understand the operation by correlating the simulation result (waveform diagram) with the design circuit.

  In addition, although there is no functional or system operation error, there may be a situation in which it is desired to analyze the signal change in detail at the gate level from the viewpoint of the delay time of the circuit (cell library, etc.) and power consumption.

  The specific design contents of the circuit are an RTL description (before logic synthesis) and a netlist (after logic synthesis) of logic elements (including virtual elements for modeling a library or the like). This is associated with the waveform diagram by the signal name. Therefore, the designer looks at the signal name on the left side of the waveform diagram and refers to the corresponding logical description of the design contents to examine whether the waveform diagram changes correctly and to analyze the operation of the circuit. Do.

  The waveform diagram describes in parallel how each signal changes over time. The relationship between the waveforms is not described. Therefore, skill is required for the analysis work. Even if you are skilled, it takes time.

  At this time, on the basis of the logical causal relationship of each signal constructed as the design contents of the circuit, it is possible to fill in auxiliary lines such as arrows between the changes in the waveform diagram signals. It will be very helpful to understand the contents of. This is often used to describe the design before the age when gate level design is common (before the prevalence of logic synthesis, 1980s).

  The creation of this auxiliary line has not been automated, and it has long been carried out manually on paper or on computers using manual graphic editing programs (for example, patent documents). 1 paragraph 0010, patent document 2 paragraph 0023, etc.).

JP 2005-202857 A JP-A-9-128411

  However, in order to correctly create auxiliary lines manually, it is necessary to understand the circuit contents and the correlativity of the waveforms first. The creator is forced to bear the same burden as the consideration and analysis. The burden for understanding the circuit operation is not limited to the digital logic circuit, but is the same for an analog circuit, a circuit in which analog and digital are mixed, and the like. Even in an analog circuit, for example, in a circuit that performs non-linear or discrete operations such as a communication circuit, a power supply circuit, an AD converter, and a control circuit, digital information is mixed in the signal and the operation state, and the waveform of the signal is also included. A place where an abrupt change (near discontinuity) or a non-differentiable position appears as a place where the operation state is switched. (In the present invention, the circuit includes a digital logic circuit, an analog circuit, a circuit in which analog and digital are mixed, etc.)

  Accordingly, an object of the present invention is to provide a timing chart analysis support system and the like suitable for understanding circuit operation by automatically displaying auxiliary lines on a waveform diagram.

  The invention according to claim 1 is a timing chart analysis support system that supports analysis of waveform data of a plurality of signals related to a circuit to be analyzed, wherein the waveform data of each signal or a part of signals of the plurality of signals Event extracting means for extracting a plurality of events satisfying a predetermined event extraction condition from a combination; virtual event extracting means for extracting a virtual event from a signal related to each event based on circuit data of the circuit to be analyzed; Dependencies between events extracted by the event extraction means, dependencies between virtual events extracted by the virtual event extraction means, events extracted by the event extraction means, and virtual event extraction means Dependency generation means for generating dependency relationships between virtual events and display devices Contrast, the generated dependency by the dependence generating means, in which and a display control means for displaying together with the waveform data of a plurality of signals for the circuit of the analyzed.

  The invention according to claim 2 is the timing chart analysis support system according to claim 1, wherein the virtual event extraction unit is related to the extracted virtual event based on circuit data of the circuit to be analyzed. A new virtual event is extracted from the signal.

  The invention according to claim 3 is a timing chart analysis support device that supports analysis of waveform data of a plurality of signals related to a circuit to be analyzed, wherein the waveform data of each signal or a part of signals of the plurality of signals Event extracting means for extracting a plurality of events satisfying a predetermined event extraction condition from a combination; virtual event extracting means for extracting a virtual event from a signal related to each event based on circuit data of the circuit to be analyzed; Dependencies between events extracted by the event extraction means, dependencies between virtual events extracted by the virtual event extraction means, events extracted by the event extraction means, and virtual event extraction means Dependency generation means for generating dependency relationships between virtual events. It is.

  The invention according to claim 4 includes display control means for causing the display device to display the dependency relationship generated by the dependency relationship generating means according to claim 3 together with the waveform data of a plurality of signals related to the circuit to be analyzed. The display control device.

  The invention according to claim 5 is the display control apparatus according to claim 4, wherein the display control means determines whether or not to display the waveform data of each signal based on a predetermined display condition, and displays When an event related to a signal not to be displayed and a virtual event mediate a dependency between events to be displayed, between virtual events, or between an event and virtual events, an event not to be displayed and a virtual event between the events to be displayed are omitted. Or a dependency relationship between an event and a virtual event, and when not mediating, the display of the dependency relationship regarding the event and the virtual event that is not displayed is omitted, or between the event regarding the signal to be displayed, between the virtual events, or Display position or display order of each signal based on dependency between event and virtual event It is those determined.

  The invention according to claim 6 is a timing chart analysis support method for supporting analysis of waveform data of a plurality of signals related to a circuit to be analyzed, wherein the event extraction means includes the waveform data of each signal or the plurality of signals. An event extraction step for extracting a plurality of events satisfying a predetermined event extraction condition from a combination of some signals, and a virtual event extraction means, based on circuit data of the circuit to be analyzed, from signals related to each event A virtual event extracting step for extracting a virtual event; and a dependency relationship generating means, a dependency relation between the events extracted by the event extracting means, a dependency relation between the virtual events extracted by the virtual event extracting means, and the The event extracted by the event extraction means and the virtual event extraction means A dependency generation step for generating a dependency relationship between the generated virtual events, and a display control unit for the display device to display the dependency relationship generated by the dependency relationship generation unit as a plurality of signals related to the circuit to be analyzed. And a display control step for displaying together with the waveform data.

  The invention according to claim 7 is a program for realizing the timing chart analysis support method according to claim 6 in a computer.

  The invention according to claim 8 is a recording medium for recording the program according to claim 7.

  The plurality of signals related to the analysis target circuit are, for example, an input signal and an output signal of the analysis target circuit. The event extraction means, for example, from the waveform data of each signal, those including a predetermined continuous signal pattern, those at the time when the signal changes, those at the time when the evaluation of a plurality of combinations of signals changes, etc. as events To extract. The virtual event extraction means, for example, for a signal input to an element related to an event or a signal output from the element, regardless of whether or not the signal has changed, Thing, the thing of the time of outputting in connection with an event, etc. are extracted as a virtual event.

  Furthermore, not only the waveform data of a plurality of signals, but also a combination of some signals of a plurality of signals from which events have been extracted may be displayed.

  Further, the display control means may assign a tag name to a logical value or a change in the logical value at a certain time or period, trace the propagation / retroactivity of the tag, and display the result together with the waveform diagram.

  According to the present invention, an event is extracted by the event extraction unit, a virtual event is extracted by the virtual event extraction unit, and these dependency relationships are generated by the dependency generation unit, thereby generating auxiliary line candidates. . Supports understanding of the contents of the waveform diagram by automatically displaying a number of auxiliary line candidates suitable for understanding the circuit operation together with the waveform data through event / virtual event extraction processing and display control means. It becomes possible.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the circuit to be analyzed will be described centering on a digital logic circuit, but may be an analog circuit or a mixture of digital and analog circuits.

  FIG. 1 is a block diagram of a timing chart analysis support system 1 which is an embodiment of the present invention. In FIG. 1, a timing chart analysis support system 1 supports analysis of a timing chart regarding simulation results of an input signal and an output signal generated by a logic simulation by a waveform diagram generation apparatus 101 for a digital logic circuit to be analyzed. Is.

  The waveform diagram generating apparatus 101 includes a digital logic circuit design storage unit 103 that stores a design of a digital logic circuit to be analyzed, a test vector storage unit 105 that stores definitions of input values, and a simulator setting storage unit 107 such as a time range. A logic simulator 109 that performs a logic simulation based on information stored in the digital logic circuit design storage unit 103, the test vector storage unit 105, and the simulator setting storage unit 107, and a simulation result output that stores a simulation result of the logic simulator 109 A storage unit 111 is provided.

  The timing chart analysis support system 1 analyzes the analysis result of the timing chart analysis support device 3 with respect to the timing chart analysis support device 3 that analyzes the dependency of the simulation result of the input signal and the waveform diagram generation device 101 and the display device 121. A display control device 5 is provided that displays the input signal and the simulation result of the waveform diagram generation device 101 in a superimposed manner.

  The timing chart analysis support device 3 includes a logical dependency extraction unit 11 that extracts a logical dependency between signals based on the design of the logic circuit to be analyzed stored in the digital logic circuit design storage unit 103, Based on the information about the signals stored in the test vector storage unit 105, the simulator setting storage unit 107, and the simulation result output storage unit 111, for example, by analyzing the time when these signals are changed by differentiation in time, An event extracting unit 13 for extracting the current time as an event, and a signal and a time related to the event extracted by the event extracting unit 13 based on the logical dependency extracted by the logical dependency extracting unit 11 A virtual event extraction unit 15 that extracts a virtual event based on a combination of Dependency between extracted events, dependency between virtual events extracted by the virtual event extraction unit 15, and between events extracted by the event extraction unit 13 and virtual events extracted by the virtual event extraction unit 15 A dependency generation unit 17 for generating the dependency relationship. The timing chart analysis support device 3 includes an extraction parameter storage unit 19 that stores parameters related to events to be extracted and dependency relationships, and includes a logical dependency relationship extraction unit 11, an event extraction unit 13, a virtual event extraction unit 15, and dependency relationships. The generation unit 17 refers to the extraction parameter stored in the extraction parameter storage unit 19 as necessary.

  The display control device 5 has generated the waveform data of the signals stored in the test vector storage unit 105 and the simulation result output storage unit 111 and the simulation setting stored in the simulator setting storage unit 107 by the dependency generation unit 17. A waveform display unit 21 having a dependency relationship display generation unit 23 that is superimposed on the dependency relationship, and a waveform display image storage unit 25 that stores an image on which the dependency relationship is superimposed are provided.

  Next, the operation of the timing chart analysis support system 1 in FIG. 1 will be described by taking as an example a case where it is applied to a combinational circuit.

  FIG. 2 is a diagram illustrating a combinational logic circuit which is an example of a logic circuit to be processed according to the present embodiment. This logic circuit is a 2-bit addition circuit. The input signals of this logic circuit are A [0], B [0], A [1] and B [1], and the intermediate variable signals are C [0], HS [1], HC [1] and PC [ 1] and the output signals are S [0], S [1] and C [1]. A [0] and B [0] are input to the exclusive OR element XOR1, and the result of the exclusive OR by XOR1 is the output signal S [0]. A [0] and B [0] are input to the AND element AND1, and the result of the AND operation by AND1 is the intermediate variable signal C [0]. A [1] and B [1] are input to the exclusive OR element XOR2, and the result of the exclusive OR by XOR2 is the intermediate variable signal HS [1]. A [1] and B [1] are input to the AND element AND2, and the result of the AND operation by AND2 is the intermediate variable signal HC [1]. HS [1] and C [0] are input to the exclusive OR element XOR3, and the result of the exclusive OR by XOR3 is the output signal S [1]. Further, HS [1] and C [0] are input to the AND element AND3, and the result of the AND operation by AND3 is the intermediate variable signal PC [1]. PC [1] and HC [0] are input to the OR element OR1, and the result of the OR operation by AND3 is the output signal C [1]. Hereinafter, AND1, AND2, AND3, XOR1, XOR2, XOR3, and OR1 are referred to as logic symbols.

  The delay time between the inputs and outputs of AND1, AND2, and AND3 is 3, the delay time between the inputs and outputs of XOR1, XOR2, and XOR3 is 2, and the delay time between the inputs and outputs of OR1 is 3. The delay time of each logical symbol is described in each logical symbol in FIG. In this embodiment, for each logic symbol circuit, the delay time from each input to the output takes the same value regardless of the direction of signal change (rising or falling). To do.

  FIG. 3 is a waveform diagram as a result of applying the illustrated input signal to the logic circuit of FIG. Information about the input signals A [0], B [0], A [1] and B [1] is stored in the test vector storage unit 105 in FIG. 1, and the intermediate variable signal C [[ 0], HS [1], HC [1] and PC [1] and information on the output signals S [0], S [1] and C [1] are stored.

  The operation of the logic circuit of FIG. 2 will be understood in detail with reference to the circuit diagram of FIG. 2 and the waveform diagram of FIG. In the waveform diagram of FIG. 3, if an auxiliary line indicating the dependency of the waveform change is properly displayed, it will be helpful for understanding.

  4 and 5 show an example of an auxiliary line indicating the dependency of waveform change in the waveform diagram of FIG.

  The logical dependency extraction unit 11 in FIG. 1 extracts logical dependency between signals based on the circuit design data shown in FIG. 2 stored in the digital logic circuit design storage unit 103.

  With reference to FIG. 4A, the operation of the timing chart analysis support system 1 in FIG. 1 will be described with respect to AND1 in FIG. The logical dependency extraction unit 11 extracts the dependency that A [0] and B [0] are input to AND1, C [0] is output, and the delay time is 3.

  The event extraction unit 13 in FIG. 1 analyzes the time points when A [0], B [0], and C [0] are changed, for example, by differentiation with respect to time, and extracts them as events. In FIG. 4A, event 1 is extracted for A [0], event 2 is extracted for B [0], and event 3 is extracted for C [0].

  Next, the virtual event extraction unit 15 extracts the virtual event 1 for the output C [0] of the AND1 after the delay time with respect to the event 1, and goes back from the virtual event 1 with respect to B [0] as another input. The virtual event 2 that is the point in time is extracted. The virtual event extraction unit 15 does not perform the virtual event extraction process for the event 2 because the event 3 has already been extracted after the delay time. A virtual event 3 that is a time point delayed from the event 3 for A [0] is extracted.

  Next, the dependency relationship generation unit 17 generates dependency relationships between the event 1 and the virtual event 1, between the virtual event 2 and the virtual event 1, between the virtual event 3 and the event 3, and between the event 2 and the event 3.

  Next, the dependency relationship display generating unit 23 displays the dependency relationship resulting from the event as a solid line and the dependency relationship resulting from the virtual event as a broken line. The waveform display unit 21 generates a waveform in which the waveform diagrams of A [0], B [0], and C [0], events and virtual events, and the dependency relationship display by the dependency relationship display generation unit 23 are superimposed. It is stored in the display image storage unit 25. The image stored in the waveform display image storage unit 25 is displayed on the display device 121.

  FIG. 4B is an analysis example regarding XOR1 of FIG. The event extraction unit 13 extracts events 1, 2, 4, and 5 based on signal changes of A [0], B [0], and S [0]. The virtual event extraction unit 15 extracts virtual events 2 and 3. The dependency generation unit 17 generates a dependency between event 1 and event 4, between virtual event 2 and event 4, between virtual event 3 and event 5, and between event 2 and event 5. The operation of the display control device 5 is the same as in the case of FIG.

  FIG. 4C is an analysis example regarding XOR2 of FIG. The event extraction unit 13 extracts events 6, 7, 8, and 9 based on signal changes of A [1], B [1], and HS [1]. The virtual event extraction unit 15 extracts virtual events 4 and 5. The dependency relationship generation unit 17 generates dependency relationships between the events 6 and 8, between the virtual events 4 and 8, between the virtual events 5 and 9, and between the events 7 and 9. The operation of the display control device 5 is the same as in the case of FIG.

  FIG. 4D is an analysis example regarding AND2 in FIG. The event extraction unit 13 extracts events 6, 7, and 10 based on signal changes of A [1], B [1], and HC [1]. The virtual event extraction unit 15 extracts virtual events 6, 4, and 5. The dependency relationship generation unit 17 generates dependency relationships between the event 6 and the virtual event 6, between the virtual event 4 and the virtual event 6, between the virtual event 5 and the event 10, and between the event 7 and the event 10. The operation of the display control device 5 is the same as in the case of FIG.

  FIG. 5A shows an analysis example related to XOR3 in FIG. The event extraction unit 13 extracts events 3, 8, 9, 11, 12, and 13 based on signal changes of C [0], HS [1], and S [1]. The virtual event extraction unit 15 extracts virtual events 7, 1, 8. The dependency generation unit 17 includes virtual events 7 and 11, events 8 and 11, virtual events 1 and 12, events 9 and 12, events 3 and 13, and virtual events 8 and 11. A dependency relationship between the events 13 is generated. The operation of the display control device 5 is the same as in the case of FIG.

  FIG. 5B is an analysis example regarding XOR 3 in FIG. The event extraction unit 13 extracts events 3, 8, and 9 based on signal changes of C [0], HS [1], and PC [1]. The virtual event extraction unit 15 extracts virtual events 9, 7, 10, 1, 11, and 8. The dependency generation unit 17 includes a virtual event 7 and a virtual event 9, an event 8 and a virtual event 9, a virtual event 1 and a virtual event 10, an event 9 and a virtual event 10, an event 3 and a virtual event 11, and , A dependency relationship between the virtual event 8 and the virtual event 11 is generated. The operation of the display control device 5 is the same as in the case of FIG.

  FIG. 5C is an analysis example regarding OR1 of FIG. The event extraction unit 13 extracts events 10 and 14 based on signal changes of HC [1], PC [1], and C [1]. The virtual event extraction unit 15 extracts the virtual event 9. The dependency generation unit 17 generates a dependency between the event 10 and the event 14 and between the virtual event 9 and the event 14. The operation of the display control device 5 is the same as in the case of FIG.

  The waveform display unit 21 may display a part of the dependency relationship generated by the dependency relationship generation unit 17. For example, you may make it display only the dependence relationship between the events extracted by the signal change. Since this covers all changes, there is also one aspect where the trend of circuit changes can be overviewed and the characteristics can be grasped. However, if arrows are displayed for all changes, the number of displayed arrows increases, making it difficult to see. When the circuit scale is large and complicated, it is difficult to understand the operation of the circuit by following the arrows. In the operation of the combinational logic circuit, a value at the time when the input and output are stabilized is used as an output value, and a change at an unstable stage is often not considered as a logical operation of the circuit as a transient change.

  FIG. 6 is superimposed on the waveform diagram of FIG. 3, and the resulting waveform change (intermediate variable and waveform change on the output) is the last when there is an odd number of changes in one signal during the set period. It is the figure which entered the causal relationship of the waveform change limited to only the change. FIG. 6 (a) displays all signals, and FIG. 6 (b) omits signals unrelated to the causal display. Causal relationships related to transitional changes are eliminated, and only signal changes that contribute to changes resulting in the final calculation results are displayed. Compared to all changes, the display is very simple.

  Changes in signals B [1] and B [0] are delayed by one unit time from changes in signals A [1] and A [0]. Considering this as a delay given to the input, FIG. 6 shows the causal relationship of the change on the maximum delay path necessary to determine the output for the change in the waveform diagram of FIG. However, it should be noted that the maximum delay with respect to the input / change of the waveform diagram of FIG. 3 is displayed in FIG. 6 and is not necessarily a critical path.

  The display in FIG. 6 is simple and the displayed conditions are easy to understand. However, in FIG. 6, only the change on the maximum delay path shows the causal relationship. For this reason, there is a lack of information when considering the reasons for changes in individual signals. The reason why the output of a certain logic symbol changes is that one of the input signals has changed (a change in the signal has appeared at the output after the delay time has elapsed), and the other unchanged signal has the value of the changed signal. There is a logic value that is propagated to the output. For example, in FIG. 4A, a change in B [0] from L to H (event 2) appears in C [0] after 3 hours (event 3). It can be said that A [0] had a value of H for a certain period including. FIG. 6 does not give any information about this causal relationship between other unchanged signals and outputs.

  FIG. 7 is a diagram showing the causal relationship of the virtual event in addition to the causal relationship display of FIG. In FIG. 7 (a), each signal is displayed in the order of the signals displayed in FIG. 3, and in FIG. 7 (b), it is classified into two depending on the dependency relationship between the event and the virtual event, and the dependency relationship is displayed. It is. In FIG. 7, not only the waveform change but also the signal value that has not changed are entered as the cause of the change. According to this display, all the causal inputs for all waveform changes are entered, and there is a great deal of information that can be read. However, arrows are mixed and there is a possibility of misreading. In the display example of FIG. 7B, it is easy to understand that there are two change propagation sequences.

  Further, the virtual event extraction unit 15 may extract not only the event-related items but also the state of the signal that causes the extracted virtual event as a new virtual event, for example. FIG. 8 is a diagram illustrating another example of the event extracted regarding the event 14 and the virtual event. The event 14 is dependent on the event 10 and the virtual event 9 as shown in FIG. The event 10 is dependent on the virtual event 5 and the event 7 as shown in FIG. Referring to FIG. 2, intermediate variable signal PC [1] including virtual event 9 is output from AND3. AND3 inputs C [0] and HS [1], and its delay time is 3. Therefore, in C [0] and HS [1], the points of time that are 3 units time back from the virtual event 9 are extracted as the virtual event 12 and the virtual event 13, respectively. Further, at A [0] and B [0], the points in time from the virtual event 12 that are three times behind the delay time of AND1 are extracted as a virtual event 14 and a virtual event 15, respectively, and at A [1] and B [1] The points in time from the event 13 to the XOR2 delay time 2 are extracted as the virtual event 16 and the virtual event 17, respectively.

  In the first embodiment, the waveform diagram of FIG. 3 is obtained by logic simulation, but may be obtained by operating an actual machine.

  Further, as the causal relationship to be displayed, for example, it is limited only to the final change within a certain period such as the period displayed in the figure, the period instructed by the user input, or one cycle period of the synchronous circuit, The cause may be a signal value that has not changed other than the waveform change.

  The operation of the timing chart analysis support system 1 in FIG. 1 will be described by taking as an example a case where it is applied to a sequential circuit in a cycle-based display.

  FIG. 9 is a configuration diagram of the circuit of the RTL design description of the sequential circuit to be processed in this embodiment. This circuit is a part of a uniquely designed serial interface circuit taken out for explanation. 10 to 12 are RTL design descriptions of sequential circuits to be processed in this embodiment, and are described in Verilog HDL.

  FIG. 13 is a diagram showing a waveform diagram including the input including a result of performing a cycle-based simulation by giving an appropriate input to the circuits of FIGS. 9 to 12. Note that the reset function by the asynchronous reset signal RESET_X is not considered. Add an auxiliary line with causal arrows on this waveform diagram.

  The RTL design description by Verilog HDL defines the intermediate variable / output signal value of each cycle from the input / intermediate variable of the previous cycle. For each definition, formally, the output side (intermediate variable / output) can be defined as a function on the input side (input / intermediate variable). For example, the output SOUT is calculated by quoting the intermediate variables ER_EN_ACC, rw_flag, state, bpos, R_DATA in the relevant part of the RTL description, so the format is SOUT = F (ER_EN_ACC, rw_flag, state, bpos, R_DATA) Can be written.

  Here, as one auxiliary line entry method, the timing chart analysis support device 3 in FIG. 1 regards each variable as having a causal relationship every cycle with the variable in the function input list, and the display control device 5 It is possible to fill in an auxiliary line. However, it is expected that a large number of auxiliary lines will come and go on the waveform diagram.

  Even if there is a function relationship, the value actually propagates from the variable serving as the function input to the variable serving as the output. In other words, the situation where the value of the variable on the output side is determined by the focused input variable depends on what value the other input variable takes. For this reason, depending on the values of other input variables, there is a situation where the output side does not change no matter how the value of the noted variable changes (a situation where it cannot be said that the value is propagated to the output side). For example, in SOUT = F (ER_EN_ACC, rw_flag, state, bpos, R_DATA), when ER_EN_ACC = 0, SOUT = 1 is obtained regardless of the values of the rw_flag, state, bpos, and R_DATA signals. In such a situation, it is considered reasonable not to display the causal arrow from the focused variable to the output side in order to make the display easier to understand.

  Therefore, the timing chart analysis support device 3 first pays attention to some variables in the function for obtaining each signal on the waveform diagram as the first method for narrowing down the display of the auxiliary line, and other variables include each cycle. The value of the simulation result is applied to determine whether or not a variable focused on the calculation result of the function output appears in the form of a variable. If it appears, it is determined that the value propagates, that is, there is a causal relationship. This method can be realized by an algorithm similar to the symbolic simulation.

  14 and 15 show an auxiliary line with arrows indicating the causal relationship for each cycle based on this method. FIG. 14 mainly describes a part of the causal relationship based on the intermediate variable state and the causal relationship based on the input EN_ACC, the intermediate variable bpos, the input SIN, the intermediate variable ER_SIN, and the intermediate variable rw_flag. FIG. 15 mainly describes a part of the causal relationship based on the intermediate variable state and the causal relationship based on the intermediate variable ER_EN_ACC.

  At this point, all the auxiliary lines in FIGS. 14 and 15 are displayed. This means that a relatively large number of auxiliary lines are entered. An example of the causal relationship that results in SOUT. For example, in the case of cycle 18 → 19, the function input that determines SOUT is ER_EN_ACC = 1, rw_flag = 0, state = DATA, bpos = 0, R_DATA = X . Therefore, the first condition of the second if statement in the always statement that determines SOUT in the RTL description is satisfied. Therefore, it can be defined that the four variables ER_EN_ACC, rw_flag, state, and bpos have a causal relationship with SOUT. For example, if SOUT is expressed with state as a variable, since the other conditions of the if statement are not satisfied, the expression is SOUT = (state == ST_DATA). Thus, it can be said that state has a causal relationship with SOUT. For example, in the case of cycle 10 → 11, ER_EN_ACC = 1, rw_flag = 0, state = ADDR, bpos = 0, and R_DATA = X. Therefore, the condition of the if statement is not satisfied except for the first one, and SOUT = 0. Changing any variable to another value does not change SOUT = 0. Therefore, it can be defined that none of the variables are propagated.

  In addition to narrowing down the display of the auxiliary lines in FIGS. 14 and 15, FIG. 16 shows only the case where the causal-side signal on the causal auxiliary lines has a value different from the previous cycle. As a result, it is possible to narrow down considerably, and the display is clear and the causal relationship that is the main point of change can be displayed.

  FIG. 17 shows not only the display of the auxiliary lines in FIG. 16 but also only the case where the cause and result sides of the auxiliary lines of each causal relationship have different values from the previous cycle.

  FIG. 18 is a place where there is always a causal relationship in addition to narrowing down the display of the auxiliary line in FIG. 17, that is, a place where the value of the previous cycle is taken as it is, and a one-cycle delay circuit (configured by D-FF) As for the portion that constitutes, the display is omitted except for the case where the causal relationship of other variables is in contact (the cause or result of each other becomes the signal value of the same cycle). In such places, the causal relationship is continuous, making it difficult to see the display of the auxiliary line. Here, it is limited only to important timing.

  FIG. 19 is a diagram in which some intermediate variables are deleted from the waveform diagram display. It is necessary to change the display method of auxiliary lines by deleting intermediate variables. Here, only when the link is possible (the intermediate variable to be deleted connects the causal relationship in the form of a result / cause), the causal relationship is displayed on a new waveform diagram. As a result, the auxiliary line display necessary for many cases can be maintained and displayed.

  FIG. 20 is a diagram showing processing for performing tag display instead of auxiliary line display using auxiliary line display. In this example, a tag is set in cycle 19 of the output signal SOUT as shown in the figure, and the propagation of the tag is examined retroactively to the input side / past. There are various definition methods for determining whether or not a tag propagates. Here, depending on the presence or absence of the causal relationship described in the above description (for example, the description of FIGS. 14 and 15), if there is a causal relationship, the tag Shall propagate. As a result, the causal arrows drawn on FIGS. 14 and 15 are traced backward on the past side starting from the cycle 19 of the signal SOUT, and the tags propagated for all passing signal / cycle locations are added. do it. All the auxiliary lines entered in FIG. 20 can be traced in this way.

  FIG. 21 is a diagram in which hatched lines (downward to the right) are overlaid on signal / cycle locations to which tags can be attached by the method of FIG. Values that affect cycle 19 of signal SOUT can be comprehensively displayed. It is easy to see because there is no causal auxiliary line.

  As described above, in the present invention, the causal relationship between the signals of each cycle is obtained from the RTL description of the design contents in the waveform diagram in the cycle base notation, and further, the narrowing is performed based on the change of the waveform, and the limited causal relationship is determined. By filling in the auxiliary line arrows, it is possible to obtain a display that is very helpful in understanding the contents of the waveform diagram. In addition, by displaying tag tracking from similar causal relationships instead of auxiliary lines, it is possible to display causal relationships related to the signal of interest, and to provide information useful for understanding and analyzing waveform diagrams. it can.

  In the present embodiment, the operation is mainly described as being performed by the timing chart analysis support device 3. However, for example, a part of the processing such as simple judgment of whether to display / not display the causal relationship is performed by the display control device 5. It may be performed.

  The operation of the timing chart analysis support system 1 in FIG. 1 will be described by taking as an example a case where it is applied to a sequential circuit in a cycle-based display. The sequential circuit to be processed in this embodiment is shown in FIGS. 9 to 12, and the waveform diagram is shown in FIG.

  FIG. 22 is a reference diagram of a process of drawing an auxiliary line by paying attention to the structure of the RTL description and taking into consideration the branch condition of the calculation.

  Each intermediate variable / output variable is defined by the RTL description. In these, for example, conditional branches are used for expression in each description like rw_flag, state, and bpos in the 26th to 41st lines in FIG. For each variable, which condition is satisfied in each cycle and which branch processing is performed are determined by analyzing the syntax of the RTL description and applying the simulation result.

  In FIG. 22, the conditional branch used (branch condition state, branch condition bpos, branch condition rw_flag) is also shown on the waveform diagram, and the timing chart analysis support apparatus 3 uses a virtual waveform (state variable). To process.

  For each variable, the location where the conditional branching changes (different from the previous cycle) can be said to be important both in terms of timing and functionality. Therefore, in this embodiment, when the variable on the output side is changed in the next cycle due to the cycle in which the conditional branch is changed, the fact that the satisfaction of the condition has affected the signal is highlighted. .

  The event extraction unit 13 extracts the change point of the conditional branch as an event. The virtual event extraction unit 15 extracts a signal that has not changed as a cause as a virtual event (or a logical value that supports the occurrence of the change) as a virtual event.

  FIG. 23 is a diagram in which the virtual waveform of the conditional branch is removed from FIG. A causal relationship about the output that changes due to the change of the conditional branch on the RTL description is displayed. It can be said that this is an auxiliary line that can be used as a reference when analyzing RTL descriptions.

  With reference to FIG. 24, an example in which the timing chart analysis support system 1 of FIG. 1 is applied to an analog circuit will be described.

FIG. 24 is a diagram illustrating an example of a circuit to be analyzed, a waveform diagram, and auxiliary lines. FIG. 24A shows a circuit to be analyzed. The input _VIN is input to an integrating circuit composed of a resistor _RIN and a capacitor C, and an intermediate variable _Vc is output, which is input to the positive input of the operational amplifier. Further, the constant voltage output V _{ref of the} voltage dividing circuit composed of R ₁ and R ₂ is input to the negative input of the operational amplifier, and the output _VOUT is output via the operational amplifier.

FIG. 24B shows a simulation result when the step input voltage shown in FIG. 24A is applied to the input _VIN of the circuit shown in FIG. When V _IN = V _dd and a potential difference (V _dd −V _c ) is generated in the resistor R _IN , current flows and the capacitor C is charged. The voltage V _c gradually _{approaches the} voltage V _dd while drawing an exponential curve. When V _c = V _ref is exceeded, the value of the output V _OUT of the operational amplifier changes from 0 to V _dd . Note that the delay between the input and output of the operational amplifier is assumed to be 0, and the specification of the operational amplifier is Rail-to-Rail output.

FIG. 24C is a diagram showing a display example of auxiliary lines indicating events, virtual events, and dependency relationships superimposed on the waveform diagram of FIG. Events that can be extracted from the waveform diagram are step-by-step changes in V _IN and V _OUT and changes in which V _c becomes non-differentiable. These events are indicated by Δ in the figure.

The event of the Δ mark of V _c is caused by the change of V _IN and the function of the passive elements R _IN and C. Therefore, this is an event resulting from the event of the Δ mark of _VIN . From the function of the operational _amplifier, the step change in _{V OUT,} it is responsible for voltage _{V c} exceeds _{V ref.} Thus, it is possible to extract a virtual event (○ mark) on V _c at the same time.

Even if V _OUT is not displayed, it is possible to extract a virtual event when the voltage change of Vc passes V _ref from the circuit structure.

The reason why V _c reaches V _ref can be attributed to the fact that V _IN maintains the voltage V _dd until the same time. A virtual event can be defined for the signal _{VIN at the} same time (o mark, solid line) or a period from the step change to the same time (oval mark, broken line). Which representation should be used may be selected depending on the purpose of analysis and the ease of display.

1 is a block diagram of a timing chart analysis support system 1 that is an embodiment of the present invention. FIG. 3 is a diagram illustrating a combinational logic circuit to be processed according to the first exemplary embodiment. FIG. 3 is a waveform diagram as a result of applying and operating the illustrated input signal to the logic circuit of FIG. 2. FIG. 4 is a first diagram illustrating an example of an auxiliary line indicating a dependency of waveform change in the waveform diagram of FIG. 3. FIG. 4 is a second diagram illustrating an example of an auxiliary line indicating the dependency of waveform change in the waveform diagram of FIG. 3. FIG. 4 is a diagram in which a causal relationship of waveform change is entered by limiting to only the last change when there is an odd number of changes in one signal during a set period, superimposed on the waveform diagram of FIG. 3. It is the figure which also displayed the causal relationship of the virtual event together with the display of the causal relationship of FIG. It is a figure which shows another example of the event extracted regarding the event 14, and a virtual event. FIG. 11 is a configuration diagram of a circuit in an RTL design description of a sequential circuit to be processed in the second embodiment. FIG. 10 is a first diagram illustrating an RTL design description of a sequential circuit to be processed in the second embodiment. FIG. 10 is a second diagram illustrating an RTL design description of a sequential circuit to be processed in the second embodiment. FIG. 10 is a third diagram illustrating an RTL design description of a sequential circuit to be processed in the second embodiment. It is the figure which showed the waveform figure of the result of having given an appropriate input to the circuit of FIG. It is FIG. 1 which filled in the auxiliary line with the arrow which shows the causal relationship about each cycle based on the method by paying attention to one part variable and whether the change appeared in the other variable. It is FIG. 2 which filled in the auxiliary line with the arrow which shows the causal relationship about each cycle based on the method by paying attention to one part variable and whether the change appeared in the other variable. In addition to narrowing down the display of the auxiliary lines in FIGS. 14 and 15, the causal auxiliary lines are shown only when the cause side signal has a value different from the previous cycle. In addition to narrowing down the display of auxiliary lines in FIG. 16, the causal-related auxiliary lines are shown only when the cause / result side has values different from the previous cycle. In addition to narrowing down the display of the auxiliary line in FIG. 17, only the case where the value of the previous cycle is taken as it is and the portion forming the delay circuit of one cycle is in contact with the causal relationship of other variables is displayed. FIG. It is the figure which deleted some intermediate variables from the waveform diagram display of FIG. It is the figure which showed the process for performing a tag display instead of an auxiliary line display by the auxiliary line display. FIG. 21 is a diagram in which hatched lines (lower right) are overlaid with respect to signal / cycle locations to which tags can be attached by the method of FIG. 20. In Example 3, it is a reference figure of the process which pays attention to the structure of RTL description and fills in an auxiliary line in consideration of the branch condition of calculation. It is the figure which removed the virtual waveform of the conditional branch from FIG. It is a figure which shows an example of the analysis object circuit of Example 4, a waveform diagram, and an auxiliary line.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Timing chart analysis support system, 3 Timing chart analysis support apparatus, 5 Display control apparatus, 11 Logical dependency extraction part, 13 Event extraction part, 15 Virtual event extraction part, 17 Dependency generation part

Claims (8)

A timing chart analysis support system that supports analysis of waveform data of a plurality of signals related to a circuit to be analyzed,
Event extracting means for extracting a plurality of events satisfying a predetermined event extraction condition from a combination of a part of the plurality of signals or the waveform data of each signal;
Virtual event extraction means for extracting a virtual event from a signal related to each event based on circuit data of the circuit to be analyzed;
Dependencies between events extracted by the event extraction means, dependencies between virtual events extracted by the virtual event extraction means, events extracted by the event extraction means, and virtual event extraction means Dependency generation means for generating dependency relationships between virtual events;
Display control means for causing the display device to display the dependency relationship generated by the dependency relationship generating means together with waveform data of a plurality of signals relating to the circuit to be analyzed;
A timing chart analysis support system comprising:   The timing chart analysis support system according to claim 1, wherein the virtual event extraction unit extracts a new virtual event from a signal related to the extracted virtual event based on circuit data of the circuit to be analyzed. A timing chart analysis support device that supports analysis of waveform data of a plurality of signals related to a circuit to be analyzed,
Event extracting means for extracting a plurality of events satisfying a predetermined event extraction condition from a combination of a part of the plurality of signals or the waveform data of each signal;
Virtual event extraction means for extracting a virtual event from a signal related to each event based on circuit data of the circuit to be analyzed;
Dependencies between events extracted by the event extraction means, dependencies between virtual events extracted by the virtual event extraction means, events extracted by the event extraction means, and virtual event extraction means Dependency generation means for generating dependency relationships between virtual events;
A timing chart analysis support device comprising:   A display control device comprising display control means for causing the display device to display the dependency relationship generated by the dependency relationship generating means according to claim 3 together with waveform data of a plurality of signals related to the circuit to be analyzed. The display control means determines whether or not to display the waveform data of each signal based on a predetermined display condition,
When events and virtual events related to signals that are not displayed mediate dependencies between events to be displayed, between virtual events, or between events and virtual events, events that are not displayed and between virtual events that are displayed without virtual events, virtual Generate as a dependency between events, or between events and virtual events, omit display of dependencies not related to events and virtual events when not mediating, or
Determine the display position or display order of each signal based on the dependency relationship between the events related to the signal to be displayed, between the virtual events, or between the events and the virtual events.
The display control apparatus according to claim 4. A timing chart analysis support method for supporting analysis of waveform data of a plurality of signals related to a circuit to be analyzed,
An event extracting step for extracting a plurality of events satisfying a predetermined event extraction condition from a combination of waveform data of each signal or a part of the plurality of signals,
A virtual event extracting means for extracting a virtual event from a signal related to each event based on circuit data of the circuit to be analyzed;
Dependency generation means includes a dependency relation between events extracted by the event extraction means, a dependency relation between virtual events extracted by the virtual event extraction means, and an event extracted by the event extraction means and the virtual A dependency generation step for generating a dependency between virtual events extracted by the event extraction means;
Timing chart analysis support method including   A program for realizing the timing chart analysis support method according to claim 6 in a computer.   A recording medium for recording the program according to claim 7.