JP2008136928A - Method of driving droplet discharge head, droplet discharge device and electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of driving droplet discharge head by which the uniformity of film thickness of a film pattern formed by discharging droplets is improved, a droplet discharge device and an electro-optical device. <P>SOLUTION: A head driving circuit latches lower selection data SIL through a latch 62 and stores data concerning a nozzle for discharging the droplets. The head driving circuit judges a drawing mode on the basis of mode selection data AD1-AD3 through a state counter 63 and a duty control signal generating circuit 65 and when the drawing mode is the duty mode, an output timing control signal for selecting one of a plurality of the nozzle groups is generated in every state. The head driving circuit generates a signal (output control signal P1) for directing the discharge of droplets to each nozzle in the state regulated for the correspondent nozzle group is generated. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a droplet discharge head driving method, a droplet discharge device, and an electro-optical device.

In general, a liquid crystal display is equipped with a color filter substrate having a large number of pixels. Each pixel of the color filter substrate receives light from the light source, transmits light of a specific wavelength, and displays a full color image on the liquid crystal display. In the color filter manufacturing process, an inkjet method using a droplet discharge head is employed in order to improve productivity and reduce production costs (for example, Patent Document 1).

The droplet discharge head includes a plurality of cavities for storing a liquid material, a plurality of nozzles arranged in one direction so as to communicate with the cavity, and a plurality of actuators (for example, piezo elements) that pressurize the liquid material in each cavity. And a resistance heating element). The droplet discharge head inputs a drive waveform signal common to the actuators selected based on the drawing data, and discharges liquid droplets from the nozzles corresponding to the actuators. In the inkjet method, a pixel is formed by supplying a filter material to a droplet discharge head, discharging droplets of the filter material toward a color filter substrate, and drying the droplets that have landed on the substrate.

In the ink jet method, drawing with excellent gradation expression is desired as the drawing target is highly refined. Japanese Patent Application Laid-Open No. H10-228707 provides common waveform generation means for generating a plurality of drive voltage waveforms corresponding to the ink ejection amount, and selects any one of the drive voltage waveforms generated by the common waveform generation means based on the gradation data signal. To supply to the actuator. According to this, the size of the droplet can be changed by different drive waveform signals, and excellent gradation expression can be achieved without changing the design of the inner diameter of the nozzle and the nozzle formation pitch.
JP-A-8-146214 Japanese Patent Laid-Open No. 9-11457

In the inkjet method, the color filter substrate and the droplet discharge head are relatively moved in a predetermined scanning direction, and the drive waveform signal is input to each actuator at a predetermined discharge frequency.
Thereby, the droplets for the arranged nozzles are sequentially ejected at a predetermined ejection frequency, and the liquid pattern is sequentially drawn along the scanning direction of the color filter substrate.

However, the droplet discharge heads lead out the liquid material from one common tank toward all the nozzles. Therefore, the following problems were invited. That is, in a droplet discharge head, when a large number of nozzles discharge droplets at the same time, the flow resistance of each nozzle greatly affects the supply pressure of the liquid material (for example, crosstalk occurs between adjacent nozzles). This causes large variations in the discharge weight of each nozzle. This results in a relatively large droplet, or
The relatively small droplets continue along the scanning direction, and a film thickness step along the scanning direction of the droplet discharge head is formed, so that the display image quality of the liquid crystal display is significantly lowered.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for driving a droplet discharge head that improves the film thickness uniformity of a film pattern formed by discharging droplets. It is an object to provide a discharge device and an electro-optical device.

The droplet discharge head driving method of the present invention is a droplet discharge head driving method that selectively drives a plurality of drive nozzles for discharging droplets from a plurality of nozzles arranged in a predetermined direction. The plurality of nozzles are divided into a plurality of predetermined blocks, and each of the plurality of drive nozzles is driven at a different timing for each corresponding block.

According to the droplet ejection head driving method of the present invention, each block ejects droplets at different timings. Accordingly, it is possible to reduce the overlap of the discharge timing by the number of blocks, and it is possible to suppress the variation in droplet weight caused by the simultaneous discharge.
As a result, the droplet weight for each nozzle can be made uniform, and as a result, the film thickness uniformity of the film pattern formed by discharging the droplets can be improved.

This droplet discharge head driving method may be configured to drive different blocks for each predetermined discharge frequency.
According to the driving method of the droplet discharge head, the same block discharges droplets discretely.
Therefore, compared to the case where the same block continuously discharges droplets, the droplet discharge distribution can be made uniform. As a result, the film thickness uniformity of the film pattern can be improved.

This droplet discharge head driving method may be configured such that each of adjacent nozzles is divided into different blocks.
According to this droplet discharge head driving method, each adjacent nozzle discharges droplets at different timings. Therefore, crosstalk between nozzles can be avoided more reliably. As a result, the film thickness uniformity of the film pattern formed by discharging droplets can be improved.

In this droplet discharge head driving method, a rank corresponding to the weight of the droplet discharged to each of a plurality of nozzles is associated, and the drive nozzle is driven to predefine the weight of the droplet. The drive waveform signal for calibrating to a predetermined weight may be generated for each rank, and the drive waveform signal corresponding to the rank may be supplied to each of the drive nozzles.

According to this method for driving a droplet discharge head, the weight of each droplet is set to a predetermined weight. Therefore, it is possible to make the droplet weight for each nozzle more uniform.

The droplet discharge device according to the present invention includes a storage unit that stores nozzle selection data for selecting a plurality of drive nozzles from a plurality of nozzles arranged in a predetermined direction, and a plurality of blocks in which the plurality of nozzles are determined in advance. And a selection signal generating means for generating a block selection signal for selecting any one of the plurality of blocks at each droplet discharge timing, and the block selection signal at each droplet discharge timing. Output means for outputting a drive waveform signal for causing the droplets to be ejected to the drive nozzle that is the nozzle in the selected block and selected by the nozzle selection data.

According to the droplet discharge device of the present invention, each block discharges droplets at different timings. Accordingly, it is possible to reduce the overlap of the discharge timing by the number of blocks, and it is possible to suppress the variation in droplet weight caused by the simultaneous discharge. As a result, the droplet weight for each nozzle can be made uniform, and as a result, the film thickness uniformity of the film pattern formed by discharging the droplets can be improved.

In this liquid droplet ejection apparatus, the selection signal generation unit counts the number of times of input of a clock signal generated at the timing of ejection of the liquid droplet, and associates the number of times of input in advance with each of the plurality of blocks, The block selection signal for selecting a block associated with the number of times of input from the plurality of blocks may be generated at each droplet discharge timing.

According to this droplet discharge device, a block for discharging a droplet is selected according to the number of clock signal inputs. Therefore, simultaneous discharge by a plurality of blocks can be reliably avoided. As a result, it is possible to reliably improve the film thickness uniformity of the film pattern formed by discharging the droplets.

In this droplet discharge apparatus, the storage unit stores mode selection data for designating a predetermined drawing mode from among a plurality of drawing modes having different numbers of blocks, and the selection signal generating unit is configured to store the drawing signal. The number of times of input is associated with each of the plurality of blocks corresponding to a mode in advance, and each of the plurality of blocks is selected based on the drawing mode specified by the mode selection data at each droplet discharge timing. The structure which produces | generates the said block selection signal for selecting the block matched with the said frequency | count of input may be sufficient.

According to this droplet discharge device, the number of blocks can be selected by mode selection data. Therefore, the block selection range can be expanded, and as a result, the drawing target range can be expanded.

In this droplet discharge apparatus, the selection signal generation unit may be configured to divide each of adjacent nozzles into different blocks.
According to this droplet discharge device, each adjacent nozzle discharges droplets at different timings. Therefore, crosstalk between nozzles can be avoided more reliably. As a result, the film thickness uniformity of the film pattern formed by discharging droplets can be improved.

In this droplet discharge device, the storage unit stores information for associating each of the plurality of nozzles with a rank corresponding to the discharge weight, and the output unit sets the discharge weight to a predetermined weight. A drive waveform signal to be calibrated may be generated for each rank, and the drive waveform signal corresponding to the rank may be output to each of the drive nozzles based on the information stored in the storage unit. .

According to this droplet discharge device, each drive nozzle is driven by a drive waveform signal for discharging a predetermined weight. Therefore, the droplet weight for each nozzle can be made more uniform, and as a result, the film thickness uniformity of the film pattern formed by discharging the droplets can be further improved.

The electro-optical device of the present invention is an electro-optical device having a thin film formed by drying droplets discharged onto a substrate, and the thin film is formed by the droplet discharging device. apparatus.

According to the electro-optical device of the present invention, the film thickness uniformity of various thin films can be improved. As a result, the optical characteristics of the electro-optical device can be improved.

Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS. First, the liquid crystal display device 1 as an electro-optical device will be described. FIG. 1 is a perspective view showing the entire liquid crystal display device, and FIG. 2 is a perspective view showing a color filter substrate provided in the liquid crystal display device.

In FIG. 1, the liquid crystal display device 1 includes a backlight 2 and a liquid crystal panel 3. The backlight 2 irradiates the entire surface of the liquid crystal panel 3 with light emitted from the light source 4. LCD panel 3
Includes an element substrate 5 and a color filter substrate 6, and the element substrate 5 and the color filter substrate 6 are bonded together by a rectangular frame-shaped sealing material 7, and the liquid crystal LC is sealed in the gap. The liquid crystal LC modulates the light from the backlight 2 and displays a desired image on the color filter substrate 6.
Is displayed on the top surface.

In FIG. 2, on the upper surface of the color filter substrate 6 (the lower surface in FIG. 1; the side surface facing the element substrate 5), a lattice-shaped light shielding layer 8 and a large number of spaces (pixels 9) surrounded by the light shielding layer 8 are formed. )When,
Is formed. The light shielding layer 8 is formed of a resin containing a light shielding material such as chromium or carbon black, and shields light transmitted through the liquid crystal LC. In each pixel 9, a color filter CF is formed as a thin film that transmits light of a specific wavelength. The color filter CF is, for example,
A red filter CFR that transmits red light, a green filter CFG that transmits green light,
A blue filter CFB that transmits blue light. The color filter CF is formed using the droplet discharge device of the present invention. That is, the color filter CF is formed by discharging droplets of each filter material into the corresponding pixels 9 and drying the droplets that have landed in each pixel 9.

Here, the upper surface (the lower surface in FIG. 1) of the color filter substrate 6 is referred to as an ejection surface 6a.
Next, a droplet discharge device for forming the color filter CF will be described. FIG.
FIG. 3 is an overall perspective view showing a droplet discharge device.

In FIG. 3, the droplet discharge device 10 includes a base 11 formed in a rectangular parallelepiped shape. A pair of guide grooves 12 extending along the longitudinal direction (Y direction) is formed on the upper surface of the base 11,
A substrate stage 13 is attached to the pair of guide grooves 12. The substrate stage 13 is connected to an output shaft of a stage motor provided on the base 11. The substrate stage 13 places the color filter substrate 6 with the discharge surface 6a facing upward, and positions and fixes the color filter substrate 6. The substrate stage 13 is scanned at a predetermined speed along the guide groove 12 when the stage motor rotates normally or reversely, and scans the color filter substrate 6 along the Y direction.

On the upper side of the base 11, a guide member 14 formed in a gate shape is installed along the X direction orthogonal to the Y direction. An ink tank 15 is disposed above the guide member 14.
The ink tank 15 stores a liquid material (filter ink Ik) containing a filter material, and derives the filter ink Ik at a predetermined pressure.

The guide member 14 is formed with a pair of upper and lower guide rails 16 extending in the X direction, and a carriage 17 is attached to the pair of upper and lower guide rails 16. The carriage 17 is connected to an output shaft of a carriage motor provided on the guide member 14. A plurality of droplet discharge heads 18 (hereinafter simply referred to as discharge heads 18) arranged in the X direction are mounted on the lower side of the carriage 17. The carriage 17 is scanned along the guide rail 16 when the carriage motor rotates forward or backward, and scans each ejection head 18 along the X direction.

4 is a view of the discharge head 18 as viewed from the lower side (substrate stage 13), and FIG.
It is AA sectional view taken on the line.
In FIG. 4, on the upper side (lower side in FIG. 3) of the ejection head 18, a nozzle plate 19
Is provided. A nozzle forming surface 19a parallel to the color filter substrate 6 is formed on the upper surface (the lower surface in FIG. 3) of the nozzle plate 19, and 180 nozzles penetrating in the normal direction of the nozzle forming surface 19a are formed in the nozzle forming surface 19a. Through holes (nozzles N) are arranged at equal intervals along the X direction. On the lower side of the discharge head 18 (upper side in FIG. 3), the head substrate 20
And an input terminal 20a is provided at one end of the head substrate 20. Various signals for driving the ejection head 18 are input to the input terminal 20a.

Here, the nozzle N most positioned in the X arrow direction is defined as the first nozzle N1, and the second nozzle N2,..., The 179th nozzle N179, the 180th nozzle N18 are sequentially arranged in the opposite X arrow direction.
0.

In FIG. 5, cavities 21 communicating with the ink tanks 15 are formed above the nozzles N, respectively. Each cavity 21 is supplied with filter ink Ik from a common ink tank 15. Each cavity 21 stores the filter ink Ik and supplies it to the corresponding nozzle N. A diaphragm 22 that can vibrate in the vertical direction is attached to the upper side of each cavity 21 so that the volume of the corresponding cavity 21 can be enlarged and reduced. On the upper side of the diaphragm 22, piezoelectric elements PZ as actuators are disposed. Each piezoelectric element PZ has a signal (drive waveform signal C) for driving the piezoelectric element PZ.
When OM) is input, the corresponding diaphragm 22 is vibrated by contracting and expanding in the vertical direction.

Each cavity 21 has a corresponding nozzle N when the corresponding diaphragm 22 vibrates.
The filter meniscus is vibrated in the vertical direction, and the filter ink Ik having a predetermined weight corresponding to the drive waveform signal COM (drive voltage) is ejected as a droplet D from the corresponding nozzle N. The ejected droplet D flies along a substantially normal line of the color filter substrate 6 and lands on a position on the ejection surface 6a opposite to the nozzle N.

In FIG. 4, a droplet weight device 23 is disposed on the left side of the base 11. The droplet weight device 23 measures the weight of the droplet D (actual weight Iw as the discharge weight) for each nozzle N, and a known weight measuring device can be used. The droplet weight device 23 includes, for example,
It is possible to use an electronic balance that receives the discharged droplets D in a receiving pan and measures the droplets D. Further, the droplet weight device 23 uses a piezoelectric vibrator having an electrode, discharges the droplet D toward the electrode, and based on the resonance frequency of the piezoelectric vibrator that changes due to the landing of the droplet D. What detects the actual weight Iw of the droplet D can be used.

Here, the average value of the actual weight Iw of each droplet D ejected from all the nozzles N in the row is referred to as an average actual weight Iwcen. In addition, the average actual weight Iwcen is calculated as Iwmax when the maximum actual weight Iw among the discharged droplets D is Iwmax and the minimum actual weight Iw is Iwmin.
It is defined by cen = (Iwmax + Iwmin) / 2. The average actual weight Iwcen is
It is defined for each of the plurality of ejection heads 18 mounted on the carriage 17.

Next, the electrical configuration of the droplet discharge device 10 will be described with reference to FIGS. FIG.
4 is a block circuit diagram showing an electrical configuration of the droplet discharge device 10. FIG.
In FIG. 6, the control device 30 causes the droplet discharge device 10 to execute various processing operations (for example, a drawing process in the “normal mode” and a drawing process in the “duty (DUTY) mode)”.

The control device 30 includes an external I / F 31, a control unit 32 including a CPU, a RAM 33 as a storage unit including a DRAM and an SRAM and storing various data, and a ROM 34 storing various control programs. In addition, the control device 30 includes an oscillation circuit 35 that generates a clock signal, a drive waveform generation circuit 36 as a drive waveform signal generation unit that generates a drive waveform signal COM, and a weight device for driving the droplet weight device 23. A driving circuit 37, a motor driving circuit 38 for scanning the substrate stage 13 and the carriage 17, and an internal I / F 39 for transmitting various signals are included. The control device 30 is connected to the input / output device 40 via the external I / F 31. The control device 30 is connected to the substrate stage 13, the carriage 17, and the droplet weight device 23 via the internal I / F 39. In addition, the control device 30
It is connected to a plurality of head drive circuits 41 corresponding to each of the ejection heads 18 via an internal I / F 39.

The input / output device 40 is an external computer having, for example, a CPU, RAM, ROM, hard disk, liquid crystal display, and the like. The input / output device 40 outputs various control signals and various data for driving the droplet discharge device 10 to the external I / F 31 in accordance with a control program stored in the ROM or the hard disk. For example, the input / output device 40 outputs mode data Im for selecting a drawing mode, drawing data Ip, reference drive voltage data Iv, and head data Ih to the external I / F 31. The external I / F 31 includes mode data Im, drawing data Ip, reference drive voltage data Iv, and head data I input from the input / output device 40.
h or the like is received.

Here, the drawing mode is a mode for controlling the discharge state of the droplet D, and is “normal mode”, “1/1 DUTY”, “1/2 DUTY”, “1/3 DUTY”, “1”. / 4DU
TY ”and five types of modes.

The drawing data Ip is information about the position and film thickness of the color filter CF, information about the discharge position of the droplet D, information about the scanning speed of the substrate stage 13, and the like.
Various data for causing the droplets D to be discharged.

The reference drive voltage data Iv is data relating to a drive voltage (reference drive voltage Vh0) for calibrating the average actual weight Iwcen to a predetermined weight (reference weight). The reference drive voltage data Iv is defined for each ejection head 18 because the average actual weight Iwcen of each ejection head 18 is different. That is, the reference drive voltage data Iv is the discharge head 18.
This is data for calibrating the average actual weight Iwcen of the reference weight to a common reference weight.

The head data Ih is data in which each of the nozzles N (piezoelectric elements PZ) is classified into four types of “ranks”, and is data in which each nozzle N is associated with a rank based on the weight of the droplet D. . In the head data Ih, for example, as shown in FIG. 7, the rank “1” is set for the nozzle N where the actual weight Iw of the discharged droplet D satisfies Iwcen × 1.02> Iw ≧ Iwcen × 1.01. Has been. The actual weight Iw of the discharged droplet D is Iwcen × 1.0
Rank “2” is set for the nozzle N satisfying 1> Iw ≧ Iwcen, and rank “3” is set for the nozzle N satisfying Iwcen> Iw ≧ Iwcen × 0.99 as the actual weight Iw of the discharged droplet D. Is set. In addition, the actual weight Iw of the discharged droplet D is Iwcen × 0.9.
Rank “4” is set for the nozzle N satisfying 9> Iw ≧ Iwcen × 0.98.

In FIG. 6, a RAM 33 is used as a reception buffer 33a, an intermediate buffer 33b, and an output buffer 33c.
The ROM 34 stores various control routines executed by the control unit 32 and various data for executing the control routine. For example, the ROM 34 stores rank data for associating the drive waveform signal COM corresponding to the rank with respect to each nozzle N at that time.
As shown in FIG. 7, the rank data means that each rank (“1” to “4”) is divided into four different drive waveform signals COM (first drive waveform signal COMA, second drive waveform signal COMB, third Data for associating with any one of the drive waveform signal COMC and the fourth drive waveform signal COMD). That is, the rank data is data for associating each of the nozzles N with the drive waveform signal COM corresponding to the rank.

In FIG. 6, the oscillation circuit 35 generates a clock signal for synchronizing various data and various drive signals. The oscillation circuit 35 generates a transfer clock SCLK used at the time of serial transfer of various data, for example. The oscillation circuit 35 generates a latch signal (pattern data latch signal LATA and common selection data latch signal LATB) used in parallel conversion of various serially transferred data. The oscillation circuit 35 generates a state switching signal CHA for defining the discharge timing of the droplet D.

The drive waveform generation circuit 36 includes a waveform memory 36a, a latch circuit 36b, and a D / A converter 36c.
And an amplifier 36d. The waveform memory 36a stores waveform data for generating each drive waveform signal COM in association with a predetermined address. The latch circuit 36b latches the waveform data read from the waveform memory by the control unit 32 with a predetermined clock signal. The D / A converter 36c converts the waveform data latched by the latch circuit 36b into an analog signal, and the amplifier 3
6d amplifies the analog signal converted by the D / A converter 36c to simultaneously generate the drive waveform signal COM.

When the input / output device 40 receives the reference drive voltage data Iv, the control unit 32 reads the waveform data in the waveform memory 36a with reference to the reference drive voltage data Iv via the drive waveform generation circuit 36. Then, the control unit 32, via the drive waveform generation circuit 36, has four types of drive waveform signals COM (first drive waveform signal COMA, second drive waveform signal COMB,
The third drive waveform signal COMC and the fourth drive waveform signal COMD) are generated.

The control unit 32 is connected to the first to fourth drive waveform signals COMA, CO via the drive waveform generation circuit 36.
MB, COMC, and COMD are generated as signals having different drive voltages corresponding to the ranks “1” to “4”, respectively. For example, as illustrated in FIGS. 7 and 8, the control unit 32 sets the first drive waveform signal COMA to a drive voltage (first drive voltage Vha) corresponding to the nozzle N of rank “1”.
It generates as a signal consisting of The first drive voltage Vha is a voltage at a level lower than the reference drive voltage Vh0 (for example, Vha = Vh0 × 0.985). As a result, the rank “1”
When the first drive waveform signal COMA is input to the corresponding piezoelectric element PZ,
The drive amount (expansion / contraction amount) of the corresponding piezoelectric element PZ is reduced by the amount corresponding to the first drive voltage Vha to calibrate the actual weight Iw of the droplet D, and the actual weight Iw of the droplet D is calculated as the average actual weight Iwcen ( Reference weight).

Similarly, the control unit 32 outputs the second drive waveform signal COMB, the third drive waveform signal COMC, and the fourth drive waveform signal COMD via the drive waveform generation circuit 36 to rank “2” and rank “
3 ”and the drive voltage corresponding to the rank“ 4 ”(second drive voltage Vhb, third drive voltage Vhc, fourth
It is generated as a signal consisting of drive voltage Vhd). Second drive voltage Vhb, third drive voltage V
hc and the fourth drive voltage Vhd are Vhb = Vh0 × 0.995 and Vhc = Vh0 ×, respectively.
1.005, Vhd = Vh0 × 1.015. The nozzles N of rank “2”, rank “3”, and rank “4” are supplied to the corresponding piezoelectric element PZ by the second drive waveform signal COMB, the third
When the drive waveform signal COMC and the fourth drive waveform signal COMD are input, the actual weight Iw of the droplet D is calibrated by the drive voltage corresponding to the rank, and the actual weight Iw of the droplet D is set as the reference weight.

As a result, all nozzles N (piezoelectric elements PZ) can normalize the actual weight Iw of each droplet D to a common reference weight when the drive waveform signal COM corresponding to the rank is input. .

In FIG. 6, the control unit 32 outputs a drive control signal corresponding to the weight device drive circuit 37. The weight device drive circuit 37 responds to the drive control signal from the control unit 32, and receives the internal I / F 39.
Then, the droplet weight device 23 is driven.

The control unit 32 outputs a drive control signal corresponding to the motor drive circuit 38. The motor drive circuit 38 scans the substrate stage 13 and the carriage 17 via the internal I / F 39 in response to the drive control signal from the control unit 32.

The control unit 32 temporarily stores the head data Ih received by the external I / F 31 in the reception buffer 33a. The control unit 32 converts the head data Ih into an intermediate code and stores it as intermediate code data in the intermediate buffer 33b. The control unit 32 reads the intermediate code data from the intermediate buffer 33b, expands it into common selection data with reference to the rank data in the ROM 34, and stores the common selection data in the output buffer 33c.

The common selection data is a 2-bit value (“0”) at each grid point of the dot pattern grid.
0 ”,“ 01 ”,“ 10 ”,“ 11 ”), and any one of the first to fourth drive waveform signals COMA, COMB, COMC, COMD for each of the four values. The dot pattern grid is a grid with a minimum interval that is defined on the ejection surface 6a, which is a two-dimensional drawing plane, and that is defined by the ejection cycle of the droplets D.

When the common selection data corresponding to one scan of the substrate stage 13 is obtained, the control unit 32 generates serial data synchronized with the transfer clock SCLK using the common selection data, and transmits the serial data via the internal I / F 39. Serial data is serially transferred to the head drive circuit 41. When serially transferring the common selection data for one scan, the control unit 32 erases the contents of the intermediate buffer and executes the expansion process for the next intermediate code data.

Here, the serial data generated using the common selection data is referred to as serial common selection data SIB. The serial common selection data SIB is data that is commonly used regardless of the drawing mode.

In FIG. 9, the serial common selection data SIB corresponds to 180-bit higher selection data SIH in which 1-bit value is associated with each of the 180 nozzles N, and 1-bit value is associated with each of the 180 nozzles N. 180-bit lower selection data SIL and 32-bit control data CR.

The upper selection data SXH is composed of upper bits of a 2-bit value for selecting the type of the drive waveform signal COM. The lower selection data SXL is composed of lower bits of a 2-bit value for selecting the drive waveform signal COM.

The control unit 32 uses the upper selection data SXH and the lower selection data SXL via the head driving circuit 41, and drives each of the 180 nozzles N (piezoelectric elements PZ) according to the truth table shown in FIG. Associate COM types. For example, the control unit 32 associates the first drive waveform signal COMA with the nozzle N (piezoelectric element PZ) whose upper selection data SXH is “0” and lower selection data SXL is “0” via the head drive circuit 41. Control unit 3
2 shows that the second drive waveform signal COMB and the third drive waveform signal C are respectively applied to the nozzles N (piezoelectric elements PZ) of which the upper selection data SXH and the lower selection data SXL are “01”, “10”, “11”
The OMC is associated with the fourth drive waveform signal COMD.

The control data CR is 3-bit mode selection data (first mode selection data AD1, second
Mode selection data AD2 and third mode selection data AD3). The first to third mode selection data AD1, AD2, AD3 are data for defining the drawing mode.

The control unit 32 uses the first to third mode selection data AD1, AD2, and AD3 to define the drawing mode for the head drive circuit 41 according to the truth table shown in FIG. For example, the control unit 32 sets the first, second, and third mode selection data AD1, AD2, AD3 to “0XX” (
When X is “0” or “1”), the head drive circuit 41 is specified that the drawing mode is the normal mode (DUTY mode is off). In the control unit 32, the first, second and third mode selection data AD1, AD2, AD3 are “100”, “101”, “110”.
, 111 ”, the drawing mode is“ 1/1 DUT ”for the head drive circuit 41, respectively.
Y ”,“ 1/2 DUTY ”,“ 1/3 DUTY ”,“ 1/4 DUTY ”(DUTY mode is on).

In FIG. 6, the control unit 32 temporarily stores the drawing data Ip received by the external I / F 31 in the reception buffer 33a. The control unit 32 draws the drawing data I according to the mode data Im.
p is converted into an intermediate code and stored in the intermediate buffer 33b as intermediate code data.

When the drawing mode is the “normal mode”, the control unit 32 reads the intermediate code data from the intermediate buffer 33b, develops it into dot pattern data, and stores the dot pattern data in the output buffer 33c.

On the other hand, the control unit 32 determines that the drawing mode is “DUTY mode” (“1/1 DUTY”, “1
/ 2 DUTY ”,“ 1/3 DUTY ”,“ 1/4 DUTY ”), the intermediate code data is read from the intermediate buffer 33b, expanded into dot pattern data corresponding to the“ DUTY mode ”, and the dot pattern data is output. The data is stored in the buffer 33c.

The dot pattern data is data associating whether or not the droplet D is ejected (ejection / non-ejection) to each position (each grid of the dot pattern grid) on the two-dimensional drawing plane (ejection surface 6a). The dot pattern data is data for associating a 1-bit value (“0” or “1”) with each grid of the dot pattern grid. The dot pattern lattice is a lattice having a minimum interval defined by the discharge period of the droplet D.

When the dot pattern data corresponding to one scan of the substrate stage 13 is developed, the control unit 32 generates serial data synchronized with the transfer clock SCLK using the dot pattern data, and via the internal I / F 39, The serial data is serially transferred to the head drive circuit 41. When the dot pattern data for one scan is serially transferred, the control unit 32 erases the contents of the intermediate buffer 33b and executes the development process for the next intermediate code data.

Here, the serial data generated using the dot pattern data is referred to as serial pattern data SIA.
In FIG. 12, the serial pattern data SIA includes 180-bit upper selection data SIH in which 1-bit value is associated with each of the 180 nozzles N, and 1-bit value is associated with each of the 180 nozzles N. 180-bit lower-order selection data SIL and 32-bit pattern data SP. The control unit 32 selects the upper selection data SIH and the lower selection data S depending on whether the drawing mode is the “normal mode” or the “DUTY mode”.
The contents of IL and pattern data SP are changed as follows.

When the drawing mode is the “normal mode”, the upper selection data SIH is composed of upper bits of a 2-bit value for selecting a dot gradation. The lower selection data SIL is
It is composed of lower bits of a 2-bit value for selecting a dot gradation. As shown in FIG. 13, the pattern data SP has 8 bits for each of four values (“00”, “01”, “10”, “11”) defined by the upper selection data SIH and the lower selection data SIL. 32 bit data (each switch data Pnm (nm = 00-03, 10-13)
,..., 70 to 73). Each switch data Pnm ("0" or "1"
Are bit data for defining whether the piezoelectric element PZ is on or off.

In FIG. 13, the state switching signal CHA is a pulse signal for defining the discharge timing of the droplet D, and is generated at the discharge frequency of the droplet D. Here, a state defined for each pulse of the state switching signal CHA is referred to as a “state”. State switching signal CH
A is a plurality of states (for example, “0”) from when the preceding pattern data latch signal LATA is generated until the subsequent pattern data latch signal LATA is generated.
To "7" states).

When the drawing mode is the “normal mode”, the control unit 32 passes through the head drive circuit 41,
Each data of the pattern data SP (each switch data Pnm) according to the truth table shown in FIG.
) To each state. For example, the control unit 32 switches the switch data P00, P10,... To the nozzle N (piezoelectric element PZ) whose upper selection data SIH is “0” and lower selection data SIL is “0” via the head drive circuit 41.・ Associating P70. The control unit 32 associates the switch data P00, P10,..., P70 with the states “0” to “7”, respectively. Then, the control unit 32 sends a drive waveform signal CO to the piezoelectric element PZ via the head drive circuit 41 in the state of the switch data P00 to P70 set to “1”.
M is supplied. For example, when P00 to P60 are “0” and P70 is “1”, the control unit 32 turns off the piezoelectric element PZ while the state is “0” to “6”, and the state is “7”.
At this timing, the piezoelectric element PZ is turned on.

Similarly, the control unit 32 determines that the upper selection data SIH and the lower selection data SIL are “
The switch data P01 to P71, P02 to P72, and P03 to P73 are associated with the nozzles N (piezoelectric elements PZ) of “01”, “10”, and “11” according to the truth table shown in FIG. Are switch data P01-P71, P02-P72, P03-
P73 is associated with each state “0” to “7”. Then, the control unit 32 switches the switch data P01 to P71, P02 to P1 set to “1” via the head drive circuit 41.
The drive waveform signal COM is supplied to the corresponding piezoelectric element PZ in the states of P72 and P03 to P73.

As a result, when the drawing mode is the “normal mode”, all the nozzles N discharge the droplets D with the drive pulse pattern defined by the upper selection data SIH and the lower selection data SIL, and achieve a desired gradation. Can be realized.

On the other hand, when the drawing mode is the “DUTY mode”, the upper selection data SIH and the pattern data SP are dummy data for enabling the serial pattern data SIA to be transferred by the transfer clock SCLK, and are composed of invalid data. Is done. The lower selection data SIL is nozzle selection data for selecting the nozzle N that discharges the droplet D.
1 that specifies whether the piezoelectric element PZ is turned on or off by a 1-bit value ("1" or "0")
It consists of 80 bits.

When the drawing mode is the “DUTY mode”, the control unit 32 causes the head driving circuit 41 to execute the drawing process using only the lower selection data SIL in the serial pattern data SIA.

Next, the head drive circuit 41 will be described below.
In FIG. 14, the head drive circuit 41 includes a common selection control signal generation circuit 50 and an output control signal generation circuit 60. The head drive circuit 41 includes an output synthesis circuit 70 (first to fourth common output synthesis circuits 70A, 70B, 70C, and 70D) and a level shifter that boosts a logic signal to a drive voltage level of an analog switch. 71 (first to fourth common level shifters 71A, 71B, 71C, 71D). The head drive circuit 41 includes four switch circuits 72 (first to fourth common switch circuits 72A, 72B, and 7) each having an analog switch for supplying each drive waveform signal COM to the piezoelectric element PZ.
2C, 72D).

First, the common selection control signal generation circuit 50 for generating the common selection control signals PXA, PXB, PXC, and PXD will be described below.
In FIG. 15, the common selection control signal generation circuit 50 includes a shift register 51, a latch 52, and a common selection data decoding circuit 53.

The shift register 51 includes a control data register 51A and a lower selection data register 51B.
And the upper selection data register 51C, and the serial common selection data SIB and the transfer clock SCLK are input from the control device 30.

The control data register 51A is the control data C of the serial common selection data SIB.
R is serially transferred and sequentially shifted by the transfer clock SCLK to store 32-bit control data CR. The control data register 51A makes it possible to read the first to third mode selection data AD1, AD2, AD3 from the stored control data CR.

The lower selection data register 51B serially transfers the lower selection data SXL among the serial common selection data SIB, and sequentially shifts by the transfer clock SCLK to store 180-bit lower selection data SXL. The upper selection data register 51C serially transfers the upper selection data SXH out of the serial common selection data SIB.
The 180-bit higher-order selection data SXH is stored by sequentially shifting with CLK.

The latch 52 includes a control data latch 52A, a lower selection data latch 52B, and an upper selection data latch 52C. From the control device 30, a latch signal LATB for common selection data
Is entered.

When the common selection data latch signal LATB is input, the control data latch 52A latches the data in the control data register 51A, that is, the control data CR, and outputs the latched data to a predetermined control circuit. The lower selection data latch 52B latches the data of the lower selection data register 51B, that is, the lower selection data SXL, when the common selection data latch signal LATB is input. When the common selection data latch signal LATB is input, the upper selection data latch 52C receives the data in the upper selection data register 51C,
That is, the upper selection data SXH is latched.

The common selection data decoding circuit 53 reads the lower selection data SXL latched by the lower selection data latch 52B and the upper selection data SXH latched by the upper selection data latch 52C. The common selection data decoding circuit 53 uses the lower selection data SXL and the upper selection data SXH and uses four different drive waveform signals CO in accordance with the truth table shown in FIG.
Whether to use each of M (selection / non-selection) is defined. The common selection data decoding circuit 53 generates data defining selection / non-selection of each drive waveform signal COM for each of the 180 nozzles N.

Here, the data defining the selection / non-selection of the first drive waveform signal COMA is referred to as a first common selection control signal PXA. Further, the second drive waveform signal COMB, the third drive waveform signal C
Data that defines the selection / non-selection of the OMC and the fourth drive waveform signal COMD are referred to as a second common selection control signal PXB, a third common selection control signal PXC, and a fourth common selection control signal PXD, respectively.

Next, the output control signal generation circuit 60 for generating the output control signal PI will be described below.
16, the output control signal generation circuit 60 includes a shift register 61, a latch 62, a state counter 63, a pattern data selection circuit 64, a DUTY control signal generation circuit 65, and a pattern data synthesis circuit 66. .

The shift register 51, the latch 52, the latch 62, and the RAM 33 constitute storage means. The state counter 63 and the DUTY control signal generation circuit 65 constitute a selection signal generation unit. The common selection control signal generation circuit 50,
Output composition circuit 70, level shifter 71, switch circuit 72, pattern data composition circuit 66
The output means is configured by.

The shift register 61 includes a pattern data register 61A and a lower selection data register 6
1B and upper selection data register 61C, and serial pattern data SIA and transfer clock SCLK are input from control device 30.

In the pattern data register 61A, the pattern data SP of the serial pattern data SIA is serially transferred and sequentially shifted by the transfer clock SCLK to store 32-bit pattern data SP. The lower selection data register 61B serially transfers the lower selection data SIL in the serial pattern data SIA, and sequentially shifts by the transfer clock SCLK to store 180-bit lower selection data SIL. The upper selection data register 61C serially transfers the upper selection data SIH out of the serial pattern data SIA and sequentially shifts by the transfer clock SCLK to store 180-bit upper selection data SIH.

The latch 62 includes a pattern data latch 62A, a lower selection data latch 62B, and an upper selection data latch 62C, and the pattern data latch signal LA from the control device 30.
TA is input.

When the pattern data latch signal LATA is input, the pattern data latch 62A latches the data in the pattern data register 61A, that is, the pattern data SP. When the pattern data latch signal LATA is input, the lower selection data latch 62B latches the data in the lower selection data register 61B, that is, the lower selection data SIL. When the pattern data latch signal LATA is input, the upper selection data latch 62C latches the data in the upper selection data register 61C, that is, the upper selection data SIH.

The state counter 63 is a 3-bit counter circuit and includes a state switching signal CHA.
The state is changed by counting at the rising edge of. State counter 63
After counting the state from “0” to “7”, the state is returned to “0” by inputting the state switching signal CHA. The state counter 63 is reset when the LATA signal becomes “H” level (high potential level), and returns the state to “0”. When the state switching signal CHA and the pattern data latch signal LATA are input from the control device 30, the state counter 63 counts the state value and outputs it to the pattern data selection circuit 64 and the DUTY control signal generation circuit 65. .

The pattern data selection circuit 64 reads the first to third mode selection data AD1, AD2, AD3 from the control data register 51A, and determines the type of drawing mode according to the truth table shown in FIG.

When the pattern data selection circuit 64 determines that the drawing mode is the “normal mode”,
Based on the value of the state output by the state counter 63 and the pattern data SP latched by the pattern data latch 62A, switch data Pn0 to Pn3 corresponding to the value of the state is selected at any given time. The pattern data selection circuit 64 outputs the selected switch data Pn0 to Pn3 to the pattern data synthesis circuit 66. That is, the pattern data selection circuit 64 receives the pattern data latch signal LATA from the pattern data latch 62A.
The pattern data SP latched by the pattern data latch 62A is read, and the switch data P corresponding to the state value “n” is read according to the truth table shown in FIG.
Select n0 to Pn3. For example, the pattern data selection circuit 64 includes the state counter 6
When the state 3 is “0”, the pattern data SP corresponding to the state “0”, that is,
The switch data P00 to P03 shown in FIG. 13 are output to the pattern data synthesis circuit 66.

When determining that the drawing mode is the “DUTY mode”, the pattern data selection circuit 64 disables the above processing and waits until the drawing mode becomes the “normal mode”.
The DUTY control signal generation circuit 65 reads the first to third mode selection data AD1, AD2, AD3 from the control data register 51A, and determines the type of the drawing mode according to the truth table shown in FIG.

When determining that the drawing mode is the “DUTY mode”, the DUTY control signal generation circuit 65 generates ten types of output timing control signals as block selection signals for each state output by the state counter 63. The output timing control signal is output to the pattern data synthesis circuit 66.

The output timing control signal is a signal for causing the plurality of nozzles N associated in advance to have the same discharge timing. The output timing control signal is displayed in the drawing mode (“1/1 DUTY”, “1/2 DUTY”, “1/3 DUTY”, “1/4 DUTY”).
Y "), and the 10 types of signals generated as shown in FIG. 12, as shown in FIG. 12, 1/1 control signal D1N0, 1/2 first control signal D2N0, and 1/2 second control signal D2N1. And including. The output timing signals are 1/3 first control signal D3N0 and 1/3 second control signal D.
3N1, 1/3 third control signal D3N2. Furthermore, the output timing control signal is
1/4 first control signal D4N0, 1/4 second control signal D4N1, and 1/4 third control signal D
4N2 and 1/4 fourth control signal D4N3.

Each output timing control signal includes a plurality of nozzles N (blocks) to be controlled.
Are associated in advance. In FIG. 12, “◯” marks indicate the nozzles N that are associated in advance with the output timing control signals. For example, all the nozzles N are associated with the 1/1 control signal D1N0 in advance.

The odd-numbered nozzles N and the even-numbered nozzles N are associated with the 1/2 first control signal D2N0 and the 1/2 second control signal D2N1, respectively. That is, all the nozzles N are associated with one of the 1/2 first control signal D2N0 and the 1/2 second control signal D2N1, respectively.

The 1/3 first control signal D3N0 includes the 12n + 1, 4, 7, and 10th nozzles N (1 /
3 first nozzle groups) are associated with each other. Also, 1/3 second control signal D3N1 and 1/3
The third control signal D3N2 includes the 12n + 2, 5, 8, and 11th nozzles N (1
/ 3 2nd nozzle group) and 12n + 3, 6, 9, and 12th nozzle N (1/3 third nozzle group) are associated with each other. That is, all the nozzles N are associated with any one of the 1/3 first control signal D3N0, the 1/3 second control signal D3N1, and the 1/3 third control signal D3N2.

The ¼ 1st control signal D4N0 and the ¼ second control signal D4N1 have the 12th
The +1, 5, and 9th nozzles N (1/4 first nozzle group) are associated with the 12n + 3, 7, and 11th nozzles N (1/4 second nozzle group). Also, 1/4 third control signal D
4N2 and 1/4 fourth control signal D4N3 include 12n + 2, 6, 10th nozzle N (1/4 third nozzle group) and 12n + 4, 8th, 12th nozzle N (1/4), respectively. 4th
Nozzle group). That is, all the nozzles N are any one of the 1/4 first control signal D4N0, the 1/4 second control signal D4N1, the 1/4 third control signal D4N2, and the 1/4 fourth control signal D4N3. Are associated with each other.

When the DUTY control signal generation circuit 65 determines that the drawing mode is “1/1 DUTY”, the 1/1 control signal D1N0 is set to “H” for each state output by the state counter 63, as shown in FIG. Set to level (level indicating discharge timing). At this time, the DUTY control signal generation circuit 65 sets all the output timing control signals other than the 1/1 control signal D1N0 to the “L” level (a level indicating non-ejection timing).

That is, when determining that the drawing mode is “1/1 DUTY”, the DUTY control signal generation circuit 65 outputs each output timing control signal for each state, and synchronizes the ejection timings of all the nozzles N to each state. .

When the DUTY control signal generation circuit 65 determines that the drawing mode is “½ DUTY”, as shown in FIG. 18, the ½ duty first and second control signals D2N0 and D2N1 are alternately “ Switch to H ”level. At this time, the DUTY control signal generating circuit 65 is 1 /
(2) All the output timing control signals other than the first control signal D2N0 and the 1/2 second control signal D2N1 are maintained at the “L” level.

That is, when determining that the drawing mode is “1/2 DUTY”, the DUTY control signal generation circuit 65 outputs each output timing control signal for each state, and discharge timing of the even-numbered nozzles N and odd-numbered nozzles. The ejection timing of the nozzle N is synchronized with the even-numbered state and the odd-numbered state, respectively.

When the DUTY control signal generation circuit 65 determines that the drawing mode is “1/3 DUTY”, as shown in FIG. 18, the 1/3 first to third control signals D3N0, D3N1, and D3N2 are successively 3 Switch to the “H” level in a different state of the two states. At this time, the DUTY control signal generation circuit 65 generates the 1/3 first to third control signals D3N0, D3N1,
All of the output timing control signals other than D3N2 are maintained at the “L” level.

That is, when it is determined that the drawing mode is “1/3 DUTY”, the DUTY control signal generation circuit 65 outputs each output timing control signal for each state, and 1/3 first to third
Each of the ejection timings of the nozzle group is synchronized with a different state among three consecutive states. For example, in FIG. 18, the DUTY control signal generation circuit 65 synchronizes the discharge timing of the 1/3 first nozzle group with the states “0”, “3”, and “6”, and The discharge timing is synchronized with the states “1”, “4”, and “7”. Also, DUTY
The control signal generation circuit 65 sets the discharge timing of the 1/3 third nozzle group to the states “2”, “
5 ”and“ 0 ”.

When the DUTY control signal generation circuit 65 determines that the drawing mode is “¼ DUTY”, as shown in FIG. 18, the ¼ first to fourth control signals D4N0, D4N1, D4N2,
D4N3 is switched to the “H” level in a different state among the four consecutive states. At this time, the DUTY control signal generation circuit 65 generates the 1/4 first to fourth control signals D4N0,
All of the output timing control signals other than D4N1, D4N2, and D4N3 are maintained at the “L” level.

That is, when determining that the drawing mode is “1/4 DUTY”, the DUTY control signal generation circuit 65 outputs each output timing control signal for each state, and the 1/4 first to fourth
Each of the ejection timings of the nozzle group is synchronized with a different state among four consecutive states. For example, in FIG. 18, the DUTY control signal generation circuit 65 synchronizes the discharge timing of the 1/4 first nozzle group with the states “0”, “4”, “0”, and The discharge timing is synchronized with the states “1” and “5”. Further, the DUTY control signal generation circuit 65 synchronizes the discharge timing of the 1/4 third nozzle group with the states “2” and “6”, and sets the discharge timing of the 1/4 fourth nozzle group to the state “3”. , “7”.

In FIG. 16, the pattern data synthesis circuit 66 receives the lower selection data SIL latched by the lower selection data latch 52B and the upper selection data SIH latched by the upper selection data latch 52C. Further, the switch data Pn0 to Pn3 output from the pattern data selection circuit 64 and the output timing control signals output from the DUTY control signal generation circuit 65 are input to the pattern data synthesis circuit 66.

The pattern data synthesis circuit 66 is 180-bit data (output control) that defines whether or not the droplets D are ejected to all the nozzles N for each state (value of each bit: “0” or “1”). Signal PI).

When the drawing mode is “normal mode”, the pattern data synthesis circuit 66 uses the lower selection data SIL, the upper selection data SIH, and the switch data Pn0 to Pn3.
The output control signal PI is generated according to the truth table shown in FIG.

For example, as shown in FIG. 19, the pattern data synthesis circuit 66 includes four AND gates 66a, 66b, 66c, 66d corresponding to one nozzle N, and these AND gates 66.
and an OR gate 66e to which the outputs of a, 66b, 66c and 66d are inputted. Upper AND selection data SIH, lower selection data SIL, and corresponding switch data Pn0 to Pn3 are input to AND gates 66a, 66b, 66c, and 66d, respectively.
When the upper selection data SIH and the lower selection data SIL are “00”, the AND gate 66
Only a is valid, and the switch data Pn0 (“0” or “1”) is output as the output control signal PI of the corresponding nozzle N. When the upper selection data SIH and the lower selection data SIL are “01”, “10”, “00”, AND gates 66b, 66, respectively.
Only c and 66d are valid, and switch data Pn1, Pn2, and Pn3 (“0” or “1”) are output as the output control signal PI of the corresponding nozzle N. As a result, FIG.
The switch data Pnm corresponding to the truth table shown in 3 is output as the output control signal PI.

When the drawing mode is the “DUTY mode”, the pattern data synthesis circuit 66 generates the output control signal PI using the lower selection data SIL and each output timing control signal. That is, the pattern data synthesis circuit 66 selects the nozzle N selected by the lower selection data SIL.
On the other hand, an output control signal PI for discharging the droplet D is generated at a timing (state) defined by each output timing control signal.

For example, as shown in FIG. 20, the pattern data synthesis circuit 66 includes four AND gates 67a, 67b, 67c, 67d corresponding to one nozzle N, and these AND gates 67.
and an OR gate 67e to which outputs of a, 67b, 67c and 67d are inputted. Common AND lower selection data SIL is input to each AND gate 67a, 67b, 67c, 67d. In addition, the AND gates 67a, 67b, 67c, and 67d have "1/1 DUTY", "1/2 DUTY", and "1 / 3D" corresponding to the nozzle N, respectively.
Output timing control signals for “UTY” and “1/4 DUTY” are input.

For example, each AND gate corresponding to the (12n + 1) th nozzle N has a 1/1 control signal D1N0, a 1/2 first control signal D2N0, a 1/3 first control signal D3N0, 1/4 according to FIG. The first control signal D4N0 is input. In addition, each AND gate corresponding to the 12n + 2nd nozzle N has a 1/1 control signal D1N0, a 1/2 second control signal D2N1, a 1/3 second control signal D3N1, and a 1/4 second control signal. D4N1 is input.

When the drawing mode is “1/2 DUTY”, only the AND gate 67b is valid in the AND gates corresponding to all the nozzles N.
The AND gate 67b corresponding to the (12n + 1) th (odd-numbered) nozzle N is when the 1/2 first control signal D2N0 is at “H” level (bit value is “1”) (state is “0”, “
2), “4”, “6”). That is, the pattern data synthesis circuit 66
The lower selection data SIL corresponding to the nozzle N is “1”, and the state is “0”.
, “2”, “4”, and “6”, a signal for discharging the droplet D from the nozzle N (a signal having a bit value of “1”) is output as the output control signal PI.

On the other hand, each AND gate 67b corresponding to the 12n + 2nd (even number) nozzle N is
1/2 When the second control signal D2N1 is at “H” level (bit value is “1”) (state is “
1), “3”, “5”, “7”). That is, the pattern data synthesizing circuit 66, when the lower selection data SIL corresponding to the nozzle N is “1” and the states are “1”, “3”, “5”, “7”, A signal for discharging the droplet D from the nozzle N (a signal having a bit value “1”) is output as the output control signal PI.

Accordingly, the pattern data synthesis circuit 66 outputs the output control signal PI for ejecting the droplets D from the selected odd-numbered nozzles N and the selected even-numbered ones when the drawing mode is “1/2 DUTY”. The output control signal PI for discharging the droplet D from the nozzle N is alternately output for each state.

Similarly, the drawing mode is “1/1 DUTY”, “1/3 DUTY”, “1/4 DUTY”.
In the AND gates corresponding to all the nozzles N, the AND gates 67a are respectively provided.
Only the AND gate 67c and the AND gate 67d are valid.

As a result, the pattern data synthesis circuit 66 outputs an output control signal PI for discharging droplets D from all the selected nozzles N for each state when the drawing mode is “1/1 DUTY”.

Further, the pattern data synthesis circuit 66 is configured so that when the drawing mode is “1/3 DUTY”,
In three consecutive states, 1/3 first nozzle group, 1/3 second nozzle group, 1/3, respectively.
An output control signal PI for discharging the droplet D from the third nozzle group is output.

Further, the pattern data synthesis circuit 66 is configured so that when the drawing mode is “1/4 DUTY”,
In four consecutive states, 1/4 first nozzle group, 1/4 second nozzle group, 1/4, respectively.
An output control signal PI for discharging the droplet D from the third nozzle group and the 1/4 fourth nozzle group is output.

In FIG. 14, the output synthesis circuit 70 includes a first common output synthesis circuit 70A, a second common output synthesis circuit 70B, a third common output synthesis circuit 70C, and a fourth common output synthesis circuit 70.
D. A 180-bit output control signal PI is commonly input from the output control signal generation circuit 60 to each of the output synthesis circuits 70A, 70B, 70C, and 70D. In addition, the output synthesis circuits 70A, 70B, 70C, and 70D include a first common selection control signal PXA, a second common selection control signal PXB, a third common selection control signal PXC, and a first common selection control signal generation circuit 50, respectively. A 4-common selection control signal PXD is input.

The first to fourth common output combining circuits 70A, 70B, 70C, and 70D are configured by AND gates corresponding to one nozzle N, respectively. Each A of the first common output synthesis circuit 70A
A corresponding output control signal PI and a corresponding first common selection control signal PXA are input to the ND gates. Whether each AND gate of the first common output synthesis circuit 70A supplies the first drive waveform signal COMA to the corresponding piezoelectric element PZ (supply / non-supply).
Is output (first selected common output control signal CPA). Each AND gate of the second common output synthesis circuit 70B has a corresponding output control signal PI and a corresponding second.
The common selection control signal PXB is input. Each AND of the second common output synthesis circuit 70B
The gate outputs a signal (second selection common output control signal CPB) defining supply / non-supply of the second drive waveform signal COMB to the corresponding piezoelectric element PZ. A corresponding output control signal PI and a corresponding third common selection control signal PXC are input to each AND gate of the third common output combining circuit 70C. Each AN of the third common output synthesis circuit 70C
The D gates output a signal (third selection common output control signal CPC) defining supply / non-supply of the third drive waveform signal COMC to the corresponding piezoelectric element PZ. The corresponding output control signal PI and the corresponding fourth common selection control signal PXD are input to each AND gate of the fourth common output synthesis circuit 70D. Fourth common output synthesis circuit 70D
Each of the AND gates outputs a signal (third selection common output control signal CPC) defining supply / non-supply of the fourth drive waveform signal COMD to the corresponding piezoelectric element PZ.

In the first common output combining circuit 70A, for example, the output control signal PI is “1”, and
When the first common selection control signal PXA is “1”, the first selection common output control signal CPA (the signal whose bit value is “1”) for supplying the first drive waveform signal COMA to the corresponding piezoelectric element PZ is used. Output. Conversely, in the first common output synthesis circuit 70A, the output control signal PI is “0”,
Alternatively, when the first common selection control signal PXA is “0”, the first selection common output control signal CPA (the signal whose bit value is “0”) for not supplying the first drive waveform signal COMA to the piezoelectric element PZ. ) Is output.

As a result, each of the 180 nozzles N (piezoelectric elements PZ) determines whether or not the droplet D is ejected or not based on the output control signal PI, and the first to fourth common selection control signals PXA and PXB.
, PXC, and PXD determine the supply / non-supply of each drive waveform signal COM.

The level shifter 71 has first to fourth drive waveform signals COMA, COMB, COMC, COM.
There are four D level shifters (first common level shifter 71A, second common level shifter 71B, third common level shifter 71C, and fourth common level shifter 71D). The first to fourth common level shifters 71A, 71B, 71C, 71D are supplied from the corresponding output synthesis circuit 70 to the first to fourth selected common output control signals CPA, CPB, CP, respectively.
C and CPD are input. First to fourth common level shifters 71A, 71B, 71C, 7
1D boosts the first to fourth selected common output control signals CPA, CPB, CPC, and CPD to the drive voltage level of the analog switch, and outputs open / close signals corresponding to the 180 piezoelectric elements PZ.

The switch circuit 72 has first to fourth drive waveform signals COMA, COMB, COMC, COM.
4 D switch circuits (first common switch circuit 72A, second common switch circuit 72B, third common switch circuit 72C, and fourth common switch circuit 72D). The first to fourth common switch circuits 72A, 72B, 72C, and 72D each have 180 analog switches corresponding to the piezoelectric elements PZ. Open / close signals are input from the corresponding level shifters 71 to the first to fourth common switch circuits 72A, 72B, 72C, 72D, respectively. Corresponding drive waveform signals COM are input to the input terminals of the four analog switches, and corresponding piezoelectric elements PZ are commonly connected to the output terminals of the four analog switches. Each analog switch receives an open / close signal from the corresponding level shifter 71, and outputs a drive waveform signal COM corresponding to the corresponding piezoelectric element PZ when the open / close signal is at "H" level.

Thereby, each of the 180 nozzles N (piezoelectric elements PZ) is selected by the first to fourth selected common output control signals CPA, C when the discharge operation of the droplet D is selected by the output control signal PI.
The first to fourth drive waveform signals COMA, COMB corresponding to the rank by PB, CPC, CPD
, COMC, COMD are supplied.

Next, a method for driving the droplet discharge head 18 mounted on the droplet discharge device 10 will be described below. FIG. 21 is a timing chart for explaining the drive waveform signal COM supplied to each piezoelectric element PZ.

First, as shown in FIG. 3, the color filter substrate 6 is placed on the substrate stage 13 with its discharge surface 6a facing upward. At this time, the substrate stage 13 arranges the color filter substrate 6 in the anti-Y arrow direction of the carriage 17. From this state, the input / output device 40 inputs the mode data Im, the drawing data Ip, the reference drive voltage data Iv, and the head data Ih to the control device 30. At this time, the mode data Im is data for selecting “1/2 DUTY”. The reference drive voltage data Iv and the head data Ih are generated based on the actual weight Iw of each droplet D measured by the droplet weight device 23, respectively.

In the head data Ih, the first nozzle N1 and the second nozzle N2 located in the X arrow direction are classified into a rank “1”, and the third nozzle N3 and the fourth nozzle N4 are classified into a rank “2”. Then, the fifth nozzle N5 and the sixth nozzle N6 are classified into a rank of “3”. Also, first to first
The piezoelectric elements PZ corresponding to the sixth nozzles N1 to N6 are respectively the first piezoelectric element PZ1, the second piezoelectric element PZ2, the third piezoelectric element PZ3, the fourth piezoelectric element PZ4, the fifth piezoelectric element PZ5, and the sixth piezoelectric element PZ6. That's it.

The control device 30 scans the carriage 17 via the motor drive circuit 38 and moves the carriage 17 so that each ejection head 18 passes over the color filter substrate 6 when the color filter substrate 6 is scanned in the Y arrow direction. Deploy. When the carriage 17 is arranged, the control device 30 starts scanning the substrate stage 13 via the motor drive circuit 38.

The control device 30 expands the head data Ih input from the input / output device 40 into common selection data. When the control device 30 develops the common selection data corresponding to one scan of the substrate stage 13, as shown in FIG. 21, the control device 30 generates the serial common selection data SIB using the common selection data, and the serial common selection data SIB. Are serially transferred to the head drive circuit 41 in synchronization with the transfer clock SCLK.

The control device 30 outputs a common selection data latch signal LATB to the head drive circuit 41 and causes the head drive circuit 41 to latch the serial common selection data SIB. The head drive circuit 41 reads the first to third mode selection data AD1, AD2, AD3 included in the control data CR of the serial common selection data SIB, and determines the drawing mode according to the truth table shown in FIG.

Next, the control device 30 develops the drawing data Ip input from the input / output device 40 into dot pattern data. When the dot pattern data corresponding to one scan of the substrate stage 13 is developed, the control device 30 generates the serial pattern data SIA corresponding to the DUTY mode using the dot pattern data, and transfers the serial pattern data SIA to the transfer clock SCLK. The data is serially transferred to the head drive circuit 41 in synchronization with the above.

When the substrate stage 13 reaches a predetermined drawing start position, the control device 30 outputs a pattern data latch signal LATA to the head drive circuit 41 as shown in FIG. (Upper selection data SIH, lower selection data SIL, and pattern data SP) are latched.

When the control device 30 outputs the pattern data latch signal LATA to latch the serial pattern data SIA, the control device 30 sequentially outputs the state switching signal CHA to the head drive circuit 41 to change the state from “0” to “1”, “2”. ”,“ 3 ”,“ 4 ”,... In addition, the control device 30 refers to the reference drive voltage data Iv and sends four types of drive waveform signals COM (first drive waveform signal COMA, second drive waveform signal COMB,
The third drive waveform signal COMC and the fourth drive waveform signal COMD) are generated. The control device 30 synchronizes the first to fourth drive waveform signals COMA, COMB, COMC, COMD with the pattern data latch signal LATA and the state switching signal CHA, respectively, and the head drive circuit 4.
1 for each state.

When the head drive circuit 41 latches the serial pattern data SIA, the first to third
Based on the mode selection data AD1, AD2, AD3, the upper selection data SIH and the pattern data SP are invalidated. Further, the head drive circuit 41 generates each output timing control signal corresponding to “1/2 DUTY” based on the first to third mode selection data AD1, AD2, AD3.

That is, the head drive circuit 41 outputs the output control signal PI for discharging the droplets D from the odd-numbered nozzles N among the nozzles N selected based on the lower selection data SIL, and the droplets from the even-numbered nozzles N. An output control signal PI for discharging D is alternately generated for each state. The head drive circuit 41 defines a discharge operation by the odd-numbered nozzles N and a discharge operation by the even-numbered nozzles N for each state.

For example, as shown in FIG. 21, the first piezoelectric element PZ1, the third piezoelectric element PZ3, and the fifth piezoelectric element PZ5 corresponding to the odd-numbered nozzles N have “0”, “2”, “4”, “6”
The even-numbered state defines the discharge operation of the droplet D. Further, the second piezoelectric element PZ2, the fourth piezoelectric element PZ4, and the sixth piezoelectric element PZ6 corresponding to the even-numbered nozzles N have “1”, “3”,
The ejection operation of the droplet D is defined by the odd states “5” and “7”.

Further, when the head drive circuit 41 latches the serial common selection data SIB, the head drive circuit 41 follows the upper selection data SXH and the lower selection data SXL and the truth table shown in FIG.
The type of the drive waveform signal COM is defined for each nozzle N (piezoelectric element PZ).

For example, in the first and second piezoelectric elements PZ1, PZ2, the corresponding upper selection data SXH and lower selection data SXL are “00”, and the first drive waveform signal COMA is defined according to the truth table shown in FIG. The That is, the first drive waveform signal COMA corresponding to the rank is supplied to the first and second piezoelectric elements PZ1, PZ2 classified in the rank of “1”.

Further, the third and fourth piezoelectric elements PZ3 and PZ4 have corresponding upper selection data SX.
H and lower selection data SXL are “01”, and the second drive waveform signal COMB is defined according to the truth table shown in FIG. That is, the third and fourth classified in the rank of “2”
The piezoelectric element PZ3, PZ4 is supplied with the second drive waveform signal COMB corresponding to the rank.

Further, the fifth and sixth piezoelectric elements PZ5 and PZ6 are respectively provided with corresponding upper selection data SX.
H and lower selection data SXL are “11”, and the third drive waveform signal COMC is defined according to the truth table shown in FIG. That is, the fifth and sixth classified in the rank of “3”
The piezoelectric element PZ5, PZ6 is supplied with the second drive waveform signal COMB corresponding to the rank.

As a result, all the nozzles N that eject the droplets D receive the drive waveform signal COM corresponding to the rank, and eject the droplets D having a substantially reference weight. In addition, all the nozzles N that discharge the droplets D can avoid the simultaneous discharge of the adjacent nozzles N by the drawing mode of “1/2 DUTY”. Accordingly, all the nozzles N that discharge the droplet D discharge the droplet D having a reference weight with higher accuracy.

Next, effects of the present embodiment configured as described above will be described below.
(1) According to the above embodiment, the head drive circuit 41 latches the lower selection data SIL via the latch 62 and stores data relating to the nozzle N for ejecting the droplet D. The head drive circuit 41 determines the drawing mode based on the mode selection data AD1 to AD3 via the state counter 63 and the DUTY control signal generation circuit 65, and the drawing mode is “DUT”.
When the “Y mode” is selected, an output timing control signal for selecting any one of the nozzle groups corresponding to the “DUTY mode” is generated for each state. The head drive circuit 4
1 generates an output control signal PI for causing each of the nozzles N that eject the droplet D to eject the droplet D in a state defined in the corresponding nozzle group via the pattern data synthesis circuit 66.

Accordingly, each nozzle group discharges the droplet D in a different state. Accordingly, it is possible to reduce the overlap of the discharge timing by the number of nozzle groups, and it is possible to suppress variations in droplet weight due to simultaneous discharge. As a result, the weight of the droplets for each nozzle N can be made uniform, and as a result, the color filter CF formed by discharging the droplets D.
The film thickness uniformity can be improved.

(2) According to the above embodiment, the state counter 63 switches the state by counting the number of times the state switching signal CHA generated at the discharge timing of the droplet D is input. DUT
The Y control signal generation circuit 65 associates a state value with each of the plurality of nozzle groups in advance. Then, the DUTY control signal generation circuit 65 generates an output timing control signal for selecting a nozzle group corresponding to the current state according to the output value of the state counter 63.

Therefore, the nozzle group for discharging the droplet D is selected according to the state. As a result, simultaneous discharge by a plurality of nozzle groups can be reliably avoided. As a result, the film thickness uniformity of the color filter CF formed by discharging the droplets D can be reliably improved.

(3) According to the above embodiment, the shift register 51 stores the mode selection data AD1 to AD3 for determining the drawing mode. The DUTY control signal generation circuit 65 associates a state value with each nozzle group in the “DUTY mode” designated by the mode selection data AD1 to AD3. Then, the DUTY control signal generation circuit 65 receives the designated “DUTY”.
An output timing control signal for selecting a nozzle group associated with the current state from among the nozzle groups of “mode” is generated.

Accordingly, the number of nozzle groups can be selected by the mode selection data AD1 to AD3. Therefore, the selection range of the nozzle group can be expanded, and as a result, the range to be drawn can be expanded.

In addition, you may change the said embodiment as follows.
In the above embodiment, “½ DUTY” is designated by the mode selection data AD1 to AD3. For example, “1” is set by the mode selection data AD1 to AD3.
/ 3DUTY "or" 1/4 DUTY "may be designated.

Then, as shown in FIG. 22, 1/3 first nozzle group (first and fourth piezoelectric elements PZ1, P
Z4) defines the discharge operation of the droplet D in each of the states “0”, “3”, “6”,. Further, “1” is applied to the 1/3 second nozzle group (second and fifth piezoelectric elements PZ2, PZ5).
, “4”, “7”,..., The discharge operation of the droplet D is defined. For the 1/3 third nozzle group (third and sixth piezoelectric elements PZ3, PZ6), “2”, “5”, “0”,...
The configuration may be such that the discharge operation of the droplet D is defined in each state.

Alternatively, as shown in FIG. 23, a 1/4 first nozzle group (first and fifth piezoelectric elements PZ1,
In PZ5), the discharge operation of the droplet D is defined in each of the states “0”, “4”, “0”,. In addition, the 1/4 second nozzle group (second and sixth piezoelectric elements PZ2 and PZ6) includes “1
”,“ 5 ”,“ 1 ”,..., The discharge operation of the droplet D is defined. Also, 1 /
4 For the third nozzle group (third piezoelectric element PZ3), the discharge operation of the droplet D is defined in each state of “2”, “6”, “2”,. Also, a 1/4 fourth nozzle group (fourth piezoelectric element PZ4
) May be configured to define the discharge operation of the droplet D in each of the states “3”, “7”, “3”,.

In the above embodiment, the drawing mode is set to “normal mode”, “1/1 DUTY”, “1/2”.
It is embodied in “DUTY”, “1/3 DUTY”, “1/4 DUTY”. For example, the present invention may be embodied as “1/5 DUTY” or “1/6 DUTY”, and the drawing mode of the present invention does not limit the number of nozzle group divisions.

In the above embodiment, the control device 30 is configured to transfer only the serial common selection data SIB in advance and store the lower selection data SIL. Then, the head drive circuit 41
Each time the serial pattern data SIA is latched to generate the output control signal PI, the first to fourth common selection control signals PXA, P are used by using the lower-order selection data SIL stored in advance.
XB, PXC, and PXD are generated.

For example, every time the control device 30 transfers the serial pattern data SIA, the control device 30 transfers the serial common selection data SIB and the pattern data latch signal LATA.
Alternatively, the common selection data latch signal LATB may be output each time. Then, every time the output control signal PI is generated, the first to fourth common selection control signals PXA, PXB, PXC, and PXD for defining selection / non-selection of the drive waveform signal COM may be generated. .

According to this, every time the ejection operation of the droplet D is set, the drive waveform signal COM corresponding to the rank is associated with each of all the nozzles N. Therefore, the variation in the discharge weight for each nozzle N can be further reduced.

In the above embodiment, the control unit 32 is configured to develop the drawing data Ip into dot pattern data. For example, the input / output device 40 may develop the drawing data Ip into dot pattern data, and the input / output device 40 may input the dot pattern data to the control device 30.

In the above embodiment, the actuator is embodied in the piezoelectric element PZ. For example, the actuator may be embodied as a resistance heating element as long as it receives a predetermined drive waveform signal COM and discharges the droplet D.

In the above embodiment, each ejection head 18 is configured to include 180 nozzles N in only one row. For example, each ejection head 18 may be configured to include two or more rows of 180 nozzles N, and the number of nozzles in the row may be embodied with a quantity larger than 180.

In the above embodiment, the electro-optical device is embodied in the liquid crystal display device 1, and the color filter CF is manufactured using the droplets D. For example, the alignment film of the liquid crystal display device 1 may be manufactured using the droplets D. Alternatively, the electro-optical device may be embodied as an electroluminescence display device, and a light-emitting element may be manufactured by discharging droplets D containing a light-emitting element forming material.

FIG. 11 is a perspective view illustrating a liquid crystal display device. Similarly, the perspective view explaining a color filter substrate. Similarly, the perspective view explaining a droplet discharge device. Similarly, the perspective view explaining a droplet discharge head. Similarly, the principal part sectional drawing explaining a droplet discharge head. Similarly, the electric block circuit diagram explaining the electrical constitution of a droplet discharge device. Similarly, the figure explaining the rank of the nozzle. Similarly, the figure explaining a drive waveform signal. Similarly, the figure explaining serial common selection data. Similarly, the figure explaining pattern data. Similarly, the figure explaining drawing mode. Similarly, the figure explaining serial pattern data. Similarly, a timing chart for explaining pattern data. Similarly, the electric block circuit diagram explaining a head drive circuit. Similarly, a circuit diagram illustrating a common selection control signal generation circuit. Similarly, the electric block circuit diagram explaining an output control signal generation circuit. Similarly, the figure explaining an output timing control signal. Similarly, a timing chart for explaining an output timing control signal. Similarly, a circuit diagram illustrating a pattern data synthesis circuit. Similarly, a circuit diagram illustrating a pattern data synthesis circuit. Similarly, a timing chart for explaining the drive timing of the head drive circuit. 6 is a timing chart for explaining drive timing of a head drive circuit according to a modification. 6 is a timing chart for explaining drive timing of a head drive circuit according to a modification.

Explanation of symbols

AD1, AD2, AD3 ... mode selection data, CF ... color filter as a thin film, C
OM, COMA, COMB, COMC, COMD ... drive waveform signal, D ... droplet, N ... nozzle, 10 ... droplet discharge device, 33 ... RAM constituting storage means, 50 ... common selection control signal constituting output means Generation circuit 52, 62 ... Latch constituting storage means, 63 ... State counter constituting selection signal generation means, 65 ... DUTY control signal generation circuit constituting selection signal generation means, 66 ... Pattern data constituting output means Synthesis circuit.

Claims (10)

A method of driving a droplet discharge head for selecting and driving a plurality of drive nozzles from a plurality of nozzles arranged in a predetermined direction,
Dividing the plurality of nozzles into a plurality of predetermined blocks;
Driving each of the plurality of drive nozzles at different timing for each corresponding block;
A method of driving a droplet discharge head characterized by the above. A method for driving a droplet discharge head according to claim 1,
Driving the different blocks for each predetermined ejection frequency;
A method of driving a droplet discharge head characterized by the above. A method for driving a droplet discharge head according to claim 1 or 2,
Dividing each adjacent nozzle into different said blocks;
A method of driving a droplet discharge head characterized by the above. A method for driving a droplet discharge head according to any one of claims 1 to 3,
Associating a rank corresponding to the discharge weight to each of the plurality of nozzles,
A drive waveform signal for calibrating the discharge weight to a predetermined weight is generated for each rank,
Supplying the drive waveform signal corresponding to the rank to each of the drive nozzles;
A method of driving a droplet discharge head characterized by the above. Storage means for storing nozzle selection data for selecting a plurality of drive nozzles from a plurality of nozzles arranged in a predetermined direction;
A selection signal generating unit that divides the plurality of nozzles into a plurality of predetermined blocks and generates a block selection signal for selecting any one of the plurality of blocks at each droplet discharge timing;
For discharging the droplets to the nozzles in the block selected by the block selection signal and the driving nozzles selected by the nozzle selection data at each droplet discharge timing. An output means for outputting a drive waveform signal;
A droplet discharge apparatus comprising: The droplet discharge device according to claim 5,
The selection signal generating means includes
Counting the number of clock signal inputs generated at the droplet discharge timing, associating the number of inputs in advance with each of the plurality of blocks, for each droplet discharge timing,
Generating the block selection signal for selecting a block associated with the input count from the plurality of blocks;
A droplet discharge device characterized by the above. The droplet discharge device according to claim 6,
The storage means
Storing mode selection data for designating a predetermined drawing mode from a plurality of drawing modes having different numbers of blocks;
The selection signal generating means includes
Associating the number of inputs in advance with each of the plurality of blocks corresponding to the drawing mode,
The block selection signal for selecting a block associated with the input count from the plurality of blocks based on the drawing mode specified by the mode selection data at each droplet discharge timing. Generating,
A droplet discharge device characterized by the above. A droplet discharge device according to any one of claims 5 to 7,
The selection signal generating means includes
Dividing each adjacent nozzle into different said blocks;
A droplet discharge device characterized by the above. A droplet discharge device according to any one of claims 5 to 8,
The storage means
Storing information for associating each of the plurality of nozzles with a rank corresponding to the discharge weight;
The output means includes
A drive waveform signal for calibrating the discharge weight to a predetermined weight is generated for each rank, and the drive waveform signal corresponding to the rank is generated for each of the drive nozzles based on the information stored in the storage unit. Output,
A droplet discharge device characterized by the above. An electro-optical device having a thin film formed by drying droplets discharged onto a substrate,
The thin film is
An electro-optical device formed by the droplet discharge device according to claim 5.

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