JP2008130913A - Semiconductor device and manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be manufactured efficiently while restricting variation in flowing current. <P>SOLUTION: A constant current diode A1 includes an anode 1 and cathode 2, an n-type semiconductor layer 3 having a drain region conducted to the anode 1, a source region conducted to the cathode 2, and a p-type semiconductor layer 4 having a gate region conducted to the cathode 2. The n-type semiconductor layer 3 has a front face connected with the cathode 2 and a rear face connected with the anode 1. In the p-type semiconductor layer 4, two or more wall portion pairs 41a made of wall portions in a pair, each extending from the front face to the rear face of the n-type semiconductor layer 3 are arranged in a direction perpendicular to the thickness direction of the n-type semiconductor layer 3, and a portion between the wall portion pairs 41a out of the front face side portion of the n-type semiconductor layer 3 is an n<SP>+</SP>-type semiconductor layer 32 as the source region. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device configured as a constant current diode capable of keeping the magnitude of a flowing current constant.

For example, a semiconductor device called a constant current diode is used as means for controlling the magnitude of the current supplied to the light emitting diode to a magnitude according to the specification of the light emitting diode. The structure of the constant current diode corresponds to a field effect transistor (FET) in which a source region and a gate region are short-circuited (see, for example, Patent Document 1). FIG. 6 shows a constant current diode X which is an example of a conventional constant current diode. The anode 91 is electrically connected to the n ⁺ type semiconductor layer 93a through the metal layer 97. The cathode 92 is connected to a p-type semiconductor layer 94a configured as a substrate. An n ⁻ type semiconductor layer 93c is epitaxially grown on the p type semiconductor layer 94a. The two isolation portions 94b are for separating the n ⁻ type semiconductor layer 93c. A p-type semiconductor layer 94c and n ⁺ -type semiconductor layers 93a and 93b are formed between the two isolation portions 94b. In the constant current diode X, the n ⁺ type semiconductor layer 93a functions as a drain region, the n ⁺ type semiconductor layer 93b functions as a source region, and the p type semiconductor layer 94c functions as a gate region. The n ⁺ type semiconductor layer 93 b and the p type semiconductor layer 94 c are electrically connected to each other by the metal layer 96. The insulating layer 95 is for preventing the metal layers 96 and 97 from conducting with an inappropriate portion. With such a configuration, the constant current diode X is configured to flow a constant current regardless of the voltage between the anode 91 and the cathode 92.

However, the magnitude of the current flowing through the constant current diode X is determined by the acceptor concentration of the p-type semiconductor layer 94a, the thickness of the n ⁻ -type semiconductor layer 93c, and the depth of the p-type semiconductor layer 94c. For this reason, there is an error in the concentration of the acceptor added when manufacturing the p-type semiconductor layer 94a as the substrate, the thickness for growing the n ⁻ -type semiconductor layer 93c is inaccurate, or the p-type semiconductor layer 94c. If the accuracy of the depth at which the acceptor is diffused is not sufficient to form the current, the magnitude of the current flowing through the constant current diode X tends to vary.

In order to manufacture the constant current diode X, the n ⁻ type semiconductor layer 93c is epitaxially grown, and then the acceptor is formed to form the isolation portion 94b, the p type semiconductor layer 94c, and the n ⁺ type semiconductor layers 93a and 93b. Alternatively, it is necessary to perform the donor diffusion process about three times. In each diffusion process, a mask that exposes a region in which the acceptor or donor is diffused is disposed, and the donor or acceptor is implanted. As described above, since it is necessary to repeatedly perform the diffusion treatment, the improvement in the manufacturing efficiency of the constant current diode X has been hindered.

Japanese Patent Laid-Open No. 58-21865

  The present invention has been conceived under the circumstances described above, and provides a semiconductor device and a method for manufacturing the same that can suppress the variation in the magnitude of the flowing current and can be efficiently manufactured. Is the subject.

  The semiconductor device provided by the first aspect of the present invention includes an anode and a cathode, an n-type semiconductor layer having a drain region conducting to the anode and a source region conducting to the cathode, and a gate region conducting to the cathode. A p-type semiconductor layer, wherein the cathode is connected to the surface of the n-type semiconductor layer, and the anode is connected to the back surface of the n-type semiconductor layer. A plurality of wall portion pairs each consisting of a pair of wall portions extending from the front surface to the back surface of the n-type semiconductor layer are arranged in a direction perpendicular to the thickness direction of the n-type semiconductor layer; In the surface side portion of the n-type semiconductor layer, a portion sandwiched between the plurality of wall portion pairs is the source region.

  According to such a configuration, the magnitude of the current flowing through the semiconductor device is determined by the width of the portion sandwiched between the pair of adjacent wall portions in the n-type semiconductor layer. The wall pair can be formed, for example, by providing a plurality of trenches by etching in the n-type semiconductor layer and then diffusing acceptors on the inner surfaces of these trenches. The interval between these trenches can be finished relatively accurately. Therefore, variation in the magnitude of the current flowing through the semiconductor device can be suppressed. In addition, when the semiconductor device is manufactured, the diffusion treatment using a mask is essential only when the p-type semiconductor layer is formed. Therefore, the manufacturing efficiency of the semiconductor device can be improved.

  In a preferred embodiment of the present invention, the p-type semiconductor layer is composed of a plurality of U-shaped portions, each of which is connected to a portion of the wall portion pair near the back surface of the n-type semiconductor layer. According to such a configuration, it is possible to prevent the portion that becomes the drain region of the n-type semiconductor layer and the cathode from being inappropriately conducted.

  In a preferred embodiment of the present invention, an insulating member is interposed between the pair of wall portions constituting the wall pair. According to such a configuration, it is more preferable to prevent the portion of the n-type semiconductor layer that becomes the drain region and the cathode from being inappropriately conducted.

  According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: etching a surface of an n-type semiconductor layer having a source region located on the front surface side and a drain region located on the back surface side; Forming a plurality of recesses that are open to the surface, and adding an acceptor from the inner surface of the recess, thereby forming a plurality of wall pairs each consisting of a pair of wall portions extending in the thickness direction of the n-type semiconductor layer. A step of forming a p-type semiconductor layer, a step of conducting an anode to a portion to be the drain region, a step of conducting a cathode to the portion to be the source region and the p-type semiconductor layer as a gate region, It is characterized by having.

  According to such a configuration, it is possible to accurately finish the width of the portion sandwiched between the plurality of wall portion pairs in the n-type semiconductor layer. Thereby, the magnitude of the current flowing to the semiconductor device can be set to a desired value. In the above manufacturing method, for example, the number of diffusion processes using a mask can be reduced, and the manufacturing efficiency can be improved.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

  FIG. 1 shows an example of a semiconductor device according to the present invention. The constant current diode A1 of the present embodiment includes an anode 1, a cathode 2, an n-type semiconductor layer 3, a p-type semiconductor layer 4, an insulating member 5, an insulating layer 6, and a metal layer 7. The anode 1 and the cathode 2 Regardless of the magnitude of the voltage between them, a constant current can be passed. The constant current diode A1 is finished so that the dimension in plan view is about 0.4 mm square.

The anode 1 is an electrode into which a current flows, and is called a so-called anode. The anode 1 is connected to an n ⁻ type semiconductor layer 31 which is a back side portion of the n type semiconductor layer 3.

  The cathode 2 is an electrode on the side from which current flows out from the constant current diode A1, and is called a so-called cathode. The cathode 2 is connected to the metal layer 7.

The n-type semiconductor layer 3 is made of, for example, a material in which P as a donor is added to Si, and includes an n ⁻ type semiconductor layer 31 and an n ⁺ type semiconductor layer 32. The n ⁻ -type semiconductor layer 31 is a base part for manufacturing the constant current diode A1, and is a substrate made of a material in which P is added to Si, for example. On the other hand, the constant current diode A1 may be manufactured by removing the substrate after epitaxially growing the n ⁻ type semiconductor layer 31 on another substrate (not shown). A portion of the n ⁻ type semiconductor layer 31 connected to the anode 1 functions as a drain region.

The n ⁺ type semiconductor layer 32 is a surface side portion of the n type semiconductor layer 3 and is made of a material having a higher concentration of P as a donor than the material of the n ⁻ type semiconductor layer 31. The n ⁺ type semiconductor layer 32 is electrically connected to the cathode 2 through the metal layer 7 and functions as a source region. The n ⁺ type semiconductor layer 32 is formed by adding P to the surface side portion of the n ⁻ type semiconductor layer 31. In the present embodiment, the n-type semiconductor layer 3 is obtained by grinding a substrate having a thickness of about 625 μm to a thickness of about 150 μm at the completion of the manufacture of the constant current diode A1.

The p-type semiconductor layer 4 is made of, for example, a material obtained by adding B as an acceptor to Si and functions as a gate region. The p-type semiconductor layer 4 is electrically connected to the cathode 2 through the metal layer 7 and is in contact with the n ⁺ -type semiconductor layer 32. As described above, the dedicated gate electrode is not connected to the p-type semiconductor layer 4 as the gate region and is electrically connected to the cathode 2, so that the constant current diode A 1 depends on the voltage between the anode 1 and the cathode 2. Therefore, it is possible to flow a constant current.

The p-type semiconductor layer 4 includes a plurality of U-shaped portions 41. The plurality of U-shaped portions 41 are arranged at a constant pitch in a direction perpendicular to the thickness direction of the n-type semiconductor layer 3 and sandwich the n ⁺ -type semiconductor layer 32. The U-shaped portion 41 has a U-shaped cross section, and enters from the front side of the n-type semiconductor layer 3 toward the back surface of the n-type semiconductor layer 3. The U-shaped part 41 has a wall part pair 41a. The wall portion pair 41 a is composed of a pair of wall portions extending in the thickness direction of the n-type semiconductor layer 3. Parts of the wall pair 41a that are in the direction of the back surface of the n-type semiconductor layer 3 are connected to each other. The inside of the U-shaped part 41 is filled with the insulating member 5. The insulating member 5 is made of, for example, SiO ₂ .

  In the present embodiment, the p-type semiconductor layer 4 has a dimension in the thickness direction of the n-type semiconductor layer 3 of about 5 μm. Further, the wall portion pair 41a includes a wall portion having a thickness of about 1 μm and a pair of wall portions having a distance of about 0.5 to 2.0 μm. The interval between adjacent U-shaped portions 41 is about 2 to 3 μm.

The insulating layer 6 is made of, for example, SiO ₂ and exposes part of the n-type semiconductor layer 3 and the p-type semiconductor layer 4.

  The metal layer 7 is made of, for example, Al and is in contact with a portion of the n-type semiconductor layer 3 and the p-type semiconductor layer 4 exposed from the insulating layer 6. The metal layer 7, the n-type semiconductor layer 3 and the p-type semiconductor layer 4 are in ohmic contact with each other.

  Next, an example of a method for manufacturing the constant current diode A1 will be described below.

First, as shown in FIG. 2, a substrate to be the n ⁻ type semiconductor layer 31 is prepared. By adding P as a donor to the surface side portion of the substrate, the n ⁺ type semiconductor layer 32 is formed. Next, a plurality of elongated trenches 3a are formed in the n-type semiconductor layer 3 by using, for example, etching. These trenches 3 a have a shape and a size that penetrate the n ⁺ type semiconductor layer 32 and have their tips reaching the n ⁻ type semiconductor layer 31.

Next, B, which is an acceptor, is diffused into the n-type semiconductor layer 3 from the inner surface of the trench 3a using a mask. Thereby, as shown in FIG. 3, the p-type semiconductor layer 4 which consists of the several U-shaped part 41 is obtained. Thereafter, the insulating member 5 is formed by filling the inside of the trench 3a with SiO ₂ . Further, the insulating layer 6 and the metal layer 7 are formed using, for example, a sputtering method. Then, the constant current diode A1 is completed by connecting the anode 1 and the cathode 2.

  Next, the operation of the constant current diode A1 will be described.

According to the present embodiment, the magnitude of the current flowing through the constant current diode A1 is determined by the width of the portion sandwiched between adjacent U-shaped portions 41 in the n ⁻ -type semiconductor layer 31. The interval between adjacent U-shaped portions 41 is obtained by removing the thickness of the wall portion pair 41a from the pitch of the plurality of trenches 3a. These trenches 3a can be formed at an accurate pitch by etching. Further, it is easier to control the thickness of the wall pair 41a compared to, for example, controlling the diffusion depth of the p-type semiconductor layer 94c shown in FIG. Therefore, it is suitable for setting the magnitude of the current flowing through the constant current diode A1 to a desired value.

If the p-type semiconductor layer 4 is composed of a plurality of U-shaped portions 41, the surface of the n ⁻ -type semiconductor layer 31 is completely covered by the p-type semiconductor layer 4 and the n ⁺ -type semiconductor layer 32. . Thereby, it is possible to prevent the metal layer 7 and the n ⁻ type semiconductor layer 31 from conducting inappropriately. Furthermore, filling the inside of the U-shaped portion 41 with the insulating member 5 is suitable for preventing conduction between the metal layer 7 and the n ⁻ -type semiconductor layer 31.

  In the manufacturing process of the constant current diode A1, each of the donor and acceptor diffusion processes may be performed once. In addition, it is essential to use a mask in the diffusion process only when the p-type semiconductor layer 4 is formed. Therefore, compared with the case where the constant current diode X shown in FIG. 4 is manufactured, for example, the number of diffusion processes using a mask can be reduced, and the manufacturing efficiency can be improved.

  4 and 5 show another embodiment of the present invention. In these drawings, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those in the above embodiment.

  FIG. 4 shows a second embodiment of the semiconductor device according to the present invention. The constant current diode A2 of the present embodiment is different from the above-described embodiment in that a conducting member 71 is provided. The conducting member 71 is made of, for example, Al and fills the inside of the U-shaped portion 41. According to such a configuration, it is possible to achieve conduction between the p-type semiconductor layer 4 and the cathode 2 using not only both end surfaces of the U-shaped portion 41 but also the inner surfaces thereof.

FIG. 5 shows a third embodiment of the semiconductor device according to the present invention. In the constant current diode A3 of the present embodiment, the p-type semiconductor layer 4 is configured only by the plurality of wall portion pairs 41a, and the U-shaped portion 41 is not formed. A space between the pair of wall portions constituting the wall portion pair 41 a is filled with the insulating member 5. Even with such a configuration, the magnitude of the current flowing through the constant current diode A3 can be set to a desired value, and the manufacturing efficiency can be improved. If the insulating member 5 is provided, there is no possibility that the n ⁻ type semiconductor layer 31 and the metal layer 7 are unduly conducted.

  The semiconductor device according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present invention can be modified in various ways.

  The concave portion referred to in the present invention is not limited to the groove-shaped trench, and may be, for example, an opening having a circular cross section.

It is principal part sectional drawing which shows 1st Embodiment of the semiconductor device which concerns on this invention. FIG. 7 is a cross-sectional view of the principal part showing the step of forming a trench in the example of the method for manufacturing the semiconductor device shown in FIG. 1. FIG. 6 is a cross-sectional view of a principal part showing a step of diffusing acceptors in the example of the method for manufacturing the semiconductor device shown in FIG. It is principal part sectional drawing which shows 2nd Embodiment of the semiconductor device which concerns on this invention. It is principal part sectional drawing which shows 3rd Embodiment of the semiconductor device which concerns on this invention. It is principal part sectional drawing which shows an example of the conventional semiconductor device.

Explanation of symbols

A1, A2, A3 Semiconductor device 1 Anode 2 Cathode 3 N-type semiconductor layer 3a Trench (recess)
4 p-type semiconductor layer (gate region)
5 Insulating member 6 Insulating layer 7 Metal layer 31 n ⁻ type semiconductor layer (drain region)
32 n ⁺ type semiconductor layer (source region)
41 U-shaped part 41a Wall part pair

Claims (4)

An anode and a cathode;
An n-type semiconductor layer having a drain region conducting to the anode and a source region conducting to the cathode;
A p-type semiconductor layer having a gate region conducting to the cathode;
A semiconductor device comprising:
The n-type semiconductor layer has the cathode connected to the front surface and the anode connected to the back surface,
The p-type semiconductor layer has a direction in which a plurality of wall portion pairs each formed of a pair of wall portions extending from the front surface to the back surface of the n-type semiconductor layer are perpendicular to the thickness direction of the n-type semiconductor layer. It is configured as arranged in
Of the surface-side portion of the n-type semiconductor layer, a portion sandwiched between the plurality of wall portion pairs is used as the source region.   2. The semiconductor device according to claim 1, wherein each of the p-type semiconductor layers includes a plurality of U-shaped portions in which the portions of the wall portion pair near the back surface of the n-type semiconductor layer are connected to each other.   The semiconductor device according to claim 1, wherein an insulating member is interposed between the pair of wall portions constituting the wall portion pair. Forming a plurality of recesses opened in the surface by etching for an n-type semiconductor layer having a source region located on the front surface side and a drain region located on the back surface side;
Adding an acceptor from the inner surface of the recess to form a p-type semiconductor layer having a plurality of wall pairs each consisting of a pair of wall portions extending in the thickness direction of the n-type semiconductor layer;
Making the anode conductive to the portion to be the drain region;
Conducting a cathode to the portion to be the source region and the p-type semiconductor layer as a gate region;
A method for manufacturing a semiconductor device, comprising:

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