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JP2008187050A - System in-package device - Google Patents

System in-package device Download PDF

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Publication number
JP2008187050A
JP2008187050A JP2007020013A JP2007020013A JP2008187050A JP 2008187050 A JP2008187050 A JP 2008187050A JP 2007020013 A JP2007020013 A JP 2007020013A JP 2007020013 A JP2007020013 A JP 2007020013A JP 2008187050 A JP2008187050 A JP 2008187050A
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chip
chips
package
lsi
disposed
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Yukihiro Urakawa
幸宏 浦川
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Toshiba Corp
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Toshiba Corp
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Priority to JP2007020013A priority Critical patent/JP2008187050A/en
Priority to US12/020,190 priority patent/US8237289B2/en
Publication of JP2008187050A publication Critical patent/JP2008187050A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SIP capable of coping with an increase in the number of terminals of a chip. <P>SOLUTION: A system in-package device has: a package substrate 11; an external terminal 12 arranged at one surface side of the package substrate 11; first and second chips 13, 14 arranged side by side at the other surface side of the package substrate 11; a third chip 15 that is arranged over the first and second chips 13, 14 and covers the surface of the first and second chips 13, 14 partially; and a bump 16 arranged between the first and second chips 13, 14, and the third chip 15. The first and second chips 13, 14 exchange a signal via the third chip 15. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、システムインパッケージ装置に関する。   The present invention relates to a system-in-package apparatus.

近年、システムの高性能と低コストとの両立を図るため、１つのパッケージ内にシステムを形成するＳＩＰ(system in package)が開発されている（例えば、特許文献１を参照）。   In recent years, SIP (system in package) that forms a system in one package has been developed in order to achieve both high performance and low cost of the system (see, for example, Patent Document 1).

ＳＩＰの場合、１つのパッケージ内に複数のチップが形成されるため、これら複数のチップを接続するための配線技術が重要になる。   In the case of SIP, since a plurality of chips are formed in one package, a wiring technique for connecting the plurality of chips is important.

ＳＩＰには、複数のチップを並列に配置し、これらのチップをボンディングワイヤにより接続する並列タイプと、複数のチップを積み重ね、これらのチップをバンプにより接続する積み重ねタイプとがある。   In SIP, there are a parallel type in which a plurality of chips are arranged in parallel and these chips are connected by bonding wires, and a stacked type in which a plurality of chips are stacked and these chips are connected by bumps.

並列タイプの場合、システムの高性能化に伴ってチップの端子数が増加すると、パッケージ内で複数のチップを互いに接続できなくなる欠点がある。   In the case of the parallel type, when the number of terminals of a chip increases with the improvement in system performance, there is a disadvantage that a plurality of chips cannot be connected to each other in the package.

これに対し、積み重ねタイプの場合、直径が１００μｍ以下のマイクロバンプを使用することにより、チップの端子数が増加しても、複数のチップの接続を十分に確保できる。   On the other hand, in the case of the stacking type, the use of micro bumps having a diameter of 100 μm or less can sufficiently secure the connection of a plurality of chips even when the number of chip terminals is increased.

しかし、積み重ねタイプでは、その構造上、パッケージにヒートスプレッダーを付加することが難しい。
特開２００１−２４１５０号公報 However, in the stacked type, it is difficult to add a heat spreader to the package due to its structure.
JP 2001-24150 A

本発明は、並列タイプシステムインパッケージ装置において、チップの端子数の増加に対応可能な構造、及び、放熱性に優れた構造を提案する。   The present invention proposes a structure capable of dealing with an increase in the number of terminals of a chip and a structure excellent in heat dissipation in a parallel type system-in-package apparatus.

本発明の例に係るシステムインパッケージ装置は、パッケージ基板と、パッケージ基板の一面側に配置される外部端子と、パッケージ基板の他面側に並んで配置される第１及び第２チップと、第１及び第２チップ上に跨って配置され、第１及び第２チップの表面の一部のみを覆う第３チップと、第１及び第２チップと第３チップとの間に配置されるバンプとを備え、第１及び第２チップは、第３チップを介して信号のやりとりを行う。   A system-in-package apparatus according to an example of the present invention includes a package substrate, an external terminal disposed on one surface side of the package substrate, first and second chips disposed side by side on the other surface side of the package substrate, A third chip disposed over the first and second chips and covering only part of the surfaces of the first and second chips; and a bump disposed between the first and second chips and the third chip; The first and second chips exchange signals via the third chip.

本発明の例に係るシステムインパッケージ装置は、ヒートスプレッダーと、ヒートスプレッダーの一面側の縁に沿って配置されるパッケージ基板と、パッケージ基板上に配置される外部端子と、ヒートスプレッダーの一面側の中央に並んで配置される第１及び第２チップと、第１及び第２チップ上に跨って配置され、第１及び第２チップの表面の一部のみを覆う第３チップと、第１及び第２チップと第３チップとの間に配置されるバンプとを備え、第１及び第２チップは、第３チップを介して信号のやりとりを行う。   A system-in-package apparatus according to an example of the present invention includes a heat spreader, a package substrate disposed along an edge on one surface side of the heat spreader, an external terminal disposed on the package substrate, and one surface side of the heat spreader. A first chip and a second chip arranged side by side in the center; a third chip disposed over the first and second chips and covering only a part of the surface of the first and second chips; Bumps arranged between the second chip and the third chip are provided, and the first and second chips exchange signals via the third chip.

本発明によれば、並列タイプシステムインパッケージ装置において、チップの端子数の増加に対応可能な構造、及び、放熱性に優れた構造を実現できる。   According to the present invention, in a parallel type system-in-package apparatus, it is possible to realize a structure that can cope with an increase in the number of terminals of a chip and a structure that has excellent heat dissipation.

以下、図面を参照しながら、本発明の例を実施するための最良の形態について詳細に説明する。   The best mode for carrying out an example of the present invention will be described below in detail with reference to the drawings.

１． 概要
本発明は、並列に配置された２つのチップ（第１及び第２チップ）を配線チップ（第３チップ）により互いに接続する、という構造を提案する。 1. Overview
The present invention proposes a structure in which two chips (first and second chips) arranged in parallel are connected to each other by a wiring chip (third chip).

具体的には、配線チップは、２つのチップ上に跨がり、かつ、２つのチップの表面の一部のみを覆って配置される。また、２つのチップと配線チップとは、バンプにより互いに接続される。   Specifically, the wiring chip is arranged so as to straddle the two chips and cover only a part of the surface of the two chips. The two chips and the wiring chip are connected to each other by bumps.

これにより、システムの高性能化に伴ってチップの端子数が増加しても、パッケージ内で２つのチップの接続を確保できる。また、配線チップは、２つのチップの表面を完全に覆うことがないため、２つのチップとパッケージの外部端子との接続も確保できる。   As a result, even if the number of terminals of the chip increases as the performance of the system increases, the connection between the two chips can be secured in the package. Further, since the wiring chip does not completely cover the surfaces of the two chips, the connection between the two chips and the external terminals of the package can be ensured.

また、ヒートスプレッダーの一面側の縁に沿ってパッケージ基板を配置し、かつ、ヒートスプレッダーの中央に並んで２つのチップを配置する構造を採用すれば、放熱性の向上にも貢献できる。   Further, if a structure in which the package substrate is arranged along the edge on the one surface side of the heat spreader and two chips are arranged in the center of the heat spreader is adopted, it is possible to contribute to improvement of heat dissipation.

ここで、チップの表面とは、素子又は導電層が形成される面のことをいい、チップの裏面とは、素子及び導電層のいずれも形成されない面のことをいうものとする。   Here, the surface of the chip refers to a surface on which an element or a conductive layer is formed, and the back surface of the chip refers to a surface on which neither an element nor a conductive layer is formed.

２． 実施の形態
次に、最良と思われるいくつかの実施の形態について説明する。 2. Embodiment
Next, some preferred embodiments will be described.

(1) 第１実施の形態
A. 構造
図１は、第１実施の形態に係るシステムインパッケージ装置を示している。図２は、図１のＩＩ−ＩＩ線に沿う断面図である。 (1) First embodiment
A. Structure
FIG. 1 shows a system-in-package apparatus according to the first embodiment. 2 is a cross-sectional view taken along line II-II in FIG.

パッケージ基板１１の一面側には、アレイ状の複数の外部端子１２が配置される。本例では、複数の外部端子１２をバンプとしているが、これに限られず、例えば、ピン、パッドなどであってもよい。   On the one surface side of the package substrate 11, a plurality of external terminals 12 in an array shape are arranged. In this example, the plurality of external terminals 12 are bumps. However, the present invention is not limited to this, and for example, pins and pads may be used.

パッケージ基板１１の他面側には、互いに並んで配置される２つのＬＳＩチップ１３，１４が配置される。ＬＳＩチップ１３は、例えば、ロジックチップ、ＬＳＩチップ１４は、例えば、メモリチップである。ＬＳＩチップ１３，１４の裏面は、接着剤によりパッケージ基板１１の他面に結合される。   On the other surface side of the package substrate 11, two LSI chips 13 and 14 arranged side by side are arranged. The LSI chip 13 is, for example, a logic chip, and the LSI chip 14 is, for example, a memory chip. The back surfaces of the LSI chips 13 and 14 are bonded to the other surface of the package substrate 11 with an adhesive.

ＬＳＩチップ１３，１４上には、これらＬＳＩチップ１３，１４を跨いで配線チップ１５が配置される。配線チップ１５は、ＬＳＩチップ１３，１４を接続する導電層を有する。   On the LSI chips 13 and 14, a wiring chip 15 is disposed across the LSI chips 13 and 14. The wiring chip 15 has a conductive layer that connects the LSI chips 13 and 14.

これにより、ＬＳＩチップ１３，１４は、配線チップ１５を介して信号のやりとりを行う。ここで、配線チップ１５は、例えば、ＬＳＩチップ１３，１４を接続する導電層のみを有している。   As a result, the LSI chips 13 and 14 exchange signals via the wiring chip 15. Here, the wiring chip 15 has, for example, only a conductive layer that connects the LSI chips 13 and 14.

また、配線チップ１５は、ＬＳＩチップ１３，１４の表面の一部のみを覆う。この構造を実現するには、例えば、配線チップ１５の表面の面積を、ＬＳＩチップ１３，１４の表面の合計の面積よりも小さくすればよい。   The wiring chip 15 covers only a part of the surface of the LSI chips 13 and 14. In order to realize this structure, for example, the surface area of the wiring chip 15 may be made smaller than the total area of the surfaces of the LSI chips 13 and 14.

これにより、ＬＳＩチップ１３，１４とパッケージの外部端子１２との接続が確保される。即ち、ＬＳＩチップ１３，１４は、ボンディングワイヤ１７、導電層１８及び導電線１９を介して、複数の外部端子１２に接続される。   Thereby, the connection between the LSI chips 13 and 14 and the external terminals 12 of the package is ensured. That is, the LSI chips 13 and 14 are connected to the plurality of external terminals 12 through the bonding wires 17, the conductive layers 18, and the conductive lines 19.

ＬＳＩチップ１３，１４と配線チップ１５との間には、アレイ状の複数のバンプ（例えば、直径が１００μｍ以下のマイクロバンプ）１６が配置される。   Between the LSI chips 13 and 14 and the wiring chip 15, a plurality of arrayed bumps (for example, micro bumps having a diameter of 100 μm or less) 16 are arranged.

配線チップ１５は、ＬＳＩチップ１３，１４に対してフリップチップボンディングされるため、ＬＳＩチップ１３，１４の表面と配線チップ１５の表面とは互いに対向する形となる。   Since the wiring chip 15 is flip-chip bonded to the LSI chips 13 and 14, the surfaces of the LSI chips 13 and 14 and the surface of the wiring chip 15 are opposed to each other.

これにより、システムの高性能化に伴ってチップの端子数が増加しても、パッケージ内でＬＳＩチップ１３，１４の接続を確保できる。   Thereby, even if the number of terminals of the chip increases with the improvement of the system performance, the connection of the LSI chips 13 and 14 can be secured in the package.

B. 変形例
図３は、第１実施の形態の変形例に係るシステムインパッケージ装置を示している。図３のシステムインパッケージ装置の平面図は、図１と同じであるため、ここでは、省略する。 B. Modifications
FIG. 3 shows a system-in-package apparatus according to a modification of the first embodiment. The plan view of the system in package apparatus of FIG. 3 is the same as FIG.

この変形例の特徴は、図１及び図２の配線チップ１５に代えて、バス及びバスコントローラを有するＬＳＩチップ（バスブリッジ）２１を使用した点にある。その他については、図１及び図２と同じである。   The feature of this modification is that an LSI chip (bus bridge) 21 having a bus and a bus controller is used instead of the wiring chip 15 of FIGS. About others, it is the same as FIG.1 and FIG.2.

ＬＳＩチップ２１は、ＬＳＩチップ１３，１４上に、これらを跨いで配置される。ＬＳＩチップ２１は、ＬＳＩチップ１３，１４を接続するバスと、ＬＳＩチップ１３，１４の接続を制御するバスコントローラとを有する。   The LSI chip 21 is arranged on the LSI chips 13 and 14 so as to straddle them. The LSI chip 21 includes a bus that connects the LSI chips 13 and 14 and a bus controller that controls connection of the LSI chips 13 and 14.

また、ＬＳＩチップ２１は、ＬＳＩチップ１３，１４の表面の一部のみを覆う。この構造を実現するには、例えば、ＬＳＩチップ２１の表面の面積を、ＬＳＩチップ１３，１４の表面の合計の面積よりも小さくすればよい。   The LSI chip 21 covers only a part of the surface of the LSI chips 13 and 14. In order to realize this structure, for example, the surface area of the LSI chip 21 may be made smaller than the total area of the surfaces of the LSI chips 13 and 14.

C. まとめ
第１実施の形態によれば、並列タイプシステムインパッケージ装置において、チップの端子数の増加に対応可能な構造を実現できる。 C. Summary
According to the first embodiment, in the parallel type system-in-package apparatus, it is possible to realize a structure that can cope with an increase in the number of terminals of a chip.

(2) 第２実施の形態
A. 構造
図４は、第２実施の形態に係るシステムインパッケージ装置を示している。図５は、図４のＶ−Ｖ線に沿う断面図である。 (2) Second embodiment
A. Structure
FIG. 4 shows a system-in-package apparatus according to the second embodiment. FIG. 5 is a cross-sectional view taken along line VV in FIG.

パッケージ基板２０Ａ，２０Ｂは、ヒートスプレッダー３１の一面側の縁に沿って配置される。パッケージ基板２０Ｂ上には、アレイ状の複数の外部端子１２が配置される。本例では、複数の外部端子１２をバンプとしているが、これに限られず、例えば、ピン、パッドなどであってもよい。   The package substrates 20 </ b> A and 20 </ b> B are arranged along the edge on one surface side of the heat spreader 31. On the package substrate 20B, a plurality of external terminals 12 in an array are arranged. In this example, the plurality of external terminals 12 are bumps. However, the present invention is not limited to this, and for example, pins and pads may be used.

パッケージ基板２０Ｂのサイズは、パッケージ基板２０Ａのサイズよりも小さくなっており、ヒートスプレッダー３１の上部からみて、パッケージ基板２０Ａの一部が露出している。この部分は、ボンディング部となる。   The size of the package substrate 20B is smaller than the size of the package substrate 20A, and a part of the package substrate 20A is exposed when viewed from the top of the heat spreader 31. This part becomes a bonding part.

ボンディング部には、導電層１８が配置され、導電層１８は、導電線１９を介して外部端子１２に接続される。   A conductive layer 18 is disposed in the bonding portion, and the conductive layer 18 is connected to the external terminal 12 via a conductive wire 19.

ＬＳＩチップ１３，１４は、ヒートスプレッダー３１の一面側の中央に並んで配置される。ＬＳＩチップ１３は、例えば、ロジックチップ、ＬＳＩチップ１４は、例えば、メモリチップである。ＬＳＩチップ１３，１４の裏面は、接着剤によりパッケージ基板１１の他面に結合される。   The LSI chips 13 and 14 are arranged side by side at the center of one surface side of the heat spreader 31. The LSI chip 13 is, for example, a logic chip, and the LSI chip 14 is, for example, a memory chip. The back surfaces of the LSI chips 13 and 14 are bonded to the other surface of the package substrate 11 with an adhesive.

ＬＳＩチップ１３，１４上には、これらＬＳＩチップ１３，１４を跨いで配線チップ１５が配置される。配線チップ１５は、ＬＳＩチップ１３，１４を接続する導電層を有する。   On the LSI chips 13 and 14, a wiring chip 15 is disposed across the LSI chips 13 and 14. The wiring chip 15 has a conductive layer that connects the LSI chips 13 and 14.

これにより、ＬＳＩチップ１３，１４は、配線チップ１５を介して信号のやりとりを行う。ここで、配線チップ１５は、例えば、ＬＳＩチップ１３，１４を接続する導電層のみを有している。   As a result, the LSI chips 13 and 14 exchange signals via the wiring chip 15. Here, the wiring chip 15 has, for example, only a conductive layer that connects the LSI chips 13 and 14.

また、配線チップ１５は、ＬＳＩチップ１３，１４の表面の一部のみを覆う。この構造を実現するには、例えば、配線チップ１５の表面の面積を、ＬＳＩチップ１３，１４の表面の合計の面積よりも小さくすればよい。   The wiring chip 15 covers only a part of the surface of the LSI chips 13 and 14. In order to realize this structure, for example, the surface area of the wiring chip 15 may be made smaller than the total area of the surfaces of the LSI chips 13 and 14.

これにより、ＬＳＩチップ１３，１４とパッケージの外部端子１２との接続が確保される。即ち、ＬＳＩチップ１３，１４は、ボンディングワイヤ１７、導電層１８及び導電線１９を介して、複数の外部端子１２に接続される。   Thereby, the connection between the LSI chips 13 and 14 and the external terminals 12 of the package is ensured. That is, the LSI chips 13 and 14 are connected to the plurality of external terminals 12 through the bonding wires 17, the conductive layers 18, and the conductive lines 19.

ＬＳＩチップ１３，１４と配線チップ１５との間には、アレイ状の複数のバンプ（例えば、直径が１００μｍ以下のマイクロバンプ）１６が配置される。   Between the LSI chips 13 and 14 and the wiring chip 15, a plurality of arrayed bumps (for example, micro bumps having a diameter of 100 μm or less) 16 are arranged.

配線チップ１５は、ＬＳＩチップ１３，１４に対してフリップチップボンディングされるため、ＬＳＩチップ１３，１４の表面と配線チップ１５の表面とは互いに対向する形となる。   Since the wiring chip 15 is flip-chip bonded to the LSI chips 13 and 14, the surfaces of the LSI chips 13 and 14 and the surface of the wiring chip 15 are opposed to each other.

これにより、システムの高性能化に伴ってチップの端子数が増加しても、パッケージ内でＬＳＩチップ１３，１４の接続を確保できる。   Thereby, even if the number of terminals of the chip increases with the improvement of the system performance, the connection of the LSI chips 13 and 14 can be secured in the package.

しかも、ＬＳＩチップ１３，１４にヒートスプレッダー３１を直接接触させることができるため、放熱性の向上に貢献できる。   In addition, since the heat spreader 31 can be brought into direct contact with the LSI chips 13 and 14, it is possible to contribute to improvement in heat dissipation.

B. 変形例
図６は、第２実施の形態の変形例に係るシステムインパッケージ装置を示している。図６のシステムインパッケージ装置の平面図は、図４と同じであるため、ここでは、省略する。 B. Modifications
FIG. 6 shows a system in package apparatus according to a modification of the second embodiment. The plan view of the system in package apparatus of FIG. 6 is the same as FIG.

この変形例の特徴は、図４及び図５の配線チップ１５に代えて、バス及びバスコントローラを有するＬＳＩチップ（バスブリッジ）２１を使用した点にある。その他については、図４及び図５と同じである。   The feature of this modification is that an LSI chip (bus bridge) 21 having a bus and a bus controller is used instead of the wiring chip 15 of FIGS. About others, it is the same as FIG.4 and FIG.5.

ＬＳＩチップ２１は、ＬＳＩチップ１３，１４上に、これらを跨いで配置される。ＬＳＩチップ２１は、ＬＳＩチップ１３，１４を接続するバスと、ＬＳＩチップ１３，１４の接続を制御するバスコントローラとを有する。   The LSI chip 21 is arranged on the LSI chips 13 and 14 so as to straddle them. The LSI chip 21 includes a bus that connects the LSI chips 13 and 14 and a bus controller that controls connection of the LSI chips 13 and 14.

また、ＬＳＩチップ２１は、ＬＳＩチップ１３，１４の表面の一部のみを覆う。この構造を実現するには、例えば、ＬＳＩチップ２１の表面の面積を、ＬＳＩチップ１３，１４の表面の合計の面積よりも小さくすればよい。   The LSI chip 21 covers only a part of the surface of the LSI chips 13 and 14. In order to realize this structure, for example, the surface area of the LSI chip 21 may be made smaller than the total area of the surfaces of the LSI chips 13 and 14.

C. まとめ
第２実施の形態によれば、並列タイプシステムインパッケージ装置において、チップの端子数の増加に対応可能な構造、及び、放熱性に優れた構造を同時に実現できる。 C. Summary
According to the second embodiment, in the parallel type system-in-package apparatus, a structure capable of dealing with an increase in the number of terminals of the chip and a structure excellent in heat dissipation can be realized at the same time.

３． 適用例
本発明の例は、メモリシステムに適用できる。 3. Application examples
The example of the present invention can be applied to a memory system.

例えば、図１乃至図６におけるＬＳＩチップ１３をロジックチップとし、ＬＳＩチップ１４をメモリチップとすれば、本発明の例に係るシステムインパッケージ装置を搭載したＰＤＡ(personal digital assistance)などの電子機器を製作できる。この場合、パッケージ内にマイコンチップを搭載してもよい。   For example, if the LSI chip 13 in FIG. 1 to FIG. 6 is a logic chip and the LSI chip 14 is a memory chip, an electronic device such as a PDA (personal digital assistance) equipped with a system-in-package apparatus according to an example of the present invention is provided. Can be produced. In this case, a microcomputer chip may be mounted in the package.

また、本発明の例は、ロジックシステムに適用できる。   The example of the present invention can be applied to a logic system.

例えば、図１乃至図６における配線チップ１５又はＬＳＩチップ２１内に、インターフェイス回路を形成する。この場合、ＬＳＩチップ１３，１４に対する信号の入出力は、配線チップ１５内又はＬＳＩチップ２１内のインターフェイス回路を介して行う。   For example, an interface circuit is formed in the wiring chip 15 or the LSI chip 21 in FIGS. In this case, input / output of signals to / from the LSI chips 13 and 14 is performed via the interface circuit in the wiring chip 15 or the LSI chip 21.

例えば、図７及び図８に示す構造の場合には、ＬＳＩチップ（ロジックチップ）１３は、配線チップ１５内のインターフェイス回路、ＬＳＩチップ１４内の導電線２２、ボンディングワイヤ１７、導電層１８及び導電線１９を介して、複数の外部端子１２のうちの１つに接続される。   For example, in the case of the structure shown in FIGS. 7 and 8, the LSI chip (logic chip) 13 includes an interface circuit in the wiring chip 15, a conductive wire 22 in the LSI chip 14, a bonding wire 17, a conductive layer 18, and a conductive layer. It is connected to one of the plurality of external terminals 12 through a line 19.

また、図９及び図１０に示す構造の場合には、ＬＳＩチップ（ロジックチップ）１３は、配線チップ１５内のインターフェイス回路、配線チップ１５内のスルーホール２１、配線チップ１５の裏面の導電層２２、ボンディングワイヤ１７、導電層１８及び導電線１９を介して、複数の外部端子１２のうちの１つに接続される。   9 and 10, the LSI chip (logic chip) 13 includes an interface circuit in the wiring chip 15, a through hole 21 in the wiring chip 15, and a conductive layer 22 on the back surface of the wiring chip 15. , The bonding wire 17, the conductive layer 18, and the conductive wire 19 are connected to one of the plurality of external terminals 12.

４． むすび
本発明によれば、並列タイプシステムインパッケージ装置において、チップの端子数の増加に対応可能な構造、及び、放熱性に優れた構造を実現できる。 4). Conclusion
According to the present invention, in a parallel type system-in-package apparatus, it is possible to realize a structure that can cope with an increase in the number of terminals of a chip and a structure that has excellent heat dissipation.

本発明の例は、上述の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で、各構成要素を変形して具体化できる。また、上述の実施の形態に開示されている複数の構成要素の適宜な組み合せにより種々の発明を構成できる。例えば、上述の実施の形態に開示される全構成要素から幾つかの構成要素を削除してもよいし、異なる実施の形態の構成要素を適宜組み合わせてもよい。   The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

第１実施の形態に係るＳＩＰを示す平面図。The top view which shows SIP which concerns on 1st Embodiment. 図１のＩＩ−ＩＩ線に沿う断面図。Sectional drawing which follows the II-II line | wire of FIG. 第１実施の形態の変形例に係るＳＩＰを示す平面図。The top view which shows SIP which concerns on the modification of 1st Embodiment. 第２実施の形態に係るＳＩＰを示す平面図。The top view which shows SIP which concerns on 2nd Embodiment. 図４のＶ−Ｖ線に沿う断面図。Sectional drawing which follows the VV line | wire of FIG. 第２実施の形態の変形例に係るＳＩＰを示す平面図。The top view which shows SIP which concerns on the modification of 2nd Embodiment. 適用例としてのＳＩＰを示す断面図。Sectional drawing which shows SIP as an application example. 適用例としてのＳＩＰを示す断面図。Sectional drawing which shows SIP as an application example. 適用例としてのＳＩＰを示す断面図。Sectional drawing which shows SIP as an application example. 適用例としてのＳＩＰを示す断面図。Sectional drawing which shows SIP as an application example.

符号の説明Explanation of symbols

１１，２０Ａ，２０Ｂ： パッケージ基板、 １２： 外部端子、 １３，１４： ＬＳＩチップ、 １５： 配線チップ、 １６： バンプ、 １７： ボンディングワイヤ、 １８，２２： 導電層、 １９： 導電線、 ２１： スルーホール、 ３１： ヒートスプレッダー。   11, 20A, 20B: Package substrate, 12: External terminal, 13, 14: LSI chip, 15: Wiring chip, 16: Bump, 17: Bonding wire, 18, 22: Conductive layer, 19: Conductive line, 21: Through Hall, 31: Heat spreader.

Claims (5)

パッケージ基板と、前記パッケージ基板の一面側に配置される外部端子と、前記パッケージ基板の他面側に並んで配置される第１及び第２チップと、前記第１及び第２チップ上に跨って配置され、前記第１及び第２チップの表面の一部のみを覆う第３チップと、前記第１及び第２チップと前記第３チップとの間に配置されるバンプとを具備し、前記第１及び第２チップは、前記第３チップを介して信号のやりとりを行うことを特徴とするシステムインパッケージ装置。   A package substrate, an external terminal disposed on one surface side of the package substrate, first and second chips disposed side by side on the other surface side of the package substrate, and straddling the first and second chips A third chip that is disposed and covers only a part of the surface of the first and second chips; and a bump that is disposed between the first and second chips and the third chip. The system-in-package apparatus characterized in that the first and second chips exchange signals via the third chip. ヒートスプレッダーと、前記ヒートスプレッダーの一面側の縁に沿って配置されるパッケージ基板と、前記パッケージ基板上に配置される外部端子と、前記ヒートスプレッダーの一面側の中央に並んで配置される第１及び第２チップと、前記第１及び第２チップ上に跨って配置され、前記第１及び第２チップの表面の一部のみを覆う第３チップと、前記第１及び第２チップと前記第３チップとの間に配置されるバンプとを具備し、前記第１及び第２チップは、前記第３チップを介して信号のやりとりを行うことを特徴とするシステムインパッケージ装置。   A heat spreader, a package substrate disposed along an edge on one surface of the heat spreader, an external terminal disposed on the package substrate, and a first disposed in line in the center of the one surface of the heat spreader. And a second chip, a third chip that is disposed over the first and second chips and covers only a part of the surface of the first and second chips, the first and second chips, and the second chip A system-in-package apparatus comprising a bump disposed between three chips, wherein the first and second chips exchange signals via the third chip. 前記第３チップの表面の面積は、前記第１及び第２チップの表面の合計の面積よりも小さいことを特徴とする請求項１又は２に記載のシステムインパッケージ装置。   3. The system in package device according to claim 1, wherein an area of a surface of the third chip is smaller than a total area of the surfaces of the first and second chips. 前記第３チップは、導電層のみを有する配線チップであることを特徴とする請求項１乃至３のいずれか１項に記載のシステムインパッケージ装置。   4. The system-in-package apparatus according to claim 1, wherein the third chip is a wiring chip having only a conductive layer. 5. 前記第１チップは、ロジックチップであり、前記第２チップは、メモリチップであり、前記第３チップは、前記ロジックチップと前記メモリチップとを接続するバスと、前記ロジックチップと前記メモリチップとの接続を制御するバスコントローラとを有することを特徴とする請求項１乃至４のいずれか１項に記載のシステムインパッケージ装置。   The first chip is a logic chip, the second chip is a memory chip, the third chip is a bus connecting the logic chip and the memory chip, the logic chip and the memory chip, 5. The system-in-package apparatus according to claim 1, further comprising: a bus controller that controls connection of the system.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012529770A (en) * 2009-06-24 2012-11-22 インテル・コーポレーション Multi-chip package and method for providing multi-chip package die-to-die interconnects
JP2014078760A (en) * 2014-02-03 2014-05-01 Fujitsu Ltd Multichip module
JP2016018876A (en) * 2014-07-08 2016-02-01 日本電気株式会社 Electronic device or method of manufacturing the same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62232133A (en) * 1986-04-01 1987-10-12 Seiko Epson Corp Semiconductor packaging structure
JP2000223651A (en) * 1999-01-28 2000-08-11 United Microelectronics Corp Package for facing multichip
JP2001024149A (en) * 1999-07-12 2001-01-26 Mitsui High Tec Inc Semiconductor device
JP2003078104A (en) * 2001-09-04 2003-03-14 Hitachi Ltd Laminated semiconductor device
JP2003324183A (en) * 2002-05-07 2003-11-14 Mitsubishi Electric Corp Semiconductor device
JP2003332520A (en) * 2002-05-15 2003-11-21 Matsushita Electric Ind Co Ltd Semiconductor device
JP2004047987A (en) * 2003-06-12 2004-02-12 Rohm Co Ltd Laminate substrate body and semiconductor device
JP2005217205A (en) * 2004-01-29 2005-08-11 Nec Electronics Corp Three-dimensional semiconductor device of chip multilayer structure and spacer chip used therein

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62232133A (en) * 1986-04-01 1987-10-12 Seiko Epson Corp Semiconductor packaging structure
JP2000223651A (en) * 1999-01-28 2000-08-11 United Microelectronics Corp Package for facing multichip
JP2001024149A (en) * 1999-07-12 2001-01-26 Mitsui High Tec Inc Semiconductor device
JP2003078104A (en) * 2001-09-04 2003-03-14 Hitachi Ltd Laminated semiconductor device
JP2003324183A (en) * 2002-05-07 2003-11-14 Mitsubishi Electric Corp Semiconductor device
JP2003332520A (en) * 2002-05-15 2003-11-21 Matsushita Electric Ind Co Ltd Semiconductor device
JP2004047987A (en) * 2003-06-12 2004-02-12 Rohm Co Ltd Laminate substrate body and semiconductor device
JP2005217205A (en) * 2004-01-29 2005-08-11 Nec Electronics Corp Three-dimensional semiconductor device of chip multilayer structure and spacer chip used therein

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012529770A (en) * 2009-06-24 2012-11-22 インテル・コーポレーション Multi-chip package and method for providing multi-chip package die-to-die interconnects
JP2014168096A (en) * 2009-06-24 2014-09-11 Intel Corp Multi-chip package, and method of providing die-to-die interconnects in multi-chip package
US9875969B2 (en) 2009-06-24 2018-01-23 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10510669B2 (en) 2009-06-24 2019-12-17 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10763216B2 (en) 2009-06-24 2020-09-01 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10923429B2 (en) 2009-06-24 2021-02-16 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US11824008B2 (en) 2009-06-24 2023-11-21 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US11876053B2 (en) 2009-06-24 2024-01-16 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US12113026B2 (en) 2009-06-24 2024-10-08 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
JP2014078760A (en) * 2014-02-03 2014-05-01 Fujitsu Ltd Multichip module
JP2016018876A (en) * 2014-07-08 2016-02-01 日本電気株式会社 Electronic device or method of manufacturing the same

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