JP2008182540A - Optical transmission system integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce cost for device and operation by simplifying a multiple conversion unit configuration for multiple separation and simplifying a switch processing mechanism including clock switching or a change in connection. <P>SOLUTION: This optical transmission system integrated circuit comprises at least: an inverse conversion processing circuit 4 for demapping a plurality of low-speed transmission signals from a high-speed transmission signal; a separation processing circuit 5; a switch processing circuit 6 sorting a separated low-speed transmission signal and an input low-speed transmission signal arbitrarily; a multiple processing circuit 7 for mapping the plurality of low-speed transmission signals into the high-speed transmission signal; a conversion processing circuit 8; an input-output interface 9 for a high-speed transmission signal; and a plurality of input-output interfaces 10 for a low-speed transmission signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a node component of a ring network of a high-speed transmission signal in which a plurality of low-speed transmission signals are multiplexed. The present invention relates to a system integrated circuit.

  As a conventional technique, FIG. 17 shows a unidirectional path switched ring UPSR (Unidirectional Path Switched Ring) which is a node component of a conventional ring network, and FIG. 18 shows a bidirectional line switched ring BLSR (Bidirectional Line Switched Ring). Ring)

  The UPSR shown in FIG. 17 is a system in which the same traffic 102 is used as a working and backup in both directions of the ring at normal times, and when a failure occurs in the working, the receiving side switches to the standby.

In addition, the BLSR shown in FIG. 18 normally flows traffic 202 in one direction as the current operation, but in the event of a failure, the traffic is looped back so as to avoid that section, and a detour is made using a spare secured in the opposite direction. (See Patent Document 1).
JP 2001-177491 A

  However, in the conventional technique as described above, as shown in FIGS. 17 and 18, the reverse conversion and separation function and the multiplexing and conversion function are integrated to form UPSR and BLSR. Due to such a configuration, in order to realize an add / drop multiplexer (ADM), in addition to the demultiplexing unit that performs demultiplexing, a large-scale switch processing mechanism including clock switching or a change in connection is necessary. Equipment costs and operational costs were rising.

  The present invention has been made in view of the above, and an object of the present invention is to realize a simplification of the configuration of a multiplex conversion unit that performs demultiplexing, simplify a change of a switch processing mechanism or connection including clock switching, and an apparatus and It is to reduce operational costs.

  To achieve the above object, the present invention according to claim 1 is an input / output for inputting / outputting a high-speed transmission signal as a node component of a ring network of a high-speed transmission signal obtained by multiplexing a plurality of low-speed transmission signals. An interface, an input / output interface for inputting and outputting a plurality of low-speed transmission signals, an inverse conversion processing circuit for demapping a plurality of low-speed transmission signals from a high-speed transmission signal, a separation processing circuit, and a separated low-speed transmission signal A switch processing circuit for arbitrarily rearranging the input low-speed transmission signal, a multi-processing circuit for mapping a plurality of low-speed transmission signals to the high-speed transmission signal, and a conversion processing circuit, A first output means for multiplexing a low-speed transmission signal separated from an input high-speed transmission signal at an arbitrary position and outputting it as a high-speed transmission signal; A second output means for outputting a low-speed transmission signal separated from the transmission signal to an arbitrary position as a low-speed transmission signal; and a third output means for multiplexing the input low-speed transmission signal at an arbitrary position and outputting the multiplexed signal as a high-speed transmission signal. Output means, and fourth output means for outputting an input low-speed transmission signal as a low-speed transmission signal at an arbitrary position.

  According to a second aspect of the present invention, in the first aspect of the present invention, the input / output interface for inputting / outputting a plurality of high-speed transmission signals and the high-speed transmission signal of the internal connection in the node of the ring network are demapped. The second inverse transformation processing circuit, the first selector circuit for selecting outputs from the plurality of inverse transformation processing circuits, and the output of the externally connected inverse transformation processing circuit are mapped to the internally connected high-speed transmission signal A second conversion processing circuit for output, a fifth output means for outputting an external input high-speed transmission signal as an internal high-speed transmission signal, and a low-speed transmission signal separated from the internal high-speed transmission signal Is output as an external high-speed transmission signal and a low-speed transmission signal separated from the internal input high-speed transmission signal as a low-speed transmission signal at an arbitrary position. Comprising a seventh output means for force, the.

  According to a third aspect of the present invention, in the first aspect of the present invention, the input / output interface for inputting / outputting a plurality of high-speed transmission signals and the high-speed transmission signals connected internally in the nodes of the ring network are demapped. The second inverse transformation processing circuit, the first selector circuit for selecting outputs from the plurality of inverse transformation processing circuits, the output of the multiple processing circuit and the output of the second inverse transformation processing circuit A second selector circuit and a second conversion processing circuit for mapping the output of the multiplex processing circuit to the internally connected high-speed transmission signal, the low-speed transmission signal separated from the internal input high-speed transmission signal Sixth output means for multiplexing at an arbitrary position and outputting it as an external high-speed transmission signal, and outputting a low-speed transmission signal separated from the internal input high-speed transmission signal as a low-speed transmission signal at an arbitrary position A seventh output means for output, an eighth output means for outputting the internal high-speed transmission signal as an external high-speed transmission signal, and a low-speed transmission signal separated from the external high-speed transmission signal at an arbitrary position A ninth output means for multiplexing and outputting as an internal high-speed transmission signal; and a low-speed transmission signal separated from the internal input high-speed transmission signal for multiplexing at an arbitrary position and outputting as an internal high-speed transmission signal A tenth output means, and an eleventh output means for multiplexing the input low-speed transmission signal at an arbitrary position and outputting it as an internal high-speed transmission signal.

  According to a fourth aspect of the present invention, in any one of the first to third aspects, the third selector circuit for selecting the output of the multiprocessing circuit and the output of the first inverse conversion processing circuit, and the input And a twelfth output means for outputting a high-speed transmission signal as a high-speed transmission signal without converting it into a low-speed transmission signal. An arbitrary low-speed transmission signal is inserted into and extracted from the received high-speed transmission signal and transmitted again as a high-speed transmission signal. A FIFO for switching from the reception clock to the transmission clock, and a FIFO for switching from the reception clock to the transmission clock when transmitting the received high-speed transmission signal as a high-speed transmission signal without converting it to a low-speed transmission signal; , Is common.

  According to a fifth aspect of the present invention, in any one of the first to third aspects, the transmission low-speed transmission signal clock system and the transmission high-speed transmission signal clock system, and the transmission low-speed transmission signal clock system and the reception high-speed transmission signal are provided. There is a FIFO for changing clocks between the clock system and between the transmission high-speed transmission signal clock system and the reception high-speed transmission signal clock system, and the low-speed transmission signal output as the transmission high-speed transmission signal The selection is performed by the transmission high-speed transmission signal clock system, and the low-speed transmission signal output as the transmission low-speed transmission signal is selected by the reception high-speed transmission signal clock system.

  According to a sixth aspect of the present invention, in any one of the first to third aspects, the transmission low-speed transmission signal clock system and the transmission high-speed transmission signal clock system, and the transmission low-speed transmission signal clock system and the reception high-speed transmission signal are provided. A FIFO for changing clocks between the clock system or the transmission high-speed transmission signal clock system and between the transmission high-speed transmission signal clock system and the reception high-speed transmission signal clock system, When applied to a device that multiplexes low-speed transmission signals and outputs them as high-speed transmission signals, low-speed transmission that selects low-speed transmission signals to be output as transmission high-speed transmission signals using the transmission high-speed transmission signal clock system and outputs them as transmission low-speed transmission signals A selection means for selecting a signal in the reception high-speed transmission signal clock system and an arbitrary low-speed transmission from a high-speed transmission signal multiplexed with a low-speed transmission signal. In the case of applying to a device for insertion and removal of the signal, a selecting means for selecting all the low-speed transmission signals at the transmission speed transmission signal clock system, at least one of.

  According to the present invention, it is possible to simplify the configuration of a multiple conversion unit that performs demultiplexing, simplify the change of a switch processing mechanism or connection including clock switching, and reduce the cost of the apparatus and operation.

  The present embodiment relates to a transmission / reception integrated circuit of an optical transmission system, and particularly to a node component of a ring network of high-speed transmission signals obtained by multiplexing a plurality of low-speed transmission signals.

  Further, the present invention relates to an integrated circuit that can insert / remove an arbitrary low-speed transmission signal from a high-speed transmission signal (for example, 43.0 Gbps / OTU3) obtained by multiplexing low-speed transmission signals (for example, 10.7 Gbps / OTU2). Here, OTU2 and OTU3 are client signals and ITU-T recommendation G.264. 709 “Optical Transmission Network (OTN) Interface” refers to an optical channel transmission unit defined.

<First Embodiment>
FIG. 1 shows a configuration diagram of an optical transmission system integrated circuit according to the first embodiment. The configuration diagram shown in FIG. 1 shows an example applied to a plurality of unidirectional path switch type ring UPSR nodes 2 as node components of a ring network 1 of a high-speed transmission signal obtained by multiplexing a plurality of low-speed transmission signals. Yes.

  In FIG. 1, an integrated circuit 3, 3 ′ includes an inverse conversion processing circuit 4 for demapping a plurality of low-speed transmission signals from a high-speed transmission signal, a separation processing circuit 5, a separated low-speed transmission signal, and an input low-speed transmission. A switch processing circuit 6 capable of arbitrarily rearranging signals, a multiprocessing circuit 7 for mapping a plurality of low-speed transmission signals to high-speed transmission signals, a conversion processing circuit 8, an input / output interface 9 for high-speed transmission signals, At least an input / output interface 10 for a plurality of low-speed transmission signals is provided.

  Further, the integrated circuits 3 and 3 ′ are means for outputting a high-speed transmission signal by multiplexing the low-speed transmission signal separated from the input high-speed transmission signal at an arbitrary position according to the setting of the switch processing circuit (switch) 6. Output means), means for outputting a low-speed transmission signal separated from the input high-speed transmission signal as a low-speed transmission signal at an arbitrary position (second output means), and multiplexing the input low-speed transmission signal at an arbitrary position for high-speed transmission Means for outputting as a signal (third output means) and means for outputting the input low-speed transmission signal as a low-speed transmission signal at an arbitrary position (fourth output means).

  The unidirectional path switch type ring UPSR node 2 can be realized by the two integrated circuits 3 and 3 ′ and the selector (not shown) configured by four to select one signal from the two signals. Further, the switch processing mechanism including clock switching or connection change can be simplified from the conventional UPSR configuration (see FIG. 17), and the cost of the apparatus and operation can be reduced. Furthermore, according to the present embodiment, in addition to the functions necessary for the UPSR node, it is possible to through-output a low-speed transmission signal to be added and dropped, so that it can be applied to a connection between a high-speed transmission ring and a low-speed transmission ring. In addition, since the multiplexing position of the low-speed transmission signal can be switched (TSI: Time Slot Interchange), the band utilization efficiency can be further increased.

  FIG. 2 shows an example of normal operation of the first embodiment, in which one of the low-speed transmission signals 11 separated from the high-speed transmission signal is replaced. The selector 13 is composed of four pieces. FIG. 3 shows an operation example when an abnormality is detected according to the first embodiment, and shows a signal processing method of the signal 12 when an abnormality is detected in one inverse conversion processing circuit 4.

  In FIG. 1, the switch is configured by an 8 × 8 switch. However, it is also possible to configure two 4 × 4 switches. By implementing the second output means and the third output means, the present invention can be applied to an apparatus that separates high-speed signals, outputs them as low-speed transmission signals, multiplexes low-speed signals, and outputs them as high-speed transmission signals. If the application range is expanded, the cost of the integrated circuit can be reduced due to the mass production effect.

<Second Embodiment>
FIG. 4 shows a configuration diagram of an optical transmission system integrated circuit according to the second embodiment. FIG. 4 shows an example in which a bidirectional line switch type ring BLSR 20 is applied as a node component of a ring network 1 of a high-speed transmission signal obtained by multiplexing a plurality of low-speed transmission signals. The integrated circuits 3 and 3 ′ have the same function and configuration as those of the first embodiment, and details thereof are omitted.

  By configuring the two integrated circuits 3 and 3 ′ and twelve selectors 13 for selecting one signal from two signals, a bidirectional line switch type ring BLSR20 can be realized, and the clock is faster than the conventional configuration (see FIG. 18). A large-scale switch processing mechanism including switching or connection change is not necessary, and the cost of the apparatus and operation can be reduced.

  In addition, in the conventional BLSR configuration (FIG. 18), since the protection (signal switching) function is performed by the switch, a switch larger than necessary is necessary, but according to the present embodiment, it is not necessary. It is.

  FIG. 5 shows an example of normal operation in the second embodiment, in which one of the low-speed transmission signals separated from the high-speed transmission signal 21 is replaced. FIG. 6 shows an operation example when an abnormality is detected in the second embodiment, and shows a signal processing method when an abnormality is detected in one inverse conversion processing circuit 4.

<Third Embodiment>
FIG. 7 illustrates a configuration diagram of an optical transmission system integrated circuit according to the third embodiment. The configuration shown in FIG. 7 is an example applied to a unidirectional path switch type ring UPSR node 2 as a node component of a ring network 1 of a high-speed transmission signal obtained by multiplexing a plurality of low-speed transmission signals.

  FIG. 7 shows the configuration of the integrated circuit 31, and an inverse conversion processing circuit 4 for demapping a plurality of low-speed transmission signals from an externally connected high-speed transmission signal, and an inverse conversion for demapping an internal-connected high-speed transmission signal. A processing circuit (simple) 15, a selector circuit 16 for selecting outputs from a plurality of inverse transform processing circuits, a separation processing circuit 5 for separating the output of the selector circuit into a plurality of low-speed transmission signals, and a separated low-speed transmission signal Switch processing circuit 6 capable of arbitrarily rearranging input low-speed signals, multi-processing circuit 7 for multiplexing a plurality of low-speed transmission signals into high-speed transmission signals, and conversion for mapping the outputs of the multi-processing circuits to externally connected high-speed transmission signals A processing circuit 8, a conversion processing circuit (simple) 15 for mapping the output of an externally connected inverse conversion processing circuit to an internally connected high-speed transmission signal, and an input / output interface 9 for a high-speed transmission signal , And a input-output interface 10 of a plurality of low-speed transmission signals, the on one chip.

  Further, the integrated circuit 31 multiplexes a low-speed transmission signal separated from an input high-speed transmission signal (external / standard) at an arbitrary position according to the setting of the switch processing circuit 6 and the selector circuit 16, and transmits the high-speed transmission signal (external / standard). ) (First output means), means for outputting a low-speed transmission signal separated from the input high-speed transmission signal (external / standard) as a low-speed transmission signal at any position (second output means), Means (third output means) for multiplexing the input low-speed transmission signal at an arbitrary position and outputting it as a high-speed transmission signal (external / standard); and means for outputting the input low-speed transmission signal at any position as a low-speed transmission signal ( Fourth output means), means for outputting an input high-speed transmission signal (external / standard) as a high-speed transmission signal (internal / simple), and input high-speed transmission signal (internal / simple) did A means (sixth output means) for multiplexing a high-speed transmission signal at an arbitrary position and outputting it as a high-speed transmission signal (external / standard) and a low-speed transmission signal separated from the input high-speed transmission signal (internal / simple) And a means (seventh output means) for outputting as a low-speed transmission signal at the position.

  The unidirectional path switch type ring UPSR node 2 can be realized by the configuration of only the two integrated circuits 30 and 30 ', and the switch processing mechanism including the clock switching or the connection change can be performed from the configuration of the conventional UPSR (see FIG. 17). It can be simplified and the cost of equipment and operation can be reduced.

  Further, according to the present embodiment, in addition to the functions necessary for the UPSR node, it is possible to output through-transmission of a low-speed transmission signal to be dropped, so that it can be applied to a connection between a high-speed transmission ring and a low-speed transmission ring. Since the multiplexing position of the low-speed transmission signal can be switched (TSI: Time Slot Interchange), the band utilization efficiency can be further increased.

  In the present embodiment, the external selector can be deleted from the UPSR configuration of the first embodiment (see FIG. 1), a configuration with easier connection can be provided, and the cost can be reduced. In addition, the high-speed transmission signal conversion / inverse conversion circuit on one side is limited to the connection between integrated circuits. For example, an error correction code with low error correction capability is used, or the error correction function is omitted. Is also possible.

  FIG. 8 shows an example of normal operation in the third embodiment, in which one of the low-speed transmission signals 32 separated from the high-speed transmission signal is replaced. FIG. 9 shows an operation example when an abnormality is detected in the third embodiment. A signal processing method for the high-speed transmission signal 33 when an abnormality is detected in one inverse conversion processing circuit 4 is shown. Show.

<Fourth embodiment>
FIG. 10 shows a configuration diagram of an optical transmission system integrated circuit according to the fourth embodiment.

  The fourth embodiment shown in FIG. 10 is an example applied to the bidirectional line switch type ring BLSR2 as a node component of the ring network 1 of a high-speed transmission signal obtained by multiplexing a plurality of low-speed transmission signals. The integrated circuit 31 has the same function and configuration as those of the third embodiment, and details thereof are omitted.

  A bidirectional line switch type ring BLSW30 can be realized by the configuration of only two integrated circuits 31 and 31 ', and a large-scale switch processing mechanism including clock switching or a connection change is required as compared with the conventional configuration (see FIG. 18). This reduces the cost of equipment and operation.

  In the conventional BLSR configuration (see FIG. 18), since the protection (signal switching) function is performed by the switch, a larger-scale switch than necessary is necessary. Is unnecessary. This embodiment can reduce the number of selectors compared to the BLSR configuration of the second embodiment (see FIG. 4), and can provide a configuration with easier connection. In addition, the high-speed transmission signal conversion / inverse conversion circuit on one side is limited to the connection between integrated circuits. For example, an error correction code with low error correction capability is used, or the error correction function is omitted. Is also possible.

  FIG. 11 shows an example of normal operation of the fourth embodiment, in which one of the low-speed transmission signals separated from the high-speed transmission signal 34 is replaced. FIG. 12 shows an operation example when an abnormality is detected in the fourth embodiment, and shows a signal processing method for the high-speed transmission signal 35 when an abnormality is detected in one inverse conversion processing circuit 4. ing.

<Fifth embodiment>
FIG. 13 shows a configuration diagram of an optical transmission system integrated circuit according to the fifth embodiment.

  The configuration of the fifth embodiment shown in FIG. 13 is applied as a component of the node 40 of the ring network 1 of a high-speed transmission signal obtained by multiplexing a plurality of low-speed transmission signals.

  The integrated circuits 41 and 41 ′ according to the present embodiment include an inverse conversion processing circuit 4 for demapping externally connected high-speed transmission signals, an inverse conversion processing circuit (simple) 15 for demapping internal-connected high-speed transmission signals, and a plurality of them. The selector circuit (front) 16 that selects the output from the inverse conversion processing circuit, the separation processing circuit 5 that separates the output of the selector circuit (front) 16 into a plurality of low-speed transmission signals, the separated low-speed transmission signal and the input low-speed A switch processing circuit 6 that can rearrange transmission signals arbitrarily, a multiprocessing circuit 7 that multiplexes a plurality of low-speed transmission signals into a high-speed transmission signal, an output of the multiprocessing circuit, and an output of an inverse conversion processing circuit (simple) are selected. The selector circuit (rear) 18, the conversion processing circuit 8 that maps the output of the selector circuit (rear) 18 to the externally connected high-speed transmission signal, and the output of the multiplex processing circuit are mapped to the internal-connected high-speed transmission signal. A conversion circuit (simplified) 17 ring, the output interface 9 of the high-speed transmission signals, and a output interface 10 of a plurality of low-speed transmission signals, the on one chip.

  Further, the integrated circuits 41 and 41 ′ arbitrarily set the low-speed transmission signal separated from the input high-speed transmission signal (external / standard) by the setting of the switch processing circuit 6, the selector circuit (front) 16, and the selector circuit (rear) 18. A means for outputting a high-speed transmission signal (external / standard) multiplexed at the position (first output means) and a low-speed transmission signal separated from the input high-speed transmission signal (external / standard) at any position Output means (second output means), means (third output means) for multiplexing the input low-speed transmission signal at an arbitrary position and outputting it as a high-speed transmission signal (external / standard), and input low-speed transmission signal Is output as a low-speed transmission signal at an arbitrary position (fourth output means), and a low-speed transmission signal separated from an input high-speed transmission signal (internal / simple) is multiplexed at an arbitrary position to provide a high-speed transmission signal (external standard) Output means (sixth output means), means for outputting the low-speed transmission signal separated from the input high-speed transmission signal (internal / simple) as a low-speed transmission signal at an arbitrary position (seventh output means), Means (8th output means) for outputting input high-speed transmission signal (internal / simple) as high-speed transmission signal (external / standard) and low-speed transmission signal separated from input high-speed transmission signal (external / standard) at any position High-speed transmission by multiplexing to a desired position (9th output means) and a low-speed transmission signal separated from the input high-speed transmission signal (internal / simple) at any position Means for outputting as a signal (internal / simple) (tenth output means) and means for multiplexing an input low-speed transmission signal at an arbitrary position and outputting it as a high-speed transmission signal (internal / simple) (eleventh output means) And have.

  By providing a selector circuit (front) 16 and a selector circuit (rear) 18 as selectors at the front and rear stages of the integrated circuits 41 and 41 ′, the function of the low-speed transmission signal switching pattern is further improved than in the third and fourth embodiments. And can be applied to more complicated signal processing of the transmission signal 34.

  For example, in the first and third embodiments, the same low-speed transmission signal is input to two integrated circuits. However, in this embodiment, even one connection can be applied to a UPSR node. As a result, the cost of the apparatus can be reduced, and since switch switching during operation is limited to the connected integrated circuit, cost reduction can be realized by simplifying operation.

<Sixth Embodiment>
FIG. 14 shows a configuration diagram of an optical transmission system integrated circuit according to the sixth embodiment.

  The configuration of the sixth embodiment shown in FIG. 14 is applied as a node component of the ring network 1 of a high-speed transmission signal obtained by multiplexing a plurality of low-speed transmission signals.

  The integrated circuit 50 according to the present embodiment includes an inverse conversion processing circuit 54 ′ for demapping a plurality of low-speed transmission signals from a high-speed transmission signal, a separation processing circuit 53, an arbitrary low-speed transmission signal and an input low-speed transmission signal. Switch processing circuit 51 that can be rearranged, multi-processing circuit 52 for mapping a plurality of low-speed transmission signals to high-speed transmission signals, conversion processing circuit 54, input / output interface 58 for high-speed transmission signals, and a plurality of low-speed transmission signals A transmission signal input / output interface 57, a selector 55 for selecting a reception low-speed signal group and a reception high-speed signal, and a FIFO 56 for switching from the reception clock to the transmission clock from the output of the selector 55 are provided on one chip. ing.

  The integrated circuit 50 includes a unit (first output unit) that multiplexes a low-speed transmission signal separated from an input high-speed transmission signal at an arbitrary position according to the setting of the switch processing circuit 51 and outputs the multiplexed signal as a high-speed transmission signal; Means (second output means) for outputting a low-speed transmission signal separated from an input high-speed transmission signal to an arbitrary position as a low-speed transmission signal, and means for multiplexing the input low-speed transmission signal at an arbitrary position and outputting it as a high-speed transmission signal (Third output means), means for outputting an input low-speed transmission signal as a low-speed transmission signal at an arbitrary position (fourth output means), and high-speed transmission signal without converting the input high-speed transmission signal into a low-speed transmission signal As a twelfth output means (a twelfth output means).

  Also, when an arbitrary low-speed transmission signal is inserted / removed from the input high-speed signal and transmitted again as a high-speed transmission signal, a FIFO for changing from the reception clock to the transmission clock and the received high-speed transmission signal are converted into a low-speed transmission signal. When transmitting as a high-speed transmission signal without any problem, a FIFO is provided which is shared with a FIFO that performs transfer from the reception clock to the transmission clock.

  According to the present embodiment, the application range can be expanded to the twelfth output means, and the FIFO 56 can be shared, so that an increase in circuit scale can be suppressed.

<Seventh embodiment>
FIG. 15 is a configuration diagram of an optical transmission system integrated circuit according to the seventh embodiment.

  The seventh embodiment having the configuration shown in FIG. 15 is applied as a node component of the ring network 1 of a high-speed transmission signal obtained by multiplexing a plurality of low-speed transmission signals.

  The integrated circuit 60 according to the present embodiment includes an inverse conversion processing circuit 66 for demapping a plurality of low-speed transmission signals from a high-speed transmission signal, a separation processing circuit 64, an arbitrary low-speed transmission signal, and an input low-speed transmission signal. Switch processing circuit 61 that can be rearranged, a multiple processing circuit 63 for mapping a plurality of low-speed transmission signals to a high-speed transmission signal, a conversion processing circuit 65, an input / output interface 69 for high-speed transmission signals, and a plurality of low-speed transmission signals A transmission signal input / output interface 68, a clock transfer FIFO 67 provided between the reception low-speed transmission signal clock system (C1-4) and the transmission high-speed transmission signal clock system (C9), and a transmission low-speed transmission signal clock system (C5- C8) and the high-speed transmission signal clock system (C10), a clock transfer FIFO 25b provided between the high-speed transmission signal clock system (C10) and the transmission high-speed transmission signal clock system ( 9) and the reception high-speed transmission signal clock system as clock change FIFO67 'provided between the (C10), a has on one chip.

  The integrated circuit 60 includes a unit (first output unit) that multiplexes a low-speed transmission signal separated from an input high-speed transmission signal at an arbitrary position according to the setting of the switch processing circuit 61 and outputs the multiplexed signal as a high-speed transmission signal; Means (second output means) for outputting a low-speed transmission signal separated from an input high-speed transmission signal to an arbitrary position as a low-speed transmission signal, and means for multiplexing the input low-speed transmission signal at an arbitrary position and outputting it as a high-speed transmission signal (Third output means), means (fourth output means) for outputting an input low-speed transmission signal as a low-speed transmission signal at an arbitrary position, and inserting and extracting an arbitrary low-speed transmission signal from the input high-speed signal again. When transmitting as a low-speed transmission signal, a low-speed transmission signal output as a transmission high-speed transmission signal is selected by the transmission high-speed transmission signal clock system (C9) and output as a transmission low-speed transmission signal And means for performing selections on the received high-speed transmission signal clock system (C10) (output unit 13), a has.

  According to the present embodiment, complicated switch processing can be configured with a simple selector of the same clock by performing switch processing of a low-speed transmission signal after switching to a unified clock system.

<Eighth Embodiment>
FIG. 16 shows a configuration diagram of an optical transmission system integrated circuit according to the eighth embodiment.

  The configuration of the eighth embodiment shown in FIG. 16 is applied as a node component of the ring network 1 of a high-speed transmission signal obtained by multiplexing a plurality of low-speed transmission signals.

  The integrated circuit 70 can arbitrarily rearrange the inverse conversion processing circuit 75 for demapping a plurality of low-speed transmission signals from the high-speed transmission signal, the separation processing circuit 74, and the separated low-speed transmission signal and input low-speed transmission signal. Switch processing circuit 71, multiple processing circuit 72 for mapping a plurality of low-speed transmission signals to high-speed transmission signals, conversion processing circuit 73, input / output interface 78 for high-speed transmission signals, and input of a plurality of low-speed transmission signals Output interface 77, clock transfer FIFO 76 provided between reception low-speed transmission signal clock system (C1-4) and transmission high-speed transmission signal clock system (C9), transmission low-speed transmission signal clock system (C5-C8) and reception A clock provided between the selected clock system (CX) of the high-speed transmission signal clock system (C10) or the transmission high-speed transmission signal clock system (C9). Click handoff FIFO76 comprises' and, clock change FIFO76 provided between the transmission high-speed transmission signal clock (C9) and the received high-speed transmission signal clock system (C10) 'and' a on one chip.

  Further, the integrated circuit 34 multiplexes a low-speed transmission signal separated from the input high-speed transmission signal at an arbitrary position and outputs it as a high-speed transmission signal according to the setting of the switch, and an input high-speed transmission. Means for outputting a low-speed transmission signal separated from the signal as a low-speed transmission signal at an arbitrary position (second output means), and means for multiplexing the input low-speed transmission signal at an arbitrary position and outputting it as a high-speed transmission signal (third Output means), means for outputting an input low-speed transmission signal as a low-speed transmission signal at an arbitrary position (fourth output means), and a device for multiplexing the low-speed transmission signal and outputting it as a high-speed transmission signal, The low-speed transmission signal output as the transmission high-speed transmission signal is selected by the transmission high-speed transmission signal clock system (C9), and the low-speed transmission signal output as the transmission low-speed transmission signal is selected by the reception high-speed transmission signal clock. When applying to a device (14th output means) performed in the clock system (C10) and an apparatus for inserting / removing an arbitrary low-speed transmission signal from a high-speed transmission signal obtained by multiplexing low-speed transmission signals, all low-speed transmission signals are selected. And a means (fifteenth output means) for performing transmission at the transmission high-speed transmission signal clock system (C9).

  According to the present embodiment, complicated switch processing can be configured with a simple selector of the same clock by performing switch processing of a low-speed transmission signal after switching to a unified clock system. Furthermore, by making it possible to select a clock source of a part of the clock system according to the application device, it is possible to perform normal switch processing even when the received high-speed transmission signal is abnormal, and it is possible to realize a higher quality device. Become.

  As described above, in the first and second embodiments, by using two identical integrated circuits and several selectors, the UPSR and BLSR ring network nodes can be manufactured at low cost without using external switches. It becomes feasible. Further, compared to a simple UPSR, through output between input and output of a low-speed transmission signal is possible, so it can be applied to a connection between a high-speed transmission ring and a low-speed transmission ring. Therefore, bandwidth utilization efficiency can be further increased. Further, in the conventional BLSR, since the protection function is performed by a switch, a switch larger than necessary is necessary, but this embodiment is not necessary.

  Further, in the third, fourth and fifth embodiments, by using two identical integrated circuits, the UPSR and BLSR ring network nodes can be realized at low cost without using an external switch or an external selector. Become. In addition, the high-speed transmission signal conversion / inversion circuit on one side is limited to the connection between integrated circuits. For example, an error correction code with a low error correction capability is used, or the error correction function is omitted. Is also possible.

  Further, in the sixth embodiment, an increase in circuit scale can be suppressed by sharing the FIFO necessary for expanding the application range with another FIFO.

  In addition, in the seventh and eighth embodiments, even with complicated switching processing, switching processing of low-speed transmission signals is performed after switching to a unified clock system, so that a simple selector with the same clock is used. Is possible. Furthermore, by making it possible to select a clock source of a part of the clock system according to the application device, it is possible to perform normal switch processing even when the received high-speed transmission signal is abnormal, and it is possible to realize a higher quality device. Become.

  As described above, by using the optical transmission system integrated circuit of the present embodiment, a multiplex conversion unit that performs demultiplexing when applied as a node component of a ring network of a high-speed transmission signal obtained by multiplexing a plurality of low-speed transmission signals The simplification of the configuration, the switch processing mechanism including clock switching, or the change of connection can be simplified, and the cost of the apparatus and operation can be reduced.

1 is a configuration diagram of an optical transmission system integrated circuit according to a first embodiment. FIG. An example of normal operation of the first embodiment is shown. The example of operation at the time of abnormality detection of a 1st embodiment is shown. FIG. 3 illustrates a configuration diagram of an optical transmission system integrated circuit according to a second embodiment. An example of normal operation in the second embodiment is shown. The example of operation at the time of the abnormality detection in 2nd Embodiment is shown. FIG. 6 illustrates a configuration diagram of an optical transmission system integrated circuit according to a third embodiment. An example of normal operation in the third embodiment is shown. The example of operation at the time of abnormality detection in a 3rd embodiment is shown. FIG. 9 illustrates a configuration diagram of an optical transmission system integrated circuit according to a fourth embodiment. An example of normal operation of the fourth embodiment is shown. The example of operation at the time of abnormality detection of a 4th embodiment is shown. FIG. 10 illustrates a configuration diagram of an optical transmission system integrated circuit according to a fifth embodiment. FIG. 10 illustrates a configuration diagram of an optical transmission system integrated circuit according to a sixth embodiment. FIG. 18 illustrates a configuration diagram of an optical transmission system integrated circuit according to a seventh embodiment. FIG. 20 illustrates a configuration diagram of an optical transmission system integrated circuit according to an eighth embodiment. 1 shows a unidirectional path switch type ring UPSR which is a node component of a conventional ring network. The structure of the conventional bidirectional line switch type ring BLSR is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Ring network 2 ... Unidirectional path switch type ring UPSR node 3, 3 '... Integrated circuit 4 ... Inverse conversion processing circuit 5 ... Separation processing circuit 6 ... Switch processing circuit 7 ... Multiple processing circuit 8 ... Conversion processing circuit 9 ... High-speed transmission signal input / output interface 10 ... Low-speed transmission signal input / output interface

Claims (6)

As a node component of a ring network of high-speed transmission signals obtained by multiplexing a plurality of low-speed transmission signals,
An input / output interface for inputting and outputting high-speed transmission signals;
An input / output interface for inputting and outputting multiple low-speed transmission signals;
An inverse conversion processing circuit for demapping a plurality of low-speed transmission signals from a high-speed transmission signal;
A separation processing circuit;
A switch processing circuit for arbitrarily rearranging the separated low-speed transmission signal and the input low-speed transmission signal;
A multiprocessing circuit for mapping a plurality of low-speed transmission signals to high-speed transmission signals;
A conversion processing circuit;
Have
First output means for multiplexing a low-speed transmission signal separated from an input high-speed transmission signal by setting of a switch at an arbitrary position and outputting the multiplexed signal as a high-speed transmission signal;
A second output means for outputting the low-speed transmission signal separated from the input high-speed transmission signal as a low-speed transmission signal at an arbitrary position;
A third output means for multiplexing the input low-speed transmission signal at an arbitrary position and outputting it as a high-speed transmission signal;
A fourth output means for outputting the input low-speed transmission signal as a low-speed transmission signal at an arbitrary position;
An optical transmission system integrated circuit comprising: An input / output interface for inputting / outputting a plurality of high-speed transmission signals, a second inverse conversion processing circuit for demapping an internal connection high-speed transmission signal in a node of the ring network, and a plurality of inverse conversion processing circuits And a second conversion processing circuit for mapping the output of the externally connected inverse conversion processing circuit to the internally connected high-speed transmission signal,
A fifth output means for outputting an external input high-speed transmission signal as an internal high-speed transmission signal;
A sixth output means for multiplexing a low-speed transmission signal separated from an internal input high-speed transmission signal at an arbitrary position and outputting it as an external high-speed transmission signal;
A seventh output means for outputting a low-speed transmission signal separated from an internal input high-speed transmission signal as a low-speed transmission signal at an arbitrary position;
The optical transmission system integrated circuit according to claim 1, further comprising: An input / output interface for inputting / outputting a plurality of high-speed transmission signals, a second inverse conversion processing circuit for demapping an internal connection high-speed transmission signal in a node of the ring network, and a plurality of inverse conversion processing circuits A first selector circuit for selecting the output of the second processing circuit, a second selector circuit for selecting the output of the multiprocessing circuit and the output of the second inverse transformation processing circuit, and the output of the multiprocessing circuit are internally connected. A second conversion processing circuit for mapping to a high-speed transmission signal,
A sixth output means for multiplexing a low-speed transmission signal separated from an internal input high-speed transmission signal at an arbitrary position and outputting it as an external high-speed transmission signal;
A seventh output means for outputting a low-speed transmission signal separated from an internal input high-speed transmission signal as a low-speed transmission signal at an arbitrary position;
An eighth output means for outputting an internal input high-speed transmission signal as an external high-speed transmission signal;
A ninth output means for multiplexing a low-speed transmission signal separated from an external input high-speed transmission signal at an arbitrary position and outputting it as an internal high-speed transmission signal;
A tenth output means for multiplexing a low-speed transmission signal separated from an internal input high-speed transmission signal at an arbitrary position and outputting it as an internal high-speed transmission signal;
An eleventh output means for multiplexing the input low-speed transmission signal at an arbitrary position and outputting it as an internal high-speed transmission signal;
The optical transmission system integrated circuit according to claim 1, further comprising: A third selector circuit for selecting the output of the multiprocessing circuit and the output of the first inverse conversion processing circuit;
Twelfth output means for outputting an input high-speed transmission signal as a high-speed transmission signal without converting it to a low-speed transmission signal,
A FIFO for switching from the reception clock to the transmission clock when an arbitrary low-speed transmission signal is inserted into and extracted from the high-speed transmission signal and transmitted again as a high-speed transmission signal, and high-speed without converting the received high-speed transmission signal into a low-speed transmission signal 4. The optical transmission system integrated circuit according to claim 1, wherein a FIFO for switching from a reception clock to a transmission clock when transmitting as a transmission signal is shared. Between the reception low-speed transmission signal clock system and the transmission high-speed transmission signal clock system, between the transmission low-speed transmission signal clock system and the reception high-speed transmission signal clock system, and between the transmission high-speed transmission signal clock system and the reception high-speed transmission signal clock system , Each has a FIFO for changing clocks,
The low-speed transmission signal output as the transmission high-speed transmission signal is selected by the transmission high-speed transmission signal clock system, and the low-speed transmission signal output as the transmission low-speed transmission signal is selected by the reception high-speed transmission signal clock system. Item 4. The optical transmission system integrated circuit according to any one of Items 1 to 3. The transmission high-speed transmission signal between the reception low-speed transmission signal clock system and the transmission high-speed transmission signal clock system, between the transmission low-speed transmission signal clock system and the clock system selected the reception high-speed transmission signal clock system or the transmission high-speed transmission signal clock system There is a FIFO for changing clocks between the clock system and the reception high-speed transmission signal clock system,
When applied to a device that multiplexes low-speed transmission signals and outputs them as high-speed transmission signals, low-speed transmission that selects low-speed transmission signals to be output as transmission high-speed transmission signals using the transmission high-speed transmission signal clock system and outputs them as transmission low-speed transmission signals Selection means for performing signal selection in the reception high-speed transmission signal clock system;
When applying to an apparatus that inserts and removes any low-speed transmission signal from a high-speed transmission signal obtained by multiplexing low-speed transmission signals, selection means for performing selection of all low-speed transmission signals in the transmission high-speed transmission signal clock system,
The optical transmission system integrated circuit according to claim 1, wherein at least one of the optical transmission system integrated circuit is included.

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