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JP2008177506A - Electronic component packaging method and electronic component packaging apparatus using same - Google Patents

Electronic component packaging method and electronic component packaging apparatus using same Download PDF

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Publication number
JP2008177506A
JP2008177506A JP2007011834A JP2007011834A JP2008177506A JP 2008177506 A JP2008177506 A JP 2008177506A JP 2007011834 A JP2007011834 A JP 2007011834A JP 2007011834 A JP2007011834 A JP 2007011834A JP 2008177506 A JP2008177506 A JP 2008177506A
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electronic component
substrate
cavity
dimension
electronic components
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Nobuaki Nagou
暢明 名合
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Fujifilm Corp
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Fujifilm Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156Side view

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component packaging method which is high in flexibility of component selection, and an electronic component packaging apparatus using the same. <P>SOLUTION: An electronic component packaging substrate 10 has recessed cavities P1i, differing in depth B1i according to heights C1i of electronic components X1i, formed on the side of a top surface 11a of a multilayer substrate 11 without exceeding the thickness D of the multilayer substrate 11 such that the thicknesses A1 up to upper-end portions of electronic components 12 to 20 mounted on the side of the top surface 11a is previously set based upon the reverse surface 11b of the multilayer substrate 11 and projection quantities of all the electronic components X1i (i=1, 2, ..., m (m: a positive integer)) on the side of the top surface 11a are held within the thickness A1, and the electronic components X1i are fitted therein. Similarly, recessed cavities P2i having depths B2i are formed on the side of the reverse surface 11b, and electronic components X2i are fitted therein. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、電子部品実装方法及びこれを用いた電子部品実装基板に関し、更に詳しくは基板に形成した凹状のキャビティに電子部品を実装する電子部品実装方法及びこれを用いた電子部品実装基板に関するものである。   The present invention relates to an electronic component mounting method and an electronic component mounting substrate using the same, and more particularly to an electronic component mounting method for mounting an electronic component in a concave cavity formed on the substrate and an electronic component mounting substrate using the same. It is.

電子部品実装基板としては、複数の絶縁層と導体層とを交互に積層した多層基板に凹状のキャビティを形成し、このキャビティ内に電子部品を実装することにより電子部品の高密度実装を可能としたものが知られている(例えば特許文献1〜3)。   As an electronic component mounting board, a concave cavity is formed in a multilayer substrate in which a plurality of insulating layers and conductor layers are alternately stacked, and electronic components are mounted in this cavity, enabling high-density mounting of electronic components. Is known (for example, Patent Documents 1 to 3).

特許文献1記載の電子部品実装基板は、多層基板の表裏両面に凹状のキャビティを形成し、この中に電子部品を収納している。また、特許文献2記載の電子部品実装基板は、凹状のキャビティの中に電子部品を実装するとともにそのキャビティを跨ぐように基板の表面に別の電子部品を実装している。また、特許文献3記載の電子部品実装基板では、多層基板に形成されたキャビティの底部にICチップが接着剤にて固定されているとともに、キャビティの側部に形成された段差部に抵抗またはコンデンサ等のチップ部品が設けられている。そして、このチップ部品の一方の電極がキャビティ側部の配線パターンに半田付けされ、他方の電極がワイヤを介してICチップに接続されている。
特開2005−354093号公報 特開2004−031413号公報 実開平6−77275号公報
In the electronic component mounting substrate described in Patent Document 1, concave cavities are formed on both front and back surfaces of a multilayer substrate, and the electronic components are accommodated therein. The electronic component mounting substrate described in Patent Document 2 mounts an electronic component in a concave cavity and mounts another electronic component on the surface of the substrate so as to straddle the cavity. Further, in the electronic component mounting substrate described in Patent Document 3, an IC chip is fixed to the bottom of the cavity formed in the multilayer substrate with an adhesive, and a resistor or a capacitor is formed on the step formed on the side of the cavity. Etc. are provided. One electrode of this chip component is soldered to the wiring pattern on the side of the cavity, and the other electrode is connected to the IC chip via a wire.
JP 2005-354093 A JP 2004-031413 A Japanese Utility Model Publication No. 6-77275

ところで、携帯電話やデジタルカメラなどの電子機器の小型化,多機能化が進んでおり、更なる電子部品実装基板の小型化及び薄型化が求められている。ところが、上記特許文献1〜3記載のいずれの電子部品実装方法においても、超小型の電子部品については問題が少ないが、比較的大サイズの電子部品、特に基板の厚み方向の寸法(背の高さ寸法)が大きい電子部品を取り付けると、基板表面からの部品の突出量が大きくなって電子部品実装基板の厚み方向の寸法が増加するため、電子機器の小型化及び薄型化に影響を及ぼすという問題点がある。   Incidentally, electronic devices such as mobile phones and digital cameras are becoming smaller and more multifunctional, and further downsizing and thinning of electronic component mounting boards are required. However, in any of the electronic component mounting methods described in Patent Documents 1 to 3, there are few problems with ultra-small electronic components, but relatively large electronic components, particularly dimensions in the thickness direction of the substrate (high height). When an electronic component with a large dimension) is attached, the amount of protrusion of the component from the substrate surface increases and the dimension in the thickness direction of the electronic component mounting board increases, which affects the downsizing and thinning of electronic devices. There is a problem.

本発明は、上記のような問題点を解決するためになされたもので、比較的高さ寸法が大きな部品も問題なく使用でき、部品選択の自由度が高い電子部品実装方法及びこれを用いた電子部品実装基板を提供することを目的とする。   The present invention has been made to solve the above-described problems, and a component having a relatively large height can be used without any problem, and an electronic component mounting method having a high degree of freedom in selecting a component and the same are used. An object is to provide an electronic component mounting board.

本発明の電子部品実装方法は、基板の厚み寸法と基板に取り付けられる電子部品の高さ寸法との合計寸法が、前記電子部品の基板表面からの突出量が一定となるように予め設定された所定寸法よりも大きく、かつこの大きい分の寸法が基板の厚み寸法を超えない場合に、前記大きい分の寸法に相当する深さの凹状のキャビティを基板に形成し、前記キャビティに電子部品を取り付けることを特徴とする。また、前記キャビティの側壁面に、前記電子部品とは別の電子部品を取り付けることを特徴とする。また、前記基板は、複数の絶縁層と導体層とを交互に積層した多層基板であることを特徴とする。   In the electronic component mounting method of the present invention, the total dimension of the thickness dimension of the substrate and the height dimension of the electronic component attached to the substrate is set in advance so that the protruding amount of the electronic component from the substrate surface is constant. If the larger dimension than the predetermined dimension does not exceed the thickness dimension of the substrate, a concave cavity having a depth corresponding to the larger dimension is formed in the substrate, and an electronic component is attached to the cavity. It is characterized by that. Further, an electronic component different from the electronic component is attached to the side wall surface of the cavity. Further, the substrate is a multilayer substrate in which a plurality of insulating layers and conductor layers are alternately laminated.

また、本発明の電子部品実装基板は、前記請求項1ないし3いずれか記載の電子部品実装方法を用い、電子部品を基板に高密度実装したことを特徴とする。   An electronic component mounting board according to the present invention is characterized in that the electronic component is mounted on the substrate at a high density by using the electronic component mounting method according to any one of the first to third aspects.

本発明の電子部品実装方法及びこれを用いた電子部品実装基板によれば、基板表面からの電子部品の突出量が所定範囲内に納まるように凹状のキャビティを基板に形成し、これに電子部品を取り付けるから、比較的高さ寸法が大きな部品も問題なく使用でき、部品選択の自由度を高めることができる。また、キャビティの側壁面に別の電子部品を取り付けるから、電子部品実装基板の高密度化に寄与できるとともに、関連する部品同士を近接して配置でき、例えばバイパスコンデンサなどを最短距離で接続することができ、信号授受の速度を大幅に高速化でき、接続距離が長いことに起因するノイズの発生も抑えることができる。また、前記基板は多層基板であるから、電子部品をキャビティの底面はもちろん側壁面にもジャンパー線などを用いることなく実装することができ、組立効率の向上と電子部品実装基板の高密度化とに寄与できる。   According to the electronic component mounting method and the electronic component mounting board using the same according to the present invention, a concave cavity is formed in the substrate so that the protruding amount of the electronic component from the surface of the substrate is within a predetermined range, and the electronic component is formed on the substrate. Therefore, a part having a relatively large height can be used without any problem, and the degree of freedom in selecting a part can be increased. In addition, since another electronic component is attached to the side wall surface of the cavity, it can contribute to higher density of the electronic component mounting board, and related components can be placed close to each other, for example, by connecting a bypass capacitor at the shortest distance. Thus, the signal transmission / reception speed can be greatly increased, and the occurrence of noise due to the long connection distance can be suppressed. In addition, since the substrate is a multilayer substrate, electronic components can be mounted not only on the bottom surface of the cavity but also on the side wall surface without using jumper wires, etc., improving assembly efficiency and increasing the density of the electronic component mounting substrate. Can contribute.

本発明を実施した第1実施形態である電子部品実装基板10は、図1に示すように、多層基板11と、この表面11a側に実装された比較的大型の電子部品12〜14,小型の電子部品15〜20と、裏面11b側に実装された比較的大型の電子部品21,22,小型の電子部品23〜27とからなる。なお、前記電子部品12〜14,21,22は、詳しくは後述する凹状のキャビティ31〜35に取り付けられ、前記電子部品15〜20は表面11aに、また電子部品23〜27は裏面11bにそれぞれ取り付けられている。   As shown in FIG. 1, an electronic component mounting substrate 10 according to a first embodiment of the present invention includes a multilayer substrate 11, relatively large electronic components 12 to 14 mounted on the surface 11a side, and a small size. It consists of electronic components 15 to 20 and relatively large electronic components 21 and 22 and small electronic components 23 to 27 mounted on the back surface 11b side. The electronic components 12 to 14, 21 and 22 are attached to concave cavities 31 to 35, which will be described in detail later. The electronic components 15 to 20 are on the front surface 11a, and the electronic components 23 to 27 are on the back surface 11b. It is attached.

前記多層基板11は、例えばプリプレグからなる複数の積層された絶縁層37a〜37fと、これらの間と表面に設けられ、回路パターンなどの金属箔からなる導体層38a〜38gとからなる。なお、プリプレグは、ガラス繊維等のシートに樹脂が含浸されたもので、加熱されることによって樹脂が溶け出し、加熱を止めてプリプレグの樹脂が硬化する際に、絶縁層37a〜37f,導体層38a〜38gが互いに接合される。   The multilayer substrate 11 includes a plurality of laminated insulating layers 37a to 37f made of, for example, prepreg, and conductor layers 38a to 38g made of metal foil such as a circuit pattern provided between and on the surface thereof. The prepreg is a sheet of glass fiber or the like impregnated with a resin. When heated, the resin melts, and when the resin of the prepreg is cured by stopping the heating, the insulating layers 37a to 37f, the conductor layer 38a-38g are joined together.

電子部品実装基板10は、多層基板11の裏面11bを基準として表面11a側に実装される電子部品12〜20の上端部までの厚み寸法A1を予め設定し、この厚み寸法A1以内に表面11a側の全ての電子部品X1i(i=1,2,・・・,m(mは正整数))の突出量が揃うように、多層基板11の厚み寸法Dを超えない範囲で電子部品X1iの背の高さ寸法C1iに応じて異なる深さ寸法B1iの凹状のキャビティP1iを多層基板11の表面11a側に形成する。   The electronic component mounting substrate 10 sets in advance a thickness dimension A1 to the upper end of the electronic components 12 to 20 mounted on the front surface 11a side with respect to the back surface 11b of the multilayer substrate 11, and the surface 11a side is within this thickness dimension A1. Of the electronic component X1i (i = 1, 2,..., M (m is a positive integer)) so that the protruding amount is uniform, the thickness of the electronic component X1i is within a range not exceeding the thickness dimension D of the multilayer substrate 11. A concave cavity P1i having a different depth dimension B1i according to the height dimension C1i is formed on the surface 11a side of the multilayer substrate 11.

なお、深さ寸法B1iは、厚み寸法Dを超えない範囲であるが、電子部品X1iの保持,電子部品X1iと導体層との接続,多層基板11の強度などの面で問題がない範囲、例えば厚み寸法Dの2/3までが好ましい。また、前記電子部品12〜20は電子部品X1iの具体例、また、前記キャビティ31〜33はキャビティP1iの具体例である。また、A1≧Dとし、A1=Dは、表面11aに電子部品15〜20を取り付けない場合である。   The depth dimension B1i is a range that does not exceed the thickness dimension D. However, the depth dimension B1i is within a range in which there are no problems in terms of holding the electronic component X1i, connecting the electronic component X1i and the conductor layer, strength of the multilayer substrate 11, Up to 2/3 of the thickness dimension D is preferable. The electronic components 12 to 20 are specific examples of the electronic component X1i, and the cavities 31 to 33 are specific examples of the cavity P1i. Further, A1 ≧ D, and A1 = D is a case where the electronic components 15 to 20 are not attached to the surface 11a.

ここで、電子部品13のように、電子部品X1iの背の高さ寸法C1iに対応する深さ寸法B1iが絶縁層の厚み分(電子部品13の場合には絶縁層37a,37bの厚み分)に相当する場合には、ちょうど導体層(電子部品13の場合には導体層38c)が露呈されるから、その露呈された導体層に電子部品X1iの電極を半田付けすればよいが、深さ寸法B1iが絶縁層の厚み分に相当しない場合(電子部品12,14の場合)には、そのままでは導体層は露呈しない。このような場合には、キャビティP1iの底部に導体層を設け、これを近傍の導体層(電子部品12の場合には導体層38d)と連結し、前記底部の導体層に電子部品X1iの電極を半田付けする。   Here, like the electronic component 13, the depth dimension B1i corresponding to the height C1i of the electronic component X1i is the thickness of the insulating layer (in the case of the electronic component 13, the thickness of the insulating layers 37a and 37b). Since the conductor layer (conductor layer 38c in the case of the electronic component 13) is exposed, the electrode of the electronic component X1i may be soldered to the exposed conductor layer. When the dimension B1i does not correspond to the thickness of the insulating layer (in the case of the electronic components 12 and 14), the conductor layer is not exposed as it is. In such a case, a conductor layer is provided at the bottom of the cavity P1i, and this is connected to a nearby conductor layer (conductor layer 38d in the case of the electronic component 12), and the electrode of the electronic component X1i is connected to the bottom conductor layer. Solder.

また、多層基板11の表面11aを基準として裏面11b側に実装される電子部品21〜27の上端部(図面では最下端部)までの厚み寸法A2を予め設定し、この厚み寸法A2以内に裏面11b側の全ての電子部品X2i(i=1,2,・・・,n(nは正整数))の突出量が揃うように、多層基板11の厚み寸法Dを超えない範囲で電子部品X2iの背の高さ寸法C2iに応じて異なる深さ寸法B2iの凹状のキャビティP2iを多層基板11の裏面11b側に形成する。   In addition, a thickness dimension A2 is set in advance to the upper end portions (lowermost end portions in the drawing) of the electronic components 21 to 27 mounted on the back surface 11b side with respect to the front surface 11a of the multilayer substrate 11, and the back surface is within this thickness dimension A2. The electronic component X2i within a range not exceeding the thickness dimension D of the multilayer substrate 11 so that the protruding amounts of all the electronic components X2i on the 11b side (i = 1, 2,..., N (n is a positive integer)) are uniform. A concave cavity P2i having a different depth dimension B2i is formed on the back surface 11b side of the multilayer substrate 11 in accordance with the back height dimension C2i.

なお、前記厚み寸法A2は、前記厚み寸法A1と同じであっても、また異なっていてもよい。また、前記深さ寸法B2iは、厚み寸法Dを超えない範囲であるが、電子部品X2iの保持,電子部品X2iと導体層との接続,多層基板11の強度などの面で問題がない範囲、例えば厚み寸法Dの2/3までが好ましい。また、電子部品21〜27は電子部品X2iの具体例、またキャビティ34,35はキャビティP2iの具体例である。また、A2≧Dとし、A2=Dは、裏面11bに電子部品23〜27を取り付けない場合である。以下、多層基板11の表面11a側の構成と裏面11b側の構成とは同じであるから、以下、表面11a側についてのみ説明する。   The thickness dimension A2 may be the same as or different from the thickness dimension A1. Further, the depth dimension B2i is in a range not exceeding the thickness dimension D, but there is no problem in terms of holding the electronic component X2i, connecting the electronic component X2i and the conductor layer, strength of the multilayer substrate 11, For example, up to 2/3 of the thickness dimension D is preferable. The electronic components 21 to 27 are specific examples of the electronic component X2i, and the cavities 34 and 35 are specific examples of the cavity P2i. Further, A2 ≧ D, and A2 = D is a case where the electronic components 23 to 27 are not attached to the back surface 11b. Hereinafter, since the configuration on the front surface 11a side and the configuration on the back surface 11b side of the multilayer substrate 11 are the same, only the front surface 11a side will be described below.

図2のフローチャートに示すように、まず1個目(1→i)(st1)の電子部品X1iの背の高さ寸法C1iが次の数式(1)を満たすか否かを調べる(st2)。高さ寸法C1iが数式(1)を満たす場合には、数式(2)を用いてキャビティP1iの深さ寸法B1iを求める(st3)。   As shown in the flowchart of FIG. 2, first, it is checked whether or not the height dimension C1i of the electronic component X1i of the first (1 → i) (st1) satisfies the following formula (1) (st2). When the height dimension C1i satisfies Expression (1), the depth dimension B1i of the cavity P1i is obtained using Expression (2) (st3).

A1<C1i+D ・・・(1)   A1 <C1i + D (1)

B1i=C1i+D−A1 ・・・(2)   B1i = C1i + D−A1 (2)

続いて、得られたキャビティP1iの深さ寸法B1iが次の数式(3)を満たす場合には(st4)、この深さ寸法B1iは有効であるが、キャビティP1iの深さ寸法B1iが数式(3)を満たさない場合には(st4)、キャビティP1iが貫通孔になり、電子部品X1iの実装(保持及び接続)が困難になるとともに、多層基板11の強度上も問題があるため、このような電子部品X1iは使用不可として除外する(st5)。   Subsequently, when the depth dimension B1i of the obtained cavity P1i satisfies the following mathematical formula (3) (st4), the depth dimension B1i is effective, but the depth dimension B1i of the cavity P1i is mathematical formula ( If 3) is not satisfied (st4), the cavity P1i becomes a through hole, and mounting (holding and connection) of the electronic component X1i becomes difficult, and there is also a problem in the strength of the multilayer substrate 11. Electronic parts X1i are excluded as unusable (st5).

B1i<D ・・・(3)   B1i <D (3)

また、電子部品X1iの背の高さ寸法C1iが数式(1)を満たさない場合には、深さ寸法B1iを「0」とする(st6)。この場合には、キャビティP1iを形成することなく、電子部品X1iを表面11aの導体層38aに取り付ける。また、この場合の電子部品X1iの具体例が電子部品15〜20であり、例えばサイズが2.0mm×1.25mm×0.5mmのフェライトビーズなどである。なお、本実施形態では、表面11aからの電子部品の突出量(A1−D)は、例えば1mm以下とする。   If the height C1i of the electronic component X1i does not satisfy Expression (1), the depth B1i is set to “0” (st6). In this case, the electronic component X1i is attached to the conductor layer 38a on the surface 11a without forming the cavity P1i. Further, specific examples of the electronic component X1i in this case are the electronic components 15 to 20, for example, ferrite beads having a size of 2.0 mm × 1.25 mm × 0.5 mm. In the present embodiment, the protruding amount (A1-D) of the electronic component from the surface 11a is, for example, 1 mm or less.

そして、2→iとiをインクリメントして(st7)、i=mとなるまで(st8)順次に全ての電子部品X1iについて、キャビティP1iの深さ寸法B1iを決定する。こうして決定された深さ寸法B1iのキャビティP1iを多層基板11に形成する。なお、キャビティP1iは、絶縁層37a〜37f及び導体層38a〜38gの各々に対応する開口を形成した後、絶縁層37a〜37f及び導体層38a〜38gを積層することにより形成される。   Then, 2 → i and i are incremented (st7), and the depth dimension B1i of the cavity P1i is sequentially determined for all the electronic components X1i until i = m (st8). A cavity P1i having a depth dimension B1i determined in this manner is formed in the multilayer substrate 11. The cavity P1i is formed by stacking the insulating layers 37a to 37f and the conductor layers 38a to 38g after forming openings corresponding to the insulating layers 37a to 37f and the conductor layers 38a to 38g.

同様に、裏面11b側のキャビティP2iの深さ寸法B2iを決定し、キャビティP2iを多層基板11に形成する。このように両面に電子部品X1i,X2iを実装した電子部品実装基板10の最大厚み寸法Qは、次の数式(4)で表わされる。   Similarly, the depth dimension B2i of the cavity P2i on the back surface 11b side is determined, and the cavity P2i is formed in the multilayer substrate 11. In this way, the maximum thickness dimension Q of the electronic component mounting board 10 on which the electronic components X1i and X2i are mounted on both surfaces is expressed by the following formula (4).

Q=A1+A2−D ・・・(4)   Q = A1 + A2-D (4)

このように本発明では多層基板11に背の高い電子部品12〜14を取り付けても、表面11aに実装された小型の電子部品15〜20と同程度までしか上方に突出しないので、多層基板11の厚み方向の寸法が大きく変動することはない。よって、この電子部品実装基板10が取り付けられる電子機器も小型化及び薄型化を維持することができる。また、大型の電子部品12〜14が筐体フレーム39に干渉するのを防止することができる。また同様に、裏面11b側の大型の電子部品21,22が筐体フレーム40に干渉するのを防止することもできる。   As described above, in the present invention, even when tall electronic components 12 to 14 are attached to the multilayer substrate 11, they protrude upward only to the same extent as the small electronic components 15 to 20 mounted on the surface 11 a. The dimension in the thickness direction does not fluctuate greatly. Therefore, the electronic device to which the electronic component mounting substrate 10 is attached can also be kept small and thin. In addition, the large electronic components 12 to 14 can be prevented from interfering with the housing frame 39. Similarly, the large electronic components 21 and 22 on the back surface 11 b side can be prevented from interfering with the housing frame 40.

また、電子部品12〜14の上端の高さが同じであるから、電子部品12〜14をキャビティ内に挿入する際の降下量を一定とすることができる。これにより、ロボットハンドによる全ての電子部品X1iの降下量を一定範囲内に納めることができるから、電子部品X1iの多層基板11へのマウント精度及び取付速度を向上することができる。   Moreover, since the heights of the upper ends of the electronic components 12 to 14 are the same, the amount of descent when the electronic components 12 to 14 are inserted into the cavity can be made constant. Thereby, since the amount of descent of all the electronic components X1i by the robot hand can be kept within a certain range, the mounting accuracy and the mounting speed of the electronic components X1i on the multilayer substrate 11 can be improved.

次に、第2実施形態の電子部品実装基板42について図3を参照して説明する。なお、第1実施形態と同じ部材には同じ符号を付して説明を省略する。電子部品実装基板42は、多層基板11に形成した凹状のキャビティ44の底面44aに大型の電子部品45を取り付ける他に、キャビティ44の4つの側壁面44b〜44eに、複数個の小型の電子部品46,47,48,49,・・・を取り付けたものである。なお、前記キャビティ44の深さ寸法は、第1実施形態と同様に決められる。   Next, the electronic component mounting substrate 42 of the second embodiment will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the same member as 1st Embodiment, and description is abbreviate | omitted. The electronic component mounting substrate 42 has a plurality of small electronic components on four side wall surfaces 44b to 44e in addition to attaching the large electronic component 45 to the bottom surface 44a of the concave cavity 44 formed in the multilayer substrate 11. 46, 47, 48, 49, ... are attached. The depth dimension of the cavity 44 is determined in the same manner as in the first embodiment.

前記電子部品46,47,・・・は、主に大型の電子部品45の動作を補助する機能などを有する小型の極性部品、例えば、0402(0.4mm×0.2mm×0.12mm)サイズのバイパスコンデンサや抵抗器などのチップ部品である。このように、電子部品45の動作に関連する電子部品46,47,・・・を電子部品45のすぐ近くに配置するので、電子部品45と電子部品46,47,・・・との信号の授受が高速に行なわれ、回路全体の動作の高速化に寄与できる。   The electronic components 46, 47,... Are small polar components mainly having a function of assisting the operation of the large electronic component 45, for example, 0402 (0.4 mm × 0.2 mm × 0.12 mm) size. Chip components such as bypass capacitors and resistors. As described above, since the electronic components 46, 47,... Related to the operation of the electronic component 45 are arranged in the immediate vicinity of the electronic component 45, signals of the electronic component 45 and the electronic components 46, 47,. Transfer is performed at high speed, which can contribute to speeding up the operation of the entire circuit.

前記電子部品46,47,・・・の多層基板11の層方向に対する取付角度は、側壁面44b〜44eの大きさ,部品形状(電極ピッチ),絶縁層37a〜37fの層間ピッチから決められる。例えば、前記電子部品46は、その両電極が導体層38bに半田付けされ、その長手方向が多層基板11の層方向に対して平行(取付角度0°)に取り付けられている。   The mounting angle of the electronic components 46, 47,... With respect to the layer direction of the multilayer substrate 11 is determined from the size of the side wall surfaces 44b to 44e, the component shape (electrode pitch), and the interlayer pitch of the insulating layers 37a to 37f. For example, both the electrodes of the electronic component 46 are soldered to the conductor layer 38 b, and the longitudinal direction thereof is attached parallel to the layer direction of the multilayer substrate 11 (attachment angle 0 °).

また、前記電子部品47,48は、絶縁層37bを跨いで導体層38bと38cとにそれぞれ半田付けされ、その長手方向が多層基板11の層方向に対して垂直(取付角度90°)に取り付けられている。また、前記電子部品49は、絶縁層37bを跨いで導体層38bと38cとに半田付けされ、その長手方向が多層基板11の層方向に対して斜め(取付角度45°)に取り付けられている。   The electronic components 47 and 48 are soldered to the conductor layers 38b and 38c across the insulating layer 37b, and the longitudinal direction thereof is attached perpendicularly to the layer direction of the multilayer substrate 11 (attachment angle 90 °). It has been. The electronic component 49 is soldered to the conductor layers 38b and 38c across the insulating layer 37b, and its longitudinal direction is attached obliquely to the layer direction of the multilayer substrate 11 (attachment angle 45 °). .

なお、電子部品が多層基板11の層方向に対して垂直の場合には、電子部品のプラス電極が上になる場合と下になる場合とがあるが、例えばプラス電極が上になる場合を取付角度90°とし、プラス電極が下になる場合を取付角度270°とする。   In addition, when the electronic component is perpendicular to the layer direction of the multilayer substrate 11, there are cases where the plus electrode of the electronic component is on the upper side and the lower side. The angle is 90 °, and the case where the plus electrode is down is the mounting angle 270 °.

このように、キャビティ44の側壁面44b〜44eに電子部品46,47,・・・を自由な角度で取り付けることができるので、例えばバイパスコンデンサなどを大型の電子部品45に最短距離で接続することができ、信号授受の速度を大幅に高速化でき、接続距離が長いことに起因するノイズの発生も抑えることができる。   As described above, since the electronic components 46, 47,... Can be attached to the side wall surfaces 44b to 44e of the cavity 44 at any angle, for example, a bypass capacitor or the like is connected to the large electronic component 45 at the shortest distance. Thus, the signal transmission / reception speed can be greatly increased, and the occurrence of noise due to the long connection distance can be suppressed.

なお、前記絶縁層37a〜37fに粘着性を有するゲルポリマなどの樹脂を混入することにより、キャビティ44の側壁面44b〜44eを構成する絶縁層37a,37b,37cに粘着性を持たせると、半田付けする前に電子部品46,47,・・・を側壁面44b〜44eに容易に仮止めすることができる。また、キャビティの側壁面から絶縁層の一部をキャビティ内に突出させ、電子部品を上下から挟持して仮固定してから半田付けするようにしてもよい。   When the insulating layers 37a, 37b, and 37c constituting the side wall surfaces 44b to 44e of the cavity 44 are made adhesive by mixing a resin such as an adhesive gel polymer into the insulating layers 37a to 37f, soldering is performed. The electronic components 46, 47,... Can be easily temporarily fixed to the side wall surfaces 44b to 44e before being attached. Alternatively, a part of the insulating layer may protrude from the side wall surface of the cavity into the cavity, and the electronic component may be sandwiched from above and below, temporarily fixed, and then soldered.

次に、第3実施形態の電子部品実装基板50について図4及び図5を参照して説明する。なお、第1,2実施形態と同じ部材には同じ符号を付して説明を省略する。電子部品実装基板50の多層基板11に形成したキャビティ52は、大型の電子部品53を取り付ける底部54が最も深く狭く、周辺に向かうにつれて徐々に浅く広くなるように、3個の段差部56,57,58を設けてある。なお、キャビティ52の深さ寸法は、第1実施形態と同様に決められる。   Next, an electronic component mounting board 50 according to a third embodiment will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to the same member as 1st, 2 embodiment, and description is abbreviate | omitted. The cavity 52 formed in the multilayer substrate 11 of the electronic component mounting substrate 50 has three step portions 56 and 57 so that the bottom 54 to which the large electronic component 53 is attached is deepest and narrow, and gradually becomes shallower and wider toward the periphery. , 58 are provided. The depth dimension of the cavity 52 is determined in the same manner as in the first embodiment.

前記段差部56〜58の各面には、セラミックコンデンサや抵抗器などのチップ部品である小型の電子部品61〜75がそれぞれ取り付けられている。このように、段差部56〜58を設けているため、底部54に近い電子部品が故障した場合でもその上方部(口に近い面)に取り付けた電子部品を取り外すことなく故障した部品を取り替えることができ、メンテナンス性に優れている。   Small electronic components 61 to 75, which are chip components such as ceramic capacitors and resistors, are attached to the respective surfaces of the step portions 56 to 58, respectively. Thus, since the step portions 56 to 58 are provided, even when an electronic component close to the bottom portion 54 fails, the failed component can be replaced without removing the electronic component attached to the upper portion (surface close to the mouth). It has excellent maintainability.

次に、第4実施形態の電子部品実装基板80について図6を参照して説明する。なお、第1〜3実施形態と同じ部材には同じ符号を付して説明を省略する。電子部品実装基板80の多層基板11に形成したキャビティ82は、前記第3実施形態と同様に、段差部84〜86を設け、この各面に小型の電子部品88〜94を取り付けるとともに、底部96に大型の電子部品97を取り付けている。一方、前記第3実施形態とは異なり、踊り場部98,99を広く形成して、ここに大型の電子部品101〜103を取り付けている。   Next, an electronic component mounting board 80 of the fourth embodiment will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the same member as 1st-3rd embodiment, and description is abbreviate | omitted. The cavity 82 formed in the multilayer substrate 11 of the electronic component mounting substrate 80 is provided with stepped portions 84 to 86 as in the third embodiment, and small electronic components 88 to 94 are attached to the respective surfaces, and a bottom portion 96 is provided. A large electronic component 97 is attached to the main body. On the other hand, unlike the said 3rd Embodiment, the landing parts 98 and 99 are formed widely, and the large sized electronic components 101-103 are attached here.

このような構成によれば、前記第3実施形態と同様に電子部品実装基板のメンテナンス性を向上できるとともに、電子部品実装基板の高密度化に寄与できる。なお、多層基板11の表面11aからの底部94及び踊り場部98,99までの深さ寸法は、第1実施形態と同様に、電子部品96,101〜103の表面11aからの突出量が一定となるように決められる。   According to such a configuration, the maintainability of the electronic component mounting board can be improved as in the third embodiment, and the electronic component mounting board can be increased in density. In addition, the depth dimension from the surface 11a of the multilayer substrate 11 to the bottom part 94 and the landings 98 and 99 is the same as in the first embodiment, and the protruding amount from the surface 11a of the electronic components 96 and 101 to 103 is constant. It is decided to become.

以上説明した実施形態では、電子部品の電極をキャビティの底部の導体層に半田付けしたが、本発明はこれに限定されることなく、例えばジャンパー線を用いてキャビティの口近傍の導体層に半田付けしてもよい。このようにすると、多層基板に限らず、凹状のキャビティを形成する程度の厚みを有する基板であれば、単層基板であっても本発明を適用することができる。   In the embodiment described above, the electrode of the electronic component is soldered to the conductor layer at the bottom of the cavity. However, the present invention is not limited to this, and soldering is performed on the conductor layer near the mouth of the cavity using, for example, a jumper wire. May be attached. In this case, the present invention can be applied to a single-layer substrate as long as the substrate has a thickness sufficient to form a concave cavity, not limited to a multilayer substrate.

また、上記実施形態では、多層基板の絶縁層の層数を6層としたが、本発明はこのような数に限定されないのは勿論である。また、キャビティの側壁面に取り付ける小型の電子部品は、複数の層を跨いで取り付けてもよく、また、その取付角度は、上記のものに限定されず、自由に設定可能である。   Moreover, in the said embodiment, although the number of layers of the insulating layer of the multilayer board | substrate was six layers, of course, this invention is not limited to such a number. In addition, the small electronic component attached to the side wall surface of the cavity may be attached across a plurality of layers, and the attachment angle is not limited to the above, and can be freely set.

本発明を適用した第1実施形態の電子部品実装基板の構成を示す断面図である。It is sectional drawing which shows the structure of the electronic component mounting board | substrate of 1st Embodiment to which this invention is applied. キャビティの深さを決める際の主なシーケンスを示すフローチャートである。It is a flowchart which shows the main sequences at the time of determining the depth of a cavity. キャビティの側壁面に電子部品を実装する第2実施形態の構成を示す斜視図である。It is a perspective view which shows the structure of 2nd Embodiment which mounts an electronic component on the side wall surface of a cavity. キャビティに段差部を設けた第3実施形態の構成を示す平面図である。It is a top view which shows the structure of 3rd Embodiment which provided the level | step-difference part in the cavity. 第3実施形態の構成を示す断面図である。It is sectional drawing which shows the structure of 3rd Embodiment. 段差部の踊り場部にも電子部品を実装した第4実施形態の構成を示す断面図である。It is sectional drawing which shows the structure of 4th Embodiment which mounted the electronic component also in the landing part of the level | step-difference part.

符号の説明Explanation of symbols

10,42,50,80 電子部品実装基板
11 多層基板
12〜27,47〜49,53,61〜75,88〜94,97,101〜103,X1i,X2i 電子部品
31〜35,44,52,82,P1i,P2i キャビティ
37a〜37f 絶縁層
38a〜38g 導体層
44b〜44e 側壁面
56〜58,84〜86 段差部
98,99 踊り場部
A1,A2,D 厚み寸法
B1i,B2i 深さ寸法
C1i,C2i 高さ寸法
Q 最大厚み寸法
10, 42, 50, 80 Electronic component mounting substrate 11 Multilayer substrate 12-27, 47-49, 53, 61-75, 88-94, 97, 101-103, X1i, X2i Electronic component 31-35, 44, 52 , 82, P1i, P2i Cavity 37a-37f Insulating layer 38a-38g Conductor layer 44b-44e Side wall surface 56-58, 84-86 Stepped part 98, 99 Landing part A1, A2, D Thickness dimension B1i, B2i Depth dimension C1i , C2i Height dimension Q Maximum thickness dimension

Claims (4)

基板の厚み寸法と基板に取り付けられる電子部品の高さ寸法との合計寸法が、前記電子部品の基板表面からの突出量が一定となるように予め設定された所定寸法よりも大きく、かつこの大きい分の寸法が基板の厚み寸法を超えない場合に、前記大きい分の寸法に相当する深さの凹状のキャビティを基板に形成し、前記キャビティに電子部品を取り付けることを特徴とする電子部品実装方法。   The total dimension of the thickness dimension of the board and the height dimension of the electronic component attached to the board is larger than and larger than a predetermined dimension set in advance so that the protruding amount of the electronic component from the board surface is constant. When the minute dimension does not exceed the thickness dimension of the substrate, a concave cavity having a depth corresponding to the large dimension is formed in the substrate, and the electronic component is attached to the cavity. . 前記キャビティの側壁面に、前記電子部品とは別の電子部品を取り付けることを特徴とする請求項1記載の電子部品実装方法。   The electronic component mounting method according to claim 1, wherein an electronic component different from the electronic component is attached to a side wall surface of the cavity. 前記基板は、複数の絶縁層と導体層とを交互に積層した多層基板であることを特徴とする請求項1または2記載の電子部品実装方法。   3. The electronic component mounting method according to claim 1, wherein the substrate is a multilayer substrate in which a plurality of insulating layers and conductor layers are alternately laminated. 前記請求項1ないし3いずれか記載の電子部品実装方法を用い、電子部品を基板に高密度実装したことを特徴とする電子部品実装基板。   4. An electronic component mounting board, wherein the electronic component is mounted on the substrate at a high density using the electronic component mounting method according to claim 1.
JP2007011834A 2007-01-22 2007-01-22 Electronic component packaging method and electronic component packaging apparatus using same Pending JP2008177506A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014116603A (en) * 2012-12-11 2014-06-26 Intel Corp Recessed mounting of discrete component on organic substrate
WO2014125973A1 (en) * 2013-02-12 2014-08-21 株式会社村田製作所 Resin multi-layer substrate with built-in component, and resin multi-layer substrate
JP2016092196A (en) * 2014-11-04 2016-05-23 日本特殊陶業株式会社 Wiring board
JP2018200990A (en) * 2017-05-29 2018-12-20 京セラ株式会社 Electronic apparatus
JP2020035898A (en) * 2018-08-30 2020-03-05 京セラ株式会社 Substrate for mounting electronic element, electronic apparatus, and electronic module

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014116603A (en) * 2012-12-11 2014-06-26 Intel Corp Recessed mounting of discrete component on organic substrate
WO2014125973A1 (en) * 2013-02-12 2014-08-21 株式会社村田製作所 Resin multi-layer substrate with built-in component, and resin multi-layer substrate
JPWO2014125973A1 (en) * 2013-02-12 2017-02-02 株式会社村田製作所 Component built-in resin multilayer board
JP2016092196A (en) * 2014-11-04 2016-05-23 日本特殊陶業株式会社 Wiring board
JP2018200990A (en) * 2017-05-29 2018-12-20 京セラ株式会社 Electronic apparatus
JP2020035898A (en) * 2018-08-30 2020-03-05 京セラ株式会社 Substrate for mounting electronic element, electronic apparatus, and electronic module
JP7210191B2 (en) 2018-08-30 2023-01-23 京セラ株式会社 Electronic device mounting board, electronic device, and electronic module

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