JP2008158533A - Active matrix substrate, its manufacturing method, and display unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix substrate in which a thin-film transistor array is formed on a plastic substrate. <P>SOLUTION: The active matrix substrate includes a plastic substrate 1, a plurality of scanning wires 2 formed on the plastic substrate 1, a plurality of signal wires 5 crossing the scanning wires 2 across an insulating film, and a plurality of thin film transistors 10 on the plastic substrate 1 for operating in response to a scanning signal on the corresponding scanning wire 2, and a plurality of pixel electrodes 14 electrically connected to the signal wires 5 through the thin film transistors 10, wherein the corresponding pixel electrodes 14 and the thin film transistors 10 are connected with each other by a conductive element 9, and the pixel electrodes 14 and the conductive element 9 crosses two adjacent different scanning wires, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an active matrix substrate and a manufacturing method thereof, and a display device using the active matrix substrate and a manufacturing method thereof.

  In recent years, liquid crystal display devices are used not only as image display elements for desktop computers and television devices used indoors, but also for mobile phones, notebook or laptop personal computers, portable televisions, digital cameras, digital camcorders, etc. It is also widely used as an information display element in various portable electronic devices and further in-vehicle electronic devices such as car navigation devices.

  Among various liquid crystal display devices, liquid crystal display devices driven by matrix electrodes are roughly classified into display devices that operate by passive matrix driving and display devices that operate by active matrix driving. Among these, in the active matrix display device, a switching element is provided for each pixel arranged in a matrix of rows and columns, and a plurality of signal wirings arranged so as to cross each other. In addition, the switching element is controlled using the scanning wiring, and a desired signal charge (data signal) can be given to the selected pixel electrode.

  First, a conventional active matrix display device will be described with reference to FIGS. 43 and 44. FIG. FIG. 43 shows a schematic configuration of a liquid crystal display device, and FIG. 44 shows a cross-sectional configuration of a typical liquid crystal panel.

  As shown in FIG. 43, the liquid crystal display device includes a liquid crystal panel 50 that spatially modulates light, a gate drive circuit 51 for selectively driving switching elements in the liquid crystal panel, and each pixel in the liquid crystal panel 50. A source drive circuit 52 for supplying signals to the electrodes, a gate driver / source driver 53, and the like are included.

  As shown in FIG. 44, the liquid crystal panel 50 includes a pair of transparent insulating substrates 54 and 55 formed of glass, and a liquid crystal layer (for example, a twisted nematic liquid crystal layer) 38 sandwiched between the substrates 54 and 55. , And a pair of polarizers 56 arranged outside these.

  A plurality of pixel electrodes 114 are arranged in a matrix on the side surface of the liquid crystal layer of the substrate 54, and a desired voltage is applied to a selected portion of the liquid crystal layer 38 by the pixel electrode 114 and the common transparent electrode 36 on the counter substrate 55. Can be applied. The pixel electrode 114 is connected to the source drive circuit 52 through a thin film transistor 110 formed on the substrate 54 and a signal wiring (not shown). The switching operation of the thin film transistor 110 is controlled by a scanning wiring formed on the substrate 54. This scanning wiring is connected to the gate driver circuit 51.

  On the other hand, a black color filter, color filters (R, G, B), and a common transparent electrode 36 are provided on the surface of the substrate 55 on the liquid crystal layer side.

  Both the liquid crystal layer sides of the substrate 54 and the substrate 55 are covered with an alignment film 37, and spacers 40 having a diameter of several μm are dispersed in the liquid crystal layer 38.

  The substrate 54 having the above-described configuration is generally referred to as an “active matrix substrate”. On the other hand, the substrate 55 is referred to as a “counter substrate”.

  Hereinafter, the structure of a conventional active matrix substrate will be described.

  FIG. 45A shows a layout of a unit pixel region in a conventional active matrix substrate, and FIG. 45B shows a cross section taken along line A-A ′.

  In the illustrated example, a plurality of scanning wirings 102 and a plurality of signal wirings 105 intersecting with the scanning wirings 102 are provided on the glass substrate 121. The scanning wirings 102 and the signal wirings 105 are located at different layer levels, and are separated by an insulating film 104 arranged in an intermediate layer thereof.

  A pixel electrode 114 made of a transparent conductive film or the like is formed in a rectangular region surrounded by the scanning wiring 102 and the signal wiring 105. The pixel electrode 114 receives signal charges from the signal wiring 105 through the thin film transistor 110 formed in the vicinity of the portion where the scanning wiring 102 and the signal wiring 105 intersect. An auxiliary capacitance wiring 113 parallel to the scanning wiring 102 is formed below the pixel electrode 114, and an auxiliary capacitance is formed between the pixel electrode 114 and the auxiliary capacitance wiring 113.

  The thin film transistor 110 includes a branch line (gate electrode 103) protruding vertically from the scanning wiring 102, a gate insulating film 104 covering the gate electrode 103, and an intrinsic semiconductor layer 106 overlapping the gate electrode 103 with the gate insulating film 104 interposed therebetween. In addition, an impurity-added semiconductor layer 107 formed on the intrinsic semiconductor layer 106 and a source electrode 108 and a drain electrode 109 connected to the source / drain region of the intrinsic semiconductor layer 106 through the impurity-added semiconductor layer 107 are provided. The source electrode 108 is a branch line protruding vertically from the signal wiring 105 and is formed integrally with the signal wiring 105.

  The drain electrode 109 is a conductive member that electrically connects the drain region of the thin film transistor 110 and the pixel electrode 114, and is formed together with the signal wiring 105 and the source electrode 108 by patterning a metal film. That is, in this example, the signal wiring 105, the source electrode 108, and the drain electrode 109 belong to the same layer, and the mutual arrangement relationship is defined by the mask pattern used in the photolithography process.

  The source electrode 108 and the drain electrode 109 are connected through the channel region of the intrinsic semiconductor layer 106, and the conduction state of the channel region is controlled by the potential of the gate electrode 103. In the case where the thin film transistor 110 is an n-channel type, the thin film transistor 110 is turned on by increasing the potential of the gate electrode 103 to be equal to or higher than the inversion threshold value of the transistor. At this time, since the source electrode 108 and the drain electrode 109 are electrically connected, charge is exchanged between the signal wiring 105 and the pixel electrode 114.

  In order for the thin film transistor 110 to operate normally, at least a part of the source electrode 108 and the drain electrode 109 needs to overlap the gate electrode 103. Since the line width of the gate electrode 103 is about 10 μm or less, the gate already formed on the substrate 121 in the photolithography process for forming the signal wiring 105, the source electrode 108, and the drain electrode 109 is used. It is necessary to perform alignment (hereinafter referred to as “alignment”) with respect to the electrode 103 with high accuracy. Usually, an alignment accuracy of ± several μm or less is required.

The area of the overlapping region between the gate electrode 103 and the drain electrode 109 defines a gate-drain capacitance C _gd that affects display characteristics, and the size of the gate-drain capacitance C _gd is within the substrate plane. If it varies, the display quality deteriorates. For this reason, in the actual production process, the alignment accuracy of the exposure apparatus is controlled to be ± 1 μm or less to keep the alignment deviation as small as possible.

  As described above, the alignment accuracy required for manufacturing an active matrix substrate in recent years is very high, and an exposure apparatus that meets this requirement has been developed and put into practical use. However, before an exposure apparatus with high alignment accuracy was put into practical use, the layout of the active matrix substrate was devised to increase the alignment margin in order to improve the manufacturing yield.

  FIG. 46 is a layout of an active matrix substrate proposed in an era when the alignment accuracy of the exposure apparatus was poor. In the illustrated configuration, the drain electrode 109 extends in parallel to the signal wiring 105 from the pixel electrode 114 and intersects the scanning wiring 102. The thin film transistor 110 is formed at a portion where the signal wiring 105 and the scanning wiring 102 intersect and in the vicinity thereof. In this example, neither the scanning wiring 102 nor the signal wiring 105 has a branch line, the scanning wiring 102 itself functions as a gate electrode, and a part of the signal wiring 105 functions as a source electrode 108.

  The active matrix substrate having the above configuration is manufactured as follows.

  First, after sequentially depositing the transparent conductive film 161 and the impurity-added semiconductor layer 107 on the glass substrate 101, the impurity-added semiconductor layer 107 and the transparent conductive film 161 are patterned using the first mask, and the signal wiring 105, the drain An electrode 109 and a pixel electrode 114 are formed.

  Next, after the intrinsic semiconductor layer 106, the gate insulating film 104, and the metal thin film 102 are sequentially stacked, the metal thin film 102, the gate insulating film 104, and the intrinsic semiconductor layer 106 are sequentially patterned using a second mask. Thus, the scanning wiring 102 and the auxiliary capacitance wiring 113 are formed from the metal thin film 102.

According to such a method, even if the position of the scanning wiring 102 to be formed later is slightly shifted from the signal wiring 105 and the drain electrode 109 that are formed first, the overlapping of the signal wiring 105 and the scanning wiring 102, and An overlap between the drain electrode 109 and the scanning wiring 102 can be ensured, and variations in the gate-drain capacitance C _gd are also suppressed.

  However, in the configuration of FIG. 46, the intrinsic semiconductor layer 106 exists at the lower level of the scanning wiring 102 and extends long linearly across all the signal wirings 105. Therefore, when a scanning signal (selection signal) for turning on the thin film transistor 110 is input to the scanning wiring 105, the drain electrode 109 shown in the figure and the signal wiring 105 located on the left side of the drain electrode 109 in the drawing. In addition to functioning as a channel region of the thin film transistor 110, the semiconductor layer 106 between the drain electrode 109 and the signal wiring 105 located on the right side of the drain electrode 109 in the drawing is also a channel region of the parasitic transistor. Will function as. For this reason, crosstalk occurs between pixels adjacent to the left and right, and a high display contrast, which is a feature of the active matrix liquid crystal display device, cannot be achieved.

In order to solve the above problem, an active matrix substrate having a configuration as shown in FIG. 47 has been proposed (Patent Document 1). The basic structure of this active matrix substrate is the same as the basic structure of the active matrix substrate shown in FIG. The difference is that the scanning line 102 is not provided with a branch line (gate electrode 103), and the scanning line 102 that extends linearly functions as a gate electrode, and the drain electrode 109 is parallel to the signal line 105. It is in the extending point. By adopting such a configuration, even if slight misalignment, since the thin film transistor 110 is operating normally, also does not change the area of the overlapping region between the drain electrode 109 and the scanning lines 102, the variation of the capacitance C _gd Can be suppressed.

  47, the alignment margin can be expanded to about 10 to 20 μm. However, since most of the exposure apparatuses currently used for manufacturing the active matrix substrate achieve alignment accuracy within ± 1 μm, the structure shown in FIG. 47 is not adopted in the end. For the purpose of facilitating correction at the time of occurrence, the structure of FIG. 45 is often adopted.

In addition, a structure in which a pixel electrode is provided on an interlayer insulating film, the pixel electrode and the signal wiring are formed in different layers, and the pixel electrode is overlaid on the signal wiring has been proposed (Patent Document 2, etc.). In such a configuration, the pixel electrode and the signal wiring are formed in different layers, and the gap between the pixel electrode and the signal wiring can be eliminated, so that the area (aperture ratio) of the pixel electrode can be expanded, The power consumption of the liquid crystal display device can be suppressed.
JP-A-61-108171 JP 63-279228 A

  In recent years, in order to reduce the weight of electronic devices, it has been attempted to manufacture a liquid crystal display device using a plastic substrate that is lighter than the glass substrate instead of the glass substrate.

  However, the dimensions of the plastic substrate greatly change during the manufacturing process, and the amount of change varies depending on the process, which causes a great hindrance in practical use.

  The rate of dimensional change in the direction parallel to the main surface of the plastic substrate (hereinafter referred to as “substrate expansion / contraction rate”) is strongly influenced by the processing temperature during the manufacturing process and the amount of moisture absorbed by the plastic substrate. For example, the substrate expansion / contraction rate due to temperature is 3 to 5 ppm / ° C. for a glass substrate, whereas it is 50 to 100 ppm / ° C. for a plastic substrate. In the case of a plastic substrate, the substrate expansion / contraction rate due to moisture absorption reaches 3000 ppm.

  The substrate expansion / contraction rate of 3000 ppm is the maximum value that can be generated through all the steps in the manufacturing process. The inventor of the present application actually performs a process of fabricating a thin film transistor on a plastic substrate in order to evaluate an actual shift amount of the mask alignment in the photolithography process, and measures a substrate expansion / contraction ratio generated between the two photolithography processes. did. As a result, it was found that substrate expansion and contraction of about 500 to 1000 ppm occurred between photolithography processes requiring mask alignment.

  If such a size of the substrate expansion / contraction occurs in a 5-inch diagonal plastic substrate, the substrate size varies by 64 μm to 128 μm. If the substrate size fluctuates in such a range, the conventional active matrix substrate manufacturing method cannot manufacture a thin film transistor that operates normally.

  The inventor has evaluated the alignment margin that can be realized with the conventional structure of FIG. FIG. 48 shows a layout when an alignment margin corresponding to the line width of the signal wiring 105 is given to the basic structure of FIG. Based on this layout, the amount of expansion / contraction of the substrate that can be handled by the active matrix substrate having the conventional structure shown in FIG. The results are listed in Table 1 below.

  As can be seen from Table 1, for example, in an active matrix substrate having pixels with a pixel pitch of 250 μm, only an alignment margin of ± 14 μm or less can be obtained. With such an alignment margin, only a substrate expansion / contraction rate of 220 ppm or less can be handled.

  As can be seen from the above, as long as the conventional configuration is adopted, an active matrix substrate cannot be manufactured using a plastic substrate, and the active matrix substrate is formed using a glass substrate that is weak against impact and difficult to reduce in weight. There is no choice but to manufacture.

  The present invention has been made in view of the above points, and its main object is to produce an active matrix substrate that does not cause problems due to misalignment even when a substrate having a large expansion / contraction ratio such as a plastic substrate is used. It is to provide a method.

  Another object of the present invention is to provide an active matrix substrate in which a thin film transistor array is integrated on a plastic substrate.

  Still another object of the present invention is to provide a display device manufactured using the active matrix substrate.

  An active matrix substrate according to the present invention is formed on a substrate, a plurality of scanning wirings formed on the substrate, a plurality of signal wirings crossing the scanning wirings through an insulating film, and correspondingly An active matrix substrate including a plurality of thin film transistors that operate in response to a scanning signal on a scanning wiring, and a plurality of pixel electrodes that can be electrically connected to a corresponding signal wiring through the thin film transistor, The electrode and the thin film transistor corresponding to the electrode are interconnected by a conductive member, and the pixel electrode and the conductive member intersect with different adjacent scanning lines.

  Another active matrix substrate according to the present invention includes a substrate, a plurality of scanning wirings formed on the substrate, a plurality of auxiliary capacitance wirings, and a plurality of scanning wirings and auxiliary capacitance wirings intersecting with each other through an insulating film. Signal wiring, a plurality of thin film transistors formed on the substrate and operating in response to a signal applied to the corresponding scanning wiring, and a plurality of pixels that can be electrically connected to the corresponding signal wiring through the thin film transistor Each pixel electrode and the corresponding thin film transistor are connected to each other by a conductive member, and the pixel electrode and the conductive member are adjacent to each other in different scans. In addition to intersecting with the wiring, it also intersects with a different adjacent auxiliary capacitance wiring.

  An active matrix substrate according to the present invention includes a substrate, a plurality of scanning wirings formed on the substrate, a plurality of auxiliary capacitance wirings, and a plurality of intersections with the scanning wirings and auxiliary capacitance wirings via a first insulating film. A plurality of thin film transistors that are formed on the substrate and operate in response to a signal applied to the corresponding scanning wiring, and a plurality of thin film transistors that can be electrically connected to the corresponding signal wiring through the thin film transistor An active device comprising: a lower pixel electrode; and a plurality of upper pixel electrodes disposed on the lower pixel electrode through a second insulating film and electrically connected to the lower pixel electrode through a contact hole In the matrix substrate, the signal wiring, the conductive member, and the lower pixel electrode are all formed by patterning the same conductive film, and each pixel electrode And the thin film transistors corresponding thereto are connected to each other by a conductive member, and the lower pixel electrode and the conductive member intersect with different adjacent scanning lines, and are adjacent to different auxiliary capacitance lines. It also intersects.

  An active matrix substrate according to the present invention is formed on a substrate, a plurality of scanning wirings formed on the substrate, a plurality of signal wirings crossing the scanning wirings via a first insulating film, and the substrate. A plurality of thin film transistors that operate in response to a signal applied to a corresponding scanning line; a plurality of lower layer pixel electrodes that can be electrically connected to the corresponding signal line through the thin film transistor; and a second insulating film. An active matrix substrate having a plurality of upper layer pixel electrodes electrically connected to the lower layer pixel electrodes through contact holes, the signal line, The conductive member and the lower pixel electrode are both formed by patterning the same conductive film, and are composed of the lower pixel electrode and the upper pixel electrode. Pixel electrodes, and, the thin film transistor corresponding thereto, are connected to each other by the conductive member, the lower pixel electrode and the conductive member, respectively, intersect the adjacent different scanning lines.

  An active matrix substrate according to the present invention includes a substrate, a plurality of scanning wirings formed on the substrate, a plurality of auxiliary capacitance wirings, and a plurality of signal wirings crossing the scanning wirings and the auxiliary capacitance wirings through an insulating film. A plurality of thin film transistors which are formed on the substrate and operate in response to a signal applied to a corresponding scanning line, and a plurality of lower layer pixel electrodes which can be electrically connected to the corresponding signal line through the thin film transistor And an active matrix substrate including a plurality of upper layer pixel electrodes that are disposed on an upper layer of the lower layer pixel electrode through an insulating film and electrically connected to the lower layer pixel electrode through a contact hole, The signal wiring, the conductive member, and the lower pixel electrode are all formed by patterning the same conductive film, and the lower pixel electrode and the lower pixel electrode are formed. The pixel electrode constituted by the upper layer pixel electrode and the thin film transistor corresponding thereto are connected to each other by a conductive member, and one of the adjacent scanning wiring and auxiliary capacitance wiring intersects the lower layer pixel electrode. The other crosses the conductive member.

  In a preferred embodiment, the device includes a source electrode that branches from the signal wiring and intersects the scanning wiring, and the intersection between the conductive member and the scanning wiring includes an intersection between the signal wiring and the scanning wiring, and the scanning wiring. It is sandwiched at the intersection of the source electrode and the scanning wiring.

  In a preferred embodiment, a distance between the signal wiring and the conductive member is substantially equal to a distance between the conductive member and the source electrode.

  In a preferred embodiment, the channel portion of the thin film transistor is located approximately at the center of the adjacent signal wiring.

  In a preferred embodiment, a channel portion of the thin film transistor is covered with the upper layer pixel electrode.

  In a preferred embodiment, the semiconductor layer of each thin film transistor is formed in a self-aligned manner with respect to the scanning wiring, and the signal wiring and the conductive member are arranged so as to intersect the semiconductor layer.

  In a preferred embodiment, the signal wiring and the conductive member are arranged so as to cross over the semiconductor layer, and a channel protection layer formed in a self-aligned manner with respect to the scanning wiring in the channel region of the semiconductor layer Covered by.

  In a preferred embodiment, a side surface parallel to a direction in which the signal wiring and the conductive member extend out of the side surfaces of the channel protective layer is aligned with the outer side surface of the signal wiring and the conductive member.

  In a preferred embodiment, a distance between two side surfaces parallel to a direction in which the scanning wiring extends among side surfaces of the channel protective layer is narrower than a line width of the scanning wiring.

  In a preferred embodiment, the conductive member extends from a pixel electrode connected to the conductive member in a direction parallel to the signal wiring, and is connected to the conductive member from a tip of the conductive member. The distance to the opposite end of the pixel electrode is longer than 1 times the scanning wiring interval and less than 2 times the scanning wiring interval.

  In a preferred embodiment, each of the signal wiring, the conductive member, and the pixel electrode includes a conductive layer formed by patterning the same conductive film.

  In a preferred embodiment, each of the signal wiring, the conductive member, and the pixel electrode includes a transparent conductive layer formed by patterning the same transparent conductive film, and is included in the signal wiring. A film having a light shielding property is disposed on the transparent conductive layer.

  In a preferred embodiment, the light-shielding film has an electric resistivity made of a metal lower than an electric resistivity of the transparent conductive layer.

  In a preferred embodiment, the scanning wiring and the signal wiring do not have a portion protruding in a direction parallel to the surface of the substrate in the display region.

  In a preferred embodiment, the scanning wiring is made of a light shielding metal.

  In a preferred embodiment, each of the plurality of scanning wirings has a slit-like opening that can transmit light at least in a region where the thin film transistor is formed.

  In a preferred embodiment, each of the plurality of scanning wirings is separated into a plurality of wiring portions at least in a region where the thin film transistor is formed.

  In a preferred embodiment, the line width of each of the plurality of wiring portions is such that after forming a negative photosensitive resin layer covering the scanning wiring, the substrate is irradiated with light from the back side of the substrate, thereby When a part of the negative photosensitive resin layer is exposed, the diffraction of the light is such that substantially all of the negative photosensitive resin layer located on the plurality of wiring portions can be exposed. is there.

  In a preferred embodiment, the expansion ratio of the substrate with respect to a direction parallel to the signal wiring is smaller than the expansion ratio of the substrate with respect to a direction perpendicular to the signal wiring. The arrangement relationship is defined.

  In a preferred embodiment, the plurality of scanning lines are extended outward from the display area, and the length of the extension of each scanning line is larger than the scanning line pitch.

  In a preferred embodiment, a color filter is formed on the pixel electrode.

  In a preferred embodiment, the substrate is made of plastic.

  An active matrix substrate according to the present invention includes a plastic substrate, a first scanning wiring formed on the plastic substrate, and a first scanning wiring formed on the plastic substrate and arranged in parallel to the first scanning wiring. Two scanning wirings, a third scanning wiring formed on the plastic substrate and arranged in parallel to the second scanning wiring, and the first to third scanning wirings through an insulating film, A signal wiring that intersects, a first pixel electrode that crosses the first scanning wiring, a second pixel electrode that crosses the second scanning wiring, and the second scanning wiring are formed in a self-aligned manner. The first thin film transistor and a second thin film transistor formed in a self-aligned manner with respect to the third scanning line, and the first pixel electrode crosses the second scanning line. Conductive members Thus connected to the first thin film transistor, the second pixel electrode is connected to the second thin film transistor by a second conductive member across said third scanning line.

  A display device of the present invention includes any one of the active matrix substrates described above, a substrate facing the active matrix substrate, and a light modulation layer positioned between the active matrix substrate and the counter substrate. .

  A portable electronic device according to the present invention includes the display device.

  An active matrix substrate manufacturing method according to the present invention includes a step of forming a plurality of scanning lines on a substrate, a step of forming an insulating film covering the scanning lines, a step of forming a semiconductor layer on the insulating film, A step of forming a positive resist layer on the semiconductor layer, and irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer and then developing and aligning with the scanning wiring A step of forming a first resist mask above the scanning wiring; and a portion of the semiconductor layer that is not covered by the first resist mask is removed to include a portion that functions as a semiconductor region of the thin film transistor Forming a semiconductor layer in a self-aligned manner with respect to the scanning wiring; removing the first resist mask; and guiding the semiconductor layer so as to cover the linear semiconductor layer. A process of depositing a film and patterning the conductive film using a second resist mask to form a signal wiring and a pixel electrode crossing the scanning wiring, and from the pixel electrode to the signal wiring in parallel A conductive member intersecting with the scanning wiring adjacent to the scanning wiring intersecting with the pixel electrode is formed, and further, by patterning the linear semiconductor layer, the signal wiring and the conductive member are disposed under the signal wiring and the conductive member. Forming a semiconductor region of the thin film transistor.

  In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes, as the second resist mask, a relatively thick portion that defines the signal wiring and the conductive member, and the signal wiring and the conductive member. Forming a resist pattern having a relatively thin portion defining a gap region, etching a portion of the conductive film and the linear semiconductor layer not covered with the resist pattern, and the resist Removing a relatively thin portion of the pattern; and etching the portion of the conductive film covered by the relatively thin portion of the resist pattern to form the signal wiring and the conductive member; Is included.

  Another method of manufacturing an active matrix substrate according to the present invention includes a step of forming a plurality of scanning lines on the substrate, a step of forming an insulating film covering the scanning lines, and a step of forming a semiconductor layer on the insulating film. And forming a positive resist layer on the semiconductor layer; irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer; Forming a matched first resist mask above the scan wiring; and removing a portion of the semiconductor layer not covered by the first resist mask to include a portion functioning as a semiconductor region of the thin film transistor Forming a linear semiconductor layer in a self-aligned manner with respect to the scanning wiring; removing the first resist mask; and covering the linear semiconductor layer A step of depositing a transparent conductive film, a step of depositing a light shielding film on the transparent conductive film, and patterning the light shielding film and the transparent conductive film using a second resist mask, thereby crossing the scanning wiring. Forming a signal line and a pixel electrode, extending in parallel to the signal line from the pixel electrode, forming a conductive member that intersects a scan line adjacent to the scan line intersected by the pixel electrode; and Forming a semiconductor region of the thin film transistor under the signal wiring and the conductive member by patterning a linear semiconductor layer; applying a negative photosensitive resin material on the substrate; and a back surface of the substrate The substrate is irradiated with light from the side, thereby exposing the negative photosensitive resin material, and then developing to remove non-photosensitive portions and Comprising a step of forming a click matrix.

  In a preferred embodiment, when exposing the negative photosensitive resin material, the signal wiring, the conductive member, and the semiconductor of the thin film transistor are transmitted using light that passes through the region where the scanning wiring and the light shielding film are not formed. The negative photosensitive resin material located on the area is exposed to light so that the area where the pixel electrode is not formed is covered with the black matrix.

  In a preferred embodiment, a portion of the light shielding film that is not covered with the black matrix is etched to form a light transmitting region on the pixel electrode.

  In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes, as the second resist mask, a relatively thick portion that defines the signal wiring and the conductive member, and the signal wiring and the conductive member. Forming a resist pattern having a relatively thin portion defining a gap region, etching a portion of the conductive film and the linear semiconductor layer not covered with the resist pattern, and the resist Removing a relatively thin portion of the pattern; and etching the portion of the conductive film covered by the relatively thin portion of the resist pattern to form the signal wiring and the conductive member; Is included.

  An active matrix substrate manufacturing method according to the present invention includes a step of forming a plurality of scanning lines on a substrate, a step of forming an insulating film covering the scanning lines, a step of forming a semiconductor layer on the insulating film, Forming a channel protective layer on the semiconductor layer; forming a first positive resist layer on the channel protective layer; and irradiating the substrate with light from the back side of the substrate, thereby Forming a first resist mask aligned with the scanning wiring by developing after exposing the first positive resist layer; and developing the first resist mask out of the channel protective layer. Removing a portion that is not covered by a channel, and forming a channel protective layer having a line width narrower than the line width of the scanning wiring in a self-aligned manner with respect to the scanning wiring; Depositing a contact layer so as to cover the protective layer and the semiconductor layer; forming a second positive resist layer on the contact layer; irradiating the substrate with light from the back side of the substrate; Forming a second resist mask aligned with the scanning wiring by development after exposing the second positive resist layer by developing, and the first of the contact layer and the semiconductor layer. Removing a portion not covered by the resist mask of 2 and forming a linear contact layer and a linear semiconductor layer including a portion functioning as a semiconductor region of the thin film transistor in a self-aligned manner with respect to the scanning wiring; A step of removing the second resist mask, a step of depositing a conductive film so as to cover the linear contact layer, and a third resist mask. By patterning the conductive film, a signal wiring and a pixel electrode intersecting with the scanning wiring are formed, and the scanning wiring extending from the pixel electrode in parallel to the signal wiring and intersecting with the pixel electrode is formed. By forming a conductive member that intersects with an adjacent scanning line, and further patterning the linear contact layer, channel protective layer, and semiconductor layer, the channel protective film has an upper surface below the signal line and conductive member. Forming a partially covered semiconductor region of the thin film transistor.

  In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes, as the third resist mask, a relatively thick portion that defines the signal wiring and the conductive member, and the signal wiring and the conductive member. Forming a resist pattern having a relatively thin portion that defines a gap region; and covering the resist pattern among the conductive film, the linear contact layer, the linear channel protective layer, and the linear semiconductor layer. A step of etching a portion that is not covered, a step of removing a relatively thin portion of the resist pattern, and a portion of the conductive film and contact layer that is covered by a relatively thin portion of the resist pattern. Etching and separating the signal wiring and the conductive member.

  An active matrix substrate manufacturing method according to the present invention includes a step of forming a plurality of scanning lines on a substrate, a step of forming an insulating film covering the scanning lines, a step of forming a semiconductor layer on the insulating film, A step of forming a channel protective layer on the semiconductor layer; a step of forming a positive resist layer on the channel protective layer; and irradiating the substrate with light from a back surface side of the substrate, whereby the positive resist Forming a first resist mask aligned with the scanning wiring by developing after exposing the layer, and a portion of the channel protective layer not covered by the first resist mask Forming a channel protective layer in a self-aligned manner with respect to the scanning wiring, and depositing a contact layer so as to cover the channel protective layer and the semiconductor layer Forming a signal wiring and a pixel electrode crossing the scanning wiring by patterning the conductive film using a second resist mask, and a step of depositing a conductive film so as to cover the contact layer. And forming a conductive member extending from the pixel electrode along the signal wiring and intersecting a scanning wiring adjacent to the scanning wiring intersecting with the pixel electrode, and further, the contact layer, the channel protective layer, And patterning the semiconductor layer to form a semiconductor region of the thin film transistor whose upper surface is covered with the channel protective film below the signal wiring and the conductive member.

  In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes, as the second resist mask, a relatively thick portion that defines the signal wiring and the conductive member, and the signal wiring and the conductive member. Forming a resist pattern having a relatively thin portion that defines a gap region, and etching a portion of the conductive film, contact layer, channel protective layer, and semiconductor layer that is not covered with the resist pattern; A step of removing a relatively thin portion of the resist pattern; and etching a portion of the conductive film and the contact layer that is covered with a relatively thin portion of the resist pattern, And forming the conductive member separately.

  In a preferred embodiment, before forming the contact layer, the semiconductor layer is formed in a self-aligned manner with respect to the scanning wiring by a backside exposure method.

  In a preferred embodiment, after removing a relatively thin portion of the resist pattern, when etching a portion of the conductive film and the contact layer covered by the relatively thin portion of the resist pattern, The exposed portion of the semiconductor layer is etched to leave a semiconductor region of the thin film transistor below the channel protective layer.

  Still another active matrix substrate manufacturing method according to the present invention includes a step of forming a semiconductor film on a substrate, a step of forming a first conductive film on the semiconductor film, the first conductive film and the semiconductor film. By patterning, a plurality of signal lines, a plurality of pixel electrodes, and a conductive member extending from each pixel electrode along the signal lines are formed, and the region located between the signal lines and the conductive member Leaving the semiconductor film without removing, forming an insulating film on the substrate, forming a second conductive film on the insulating film, patterning the second conductive film, A plurality of scanning wirings intersecting the wiring, the pixel electrode, and the conductive member are formed, and the running film is included in the semiconductor film located in a region between the signal wiring and the conductive member. Comprising a step of etching portions other than the portion located below the wire.

  In a preferred embodiment, the step of patterning the first conductive film and the semiconductor film includes a relatively thick portion that defines the signal wiring, the pixel electrode, and the conductive member, the signal wiring, and the conductive member. Forming a resist mask having a relatively thin portion defining a region between the first conductive film and the semiconductor film, and etching a portion not covered by the resist mask; Removing the relatively thin portion from the resist mask; and etching the portion of the first conductive film covered by the relatively thin portion of the resist mask.

  A method of manufacturing an active matrix substrate includes a step of forming a gate electrode on a substrate, a step of forming a gate insulating film covering the gate electrode, a step of forming a semiconductor layer on the gate insulating film, and the semiconductor layer Forming a positive resist layer thereon; and irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer, and then developing the first resist layer aligned with the gate electrode. Forming a resist mask above the gate electrode; removing a portion of the semiconductor layer that is not covered by the first resist mask; and providing a semiconductor layer including a portion functioning as a semiconductor region of a thin film transistor to the gate Forming in a self-aligned manner with respect to the electrode; removing the first resist mask; and a conductive film so as to cover the semiconductor layer A source electrode and a drain electrode intersecting with the gate electrode are formed by patterning the conductive film using a second resist mask using a deposition step, and further, the source layer is patterned by patterning the semiconductor layer. Forming a semiconductor region of the thin film transistor below the electrode and the drain electrode.

  In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes, as the second resist mask, a relatively thick portion that defines the source electrode and the drain electrode, and the source electrode and the drain electrode. Forming a resist pattern having a relatively thin portion that defines a gap region; etching a portion of the conductive film and the semiconductor layer that is not covered with the resist pattern; and Removing a relatively thin portion; and etching a portion of the conductive film covered by a relatively thin portion of the resist pattern to form the source electrode and the drain electrode. .

  In a preferred embodiment, the source electrode is a part of a signal wiring extending linearly so as to intersect the scanning wiring, and the drain electrode extends in parallel from the pixel electrode along the signal wiring. .

  Still another active matrix substrate manufacturing method according to the present invention includes a step of forming a gate electrode on a substrate, a step of forming a gate insulating film covering the gate electrode, and forming a semiconductor layer on the gate insulating film. A step, a step of forming a channel protective layer on the semiconductor layer, a step of forming a first positive resist layer on the channel protective layer, irradiating the substrate with light from the back side of the substrate, Thereby, after exposing the first positive resist layer, by developing, a first resist mask aligned with the gate electrode is formed above the gate electrode, and the first of the channel protective layers is the first resist mask. Removing the portion not covered by the resist mask and disposing the channel protective layer in a self-aligned manner with respect to the gate electrode; and Depositing a contact layer so as to cover the semiconductor layer; forming a second positive resist layer on the contact layer; and irradiating the substrate with light from the back side of the substrate, thereby A step of forming a second resist mask aligned with the gate electrode by developing after exposing the second positive resist layer, and the second resist of the contact layer and the semiconductor layer. Removing the portion not covered by the mask and forming a semiconductor layer including a contact layer, a channel protective layer, and a portion functioning as a semiconductor region of the thin film transistor in a self-aligned manner with respect to the gate electrode; A step of removing the resist mask, a step of depositing a conductive film so as to cover the contact layer, and a third resist mask By patterning the conductive film, a source electrode and a drain electrode intersecting the gate electrode are formed, and by further patterning the contact layer, the channel protective layer, and the semiconductor layer, the source electrode and the drain electrode are formed. Forming a semiconductor region of the thin film transistor, the upper surface of which is partially covered with the channel protective film.

  In a preferred embodiment, the step of forming a semiconductor layer of the thin film transistor includes, as the third resist mask, a relatively thick portion that defines the source electrode and the drain electrode, and the source electrode and the drain electrode. Forming a resist pattern having a relatively thin portion that defines a gap region; and etching a portion of the conductive film, contact layer, and semiconductor layer that is not covered with the resist pattern; Removing a relatively thin portion of the resist pattern; and etching a portion of the conductive film and the contact layer covered by a relatively thin portion of the resist pattern to form the source electrode and the drain electrode. And forming them separately.

  In a preferred embodiment, the width of the channel protective layer is set narrower than the width of the semiconductor region.

  An active matrix substrate manufacturing method according to the present invention includes a step of forming a gate electrode on a substrate, a step of forming a gate insulating film covering the gate electrode, a step of forming a semiconductor layer on the gate insulating film, A step of forming a channel protective layer on the semiconductor layer; a step of forming a positive resist layer on the channel protective layer; and irradiating the substrate with light from a back surface side of the substrate, whereby the positive resist Forming a first resist mask aligned with the gate electrode by developing after exposing the layer; and a portion of the channel protective layer not covered by the first resist mask. And the channel protective layer is disposed in a self-aligned manner with respect to the gate electrode, and the channel protective layer and the semiconductor layer are covered. Depositing a contact layer; depositing a conductive film so as to cover the contact layer; and patterning the conductive film using a second resist mask to thereby form a source electrode and a drain intersecting the gate electrode The semiconductor of the thin film transistor in which an upper surface is partially covered with the channel protective film below the source electrode and the drain electrode by forming an electrode and further patterning the contact layer, the channel protective layer, and the semiconductor layer Forming a region.

  In a preferred embodiment, the step of forming a semiconductor region of the thin film transistor includes, as the second resist mask, a relatively thick portion that defines the source electrode and the drain electrode, and the source electrode and the drain electrode. Forming a resist pattern having a relatively thin portion that defines a gap region; and etching a portion of the conductive film, contact layer, and semiconductor layer that is not covered with the resist pattern; Removing the relatively thin portion of the resist pattern; and etching the portion of the conductive film and the contact layer that is covered by the relatively thin portion of the resist pattern to form the signal wiring and the conductive member And separately forming.

  In a preferred embodiment, the semiconductor layer is formed in a self-aligned manner with respect to the gate electrode by a backside exposure method before the contact layer is formed.

  In a preferred embodiment, after removing a relatively thin portion of the resist pattern, when etching a portion of the conductive film and the contact layer covered by the relatively thin portion of the resist pattern, The exposed portion of the semiconductor layer is etched to leave a semiconductor region of the thin film transistor below the channel protective layer.

  The thin film transistor of the present invention includes a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and a semiconductor formed above the gate electrode through the gate insulating film. A source electrode formed so as to intersect with the semiconductor layer, and a drain electrode formed so as to intersect with the semiconductor layer. Side surfaces parallel to the extending direction are aligned with the outer side surfaces of the source electrode and the drain electrode.

  In a preferred embodiment, a side surface parallel to a direction in which the gate electrode extends among the side surfaces of the semiconductor layer is aligned with the side surface of the gate electrode.

  In a preferred embodiment, a contact layer is provided between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.

  The thin film transistor according to the present invention includes a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and a semiconductor formed above the gate electrode through the gate insulating film. A layer, a channel protective layer formed on the semiconductor layer, a source electrode formed to cross the channel protective layer, and a drain electrode formed to cross the channel protective layer, Of the side surfaces of the channel protective layer, the side surfaces parallel to the direction in which the source electrode and the drain electrode extend are aligned with the outer side surfaces of the source electrode and the drain electrode.

  In a preferred embodiment, a distance between two side surfaces parallel to a direction in which the gate electrode extends among side surfaces of the channel protective layer is narrower than a line width of the gate electrode.

  In a preferred embodiment, of the side surfaces of the semiconductor layer, side surfaces parallel to the direction in which the gate electrode extends are aligned with the side surfaces of the gate electrode.

  In a preferred embodiment, a side surface parallel to a direction in which the source electrode and the drain electrode extend out of the side surfaces of the semiconductor layer is aligned with the outer side surface of the source electrode and the drain electrode.

  In a preferred embodiment, a contact layer is provided between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.

  According to the active matrix substrate of the present invention, the conductive member for connecting the pixel electrode to the thin film transistor extends to the position of the scanning wiring at a position away from the pixel electrode and intersects the scanning wiring. For this reason, the alignment margin between the scanning wiring and the conductive member becomes sufficiently large, and it becomes possible to use a substrate having a large expansion / contraction rate such as a plastic substrate.

  When the semiconductor layer of the thin film transistor is formed in a self-aligned manner on the scanning wiring (gate electrode), mask alignment between the semiconductor layer and the scanning wiring (gate electrode) is not necessary during manufacturing. Even if it expands and contracts greatly, no positional deviation occurs between the semiconductor layer of the thin film transistor and the scanning wiring (gate electrode).

  In the case where a channel protective layer is provided over the semiconductor layer of the thin film transistor, the channel region of the semiconductor layer is not etched during the manufacturing process, and variations in transistor characteristics are prevented. In addition, when the channel protective layer is formed in a self-aligned manner with respect to the scanning wiring (gate electrode), mask alignment between the channel protective layer and the scanning wiring (gate electrode) becomes unnecessary, so that the substrate is greatly expanded and contracted. Even in this case, there is an advantage that no positional deviation occurs between the channel protective layer and the scanning wiring (gate electrode).

  When the scanning wiring (gate electrode) is formed of a light-shielding metal, the semiconductor layer and the channel protective layer can be formed using a back exposure method.

  When the thin film transistor is covered with the black matrix, an increase in off current leakage of the thin film transistor due to external light is suppressed.

  According to the manufacturing method of the active matrix substrate of the present invention, the thin film transistor can be formed on the scanning wiring in a self-aligned manner by the backside exposure method. There is no need to make the alignment misalignment a problem. In addition, a thin film transistor that functions normally even when the substrate expands or contracts is employed because the layout is such that the signal wiring functioning as the source electrode and the conductive member functioning as the drain electrode can easily intersect the scanning wiring. Can be formed. For this reason, it becomes possible to manufacture an active matrix substrate using a plastic substrate that has been considered difficult to realize in the past.

  According to the display device of the present invention, since the active matrix substrate is provided, display can be performed using a plastic substrate that is lightweight and has excellent impact resistance.

(First embodiment)
A first embodiment of an active matrix substrate according to the present invention will be described with reference to FIGS.

  First, refer to FIG. FIG. 1 is a plan view schematically showing the layout configuration of the active matrix substrate 100 in the present embodiment.

  This active matrix substrate 100 includes an insulating substrate (hereinafter referred to as “plastic substrate”) 1 formed of a plastic material such as polyethersulfone (PES), and a thin film transistor array structure formed on the plastic substrate 1. I have.

  A plurality of scanning lines 2 and signal lines 5 are arranged on the plastic substrate 1 so as to be orthogonal to each other. The scanning wiring 2 and the signal wiring 5 belong to different layers, and are electrically insulated and separated by an insulating film provided in the intermediate layer. In FIG. 1, for the sake of simplicity, seven scanning wirings 2 and eight signal wirings 5 are shown, but in reality, a large number of scanning wirings 2 and signal wirings 5 are arranged.

  In the region where the scanning wiring 2 and the signal wiring 5 intersect, a thin film transistor (not shown in FIG. 1) is formed. A pixel electrode 14 electrically connected to the signal wiring 5 through the thin film transistor is arranged so as to get over the scanning wiring 2.

  Reference is now made to FIG. FIG. 2 is a layout diagram in which a part of the display area of the active matrix substrate 100 is enlarged, and shows two pixel areas belonging to the same pixel column.

  From the pixel electrode 14 disposed so as to get over the scanning wiring 2, the conductive member 9 extends in a direction parallel to the signal wiring 5 (Y-axis direction). The conductive member 9 functions as a drain electrode of the thin film transistor 10 and electrically interconnects the pixel electrode 14 and the thin film transistor 10.

  In the present embodiment, the semiconductor layer constituting each thin film transistor 10 is formed in a self-aligned manner with respect to the scanning wiring 2, and the signal wiring 5 and the conductive member (drain electrode) 9 are arranged so as to get over the semiconductor layer. Has been. A drain electrode 9 connected to an arbitrary thin film transistor 10 and a pixel electrode 14 connected to the drain electrode 9 traverse adjacent separate scanning wirings 2. In the example shown in FIGS. 1 and 2, when the scanning wiring 2 is selectively driven sequentially from the + Y side to the −Y side, the scanning wiring 2 is crossed with the scanning wiring 2 that is selectively driven first. The pixel electrode 14 is disposed, and the drain electrode 9 extending from the pixel electrode 14 is arranged so as to intersect the scanning wiring 2 to be selectively driven next. In this case, an auxiliary capacitor is formed between the pixel electrode 14 and the scanning wiring 2 overlapping therewith. The scanning wiring driving method is not limited to line sequential driving that proceeds from the + Y side to the -Y side. For example, interlaced driving that proceeds from the + Y side to the -Y side, or from the -Y side to the + Y side. You may employ | adopt the line sequential drive which advances toward.

  Next, reference will be made to FIGS. 3A is a cross-sectional view taken along line A-A ′ of FIG. 2, and FIG. 3B is a cross-sectional view taken along line B-B ′ of FIG. 2. FIG. 3C is a perspective view schematically showing the scanning wiring 2 and the semiconductor layers 6 and 7 of the thin film transistor 10 located thereon.

As shown in FIG. 3A, the thin film transistor 10 of this embodiment includes, in order from the lower level, a scanning wiring 2, a gate insulating film 4, an intrinsic semiconductor layer 6, and an impurity-added semiconductor layer that function as gate electrodes. 7 is included. The intrinsic semiconductor layer 6 of this embodiment is formed from non-doped amorphous silicon, and the doped semiconductor layer 7 is formed from n ⁺ microcrystalline silicon doped with an n-type impurity such as phosphorus (P) at a high concentration. ing. The signal wiring 5 and the drain electrode 9 are electrically connected to the source region and the drain region of the semiconductor layer 6 through the impurity-added semiconductor layer 7 that functions as a contact layer, respectively. As is clear from this, in this embodiment, a part of the signal wiring 5 that extends in a straight line (a portion that intersects the scanning wiring 2) functions as the source electrode 8 of the thin film transistor 10.

  As shown in FIG. 3C, in the semiconductor layer 6, a region 31 between the source region S and the drain region D functions as a channel region, and the impurity-doped semiconductor layer 7 is formed on the upper surface of the channel region 31. Does not exist. In this embodiment, a channel-etched bottom gate thin film transistor is employed, and the upper surface of the channel portion of the semiconductor layer 6 is thinly etched when the impurity-added semiconductor layer 7 is removed.

  In the present embodiment, of the side surfaces of the semiconductor layers 6 and 7, the side surface parallel to the direction in which the scanning wiring 2 extends is “aligned” with the side surface of the scanning wiring 2. Such a configuration can be realized by a self-alignment process performed using a back exposure method, as will be described later. Further, it is “aligned” with the other side surfaces of the semiconductor layers 6 and 7 and the outer side surfaces of the signal wiring 5 and the drain electrode 9. Such a configuration can be realized by performing patterning of the signal wiring 5 and the drain electrode 9 and patterning of the semiconductor layers 6 and 7 located in the lower layer using the same mask, as will be described later. In this specification, “matching” refers not only to the case where the position of a pattern edge belonging to a certain layer completely coincides with the position of a pattern edge belonging to another layer, but also to a certain degree of deviation. Is widely included. This “deviation” does not occur due to misalignment of the mask. For example, when a pattern of a plurality of layers is sequentially formed using a common mask (such as a resist mask), the amount of side etch in each layer It can be caused by changing.

  In consideration of the above, “matching” in this specification means a state in which patterns belonging to different layers have an arrangement relationship that is not affected by misalignment of the mask.

  Next, referring to FIG. 3B, which is a cross-sectional view taken along the line BB ′ of FIG. 2, the semiconductor layers 6 and 7 exist on the scanning wiring 2 even in the region where the pixel electrode 14 is formed. I understand that. However, the semiconductor layers 6 and 7 in the region where the pixel electrode is formed are separated from the semiconductor layers 6 and 7 constituting the thin film transistor 10 as apparent from FIG. There is nothing to do. For this reason, crosstalk does not occur between pixels belonging to the same row (scanning wiring).

  In the present embodiment, the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are all composed of a transparent conductive layer obtained by patterning one transparent electrode film, and the signal wiring 5, the drain electrode 9, and All of the pixel electrodes 14 belong to the same layer. The signal wiring 5, the drain electrode 9, and the pixel electrode 14 are covered with a protective insulating film 11, and a color filter 33 is provided thereon.

  Refer to FIG. 2 again.

  As described above, the drain electrode 9 that connects the pixel electrode 14 to the thin film transistor 10 extends in parallel to the signal wiring 5 from the pixel electrode 14 and selectively drives (switches) the thin film transistor 10 that is to be connected to the drain electrode 9. Intersects with the scanning wiring 2 to be operated. The drain electrode 9 is laid out so as not to intersect with the scanning wiring other than the corresponding scanning wiring 2. That is, the distance between the tip of the drain electrode 9 (the end on the −Y direction side in FIG. 2) and the opposite edge of the pixel electrode 14 (the end on the + Y direction side in FIG. 2) is 1 of the scanning wiring interval. It is set to be longer than twice and less than twice. On the other hand, in the conventional active matrix substrate, as shown in FIG. 27A, the distance between the tip of the drain electrode 9 and the opposite edge of the pixel electrode 14 is not more than one time the scanning wiring interval.

  Next, the configuration of the drain electrode 9 and the pixel electrode 14 will be described in more detail with reference to FIG.

The drain electrode 9 shown in the figure is a portion (connecting portion 15) that protrudes short from the corners on the −X side and −Y side of the pixel electrode 14 toward the signal wiring 5, and from the connecting portion 15 to the signal wiring 5. And a portion (extension portion 16) extending long in a parallel direction (−Y side). When the distance between the −Y side end of the drain electrode 9 and the −Y side end of the pixel electrode 14 connected to the drain electrode 9 is defined as “the length (L _d ) of the drain electrode 9”, the drain electrode The length L _{d of} 9 is expressed by the following equation 1.
L _d = P _pitch −DD _gap −Y _con (Formula 1)
Here, P _pitch is the pixel pitch, DD _gap is the _gap between the drain electrodes, and Y _con is the width of the connecting portion 15.

  Even after the plurality of scanning wirings 2 are formed on the plastic substrate 1 at a predetermined interval, even if the plastic substrate 1 is greatly expanded and contracted and the actual scanning wiring pitch shows an unpredictable variation, according to the configuration shown in FIG. When the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are patterned, they can be aligned so as to reliably cross the scanning wiring 2.

Margin required for alignment between the scanning lines 2 and the drain electrode 9 (pixel electrode 14), spreads the larger the length L _d of the drain electrode 9. When the pixel pitch P _pitch is assumed to be constant, the length L _d of the drain electrode 9 may be increased as long as DD _gap and Y _con can be obtained. However, the lower limit values of DD _gap and Y _con are defined by photolithography and etching techniques when patterning, and have a limit. In order to reliably separate each of the pixel electrodes 14 and to avoid the narrowing or cutting of the connection portion 15, it is necessary to secure a sufficient etching margin in the patterning process.

Usually, the gap between pixel electrodes (PP _gap ) is set as small as possible from the viewpoint of improving the aperture ratio. _Therefore , in order to maximize the length L _d of the drain electrode 9, the _gap between drain electrodes DD _{gap is set} to the pixel. The size may be set equal to the interelectrode gap PP _gap . In this case, the following formula 2 is established.
L _d = P _pitch −PP _gap −Y _con (Formula 2)

In FIG. 2, the layout in the case where Expression 2 substantially holds is shown. However, the length L _d of the drain electrode 9 does not need to have a value determined by Expression 2, and a necessary alignment margin can be ensured. It only needs to have a value.

Note that the size Y _pix measured along the X axis of the pixel electrode 14 is expressed by Equation 3 below.
Y _pix = P _pitch -PP _gap (Formula 3)

In the case of FIG. 2, the following Expression 4 is established from Expression 2 and Expression 3.
L _d = Y _pix −Y _con (Formula 4)

The alignment margin ΔY between the scanning wiring 2 and the drain electrode 9 (pixel electrode 14) is expressed by the following formula 5 when the width of the scanning wiring 2 is G _width .
ΔY = L _d −PP _gap −G _width (Formula 5)

  When it is known whether the plastic substrate 1 is expanded or contracted before performing the lithography process for forming the drain electrode 9 (pixel electrode 14) after performing the process of forming the scanning wiring 2, the display region It is preferable to give the largest alignment margin to the pixel located at the end (upper end or lower end).

  FIG. 4A shows an arrangement example when the plastic substrate 1 extends. In the arrangement example of FIG. 4A, the thin film transistor 10 and the scanning wiring 2 of the pixel located at the −Y side end in the display area overlap with the vicinity of the edge 9 </ b> E of the drain electrode 9. In the case of FIG. 4A, since the scanning wiring pitch becomes larger than the pixel pitch due to the extension of the plastic substrate 1, the intersection between the scanning wiring 2 and the drain electrode 9 is the drain corresponding to the pixel located in the + Y direction. Shift away from the edge 9E of the electrode 9. However, according to the configuration of the present embodiment, a sufficient alignment margin ΔY that absorbs the shift of the intersection is provided, so that even in the pixel (not shown) located at the + Y side end in the display area, the scanning wiring 2 and the drain electrode 9 (pixel electrode 14) are ensured an appropriate intersection.

  On the other hand, FIG. 4B shows an arrangement example when the plastic substrate shrinks. In the arrangement example of FIG. 4B, the scanning wiring 2 of the pixel located at the −Y side end in the display area is overlapped with the vicinity of the edge 14 </ b> E of the pixel electrode 14. In the case of FIG. 4B, since the scanning wiring pitch becomes smaller than the pixel pitch due to the contraction of the substrate, the intersection between the scanning wiring 2 and the pixel electrode 14 is the pixel electrode corresponding to the pixel located in the + Y direction. Shift away from 14 edges 14E. However, according to the configuration of the present embodiment, a sufficient alignment margin ΔY that absorbs the shift of the intersecting portion is provided, so that even in the pixel (not shown) located at the + Y side end portion in the display region, the scanning wiring 2 and the drain electrode 9 (pixel electrode 14) are ensured an appropriate intersection.

  In order to be able to cope with any expansion / contraction of the plastic substrate 1, as shown in FIG. 5, the central portion of the drain electrode 9 and the center line of the scanning wiring can be formed near the central portion of the plastic substrate 1. Try to match as much as possible. Thereby, it becomes possible to cope with any expansion / contraction of the plastic substrate 1.

The alignment margin ± Δy at this time is expressed by the following Expression 6.
± Δy = ± (ΔY / 2−dY) (Formula 6)
Here, dY is the alignment accuracy of the exposure apparatus.

  As described above, according to the layout employed in the present embodiment, there is a large alignment margin that can cope with the increase / decrease of the scanning wiring pitch accompanying the expansion / contraction of the plastic substrate 1, so The thin film transistor 10 can also be manufactured at the position of, so that variations in transistor characteristics and parasitic capacitance in the substrate can be reduced.

  As described above, since the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are all formed by patterning the same transparent conductive film, the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are formed. There is no need to consider alignment misalignment in the arrangement relationship.

In the conventional active matrix substrate, in order to reduce the parasitic capacitance at the intersection between the scanning wiring 2 and the signal wiring 5, it is common to provide a constriction at the wiring intersection as shown in FIG. However, in the present embodiment, as shown in FIG. 2, a configuration is adopted in which no concave portion or convex portion is provided on the side surfaces of the scanning wiring 2 and the signal wiring 5 in the display area. As a result, even if alignment misalignment occurs between the scanning wiring 2 and the signal wiring 5, the gate-drain capacitance C _{gd of} the thin film transistor 10, the on-current, the intersection capacitance of the scanning wiring / signal wiring, and the auxiliary capacitance It is possible to suppress changes in characteristics such as.

  Next, a method for manufacturing the active matrix substrate 100 will be described in detail with reference to FIGS. 6 and 7A to 7C. 6 is a plan view showing two pixel regions in main process steps, and FIGS. 7A and 7B are process cross-sectional views showing a cross section taken along line AA ′ and a line BB ′ in FIG. 6. .

First, as shown in FIGS. 6A and 7A, a plurality of scanning wirings 2 are formed on a plastic substrate 1. The scanning wiring 2 is obtained by depositing, for example, a tantalum (Ta) film having a thickness of about 200 nm on the plastic substrate 1 by sputtering or the like, and then patterning the Ta film by photolithography and etching processes. The pattern of the scanning wiring 2 is defined by the mask (first mask) used in the photolithography. The width of the scanning wiring 2 is indicated by the above G _width and can be set to about 4.0 to 20 μm, for example. On the other hand, the pitch of the scanning lines 2 (scanning line pitch) can be set to, for example, about 150 to 400 μm at the stage of the photolithography process. However, since the plastic substrate 1 expands and contracts under the influence of heat and moisture during the subsequent manufacturing process steps, the scanning wiring pitch is set until the photolithography step for forming the pixel electrodes 14 and the like is performed. About 500-1000 ppm will fluctuate from a value.

Next, as shown in FIG. 7A (b), a gate insulating film (thickness of about 200 to 500 nm) 4 made of silicon nitride (SiN _x ) is formed on the plastic substrate 1 by chemical vapor deposition (CVD). Impurity-doped semiconductor doped with n-type impurities such as non-doped amorphous silicon layer (intrinsic semiconductor layer, thickness of about 100 to 200 nm) 6 and P (phosphorus) after being deposited and completely covering the scanning wiring 2 A layer (thickness of about 10 to 50 nm) 7 is stacked on the gate insulating film 4. The intrinsic semiconductor layer 6 may be formed of polycrystalline silicon, microcrystalline silicon, or the like instead of being formed of amorphous silicon. The semiconductor layer 6 may inevitably contain a trace amount of impurities.

  Next, as shown in FIG. 7A (c), after applying a positive resist film 90 on the impurity-added semiconductor layer 7 in a photolithography process, the resist film 90 is irradiated with light from the back side of the plastic substrate 1. (Back exposure). At this time, since the scanning wiring 2 having light shielding functions as one type of optical mask, a portion of the resist film 90 positioned immediately above the scanning wiring 2 is not exposed, and the region above the area where the scanning wiring 2 does not exist. The part located at is exposed. Thereafter, by performing development, a resist mask 90 having a planar layout similar to the planar layout of the scanning wiring 2 is formed on the scanning wiring 2 as shown in FIG. By sequentially etching the doped semiconductor layer 7 and the intrinsic semiconductor layer 6 using the resist mask 90, the semiconductor layers 6 and 7 can be formed on the scanning wiring 2 in a self-aligned manner (FIG. 7A (e)). ).

  FIG. 6B shows the shape of the upper surface of the doped semiconductor layer 7 formed on the scanning wiring 2, and the intrinsic semiconductor layer 6 and the scanning wiring 2 are located at the lower level of the doped semiconductor layer 7. ing. The semiconductor layers 6 and 7 at this stage are not divided for each pixel, and extend on the scanning wiring 2 in a straight line. Note that it is possible to give a difference between the width of the scanning wiring 2 and the width of the semiconductor layers 6 and 7 by adjusting the exposure condition and the etching condition.

  In this embodiment, since the semiconductor layer is patterned using the above-described back exposure method, the thin film transistor 10 is disposed on the scanning wiring 2 (see FIG. 2). Normally, when forming a semiconductor layer for a thin film transistor after forming a scanning wiring, it is necessary to perform alignment of the semiconductor layer pattern with respect to the scanning wiring with high accuracy, but because a positional shift due to expansion and contraction increases on a plastic substrate, It is difficult to realize a thin film transistor array on a plastic substrate. On the other hand, if the backside exposure method is employed as in the present embodiment, alignment between the pattern of the semiconductor layer 6 and the scanning wiring 2 becomes unnecessary, so that it is not necessary to consider the alignment margin.

  In addition, the scanning wiring material of this embodiment is not limited to Ta, What is necessary is just the conductive material which has light-shielding property. The light shielding property is necessary to adopt the back exposure method. As a scanning wiring material other than Ta, a laminated film such as Al, Mo / Al, TiN / Al / Ti, TaN / Ta / TaN, etc. is used because of its relatively low electrical resistance and excellent compatibility with the manufacturing process. An Al-based alloy or the like can be preferably used.

  Next, after removing the resist film 90 on the impurity-added semiconductor layer 7, a transparent conductive film 91 made of indium tin oxide (ITO) is formed on the uppermost surface of the plastic substrate 1 as shown in FIG. To deposit. The material of the transparent conductive film 91 is not limited to ITO, and may be any conductive material that can sufficiently transmit visible light. For example, a transparent conductive film made of IXO may be used.

  Thereafter, by patterning the transparent conductive film 91 by photolithography and etching processes, the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are formed from the transparent conductive film 91. The layout of the signal wiring 5, the drain electrode 9, and the pixel electrode 14 is defined by a mask (second mask) used in the photolithography process. Hereinafter, the patterning process performed using the second mask will be described in detail.

  First, a resist mask 92 as shown in FIG. 6C and FIG. 7B (b) is formed by a photolithography process. The illustrated resist mask 92 includes a relatively thick resist portion (thickness: about 1.5 to 3.0 μm) 92 a that defines the shapes of the signal wiring 5, the drain electrode 9, and the pixel electrode 14, and the signal wiring 5. And a relatively thin resist portion (thickness: about 0.3 to 1.0 μm) 92 b that defines a region between the electrode 9 and the drain electrode 9.

  The configuration of the resist mask 92 will be described in more detail with reference to FIGS. FIG. 8A is a partially enlarged view showing a part of the resist mask 92, and shows an enlarged region including the signal wiring 5, the end of the drain electrode 9, and the corner of the pixel electrode 14. 8B, 8C, and 8D are a cross-sectional view taken along line C-C ', a cross-sectional view taken along line D-D', and a cross-sectional view taken along line E-E 'of FIG. FIG. 9 is a schematic perspective view of the resist mask shown in FIG.

  The resist mask 92 is obtained by irradiating a portion of the resist film located in a region between the signal wiring 5 and the drain electrode 9 with an appropriate amount of light when the resist film applied to the substrate 1 is exposed. (Half exposure method). Such exposure can be realized by utilizing the light interference effect if a slit pattern is formed at an appropriate position of the optical mask.

  In this embodiment, first, the transparent conductive film 91, the impurity-added semiconductor layer 7, and the intrinsic semiconductor layer 6 are sequentially etched using the resist mask 92 having such a special shape. FIG. 7B (c) shows a cross section at a stage where this etching is completed. At this stage, since the channel region 31 of the thin film transistor 10 is covered with the relatively thin portion 92b of the resist mask 92, the transparent conductive film 91 and the doped semiconductor layer 7 on the channel region 31 are not etched at all. Therefore, the semiconductor layer 6 that has been in the shape of a line is separated into an island by the etching, but the portion that should become the signal wiring 5 and the portion that should become the drain electrode 9 in the transparent conductive film 91 are not separated. It remains.

  Next, the resist mask 92 is thinned by ashing (ashing) the surface portion of the resist mask 92 using, for example, oxygen plasma, and the channel portion 31 of the thin film transistor 10 is covered as shown in FIG. The resist portion 92b that has been removed is removed. When oxygen plasma ashing is performed to reduce the thickness of the resist mask 92, the side surface of the resist mask 92 is also ashed by the thickness of the thin resist portion 92b. However, since the thickness of the thin resist portion 92b is about 0.3 to 1.0 μm, the dimensional shift amount by ashing is also about 0.3 to 1.0 μm. Since the variation of the dimension shift amount in the substrate surface is about ± 20% or less, the variation of the finished size is about ± 0.2 μm at the maximum, but the transistor channel width is about 5 to 10 μm, so the transistor Little effect on properties. A partial perspective view of the resist mask 92 after ashing is shown in FIG.

  In this way, after removing the thin resist portion 92b covering the channel region 31 of the thin film transistor 10, the transparent conductive film 91 and the impurity-added semiconductor layer 7 are etched again. Thus, the structure shown in FIG. 6D and FIG. 7B (e) can be obtained. By this etching, the intermediate portion located between the portion to be the signal wiring 5 and the portion to be the drain electrode 9 in the transparent conductive film 91 is removed, and the signal wiring 5 and the drain electrode 9 in the separated state are transparent. The conductive film 91 is formed. During this etching, the doped semiconductor layer 7 located on the channel region 31 is also removed, and the exposed surface of the intrinsic semiconductor layer 6 is also partially etched. Thereafter, when the resist mask 92 (92a) is removed, the structure shown in FIG. 7C (a) is obtained (see FIG. 3C).

  In the present embodiment, as described above, the linear (line-shaped) semiconductor layers 6 and 7 positioned in the intermediate layer between the transparent conductive film 91 and the scanning wiring 2 are first patterned for each pixel when the transparent conductive film 91 is patterned. Separated and patterned into an island shape (FIG. 6C). Thereafter, the signal wiring 5 and the drain electrode 9 are completely separated by a self-aligned process, and the thin film transistor 10 is completed. By adopting such a method, the semiconductor layers 6 and 7 can be self-aligned with the signal wiring 5 and the drain electrode 9, and the mask layer and the semiconductor layer that define the signal wiring 5 and the drain electrode 9 can be used. No alignment with the mask layer defining 6 is required.

  Next, as shown in FIG. 7C (b), after covering the thin film transistor 10 with the protective film 11, a color filter 33 is formed on the pixel electrode 14 by electrodeposition. If a color filter is formed on the counter substrate as in the prior art, the position of the color filter with respect to the pixel electrode 14 is greatly shifted due to the expansion and contraction of the plastic substrate, so that a normal image cannot be displayed. In the present embodiment, in order to solve such a problem, the color filter 33 is formed on the pixel electrode 14 in a self-aligning manner. Hereinafter, the electrodeposition formation of the color filter performed in this embodiment will be described with reference to FIG.

  In order to form three color filters of red (R), green (G), and blue (B) by the electrodeposition method, it is necessary to perform the electrodeposition process three times for each different color. In the present embodiment, the switching circuit 57 shown in FIG. 11 is arranged in the periphery of the display area of the active matrix substrate, and the electrodeposition is selectively performed for each color using the switching circuit 57. The switching circuit 57 includes thin film transistors and wirings, which are manufactured using a process for manufacturing wirings and thin film transistors in the display region.

  First, the case of electrodepositing a red color filter will be described. In this case, an ON signal (for example, “logic high”) of the thin film transistor is input to the control signal line Rs of the switching circuit 57, while an OFF signal (for example, “logic low”) is input to the other control signal lines Bs and Gs. To do. A voltage V for causing an electrodeposition reaction is applied to the switching circuit 57. At this time, a signal for turning on the thin film transistor in the display area is input to each scanning line 2 in advance. As a result, the voltage V is applied to the array 58 of pixel electrodes to display red, and a red paint is electrodeposited on the pixel electrodes in the array 58. At this time, the color filter 33 is also formed on the signal wiring 5 and the drain electrode 9 to which the voltage V is applied (FIG. 7C (b)).

  For the other color filters, green paint is electrodeposited on the pixel electrodes of the array 59 that should display green by repeating the same process as the electrodeposition process described above. A blue paint is electrodeposited on the pixel electrode. In this way, three color filters can be formed in a self-aligned and selective manner with respect to the pixel electrode 14. According to this method, the three color filters 33 are arranged in a stripe pattern.

  If the color filter 33 is formed of an insulating material, the effective voltage that can be applied to the liquid crystal layer during operation of the liquid crystal display device is reduced. In order to prevent such a decrease in effective voltage, the color filter is formed from a conductive material in the present embodiment.

  As described above, in this embodiment, the number of photolithography processes that require mask alignment is reduced to two by employing many self-alignment processes. For this reason, the influence of substrate expansion / contraction extends only to the mask alignment in the subsequent photolithography process with respect to the pattern formed in the previous photolithography process among the two photolithography processes. Then, by making the structure of the drain electrode 9 and the pixel electrode 14 as shown in FIG. 2, the connection between the semiconductor layer 6 of the thin film transistor 10 and the drain electrode 9 is ensured even when the plastic substrate 1 is greatly expanded and contracted. It becomes possible.

  In addition, since the plastic substrate expands and contracts greatly unlike the case of the glass substrate, when the mask alignment is performed using the same mark as the conventional alignment mark, the alignment marks between different layers cannot be overlapped with each other. . Therefore, in this embodiment, alignment markers 120a and 120b having a pattern as shown in FIG. 12 are employed. In the example shown in FIG. 12, the marker 120a formed by the first mask is composed of a two-dimensional scale pattern having a size about twice (or more) the alignment margin Δy shown in Expression 6. . The marker 120b formed by the second mask is configured by a pattern (for example, a cross pattern) that clearly shows the position of the marker 120b with respect to the marker formed by the first mask.

  With such alignment markers 120a and 120b, the amount of positional deviation between the pattern formed by the second mask and the pattern formed by the first mask is read, and the position of the second mask is determined based on the amount of deviation. adjust. For example, the mask alignment may be performed so that the shift amounts of the two alignment markers 120a and 120b shown in FIG.

(Example)
An example of the above active matrix substrate was manufactured using a 5-inch diagonal plastic substrate made of PES (thickness: about 0.2 mm). In this embodiment, the size of one pixel region is 300 μm × 100 μm, the scanning line width G _width is 10 μm, the inter-pixel electrode gap PP _gap is 5 μm, the connecting portion width Y _con is 5 μm, and the drain electrode length L _d is It was 290 μm. The alignment accuracy of the used exposure apparatus was ± 5 μm. From Expression 5, ΔY = 290−5−10 = 275 [μm] is obtained.

  In the present embodiment, the center of the drain electrode and the center of the scanning wiring are made to substantially coincide with each other at the center of the substrate so that both expansion and contraction of the plastic substrate can be handled. As a result, the alignment margin of this example was ± 132.5 μm (Δy = ΔY / 2−dY = 137.5−5 = 132.5 [μm]).

  The pattern (marker) formed on the plastic substrate by the first mask was shifted by 42 μm on one side with respect to the marker by the second mask when performing the lithography process using the second mask. This pattern shift corresponds to a substrate shrinkage of 661 ppm. However, in this embodiment, since there is an alignment margin of ± 132.5 μm, a thin film transistor that operates normally is manufactured at any position of the substrate and functions as an active matrix substrate without any problem.

  On the other hand, in the case of the conventional structure shown in FIG. 48, the allowable limit of substrate expansion / contraction is only ± 14 μm, and an active matrix substrate cannot be manufactured using a plastic substrate.

  In the structure according to the present invention and the conventional structure, the alignment margin Δy for each pixel pitch is described in Table 2 below, and a graph produced based on Table 2 is shown in FIG.

  The graph of FIG. 13 shows the relationship between the alignment margin (substrate expansion margin) Δy and the pixel pitch. As can be seen from the graph, according to the present embodiment, a large margin that cannot be obtained in the conventional example can be obtained, and a plastic substrate can be used even if the pixel pitch is considerably shortened.

  As described above, according to the present embodiment, even when a substrate that can cause stretching exceeding 500 ppm during a photolithography process that requires alignment is used, all layers including the color filter layer are formed. Since the elements can be formed in an appropriate arrangement relationship, an active matrix liquid crystal display device using a plastic substrate can be realized.

  Note that when a liquid crystal display device is manufactured using the active matrix substrate of the present embodiment, when a normally white type liquid crystal is used, the backlight light leaks through the transparent signal wiring and the vicinity thereof. More specifically, backlight light leaks from the region of the signal wiring 5, the region between the signal wiring 5 and the drain electrode 9, the region between the adjacent pixel electrodes 14, and the region between the adjacent drain electrodes 9. The contrast of the displayed image decreases. On the other hand, if the display operation is performed in the normally black mode, the pixel electrode 14 to which no voltage is applied, the region between the adjacent drain electrodes 9, and the region between the adjacent pixel electrodes 14 are displayed in black. In addition, since the signal wiring 5 to which the average voltage is applied becomes a halftone, it is possible to suppress a decrease in display contrast.

(Second Embodiment)
In the first embodiment, the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are formed by patterning a transparent conductive film such as ITO. Therefore, the signal wiring 5 that does not need to be transparent is also included in the pixel electrode 14. It is formed from the transparent conductive film similarly to. In general, the resistivity of the transparent conductive film is larger than the resistivity of the metal film, and the resistivity of ITO is 200 to 400 μΩcm. For this reason, when the signal wiring is formed from ITO, if the signal wiring 5 is too long, the signal transmission is likely to be delayed. Therefore, the size of the active matrix substrate 100 in the first embodiment is considered to be about 5 inches diagonal.

  In addition, when a black matrix is provided on the counter substrate of the active matrix substrate 100, misalignment is likely to occur between the opening portion of the black matrix and the pixel electrode 14 due to expansion and contraction of the plastic substrate. Therefore, if no black matrix is provided, external light may irradiate the thin film transistor 10 and increase the off-leakage current. When the off-leakage current of the thin film transistor 10 increases, the holding voltage to be applied to the liquid crystal layer by the pixel electrode 14 and the counter electrode decreases, so that the contrast of the display image decreases. Further, when the black matrix is not provided, the backlight leaks through the transparent signal wiring and the vicinity thereof as described above, so that the display operation in the normally white mode cannot be performed. Even if the operation is performed in the normally black mode, the contrast slightly decreases on the signal wiring 5.

  Therefore, in this embodiment, in order to solve these problems, the black matrix is arranged on the active matrix substrate by a self-aligning method.

  Hereinafter, a second embodiment of an active matrix substrate according to the present invention will be described with reference to FIGS. FIG. 14 is a plan view showing the layout of the active matrix substrate 200 in the present embodiment, FIG. 15A is a cross-sectional view taken along the line AA ′ of FIG. 14, and FIG. 14 is a cross-sectional view taken along line BB ′ of FIG.

  As is apparent from the figure, the basic configuration of the active matrix substrate 200 in the present embodiment is the same as the basic configuration of the active matrix substrate 100 in the first embodiment except for the points described below. That is, the characteristic points in this embodiment are as follows.

  (1) A black matrix 35 is disposed so as to cover a region where the pixel electrode 14 is not formed and a peripheral portion of the pixel electrode 14 (FIG. 14). That is, the signal wiring 5, the scanning wiring 2, the thin film transistor 10, the gap area between the signal wiring 5 and the drain electrode 9, the gap area between the drain electrode 9 and the pixel electrode 14, the gap area between the adjacent pixel electrodes 14, and the adjacent areas. All the gap regions of the drain electrode 9 are shielded from light by the black matrix 35.

  (2) The black matrix 35 is made of a negative photosensitive material and is patterned by backside exposure.

  (3) The color filter 33 is provided in a region where the black matrix 35 is not formed (on the pixel electrode 14) (FIGS. 15A and 15B).

  (4) A metal film 93 made of Ta is formed on the signal wiring 5 made of ITO and the drain electrode 9 (FIG. 15A).

  Since the resistivity of Ta is as low as 25 to 40 μΩcm as compared with the resistivity of ITO, the metal film 93 made of Ta functions as a “low resistance wiring” by being integrated with the signal wiring 5. For this reason, the signal transmission speed can be improved as compared with the case where the wiring is formed only from the transparent conductive film such as ITO. According to this embodiment, the diagonal size of the active matrix substrate is increased to 10 inches or more. It becomes possible to do.

  If the main purpose is the light shielding effect by the black matrix 35 and the purpose is not to reduce the resistance of the wiring, instead of providing a property metal film such as Ta on the transparent conductive layer, the light shielding performance made of a black resin material or the like is eliminated. The material layer may be disposed on the transparent conductive layer. Any metal film / insulating layer having a light shielding function functions as an optical mask necessary for patterning the black matrix 35 in the manufacturing method described below.

  Hereinafter, a method for manufacturing the active matrix substrate 200 will be described in detail with reference to FIGS. 16 and 17. FIG. 16 is a plan view showing two pixel regions in main process steps, and FIG. 17 is a process sectional view showing a cross section taken along line A-A ′ and a cross section taken along line B-B ′ in FIG. 16.

  First, as shown in FIG. 16A and FIG. 17A, a plurality of scanning wirings 2 are formed on a plastic substrate 1. The scanning wiring 2 is obtained by depositing a metal film such as aluminum (Al) or Ta on the plastic substrate 1 using a sputtering method or the like and then patterning the metal film by a photolithography and etching process. The pattern of the scanning wiring 2 is defined by the mask (first mask) used in the photolithography.

  Next, as shown in FIGS. 16B and 17B, an intrinsic semiconductor layer 6 and an impurity-added semiconductor layer 7 that are self-aligned with the scanning wiring 2 are formed on the scanning wiring 2 through the gate insulating film 4. To do. At this time, the back exposure method is used as in the first embodiment. In FIG. 16B, only the impurity-doped semiconductor layer 7 is shown, but the intrinsic semiconductor layer 6 and the scanning wiring 2 are located directly under the impurity-doped semiconductor layer 7.

  Next, after sequentially depositing a transparent conductive film 91 made of ITO or the like and a light-shielding metal film 93 made of Ta or the like on the upper surface of the plastic substrate 1, a resist mask 92 is formed as shown in FIG. As in the case of the first embodiment, the resist mask 92 includes a relatively thick portion 92 a that defines the signal wiring 5, the drain electrode 9, and the pixel electrode 14, and a region between the signal wiring 5 and the drain electrode 9. And a relatively thin portion 92b that defines

  Next, the light-shielding metal film 93, the transparent conductive film 91, the impurity-added semiconductor layer 7, and the intrinsic semiconductor layer 6 are sequentially etched using the resist mask 92. FIG. 16C and FIG. 17C show the configuration at the stage where this etching is completed. At this stage, since the channel region 31 of the thin film transistor 10 is covered with the relatively thin portion 92b of the resist mask 92, the metal film 93, the transparent conductive film 91, and the impurity-added semiconductor layer 7 in the channel region are completely etched. Not. That is, the portion to be the signal wiring 5 and the portion to be the drain electrode 9 in the transparent conductive film 91 remain unseparated.

  Next, after removing the resist portion 92b covering the channel region 31 of the thin film transistor 10 by, for example, oxygen plasma ashing, the metal film 93, the transparent conductive film 91, and the impurity-added semiconductor layer 7 are etched again. Thus, the structure shown in FIGS. 16D and 17D can be manufactured. At this stage, the metal film 93 exists not only on the signal wiring 5 and the drain electrode 9 but also on the pixel electrode 14. In order to manufacture a transmissive display device, it is necessary to selectively remove a portion of the light-shielding metal film 93 located on the pixel electrode 14. The light shielding metal film on the pixel electrode 14 is removed after the black matrix is formed by the method described below.

  As shown in FIG. 17E, after depositing a transparent protective film 11 on the uppermost surface of the plastic substrate 1, a negative photosensitive black matrix film is applied on the protective film 11. The photosensitive black matrix film is irradiated with light from the back side of the substrate 1 (backside exposure). At this time, since the pattern of the light-shielding metal film 93 functions as one type of optical mask, a portion having a relatively large area located above the pixel electrode 14 in the photosensitive black matrix film is hardly exposed. On the other hand, the light-shielding metal film 93 covering the signal wiring 5 and the drain electrode 9 has a narrow line width, and is therefore exposed by the diffraction phenomenon of light irradiated from the back surface of the substrate.

  When the non-exposed portion of the photosensitive black matrix film is removed by performing development after the back surface exposure, as shown in FIGS. 16 (e) and 17 (e), the shape of the pixel electrode 14 is substantially the same. Thus, the black matrix 35 having the above-mentioned opening above the pixel electrode 14 is formed.

  Thereafter, using the black matrix 35 as an etching mask, the protective film 11 and the light shielding metal film 93 in the region exposed through the opening of the black matrix 35 are etched. By this etching, the light shielding metal film 93 existing on the pixel electrode 14 is removed. Thereafter, the color filter 33 is formed by the electrodeposition method to obtain the configuration of FIG.

  According to the present embodiment, the upper surface of the signal wiring 5 made of a transparent conductive layer is backed (backed) by the metal film having a lower resistivity than the transparent conductive layer. Resistance (wiring resistance) is reduced, and a large-sized liquid crystal display device having a diagonal of 5 inches or more can be realized.

  In the present embodiment, the display characteristics can be greatly improved by providing the black matrix on the active matrix substrate side. Specifically, since the thin film transistor in the display region is covered with a black matrix, the off-current leakage of the transistor due to external light irradiation is suppressed, and the reduction in contrast due to such current leakage is prevented. In addition, by providing the black matrix, unnecessary leakage of backlight light is suppressed, and a decrease in contrast due to light leakage is also prevented.

(Third embodiment)
Hereinafter, a third embodiment of the active matrix substrate according to the present invention will be described with reference to FIGS. FIG. 18 is a plan view schematically showing the layout of the active matrix substrate 300 in the present embodiment, and FIGS. 19A to 19D are diagrams for explaining black matrix patterning by backside exposure. .

  As can be seen from FIG. 18, the basic configuration of the active matrix substrate 300 in the present embodiment is the same as the basic configuration of the active matrix substrate 200 in the second embodiment except for the scanning wiring 2.

  The characteristic part of this embodiment is that the scanning wiring 2 is branched into a plurality of wiring parts 2a to 2c, and the width of each wiring part 2a to 2c is set to 6 to 7 μm. Since the semiconductor layer 6 of the thin film transistor 10 is self-aligned with the scanning wiring 2, the semiconductor layer 6 is also divided into three according to the wiring portions 2a to 2c. For this reason, in this embodiment, three thin film transistors are arranged for each pixel, and they are in a state of being connected in parallel between the signal wiring 5 and the drain electrode 9. The same scanning signal is input to the plurality of wiring portions 2a to 2c constituting the scanning wiring 2, and the three thin film transistors responding thereto perform the same switching operation.

  Hereinafter, the reason why each scanning wiring is branched into a plurality of parts will be described.

  According to the backside exposure method employed in the first to second embodiments, the width of the scanning wiring 2 defines the channel width of the thin film transistor 10. Since the on-state current of the transistor is proportional to the channel width, it may be desired to increase the width of the scanning wiring 2 in order to obtain a necessary on-state current. The magnitude of the required on-current varies depending on the size of the pixel electrode 14 and the driving method, but when the size of the pixel electrode 14 is about 300 μm × 100 μm, it is necessary to design the channel width to 10 to 20 μm.

  However, when the width of the scanning line 2 exceeds 10 μm, the diffracted light cannot sufficiently wrap around the center of the scanning line 2 when the black matrix 35 is patterned using the backside exposure method. This point will be described with reference to FIGS. 19 (a) and 19 (c). 19 (a) and 19 (b) are plan views showing the shape of the black matrix 35 in the thin film transistor formation region, and FIGS. 19 (c) and 19 (d) are views of FIGS. 19 (a) and 19 (b), respectively. It is FF 'sectional view taken on the line.

  If the width of the scanning wiring 2 is too wide, the diffracted light of the light irradiated from the back side of the substrate does not reach the negative photosensitive black matrix film located at the center of the scanning wiring 2. A non-photosensitive portion of the matrix film is generated. As a result, after development, as shown in FIGS. 19A and 19C, only a region within several μm from the edge of the scanning wiring 2 is covered with the black matrix 35, and the central portion of the scanning wiring 2 is covered with the black matrix 35. It cannot be covered with. In such a black matrix 35, irradiation of external light to the thin film transistor 10 cannot be prevented, and the off current of the thin film transistor 10 increases.

  On the other hand, in the example of FIG. 19B, the scanning wiring 2 is divided into two wiring parts 2a to 2b, and a slit-shaped opening is formed between the wiring part 2a and the wiring part 2b during back exposure. The exposure area by the light passing through the opening and the diffracted light is enlarged. For this reason, as shown in FIG. 19D, the upper portion of the scanning wiring 2 is completely covered with the black matrix 35.

  Since the photosensitive resin film located on the light-shielding pattern is also sensitized by the diffracted light at the portion located about 4 μm from the edge of the light-shielding pattern, if the width of the scanning wiring 2 is about 8 μm or less, In particular, it is not necessary to divide the scanning wiring 2 into a plurality of portions. However, considering that the wiring width changes due to variations in manufacturing process parameters, it is preferable that the wiring width be at most about 6 to 7 μm.

  Reference is again made to FIG. In the configuration shown in FIG. 18, each scanning wiring 2 is divided into three wiring portions 2a to 2c. If the width of each wiring part 2a-2c is set to 6-7 micrometers, the effective width (= channel width) of the scanning wiring 2 will be 18-21 micrometers.

  Also in this embodiment, since the semiconductor layers 6 and 7 are self-aligned with the scanning wiring 2, the semiconductor layer 7 is also divided into three according to the wiring portions 2a to 2c. For this reason, three thin film transistors are arranged for each pixel, and they are connected in parallel between the signal wiring 5 and the drain electrode 9. Since the same scanning signal is input to the plurality of wiring portions 2a to 2c constituting the scanning wiring 2, and the three thin film transistors responding to the same scanning operation, the on-current can be increased.

  In the example shown in FIG. 18, the scanning wiring 2 is divided into three wiring portions, but the present invention is not limited to this. One scanning wiring to which the same signal is input may be divided into two or four or more. Note that the scanning wiring 2 may have a single wiring shape in a region other than the display region. For example, in a region where the scanning wiring is connected to the driver circuit, it is preferable that a plurality of wiring portions that receive the same signal are connected to one wiring.

  The scanning wiring 2 may be separated into a plurality of wiring portions at least in a region where the semiconductor layer 6 of the thin film transistor 10 is formed. For example, the scanning wiring 2 is separated into a plurality of portions in a region where the pixel electrode 14 is disposed. There is no need. However, since the displacement of the X-axis direction occurs due to the expansion and contraction of the plastic substrate 1, it is preferable that the planar shape of the scanning wiring is uniform regardless of the position in the display area.

  Thus, according to this embodiment, the black matrix 35 that completely covers the thin film transistor 10 can be formed even when the effective line width of the scanning wiring 2 is increased.

  In this embodiment, a light amplification type photosensitive material is used as the material of the black matrix 35, but a chemical amplification type photosensitive material may be used instead. In the case of a chemically amplified photosensitive material, since the reaction proceeds from the portion irradiated with light even if it is not directly exposed to light, there is an advantage that the amount of black matrix 35 entering on the light shielding pattern can be easily increased.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the active matrix substrate according to the present invention will be described with reference to FIGS. FIG. 20 is a plan view showing two pixel regions in main process steps for manufacturing the active matrix substrate 400 of the present embodiment, and FIG. 21 is a cross-sectional view taken along line AA ′ in FIG. It is process sectional drawing which shows a line cross section.

  In any of the first to third embodiments described above, the impurity-added semiconductor layer 7 is directly deposited on the intrinsic semiconductor layer 6, and when the signal wiring 5 functioning as the source electrode and the drain electrode 9 are separated, the impurity addition is performed. Not only the semiconductor layer 7 but also the surface of the intrinsic semiconductor layer 6 was etched. In the present embodiment, a channel protective layer is disposed between the intrinsic semiconductor layer 6 and the doped semiconductor layer 7 so that the channel region of the intrinsic semiconductor layer 6 is not etched.

  As can be seen from FIGS. 20E and 21F, the basic configuration of the active matrix substrate 400 in this embodiment is that a channel protective layer 95 is provided between the intrinsic semiconductor layer 6 and the doped semiconductor layer 7. Except for this point, the basic configuration of the active matrix substrate 100 in the first embodiment is the same. Since the function of the channel protective layer 95 is exhibited during the manufacturing process, the method for manufacturing the active matrix substrate 400 according to the present embodiment will be described in detail below.

  First, as shown in FIGS. 20A and 21A, a plurality of scanning wirings 2 are formed on a plastic substrate 1. The scanning wiring 2 is obtained by depositing a metal film such as AlNd or Ta on the plastic substrate 1 using a sputtering method or the like and then patterning the metal film by photolithography and etching processes. The pattern of the scanning wiring 2 is defined by the mask (first mask) used in the photolithography.

Next, as shown in FIG. 20B and FIG. 21B, after the intrinsic semiconductor layer 6 and the channel protective layer 95 are deposited on the substrate 1 through the gate insulating film 4, a backside exposure method is used. A channel protective layer 95 that is self-aligned with the scanning wiring 2 is formed on the scanning wiring 2. At this time, the intrinsic semiconductor layer 6 is not patterned, and only the channel protective layer 95 is patterned. The channel protective layer 95 can be preferably formed of a SiN _x film having a thickness of about 200 nm. In this embodiment, exposure conditions and etching conditions are adjusted so that the line width of the channel protective layer 95 is narrower by about 1 to 4 μm than the line width of the scanning wiring 2. As a result, the position of each edge of the channel protective layer 95 enters about 0.5 to 2 μm inside the corresponding edge of the scanning wiring 2. In order to increase the side etching amount of the channel protective layer 92 and increase the difference between the line width of the scanning wiring 2 and the line width of the channel protective layer 95, it is preferable to use isotropic etching such as wet etching.

  Next, an impurity-doped semiconductor layer 7 is deposited by CVD so as to cover the channel protective layer 95 and the intrinsic semiconductor layer 6, and then the intrinsic semiconductor layer 6 self-aligned with the scanning wiring 2 is again used by using the backside exposure method. Then, an impurity-added semiconductor layer 7 is formed on the scanning wiring 2. In FIG. 20C, only the doped semiconductor layer 7 is shown, but the channel protective layer 95, the intrinsic semiconductor layer 6, and the scanning wiring 2 are located immediately below the doped semiconductor layer 7. Yes. However, the width of the channel protective layer 95 is formed narrower than the line width of the intrinsic semiconductor layer 6 and the scanning wiring 2. Here, the “width” of the channel protective layer 95 indicates a distance between two side surfaces parallel to the direction in which the scanning wiring 2 extends among the four side surfaces of the channel protective layer 95.

  Next, after depositing a transparent conductive film 91 made of ITO or the like on the upper surface of the plastic substrate 1, a resist mask 92 is formed as shown in FIG. As in the case of the first embodiment, the resist mask 92 includes a relatively thick portion 92 a that defines the signal wiring 5, the drain electrode 9, and the pixel electrode 14, and a region between the signal wiring 5 and the drain electrode 9. And a relatively thin portion 92b that defines

  Next, using the resist mask 92, the transparent conductive film 91, the impurity-added semiconductor layer 7, the channel protective layer 95, and the intrinsic semiconductor layer 6 are sequentially etched. FIG. 20D and FIG. 21D show a configuration at a stage where this etching is completed. At this stage, since the channel region of the thin film transistor 10 is covered with the relatively thin portion 92b of the resist mask 92, the transparent conductive film 91 and the like in the channel region are not etched at all.

  Next, after removing the resist portion 92b covering the channel region of the thin film transistor 10 by, for example, oxygen plasma ashing, the transparent conductive film 91 and the impurity-added semiconductor layer 7 are etched again. In this etching, the channel protection layer 95 located at the lower level of the impurity-added semiconductor layer 7 functions as an etch stop layer, and protects the channel region of the intrinsic semiconductor layer 6 from etching. Thus, the structure shown in FIGS. 20 (e) and 21 (e) can be produced. Next, after depositing the protective film 11 on the uppermost surface of the plastic substrate 1, the color filter 33 is formed by the electrodeposition method to obtain the configuration of FIG.

  According to the present embodiment, the mask for patterning the signal wiring 5 and the drain electrode 9 is used, and the wiring-shaped channel protective layer 95 located on the scanning wiring 2 is separated for each pixel. For this reason, the channel protective layer 95 is not only self-aligned with the scanning wiring 2 but also self-aligned with the signal wiring 5 and the drain electrode 9. More specifically, of the four side surfaces of the channel protective layer 95, two side surfaces parallel to the direction in which the signal wiring 5 and the drain electrode 9 extend are aligned with the outer side surfaces of the signal wiring 5 and the drain electrode 9. .

  As a result, an alignment shift does not occur between the channel protection layer 95 and the signal wiring 5 or the drain electrode 9, and a channel protection type thin film transistor array can be manufactured over a substrate that can easily expand and contract.

  Thus, in this embodiment, it is not necessary to give a large alignment margin to the channel protective layer 95. In addition, since the distance between two side surfaces parallel to the direction in which the scanning wiring 5 extends among the side surfaces of the channel protective layer 95 is narrower than the line width of the scanning wiring 5, the channel protective layer 95 is formed on the upper surface of the semiconductor layer 6. It is possible to form a contact region in which no exists.

(Fifth embodiment)
The fifth embodiment of the active matrix substrate according to the present invention will be described with reference to FIGS. In the figure, members corresponding to the above-described embodiments are denoted by the same reference numerals.

  First, referring to FIG.

  FIG. 22 is a plan view schematically showing the layout configuration of the active matrix substrate 500 in the present embodiment. In the present embodiment, unlike the first to fourth embodiments, an auxiliary capacitance wiring (Com) 20 between the adjacent scanning wirings 2 (for example, between the wiring G1 and the wiring G2) and in parallel with the scanning wiring 2 is used. Is arranged. The auxiliary capacitance wiring 20 belongs to the same layer as the scanning wiring 2 and is formed of the same material as that of the scanning wiring. In addition, in the pixel region of the active matrix substrate 500, the auxiliary capacitance wiring 20 has a straight wiring shape with no protrusions, like the scanning wiring 2. In FIG. 22, for the sake of simplification, seven scanning wirings 2, seven auxiliary capacitance wirings 20, and eight signal wirings 5 are shown, but a large number of wirings are actually arranged.

  Reference is now made to FIG. FIG. 23 is a layout diagram in which a part of the display area of the active matrix substrate 500 is enlarged.

  A conductive member 9 extends long in a direction parallel to the signal wiring 5 (Y-axis direction) from the pixel electrode 14 disposed so as to overcome the scanning wiring 2 and the auxiliary capacitance wiring 20. The conductive member 9 functions as a drain electrode of the thin film transistor 10 and electrically interconnects the pixel electrode 14 and the thin film transistor 10.

  In the present embodiment, the semiconductor layer constituting each thin film transistor 10 is formed in a self-aligned manner with respect to the scanning wiring 2, and the signal wiring and the conductive member (drain electrode) 9 are arranged so as to get over the semiconductor layer. The The semiconductor layer is also formed on the auxiliary capacitance line 20 in a self-aligned manner, and physically forms a thin film transistor. However, a signal that always turns off the parasitic thin film transistor is input to the auxiliary capacitance line 20. As a result, the parasitic thin film transistor does not function as a switching element.

  A drain electrode 9 connected to an arbitrary thin film transistor 10 and a pixel electrode 14 connected to the drain electrode 9 traverse adjacent separate scanning lines 2 and auxiliary capacitance lines 20.

When an active matrix substrate is applied to a liquid crystal display device or the like, it is desirable to suppress a change in pixel potential due to a gate-drain capacitance C _gd of a thin film transistor in order to improve display characteristics and reduce power consumption. The change amount ΔV of the pixel potential due to C _gd is expressed by ΔV = C _gd / (C _gd + C _cs + C _lc ) · V _gpp .

Here, C _cs is an auxiliary electrode capacitance (capacitance between the scanning wiring 2 and auxiliary capacitance wiring 20 and the pixel electrode 14), C _lc is a liquid crystal capacitance, and V _gpp is a signal when the signal in the scanning wiring 2 is turned on and off. It is a potential difference. Since V _gpp , C _lc, etc. are determined by the basic characteristics of the materials and devices used, it is conceivable that ΔV is lowered by increasing the auxiliary capacitance C _cs . However, when the alignment-free structure is adopted, increasing the auxiliary capacitance C _cs by increasing the width of the scanning wiring 2 leads to increasing C _gd at the same time. For this reason, it is not preferable to control ΔV by adjusting the width of the scanning wiring 2. For example, it is assumed that the width G _{width of the} scanning wiring is increased by K times in order to increase the auxiliary capacitance C _cs . Since the auxiliary capacitance C _cs is proportional to the width G _{width of the} scanning wiring, C _{cs ′} = K · C _cs . On the other hand, since the gate-drain capacitance C _gd is also proportional to the width G _{width of the} scanning wiring, C _{gd ′} = K · C _gd . Therefore, the pull-in voltage ΔV ′ is expressed by the following Expression 7.

ΔV ′ = K · C _gd / (K · C _gd + K · C _cs + C _lc )
= C _gd / (C _gd + C _cs + C _lc / K) (Formula 7)

  As is clear from Equation 7, the pull-in voltage ΔV ′ increases as K increases. In Equation 7, when K is decreased, the pull-in voltage ΔV ′ is also decreased. However, the minimum line width of the scanning wiring 2 is determined due to restrictions on the manufacturing process and the like, and it is difficult to sufficiently reduce the pull-in voltage ΔV ′ by reducing K.

  Therefore, in this embodiment, in addition to the capacitance between the scanning wiring 2 and the pixel electrode 14, an auxiliary capacitance is formed between the auxiliary capacitance wiring 20 and the pixel electrode 14. By adjusting the width of the auxiliary capacitance line 20, the pull-in voltage ΔV can be reduced.

  In the present embodiment, in order to increase the margin for the expansion and contraction of the substrate, it is preferable to make the interval between the scanning wiring 2 and the auxiliary capacitance wiring 20 intersecting the same pixel electrode 14 as small as possible.

  Reference is now made to FIGS. 24 is a cross-sectional view taken along line A-A ′ in FIG. 23, and FIG. 25 is a cross-sectional view taken along line B-B ′ in FIG. 23.

As shown in FIG. 24, the thin film transistor 10 of the present embodiment has a stacked structure including a scanning wiring 2 that functions as a gate electrode, a gate insulating film 4, an intrinsic semiconductor 6, and an impurity doped semiconductor layer 7 in order from the lower level. have. The intrinsic semiconductor 6 of this embodiment is formed from non-doped amorphous silicon, and the impurity-added semiconductor layer 7 is formed from n ⁺ microcrystalline silicon doped with an n-type impurity such as phosphorus (P) at a high concentration. Yes. The signal wiring 5 and the drain electrode 9 are electrically connected to the source region and the drain region of the semiconductor layer 6 through the impurity-added semiconductor layer 7 that functions as a contact layer, respectively. As is clear from this, in this embodiment, a part of the signal wiring 5 that extends in a straight line (a portion that intersects the scanning wiring 2) functions as the source electrode S of the thin film transistor 10.

  As shown in FIG. 24, a region 31 between the source region S and the drain region D in the semiconductor layer 6 functions as a channel region, and the doped semiconductor layer 7 is present on the upper surface of the channel region 31. Absent. In this embodiment, a channel-etched bottom gate thin film transistor is employed, and the upper surface of the channel portion of the semiconductor layer 6 is thinly etched when the impurity-added semiconductor layer 7 is removed.

  It can be seen that the semiconductor layers 6 and 7 exist on the scanning wiring 2 even in the region where the pixel electrode 14 is formed. However, as is apparent from FIG. 24, the semiconductor layers 6 and 7 in the region where the pixel electrode is formed are separated from the semiconductor layers 6 and 7 constituting the thin film transistor 10, and the transistor operation is not performed. Absent. For this reason, crosstalk does not occur between pixels belonging to the same row (scanning wiring).

  The cross-sectional configuration on the auxiliary capacitance wiring 20 is the same as the cross-sectional configuration on the scanning wiring 20. Again, since the semiconductor layer 6 exists between the signal wiring 5 and the drain electrode 9, a thin film transistor is formed parasitically, but a voltage of about −8 to −15 V is always applied to the auxiliary capacitance wiring. Therefore, this parasitic transistor does not become conductive (ON state). Therefore, the signal wiring 5 and the drain electrode 9 are electrically separated.

  In the present embodiment, the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are all composed of a conductive layer obtained by patterning one reflective electrode film, and the signal wiring 5, the drain electrode 9, and the pixel are formed. All of the electrodes 14 belong to the same layer. The signal wiring 5, the drain electrode 9, and the pixel electrode 14 are covered with a protective insulating film 11.

  An alignment margin ΔY between the scanning wiring 2 and auxiliary capacitance wiring 20 and the drain electrode 9 (pixel electrode 14) is expressed by the following Expression 8.

ΔY = L _d −PP _gap −G _width −W _cs −CG _gap
= P _pitch -G _width -PP _gap -W _cs -GC _gap
-DD _gap -Y _con (Formula 8)
Here, G _width is the _width of the scanning wiring 2, W _cs is the width of the auxiliary capacitance wiring 20, and GC _gap is the interval between the scanning wiring and the auxiliary capacitance wiring 20.

  As described above, according to the layout adopted in the present embodiment, there is a large alignment margin that can cope with the increase / decrease of the scanning wiring pitch accompanying the expansion / contraction of the plastic substrate. In this case, a thin film transistor that operates normally can be manufactured, and variations in transistor characteristics and parasitic capacitance in the substrate can be reduced. As described above, since the signal wiring 5, the drain electrode 9, and the pixel electrode 14 are all formed by patterning the same transparent conductive film or reflective electrode material film, the signal wiring 5, the drain electrode 9 and the positional relationship between the pixel electrodes 14 do not require misalignment.

(Example)
An example of the above active matrix substrate was manufactured using a 5-inch square plastic substrate (thickness 0.2 mm) made of PES. The panel size is 3.9 inches diagonal and the resolution is 1/4 VGA (320 × RGB × 240). The size of one pixel region is 82 μm × 246 μm, the width G _width of the scanning wiring 2 is 8 μm, the gap PP _gap between the pixel electrodes is 5 μm, the width Y _{con of the} connection portion is 5 μm, the width W _cs of the auxiliary capacitance wiring is 25 μm, and the auxiliary capacitance When the gap GC _gap between the wiring 20 and the scanning wiring 2 is 10 μm and the gap DD _gap between the drains is 5 μm, ΔY = 246-8-5-25-10-5-5 = 188 μm.

  In this embodiment, the plastic substrate is arranged so that ΔY1 = ΔY2 at the center of the substrate so as to cope with both expansion and contraction of the plastic substrate. As a result, the alignment margin ΔY between the scanning wiring layer and the source wiring / lower pixel electrode layer was ± 91 μm (ΔY = ΔY / 2−dY, where dY is 3 μm with the accuracy of the alignment apparatus).

  Since the length of the display area in the ΔY direction is 240 (lines) × 246 (μm) = 59040 (μm), the allowable substrate expansion / contraction margin between the two layers is 1541 ppm. In this trial manufacture, the substrate was expanded or contracted by about 500 to 700 ppm. However, since there was a sufficient alignment margin, the thin film transistor normally operated in all pixel regions and functioned as an active matrix substrate without any problem.

  Table 2 below shows the substrate expansion / contraction margin for each pixel pitch in the structure according to the present invention and the conventional structure. It is assumed that the size of the display area is 4 inches diagonal (81.2 mm × 61 mm) and the scanning wiring terminals are arranged on the short side.

  The alignment accuracy of the exposure apparatus was ± 3 μm.

(Sixth embodiment)
In the first to fifth embodiments, since the pixel electrode 14 and the signal wiring 5 are in the same layer, the alignment margin can be expanded. However, since there is a signal wiring, the size of the pixel electrode 14 is limited, and the aperture ratio (the ratio of the pixel electrode to the pixel region in the reflective liquid crystal display device) cannot be increased.

  A liquid crystal display device using a plastic substrate is expected to be applied to a reflective liquid crystal in order to make use of the lightness and thinness of the substrate. In a reflective liquid crystal display device, it is said that sufficient visibility cannot be obtained without an aperture ratio of 70% or more. Therefore, in a reflection type liquid crystal display device on a conventional glass substrate, the pixel electrode 14 and the signal wiring 5 are arranged in different layers, and the gap between the pixel electrode 14 and the signal wiring 5 is eliminated, thereby opening 80 to 90%. The rate is secured.

  In the structures of the first to fifth embodiments, only an aperture ratio of about 30 to 50% can be obtained. Therefore, in the second embodiment shown in FIG. 26, the pixel electrode 14 has a two-layer structure. That is, the pixel electrode 14 is configured by the upper pixel electrode 14A that functions as a reflective electrode and the lower pixel electrode 14B that forms an auxiliary capacitor. The upper layer pixel electrode 14 </ b> A is arranged in a layer separate from the signal wiring 5 through an insulating film, and the lower layer pixel electrode 14 </ b> B is arranged in the same layer as the signal wiring 5. By doing so, the alignment margin can be increased without reducing the aperture ratio.

  Hereinafter, this embodiment will be described with reference to FIGS. 26 is a plan view showing the layout of the active matrix substrate 600 in the present embodiment, FIG. 27 is a cross-sectional view taken along line AA ′ in FIG. 26, and FIG. 28 is a cross-sectional view taken along line BB ′ in FIG. FIG.

  As is clear from the figure, the configuration of the active matrix substrate in the present embodiment is the same as the configuration of the active matrix substrate in the fifth embodiment in the lower layer than the lower pixel electrode 14B.

  An interlayer insulating film is disposed on the lower pixel electrode 14B, the drain electrode 9, and the signal wiring 5. Reference numeral 14A denotes an upper pixel electrode, which is made of a reflective electrode material such as AL. A contact hole is formed in part of the lower pixel electrode 14B, and the upper pixel electrode 14A and the lower pixel electrode 14B are electrically connected. Since the upper pixel electrode 14A has a larger area than the lower pixel electrode 14B, the aperture ratio can be increased. In addition, since the auxiliary capacitance is formed between the lower pixel electrode 14B, the auxiliary capacitance wiring 20, and the scanning wiring 2, it is not necessary to control alignment between the upper pixel electrode 14A and the scanning wiring layer.

  Therefore, the alignment margin ΔY between the first mask that defines the scanning wiring and the second mask that defines the source wiring 5 and the underlying pixel electrode 14B is the same as the size of the alignment margin in the fifth embodiment. Absent. Therefore, ΔY is expressed by the following equation.

ΔY = P _pitch −G _width −PP _gap −W _cs −GC _gap −DD _gap −Y _con

  Since the contact hole 21 and the upper pixel electrode 14B are formed in the upper layer of the lower pixel electrode 14B, it is necessary to consider the alignment margin for these layers as well.

The contact hole 21 must be disposed on the lower pixel electrode 14B. When the width of the contact hole is W _ch , the alignment margin between the third mask that defines the contact hole 21 layer and the second mask that defines the lower layer pixel electrode 14B is expressed by the following equation.

ΔC = P _ss −W _s −W _d −3 · SD _gap −W _ch
Here, P _ss is the source wiring pitch, W _s is the width of the source wiring, W _d is the width of the drain electrode, and SD _gap is the gap between the source and drain.

  Note that there is a limitation on the expansion and contraction of the substrate in the ΔY direction between the second mask and the third mask, but it is ignored because it is sufficiently large with respect to ΔC. Since the expansion and contraction of the plastic substrate is almost the same in the vertical direction and the horizontal direction, if the margin of ΔC is satisfied, the margin in the ΔY direction should also be satisfied.

Since the upper pixel electrode 14A needs to be formed on the contact hole 21, the alignment margin between the fourth mask that defines the upper pixel electrode 14A layer and the third mask that defines the contact hole 21 is ΔP. = P _{ss -PP tgap} . Here, PP _tgap is a gap between the upper pixel electrodes 14A.

  Next, the manufacturing process of this embodiment will be described.

  As is apparent from the figure, the same manufacturing process as that described in the first to fifth embodiments can be employed for the signal wiring 5, the drain electrode 9, and the lower pixel electrode 14B. The structure of the thin film transistor 10 may be either a channel protective film type or a channel etch type. In this embodiment, a channel etch type is adopted.

  After an interlayer insulating film 21 made of an inorganic insulating film or an organic insulating film is deposited on the thin film transistor, a contact hole 22 is formed by a photolithography process. The thickness of the interlayer insulating film 21 is, for example, 0.5 to 3 μm.

  In the insulating film deposition step, it is necessary to select a material or a film formation method that causes less expansion and contraction of the substrate. In general, the organic insulating film is less stretched than the inorganic insulating film, so that the organic insulating material is selected here.

  A reflective electrode material film made of Al, Al alloy, silver alloy or the like is deposited on the interlayer insulating film 21. The thickness of the reflective electrode material film is, for example, about 50 to 100 nm. Through the photolithography process, the upper pixel electrode 14A (reflective electrode) is formed from the reflective electrode material film. In the present embodiment, the lower pixel electrode does not strictly function as a pixel electrode, but functions as a lower electrode for the upper pixel electrode, and hence is referred to as a “lower image electrode”.

  The material of the signal wiring layer must be a transparent conductive material in the case of manufacturing a transmissive active matrix substrate. However, in the case of a reflective active matrix substrate, the conductive film may be a light shielding film or a transparent film. I do not care. However, it is necessary to select a material that can form a low-resistance contact with the upper pixel electrode 14A. Here, since Al is used as the material of the upper pixel electrode, Ti is selected as the material of the lower pixel electrode 14B, the signal wiring 5, and the drain electrode 9.

(Example)
An example of the above active matrix substrate was manufactured using a 5-inch square plastic substrate (thickness 0.2 mm) made of PES. The panel size is 3.9 "diagonal and the resolution is 1/4 VGA (320 x RGB x 240) for reflection type. The size of one pixel area is 82 µm x 246 µm, the scanning line width G _width is 8 µm, the lower layer The pixel electrode gap PP _gap is 5 μm, the connecting portion width Y _con is 5 μm, the auxiliary capacitance wiring width W _cs is 25 μm, the gap GC _gap between the auxiliary capacitance wiring and the scanning wiring is 10 μm, and the drain gap DD _gap is If it is 5 μm, then ΔY = 246-8-5-25-10-5-5 = 188 μm.

  In this embodiment, the plastic substrate is arranged so that ΔY1 = ΔY2 at the center of the substrate so as to cope with both expansion and contraction of the plastic substrate. As a result, the alignment margin ΔY between the scanning wiring layer (first mask layer) and the source wiring / lower pixel electrode layer (second mask layer) was ± 91 μm (ΔY = ΔY / 2−dY). . Here, dY is the accuracy of the alignment apparatus, and dY = 3 μm.

  Since the length of the display area in the ΔY direction is 240 (line) × 246 (μm) = 59040 (μm), the allowable substrate expansion / contraction margin between the first mask and the second mask is 1541 ppm. When the prototype was actually manufactured, the substrate was expanded or contracted by about 500 to 700 ppm. However, since there was an alignment margin, the shape of the thin film transistor and the auxiliary capacitor as designed was obtained in all pixel regions.

On the other hand, the third mask that defines the contact hole only needs to be aligned with the second mask. When the source wiring width Ws is 8 μm, the drain electrode width Wd is 8 μm, the source-drain gap SD _gap is 5 μm, and the contact hole width is 5 μm, ΔC = 82-8-8-3 × 5-5 = 46 μm It becomes.

  In this case, the substrate is arranged so that Δc1 = Δc2 at the center of the substrate so that both expansion and contraction of the substrate can be supported. As a result, the alignment margin Δc between the second mask and the third mask was ± 20 μm (Δc = ΔC / 2−dY).

  Note that also in the Y-axis direction, mask alignment was performed so that the contact hole 21 was substantially at the center of the lower pixel electrode 14B in the center of the substrate.

  Since the length of the display area in the direction parallel to ΔC is 320 × 82 × 3 = 78720 μm, the allowable substrate expansion / contraction margin is only 254 ppm. However, unlike the process between the first mask layer and the second mask layer, the CVD film formation that causes large substrate expansion and contraction is performed between the photolithography processes of the second mask layer and the third mask layer. There is no process. For this reason, when actually prototyped, there was only about 1500 ppm of expansion / contraction of the substrate at the maximum, and sufficient alignment could be achieved by this structure.

In addition, the fourth mask that defines the upper pixel electrode 14A only needs to be aligned with the third mask. When the gap PP _tgap between the upper pixel electrodes is 5 μm, ΔP = 82−5 = 77 μm.

  In this case, the substrate is arranged so that Δp1 = Δp2 at the center of the substrate so that both expansion and contraction of the substrate can be supported. As a result, the alignment margin Δp between the fourth mask and the third mask was ± 35.5 μm (Δp = ΔP / 2−dY).

  Since the length of the display area in the direction parallel to ΔP is 320 × 82 × 3 = 78720 μm, the allowable substrate expansion / contraction margin is only 451 ppm. However, there is no CVD film forming process that causes large substrate expansion / contraction between the photolithography process for the third mask and the photolithography process for the fourth mask. For this reason, the alignment between the third mask and the fourth mask is relatively easy.

  In the present embodiment, since the reflective electrode (upper pixel electrode) 14A is arranged in a layer different from the signal wiring 5, the aperture ratio (ratio of the reflective electrode in the pixel region) is 92%.

  Further, since the conventional structure requires alignment accuracy of several μm or less between all layers, the allowable substrate expansion / contraction is 150 ppm when the alignment margin is 9 μm. Therefore, in the conventional structure, an active matrix substrate cannot be manufactured using a plastic substrate.

  In the current manufacturing technology, in order to obtain TFT characteristics required as an active matrix substrate, it is necessary to form a gate insulating film and a semiconductor layer by a CVD method at a substrate temperature of 100 to 200 ° C. Therefore, in order to realize an active matrix substrate on a plastic substrate, a pixel structure having a large alignment margin between the first mask and the second mask as in the present embodiment is desirable.

  In the present embodiment, the Cs on Common structure provided with the auxiliary capacity wiring is shown, but the same effect can be obtained even when there is no auxiliary capacity wiring. FIGS. 29 to 31 show an active matrix substrate 700 according to an improved example having a structure (Cs on Gate structure) in which the auxiliary use wiring is removed from the configuration of the present embodiment. According to the active matrix substrate 700, ΔY can be further increased.

(Seventh embodiment)
By adopting the structure in the sixth embodiment, a 3.9 inch 1/4 VGA reflective liquid crystal display element can be manufactured using a plastic substrate. However, when the pixel size is smaller or the panel size is larger, the contact hole alignment margin ΔC may be insufficient. Even in the case of a panel of about 3.9 inch 1/4 VGA, it is preferable to further increase the alignment margin in view of mass production. In the present embodiment, a configuration capable of further increasing the contact hole alignment margin ΔC is employed.

  Hereinafter, this embodiment will be described with reference to FIGS. 32 is a plan view showing the layout of the active matrix substrate 800 in this embodiment, FIG. 33 is a cross-sectional view taken along line AA ′ in FIG. 32, and FIG. 34 is a cross-sectional view taken along line BB ′ in FIG. FIG.

  As can be seen from the figure, the lower layer pixel electrode 14B in this embodiment crosses the storage capacitor line 20, and the corresponding scanning line is crossed by the drain electrode 9 extending from the lower layer pixel electrode 14B. As a result, the drain electrode 9 does not exist in the region separated from the lower pixel electrode 14B along the X-axis direction, and only the source wiring 5 is disposed. For this reason, the width (X-axis direction size) of the lower layer pixel electrode 14B can be relatively widened, and as a result, the alignment margin ΔC of the contact hole can be increased. The alignment margin ΔC is expressed by the following formula.

ΔC = P _ss −W _s −2 · SD _gap −W _ch
Here, P _ss is the source pitch, W _s is the width of the source wiring, SD _gap is the gap between the pixel electrode and the source wiring, and W _ch is the width of the contact hole in the X-axis direction.

  On the other hand, the drain electrode 9 passes over only the scanning wiring 2 and does not overlap with the auxiliary capacitance wiring, and the lower pixel electrode 14B passes over only the auxiliary capacitance wiring 20 and does not overlap with the scanning wiring 2. For this reason, the substrate expansion / contraction margin ΔY between the first mask layer and the second mask layer is expressed by the following equation.

ΔY = (P _pitch −G _width −W _cs −DD _gap −DG _gap ) / 2

  In this embodiment, although it is about ½ compared to the second embodiment, it is effective when it is necessary to increase the alignment margin between the second mask layer and the third mask layer.

  Note that the active matrix substrate 800 according to the present embodiment is manufactured by a method similar to the method for manufacturing the active matrix substrate according to the sixth embodiment.

(Example)
An example of the above active matrix substrate was manufactured using a 5-inch inch plastic substrate (thickness 0.2 mm) made of PES. The panel size is 2.5 inches diagonal and the resolution is 1/4 VGA (320 × RGB × 240), which is for the reflection type. 1 pixel area size 53 × 159μm, 8μm width Gwidth scanning wirings, 10 [mu] m width W _cs of the auxiliary capacitance lines, 5 [mu] m gaps DDgap between the drain electrode and the lower layer of the pixel electrodes, the minimum between the lower pixel electrode scanning lines When the gap is 3 μm, ΔY = (159-8-10-5-3) / 2 = 133 μm.

  In this embodiment, the plastic substrate is arranged so that ΔY1 = ΔY2 at the center of the substrate so as to cope with both expansion and contraction of the plastic substrate. As a result, the alignment margin ΔY between the scanning wiring layer (first mask layer) and the source wiring / lower pixel electrode layer (second mask layer) was ± 63.5 μm (ΔY = ΔY / 2− dY and dY were 3 μm with the accuracy of the alignment device).

  Since the length of the display area in the ΔY direction is 240 lines) × 159 (μm) = 38160 (μm), the allowable substrate expansion / contraction margin between the first mask layer and the second mask layer is 1664 ppm. become.

  The alignment margin between the contact hole layer (third mask layer) and the lower pixel electrode layer (second mask layer) is ΔC = 53−8−2 × 5−5 = 30 μm. In order to be able to cope with both expansion and contraction of the substrate, it was arranged so that Δc1 = Δc2 at the center of the substrate. As a result, the alignment margin Δc between the second mask layer and the third mask layer was ± 12 μm (Δc = ΔC / 2−dY). Since the length of the display area in the direction parallel to ΔC is 320 × 53 × 3 = 50880 μm, the allowable substrate expansion / contraction margin is 590 ppm. This value is a sufficient alignment margin between the photolithography process of the second mask layer and the third mask layer without the CVD process.

  On the other hand, when the structure of the second embodiment is adopted, ΔC = 53− when the source wiring width Ws is 6 μm, the drain electrode width Wd is 6 μm, the source-drain gap SDgap is 5 μm, and the contact hole width is 5 μm. 8-8-3 × 5-5 = 17 μm, and Δc = ΔC / 2−dY is only ± 5.5 μm. The substrate expansion / contraction margin is only 108 ppm, and a sufficient manufacturing margin cannot be obtained.

  Therefore, by adopting this embodiment, it is possible to expand the photo alignment margin when the contact hole 22 that connects the upper pixel electrode 14A and the lower pixel electrode 14B is formed. For this reason, for example, a high-definition active matrix substrate exceeding 150 PPI equivalent to 2.5 inch 1/4 VGA as shown in this embodiment can be realized on a plastic substrate.

  Since the structure of the upper pixel electrode 14A is the same as that of the second embodiment, a high aperture ratio can be obtained. In this embodiment, the aperture ratio is 88%.

(Eighth embodiment)
Hereinafter, this embodiment will be described with reference to FIGS. 35 is a plan view showing a layout of the active matrix substrate 900 in the present embodiment, FIG. 36 is a cross-sectional view taken along the line AA ′ in FIG. 35, and FIG. 37 is a cross-sectional view taken along the line BB ′ in FIG. FIG. 38 is a cross-sectional view taken along the line CC ′ of FIG.

  The difference between the active matrix substrate 900 according to the present embodiment and the active matrix substrate according to the first to seventh embodiments is the shape of the thin film transistor.

  In the present embodiment, the source electrode 8B branched from the signal wiring 5 passes through the vicinity of the end of the drain electrode 9 and is bent in a direction parallel to the signal wiring 5. The source electrode 8 </ b> B sandwiches the drain electrode 9 together with the signal wiring 5. The signal wiring 5 (source electrode 8A), the source electrode 8B, and the drain electrode 9 are all arranged so as to get over the scanning wiring 2 and the semiconductor layer 6 on the scanning wiring.

  As shown in FIG. 36, since the semiconductor layer 6 remains on the entire upper surface of the scanning wiring 2, a region between the signal wiring 5 (source electrode 8A) and the drain electrode 9 on the scanning wiring 2, and The region between the source electrode 8B and the drain electrode 9 functions as a thin film transistor.

  On the other hand, since a semiconductor layer also exists between the source electrode 8B and the adjacent signal wiring 5 (source electrode 8A), this region can function as a parasitic thin film transistor. However, since the signal on the adjacent signal line 5 is shielded by the source electrode 8B, the potential of the pixel electrode 14B is not affected via the drain electrode 9.

In the present embodiment, as is apparent from FIG. 38, the following expression is established.
ΔY = (P _pitch −G _width −W _cs −Ws−3 SD _gap ) / 2

  According to this embodiment, the process of removing semiconductor layers other than the channel part of a thin-film transistor by a half exposure technique is unnecessary. This makes it possible to shorten the manufacturing process time and improve the manufacturing yield of the active matrix substrate.

(Ninth embodiment)
Hereinafter, this embodiment will be described with reference to FIGS. FIG. 39 is a plan view showing a layout of the active matrix substrate 1000 in the present embodiment, and FIG. 40 is a cross-sectional view taken along line AA ′ of FIG.

  The active matrix substrate 1000 according to this embodiment has a configuration similar to that of the active matrix substrate 900 according to the eighth embodiment. One of the characteristic points of the active matrix substrate 1000 is that the drain electrode 9 is arranged at the approximate center between two adjacent signal wirings 5. The upper pixel electrode 14A completely covers the channel portion of the thin film transistor. In other words, the position of the drain electrode 9 is set so that the upper pixel electrode 14A completely covers the channel portion of the thin film transistor. In other respects, the configuration of the active matrix substrate 1000 is the same as the configuration of the active matrix substrate 900.

  With such a configuration, light leakage current of the thin film transistor 10 is suppressed, so that contrast when applied to a liquid crystal display device can be improved.

  In the present embodiment, as is apparent from FIG.

ΔY = (P _pitch −G _width −W _cs −2 · Ws−3 · SD _gap ) / 2

  In the present embodiment, the signal wiring 5, the drain electrode 9, and the source electrode 8 </ b> B have portions extending in parallel with each other, and these portions are orthogonal to the scanning wiring 2. In order to obtain the effect of the present invention, the parallel portion and the scanning wiring 2 do not need to be orthogonal to each other, and may intersect at an angle other than 90 degrees.

  The drain electrode 9 may be provided at a position slightly deviated from the center of the adjacent signal wiring 5 due to misalignment. However, the drain electrode 9 is within a range of ± 25% of the pixel pitch (pixel pitch measured along the X-axis direction) from a straight line passing along the Y-axis through the center of the corresponding lower pixel electrode 14B. Is preferred.

  According to the present embodiment, as in the eighth embodiment, the step of removing the semiconductor layer other than the channel portion of the thin film transistor by the half exposure technique is unnecessary. This makes it possible to shorten the manufacturing process time and improve the manufacturing yield of the active matrix substrate.

(Tenth embodiment)
In the above embodiments, the scanning wiring is formed at the lower layer level and the semiconductor layer of the thin film transistor is formed at the upper layer level. A transistor having this configuration is called a “bottom gate transistor (reverse staggered transistor)” because a scanning wiring functioning as a gate electrode is located at the lowest level of the transistor. In this embodiment, an active matrix substrate is configured using a “top gate transistor (positive staggered transistor)” in which a scanning wiring functioning as a gate electrode is provided in the uppermost layer of the transistor.

  In the active matrix substrate 1100 of this embodiment, as shown in FIG. 41C and FIG. 42D, the scanning wiring 2 is formed in the upper layer level of the signal wiring 5, the drain electrode 9, and the pixel electrode 14. The signal wiring 5, the drain electrode 9, and the pixel electrode 14 are crossed.

  The semiconductor layer 6 is disposed at a lower level of the signal wiring 5, the drain electrode 9, and the pixel electrode 14, and is covered with the signal wiring 5, the drain electrode 9, and the pixel electrode 14. The gate insulating film 4 always exists immediately below the scanning wiring 2, and an auxiliary capacitance is formed between the scanning wiring 2 and the pixel electrode 14.

  Hereinafter, a method for manufacturing the active matrix substrate 500 according to the present embodiment will be described with reference to FIGS. 41 and 42.

  First, as shown in FIG. 42A, an intrinsic semiconductor layer 6 made of non-doped amorphous silicon, an impurity doped semiconductor layer 7 doped with P (phosphorus), etc., and APC (Ag-Pd) on a plastic substrate 1. After a reflective metal film 96 made of -Cu: silver alloy is laminated, a resist mask 92 is formed. The intrinsic semiconductor layer 6, the impurity-added semiconductor layer 7, and the reflective metal film 96 have thicknesses of, for example, 150 nm, 50 nm, and 150 nm, respectively. As in the case of the first embodiment, the resist mask 92 includes a relatively thick portion 92 a that defines the signal wiring 5, the drain electrode 9, and the pixel electrode 14, and a region between the signal wiring 5 and the drain electrode 9. And a relatively thin portion 92b that defines

  Next, the reflective metal film 96, the impurity-added semiconductor layer 7, and the intrinsic semiconductor layer 6 are sequentially etched using the resist mask 92. FIG. 41A and FIG. 42B show a configuration at a stage where this etching is completed. At this stage, since the channel region of the thin film transistor 10 is covered with the relatively thin portion 92b of the resist mask 92, the metal film 96 in the channel region and the doped semiconductor layer 7 are not etched at all. That is, the portion that should become the signal wiring 5 and the portion that should become the drain electrode 9 in the reflective metal film 96 remain unseparated.

  Next, after removing the resist portion 92b covering the channel region of the thin film transistor by, for example, oxygen plasma ashing, the reflective metal film 96 and the doped semiconductor layer 7 are etched again. By removing the resist mask 92, the structure shown in FIGS. 41B and 42C can be manufactured. At this stage, as shown in FIG. 41B, in the gap region between the signal wiring 5 and the drain electrode 9, the intrinsic semiconductor layer 6 located at the lower level is partially exposed.

Next, after depositing a gate insulating film 4 made of SiN _x having a thickness of 400 nm and an AlNd film having a thickness of 200 nm by using a CVD method, AlNd is patterned using a second mask, and FIG. As shown in FIG. 42D, the scanning wiring 2 is formed.

  Thereafter, an etching process using the scanning wiring 2 as a mask is performed, and the gate insulating film 4 and the intrinsic semiconductor layer 6 located in a region not covered with the scanning wiring 2 are removed. As a result, the structure shown in FIGS. 41C and 42E is obtained. By this etching, the portion of the intrinsic semiconductor layer 6 located in the region between the signal wiring 5 and the drain electrode 9 is removed except for the portion functioning as a thin film transistor. Note that semiconductor layers 6 and 7 having shapes similar to those of the pixel electrode 14 and the drain electrode 9 are finally present at the lower level of the pixel electrode 14 and the drain electrode 9, and the lower level of the signal wiring 5 is provided. Also, there are conductor layers 6 and 7 having the same shape as the signal wiring 5.

  The active matrix substrate 500 of this embodiment has a reflective pixel electrode 14 and is used to construct a reflective liquid crystal display device. According to the manufacturing method of this embodiment, since the semiconductor layers 6 and 7 are left under the pixel electrode 14, even if the pixel electrode 14 is formed of a transparent conductive film, it cannot be applied to a transmissive display device. .

  Note that the material of the scanning wiring 2 is not limited to AlNd, and may be any conductive material that can function as an etching mask when the gate insulating film 4 and the semiconductor layers 6 and 7 are etched. For example, Ta, Mo, W, Ti, Al, or an alloy thereof, APC, or ITO may be used. Alternatively, a film in which a plurality of layers made of these materials are stacked may be used.

  The material of the reflective metal film is not limited to APC, and may be Ag, Al, Au, or an alloy material thereof.

The material of the gate insulating film 4 is not limited to SiN _x , but may be an inorganic insulating material such as SiO ₂ , an organic insulating material such as BZT, or a film in which layers made of these materials are stacked.

  As described above, in the active matrix substrate of this embodiment, the pixel electrode 14 is formed of a reflective metal film, and the display device that is finally assembled is of a reflective type. On the other hand, the active matrix substrate of the first to fourth embodiments is used for a transmissive display device. In order to divert the first to fourth embodiments to the reflective type, a reflective metal film is formed in place of the transparent conductive film, and the reflective metal film is patterned, whereby the signal wiring 5, the drain electrode 9, and The pixel electrode 14 may be formed. In this case, there is no problem even if the semiconductor layers 6 and 7 remain at the lower layer level of the pixel electrode 14. For this reason, in the case of the reflection type, it is not necessary to pattern the semiconductor layers 6 and 7 into a shape aligned with the scanning wiring 2 before forming the pixel electrode 14. If the linear channel protective layer is formed on the scanning wiring as in the case of the fourth embodiment, the contact layer and the reflective metal film deposited thereon are patterned to form the signal wiring 5 and the drain electrode 9. In forming the pixel electrode 14, after removing the relatively thin portion 92b of the resist mask 92, the channel protective layer can function as a part of the etching mask. For this reason, when an unnecessary semiconductor layer located in the region between the signal wiring 5 and the drain electrode 9 is removed by etching, the semiconductor layer remains immediately below the channel protective layer and functions as a semiconductor region of the thin film transistor. Is appropriately arranged on the scanning wiring.

  Note that the configuration employed in the sixth to ninth embodiments, that is, the configuration using auxiliary capacitance wiring or the configuration in which the upper layer pixel electrode is disposed on the insulating film may be combined with the top-category transistor according to the present embodiment.

(Eleventh embodiment)
Each of the scanning wiring 2 and the signal wiring 5 in the first to fourth embodiments is composed of a linearly extending wiring, and a portion protruding in a direction parallel to the main surface of the substrate 1 or a recessed portion is provided. I don't have it. For this reason, even if an alignment shift occurs in a direction parallel to the scanning wiring 2, the layout in each pixel does not change. On the other hand, the alignment shift in the direction perpendicular to the scanning wiring 2 needs to be suppressed within a range not exceeding the alignment margin (ΔY), and the size of the alignment margin (ΔY) is smaller than the pixel pitch.

  For this reason, when the substrate expansion / contraction rate is not uniform depending on the direction, it is preferable to arrange the signal wiring 5 in parallel with the direction having a small substrate expansion / contraction rate. Therefore, in the present embodiment, the expansion / contraction ratio of the substrate 1 with respect to the direction parallel to the signal wiring 5 is smaller than the expansion / contraction ratio of the substrate 1 with respect to the direction perpendicular to the signal wiring 5. The direction is set. As a result, the alignment shift in the direction parallel to the signal wiring 5 is reduced, and it is ensured that it is within the alignment margin (ΔY).

  On the other hand, in order to secure a sufficient alignment margin in the direction parallel to the scanning wiring 2, it is necessary to make the scanning wiring 2 sufficiently long and straightly extend outside the display area (pixel area) as shown in FIG. There is. By providing such an extension in the scanning wiring 2, even if the signal wiring 5 and the pixel electrode 14 are misaligned in the direction parallel to the scanning wiring 2, the signal wiring 5 and the pixel electrode 14 are connected to the scanning wiring 2. And can be reliably crossed. The alignment margin (ΔX) in the direction parallel to the scanning wiring 2 is defined by the length of the extension of the scanning wiring 2.

  In the present embodiment, as described above, an arrangement is selected such that the substrate expansion / contraction ratio in the direction parallel to the scanning wiring 2 is relatively large, and therefore the alignment margin (ΔX) in the direction parallel to the scanning wiring 2 is It is preferable to set it larger than the alignment margin (ΔY) in the direction perpendicular to the scanning wiring 2. For this reason, in this embodiment, the length of the extension part of the scanning wiring 2 is made longer than the scanning wiring pitch.

  As mentioned above, although the example which implement | achieves an active-matrix board | substrate using a plastic substrate has been demonstrated, the application range of this invention is not limited to this. The present invention exerts a remarkable effect when using a substrate that expands and contracts during the manufacturing process, such as a plastic substrate, but among the various effects obtained by the present invention, the effect of being hardly affected by alignment misalignment is Even if a substrate other than the substrate (for example, a glass substrate) is used, it can be fully enjoyed. In particular, a favorable effect can be obtained when a large display panel is manufactured using an exposure apparatus having low alignment accuracy.

  Note that the active matrix substrate according to the present invention has an excellent effect even when applied to a display device other than a liquid crystal display device (for example, a display device using organic EL).

  Note that “intersection” in the present specification does not mean only a state in which the drain electrode 9 completely crosses over the scanning wiring 2 located in the lower layer, as shown in FIG. The case where the position of the tip (edge 9E) of the drain electrode 9 coincides with the position of the edge (side surface) of the scanning wiring 2 is included.

  According to the active matrix substrate of the present invention, the conductive member for connecting the pixel electrode to the thin film transistor extends to the position of the scanning wiring at a position away from the pixel electrode and intersects the scanning wiring. For this reason, the alignment margin between the scanning wiring and the conductive member becomes sufficiently large, and it becomes possible to use a substrate having a large expansion / contraction rate such as a plastic substrate.

1 is a top view schematically showing a layout of an active matrix substrate 100 according to a first embodiment of the present invention. 3 is an enlarged top view of a part of the display area of the active matrix substrate 100. FIG. 2A is a cross-sectional view taken along line A-A ′ in FIG. 2, FIG. 2B is a cross-sectional view taken along line B-B ′ in FIG. 2, and FIG. 3C is a perspective view corresponding thereto. (A) shows an arrangement example suitable for the case where the plastic substrate extends during the period from the formation of the scanning wiring to the patterning of the drain electrode and the pixel electrode, and (b) showing the arrangement of the plastic substrate during the same period. An arrangement example suitable for contraction is shown. An example of arrangement in the case where it is unspecified whether the plastic substrate extends or contracts after the scanning wiring is formed and before the drain electrode and the pixel electrode are patterned is shown. (A)-(d) is a top view which shows two pixel areas in the main process steps. (A)-(e) is process sectional drawing which shows the A-A 'line cross section and B-B' line cross section of FIG. 6 in the main process steps. (A)-(e) is process sectional drawing which shows the A-A 'line cross section and B-B' line cross section of FIG. 6 in the main process steps. (A)-(b) is process sectional drawing which shows the A-A 'line cross section and B-B' line cross section of FIG. 6 in the main process steps. (A) is the elements on larger scale which show a part of resist mask which prescribes | regulates a pixel electrode etc., (b), (c) and (d) are CC 'line sectional drawings of (a), respectively. , DD ′ line sectional view, and EE ′ line sectional view. FIG. 9 is a schematic perspective view of the resist mask shown in FIG. 8. It is a typical perspective view after the ashing of the resist mask of FIG. It is a figure for demonstrating the electrodeposition method of the color filter employ | adopted by embodiment of this invention. It is a top view which shows an example of the alignment marker employ | adopted by embodiment of this invention. It is a graph which shows the relationship between alignment margin (substrate expansion / contraction margin) (DELTA) y and pixel pitch. It is the top view which showed the outline of the layout of the active matrix substrate 200 in the 2nd Embodiment of this invention. 14A is a cross-sectional view taken along line A-A ′ in FIG. 14, and FIG. 15B is a cross-sectional view taken along line B-B ′ in FIG. 14. It is drawing which shows the manufacturing method of the active matrix substrate 200 in the 2nd Embodiment of this invention, and is a top view which shows two pixel areas in the main process steps. FIG. 17 is a process cross-sectional view illustrating a cross section along line A-A ′ and a cross section along line B-B ′ in FIG. 16. It is the top view which showed the outline of the layout of the active matrix substrate 300 in the 3rd Embodiment of this invention. (A) And (b) is a top view which shows the shape of the black matrix 35 in a thin-film transistor formation area, (c) And (d) is the FF 'line | wire cross section of (a) and (b), respectively. FIG. It is drawing which shows the manufacturing method of the active matrix substrate 400 in the 4th Embodiment of this invention, and is a top view which shows two pixel areas in the main process steps. FIG. 21 is a process cross-sectional view illustrating a cross section along line A-A ′ and a cross section along line B-B ′ in FIG. 20. It is a top view which shows typically the layout of the active matrix substrate 500 which concerns on the 5th Embodiment of this invention. FIG. 4 is an enlarged top view of a part of a display area of an active matrix substrate 500. It is A-A 'line sectional drawing of FIG. FIG. 24 is a sectional view taken along line B-B ′ of FIG. 23. It is the upper side figure which expanded a part of display area of active matrix substrate 600 concerning a 6th embodiment by the present invention. FIG. 27 is a sectional view taken along line A-A ′ of FIG. 26. FIG. 27 is a sectional view taken along line B-B ′ of FIG. 26. It is the top view to which a part of display area of the active matrix substrate 700 which concerns on the improvement of the 6th Embodiment by this invention was expanded. FIG. 30 is a cross-sectional view taken along line A-A ′ of FIG. 29. FIG. 30 is a sectional view taken along line B-B ′ of FIG. 29. It is the upper side figure which expanded a part of display area of active matrix substrate 800 concerning a 7th embodiment by the present invention. It is A-A 'line sectional drawing of FIG. FIG. 33 is a cross-sectional view taken along line B-B ′ of FIG. 32. It is the upper side figure to which a part of display area of active matrix substrate 900 concerning an 8th embodiment by the present invention was expanded. FIG. 36 is a sectional view taken along line A-A ′ of FIG. 35. FIG. 36 is a sectional view taken along line B-B ′ of FIG. 35. FIG. 36 is a sectional view taken along line C-C ′ of FIG. 35. It is the upper side figure to which a part of display area of active matrix substrate 1000 concerning a 9th embodiment by the present invention was expanded. FIG. 40 is a cross-sectional view taken along line A-A ′ of FIG. 39. It is a figure which shows the manufacturing method of the active-matrix board | substrate 1100 in the 10th Embodiment of this invention, and is a top view which shows two pixel areas in the main process steps. FIG. 42 is a process cross-sectional view illustrating the cross section along line A-A ′ and the cross section along line B-B ′ of FIG. 41. It is a top view of the conventional active matrix type display apparatus. It is sectional drawing of the conventional liquid crystal display panel. (A) is a planar layout view in one pixel region formed on a conventional active matrix substrate, and (b) is a cross-sectional view taken along line A-A ′. (A) is a planar layout view in one pixel region formed on a conventional active matrix substrate, and (b) is a cross-sectional view taken along line A-A ′. It is a layout diagram in one pixel region formed on a conventional active matrix substrate. It is the layout used in order to obtain | require the relationship between a pixel pitch and an alignment margin about the conventional active matrix substrate. It is a top view which shows the cross | intersection 80 of the scanning wiring 102 and the signal wiring 105 in the conventional active matrix substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plastic substrate 2 Scanning wiring 3 Gate electrode 4 Gate insulating film 5 Signal wiring 6 Intrinsic semiconductor layer 7 Impurity addition semiconductor layer 8 Source electrode 9 Drain electrode 10 Thin film transistor (TFT)
DESCRIPTION OF SYMBOLS 11 Protective insulating film 14 Pixel electrode 15 Connection part of drain electrode (part connected to pixel electrode)
20 Auxiliary capacitance wiring 21 Interlayer insulating film 22 Contact hole 23 Channel protective film 31 Channel region of thin film transistor 33 Color filter 35 Black matrix 36 Counter electrode 37 Alignment film 38 Liquid crystal layer 39 Seal 40 Spacer 50 Liquid crystal panel 51 Gate drive circuit 51
52 Source drive circuit 52
53 Gate driver / source driver 54 Transparent insulating substrate 55 Counter substrate 56 Polarizer 91 Transparent conductive film 92 Resist mask 93 Light-shielding metal film 95 Channel protective layer 96 Reflective metal film 101 Plastic substrate 102 Scanning wiring 103 Gate electrode 104 Gate insulating film 105 Signal wiring 106 Intrinsic semiconductor layer 107 Impurity-added semiconductor layer (contact layer)
108 Source electrode 109 Drain electrode 110 Thin film transistor (TFT)
113 Auxiliary capacitance line 114 Pixel electrode

Claims (23)

A plastic substrate,
A first scanning wiring formed on the plastic substrate;
A second scanning line formed on the plastic substrate and arranged in parallel to the first scanning line;
A third scanning line formed on the plastic substrate and disposed in parallel to the second scanning line;
A signal wiring crossing the first to third scanning wirings via an insulating film;
A first pixel electrode traversing the first scan line;
A second pixel electrode crossing the second scanning line;
A first thin film transistor in which a semiconductor layer is formed in a self-aligned manner with respect to the second scanning wiring;
A second thin film transistor in which a semiconductor layer is formed in a self-aligned manner with respect to the third scan wiring;
With
The first pixel electrode is connected to the first thin film transistor by a first conductive member that traverses the second scanning wiring,
The active pixel substrate, wherein the second pixel electrode is connected to the second thin film transistor by a second conductive member crossing the third scanning line. An active matrix substrate according to claim 1;
A substrate facing the active matrix substrate;
A light modulation layer located between the active matrix substrate and the counter substrate;
A display device comprising:   A portable electronic device comprising the display device according to claim 2. Forming a semiconductor film on the substrate;
Forming a first conductive film on the semiconductor film;
By patterning the first conductive film and the semiconductor film, a plurality of signal lines, a plurality of pixel electrodes, and a conductive member extending from each pixel electrode along the signal lines are formed, and the signal lines and the conductive film are formed. Leaving the semiconductor film located in a region between the members without removing;
After patterning the first conductive film and the semiconductor film, forming an insulating film on the substrate;
Forming a second conductive film on the insulating film;
The second conductive film is patterned to form a plurality of scanning wirings that intersect the signal wiring, the pixel electrode, and the conductive member, and the semiconductor film located in a region between the signal wiring and the conductive member Etching a portion other than the portion located below the scanning wiring,
For manufacturing an active matrix substrate. The step of patterning the first conductive film and the semiconductor film includes:
A resist mask having a relatively thick portion that defines the signal wiring, the pixel electrode, and the conductive member, and a relatively thin portion that defines a region between the signal wiring and the conductive member is formed. Process,
Etching a portion of the first conductive film and the semiconductor film that is not covered with the resist mask;
Removing the relatively thin portion from the resist mask;
Etching the portion of the first conductive film covered by the relatively thin portion of the resist mask;
A method for manufacturing an active matrix substrate according to claim 4. Forming a scanning wiring partly including a gate electrode on the substrate;
Forming a gate insulating film covering the gate electrode;
Forming a semiconductor layer on the gate insulating film;
Forming a positive resist layer on the semiconductor layer;
A step of irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer, and then developing to form a first resist mask aligned with the gate electrode above the gate electrode. When,
Removing a portion of the semiconductor layer that is not covered by the first resist mask, and forming a semiconductor layer including a portion functioning as a semiconductor region of a thin film transistor in a self-aligned manner with respect to the scan wiring;
Removing the first resist mask;
Depositing a conductive film to cover the semiconductor layer;
By patterning the conductive film using a second resist mask, a source electrode and a drain electrode intersecting with the scanning wiring are formed, and a signal wiring partially including the source electrode is formed. Forming a semiconductor region of the thin film transistor under the source electrode and the drain electrode by patterning a semiconductor layer;
For manufacturing an active matrix substrate. Forming the semiconductor region of the thin film transistor,
A resist pattern having, as the second resist mask, a relatively thick portion that defines the source electrode and the drain electrode and a relatively thin portion that defines a gap region between the source electrode and the drain electrode. Forming, and
Etching a portion of the conductive film and semiconductor layer that is not covered with the resist pattern;
Removing a relatively thin portion of the resist pattern;
Etching the portion of the conductive film covered by a relatively thin portion of the resist pattern to form the source electrode and the drain electrode;
A method for manufacturing an active matrix substrate according to claim 6.   8. The source electrode is a part of the signal wiring extending linearly so as to intersect the scanning wiring, and the drain electrode extends in parallel from the pixel electrode along the signal wiring. A method for producing an active matrix substrate as described in 1. above. Forming a gate electrode on the substrate;
Forming a gate insulating film covering the gate electrode;
Forming a semiconductor layer on the gate insulating film;
Forming a channel protective layer on the semiconductor layer;
Forming a first positive resist layer on the channel protective layer;
The substrate is irradiated with light from the back side of the substrate, whereby the first positive resist layer is exposed, and then developed, a first resist mask aligned with the gate electrode is formed above the gate electrode by development. Forming, and
Removing a portion of the channel protective layer that is not covered by the first resist mask, and disposing the channel protective layer in a self-aligned manner with respect to the gate electrode;
Depositing a contact layer to cover the channel protective layer and the semiconductor layer;
Forming a second resist mask above the gate electrode;
A portion of the contact layer and the semiconductor layer that is not covered with the second resist mask is removed, and a semiconductor layer including a contact layer, a channel protective layer, and a portion that functions as a semiconductor region of the thin film transistor is formed with respect to the gate electrode. Forming in a self-aligning manner,
Removing the second resist mask;
Depositing a conductive film to cover the contact layer;
By patterning the conductive film using a third resist mask, a source electrode and a drain electrode intersecting with the gate electrode are formed, and further, the contact layer, the channel protective layer, and the semiconductor layer are patterned. Forming a semiconductor region of the thin film transistor whose upper surface is partially covered with the channel protective film under the source electrode and the drain electrode;
For manufacturing an active matrix substrate. The step of forming the semiconductor layer of the thin film transistor comprises
A resist pattern having, as the third resist mask, a relatively thick portion that defines the source electrode and the drain electrode and a relatively thin portion that defines a gap region between the source electrode and the drain electrode. Forming, and
Etching a portion of the conductive film, contact layer, and semiconductor layer that is not covered with the resist pattern;
Removing a relatively thin portion of the resist pattern;
Etching a portion of the conductive film and the contact layer that was covered with a relatively thin portion of the resist pattern, and separating and forming the source electrode and the drain electrode;
A method for manufacturing an active matrix substrate according to claim 9.   The method for manufacturing an active matrix substrate according to claim 9 or 10, wherein the width of the channel protective layer is narrower than the width of the semiconductor region. Forming a gate electrode on the substrate;
Forming a gate insulating film covering the gate electrode;
Forming a semiconductor layer on the gate insulating film;
Forming a channel protective layer on the semiconductor layer;
Forming a positive resist layer on the channel protective layer;
A step of irradiating the substrate with light from the back side of the substrate, thereby exposing the positive resist layer, and then developing to form a first resist mask aligned with the gate electrode above the gate electrode. When,
Removing a portion of the channel protective layer that is not covered by the first resist mask, and disposing the channel protective layer in a self-aligned manner with respect to the gate electrode;
Depositing a contact layer to cover the channel protective layer and the semiconductor layer;
Depositing a conductive film to cover the contact layer;
By patterning the conductive film using a second resist mask, a source electrode and a drain electrode intersecting the gate electrode are formed, and further, the contact layer, the channel protective layer, and the semiconductor layer are patterned. Forming a semiconductor region of the thin film transistor whose upper surface is partially covered with the channel protective film under the source electrode and the drain electrode;
For manufacturing an active matrix substrate. Forming the semiconductor region of the thin film transistor,
A resist pattern having, as the second resist mask, a relatively thick portion that defines the source electrode and the drain electrode and a relatively thin portion that defines a gap region between the source electrode and the drain electrode. Forming, and
Etching a portion of the conductive film, contact layer, and semiconductor layer that is not covered with the resist pattern;
Removing a relatively thin portion of the resist pattern;
Etching a portion of the conductive film and contact layer that was covered by a relatively thin portion of the resist pattern, and separating and forming the signal wiring and the conductive member;
A method for manufacturing an active matrix substrate according to claim 12.   The method for manufacturing an active matrix substrate according to claim 12 or 13, wherein the semiconductor layer is formed in a self-aligned manner with respect to the gate electrode by a backside exposure method before the contact layer is formed.   After removing a relatively thin portion of the resist pattern, when etching a portion of the conductive film and the contact layer that is covered with a relatively thin portion of the resist pattern, an exposed portion of the semiconductor layer is removed. The method of manufacturing an active matrix substrate according to claim 13, wherein the semiconductor region of the thin film transistor is left under the channel protective layer by etching. A substrate,
A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode;
A semiconductor layer formed above the gate electrode through the gate insulating film;
A source electrode formed to intersect the semiconductor layer;
A drain electrode formed to intersect the semiconductor layer,
The thin film transistor in which a side surface parallel to a direction in which the source electrode and the drain electrode extend is aligned with an outer side surface of the source electrode and the drain electrode among the side surfaces of the semiconductor layer.   The thin film transistor according to claim 16, wherein a side surface parallel to a direction in which the gate electrode extends among the side surfaces of the semiconductor layer is aligned with the side surface of the gate electrode.   The thin film transistor according to claim 16 or 17, wherein a contact layer is provided between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer. A substrate,
A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode;
A semiconductor layer formed above the gate electrode through the gate insulating film;
A channel protective layer formed on the semiconductor layer;
A source electrode formed to intersect the channel protective layer;
A drain electrode formed to cross the channel protective layer,
A side surface of the channel protective layer that is parallel to a direction in which the source electrode and the drain electrode extend is aligned with an outer side surface of the source electrode and the drain electrode.   The thin film transistor according to claim 19, wherein, of the side surfaces of the channel protective layer, a distance between two side surfaces parallel to a direction in which the gate electrode extends is narrower than a line width of the gate electrode.   21. The thin film transistor according to claim 19, wherein a side surface parallel to a direction in which the gate electrode extends among the side surfaces of the semiconductor layer is aligned with the side surface of the gate electrode.   The thin film transistor according to any one of claims 19 to 21, wherein a side surface parallel to a direction in which the source electrode and the drain electrode extend is aligned with an outer side surface of the source electrode and the drain electrode among the side surfaces of the semiconductor layer. .   23. The thin film transistor according to claim 19, wherein a contact layer is provided between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.

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